A power mosfet chip with programmable gate resistance

Abstract

The application discloses a power MOSFET chip with programmable gate resistance, comprising a semiconductor substrate, a polysilicon gate layer and a gate metal layer; the gate metal layer comprises at least two mutually electrically isolated gate metal regions and a gate signal expansion region, each gate metal region corresponds to at least one high-resistance thin strip, and the gate signal expansion region is connected with each gate metal region through the high-resistance thin strip; the resistance value of the high-resistance thin strip corresponding to each gate metal region is used for constituting a gate metal region resistance, and all the gate metal region resistances are used for constituting an additional gate resistance of the power MOSFET chip, so that the programmable design of the gate resistance is realized; and an independent gate pad area is arranged on each gate metal region. The application replaces discrete components with built-in high-resistance thin strips, and eliminates PCB-level parasitic parameters from the source; and the application innovatively adopts a gate metal partition binding programmable structure to realize passive and reversible resistance dynamic adjustment.

Description

Technical Field

[0001] This invention relates to the field of MOSFET chip technology, and more particularly to a power MOSFET chip with a programmable gate resistor. Background Technology

[0002] In the development of power MOSFET devices, gate resistor design has always faced multiple technical challenges. Traditional solutions place the gate drive resistor externally on the PCB board, such as a surface-mount resistor series structure. While this achieves basic current limiting, it introduces a 2-5nH parasitic inductance, leading to gate voltage ringing and EMI noise degradation under high-frequency switching conditions. Another existing technology indicates that such discrete components also occupy more than 30% of the wiring space in the power module, severely restricting high-density integration. To reduce the impact of parasitic parameters, the industry has turned to integrated gate resistor solutions: In addition, existing technologies have proposed polysilicon resistor layer integration technology, which uses laser to adjust and solidify the resistance value. However, the adjusted resistance value cannot be changed, making it unsuitable for the dynamic switching requirements of hard / soft switching modes in new energy vehicle inverters. Other existing technologies attempt to optimize the gate metal bus pattern, achieving ±15% resistance fine-tuning through linewidth adjustment. However, process fluctuations cause inter-cell resistance deviations to exceed 10%, leading to switching asynchrony and localized overheating failures.

[0003] Existing technologies have significant limitations in addressing the need for dynamic resistance adjustment. For example, polycrystalline silicon fuse structures rely on high-voltage pulse circuits to burn out specific paths to change the resistance, an irreversible operation with a failure rate as high as 12%. Another approach uses voltage-controlled doping region technology, employing bias voltage to change the carrier concentration of the P-type islands to achieve continuous resistance adjustment, but this increases wafer costs by 37% due to the addition of three photomasks. Other existing technologies include adjusting the resistance by regulating the spacing of gate metal contact holes, but these still cannot break through the fixed resistance framework. Notably, existing technologies also propose multi-PAD parallel structures to reduce on-resistance, but the resistance matching accuracy of each sub-region is limited by photolithography alignment errors; deviations exceeding ±10% lead to current distribution imbalances. Furthermore, this design lacks resistance programming capabilities, making it difficult to meet the varying switching speed requirements of photovoltaic inverters.

[0004] The shortcomings of the above-mentioned solutions in terms of process compatibility, dynamic adjustability, and current sharing performance stem from the failure to resolve three core contradictions: first, the inherent conflict between external resistors and parasitic parameters; second, the contradiction between fixed resistance values ​​and dynamic scenarios; and third, the contradiction between current sharing requirements and the control of process fluctuations. Especially in high-current applications, the traditional multi-PAD parallel structure is prone to hot spot failure due to uncontrollable resistance values ​​and accumulated deviations, becoming a bottleneck restricting device reliability. Summary of the Invention

[0005] Technical Objective: To address the shortcomings of existing power MOSFET gate resistor designs that use external resistors, leading to parasitic inductance and causing switching ringing and EMI noise, this invention provides a power MOSFET chip with a programmable gate resistor. By replacing discrete components with a built-in high-resistance strip, it eliminates PCB-level parasitic parameters at the source. It innovatively adopts a gate metal partitioning and bonding programmable structure to achieve passive and reversible dynamic resistance adjustment on the user side, breaking through the dependence of traditional solutions on complex circuits or additional processes.

[0006] Technical solution: To achieve the above technical objectives, the present invention adopts the following technical solution.

[0007] A power MOSFET chip with a programmable gate resistor, comprising:

[0008] A semiconductor substrate on which several MOSFET units are formed;

[0009] A polycrystalline silicon gate layer covers the MOSFET unit cell region;

[0010] A gate metal layer is located above the polysilicon gate layer and is isolated by an isolation dielectric layer; the gate metal layer and the polysilicon gate layer are electrically connected through an isolation dielectric via; the gate metal layer includes at least two electrically isolated gate metal regions and a gate signal extension region;

[0011] Each gate metal region corresponds to at least one high-resistivity strip. The high-resistivity strip is on the same layer as the gate metal region or on the same layer as the polysilicon gate layer. The gate signal extension region is connected to each gate metal region through the high-resistivity strip.

[0012] The resistance value of the high-resistance strip corresponding to each gate metal region is used to form the gate metal region resistor. All gate metal region resistors are used to form the additional gate resistor of the power MOSFET chip, realizing the programmable design of the gate resistor.

[0013] Each gate metal region has an independent gate pad area, which serves as a PAD area; the gate pad area is connected to an external driving circuit, and the built-in gate resistor of the corresponding gate metal region is activated.

[0014] Furthermore, the gate metal region resistance of each gate metal region satisfies:

[0015] The gate metal region resistance values ​​of each gate metal region are the same; or the gate metal region resistance values ​​of each gate metal region are different, and the ratio of the resistance values ​​of any two regions is ≥ 1.5.

[0016] Furthermore, the additional gate resistance R when activating K gate metal regions K The minimum value R among the gate metal region resistances that activate a single gate metal region imin The following conditions must be met between R:imini / K≤R K ≤ 0.8R imin , K≥2.

[0017] Furthermore, when only a single gate pad region is connected to the external drive circuit, the gate current flows only through the high-resistance strip associated with that gate metal region; the additional gate resistance of the power MOSFET chip is the gate metal region resistance through which the gate current flows; the gate metal region resistance is composed of the resistance value of the high-resistance strip corresponding to that gate metal region, and the resistance values ​​of the high-resistance strips are in parallel.

[0018] When at least two gate pad regions are connected to an external driving circuit, the gate current flows in parallel through multiple high-resistance strips of gate metal regions. At this time, the gate metal region resistances of each activated gate metal region are in parallel.

[0019] Furthermore, when K gate metal regions are connected in parallel, the resistance value R of the additional gate resistor... K satisfy:

[0020] ,

[0021] Among them, R i Let be the gate metal region resistance corresponding to the i-th gate metal region.

[0022] Furthermore, the ratio of the length L to the width W of the high-resistivity strip satisfies L / W ≥ 1.

[0023] Furthermore, when the material of the high-resistivity strip is polycrystalline silicon, the width W of the high-resistivity strip is ≤ 100μm and the length L is ≥ 20μm.

[0024] Furthermore, the gate metal region can be arranged in a rectangular block layout or a sector layout. In the case of a rectangular block layout, each gate metal region is distributed in a rectangular or rounded rectangle. In the case of a sector layout, each gate metal region is distributed according to the central angle, with the gate signal extension region as the center.

[0025] Beneficial effects: In a power MOSFET chip, this invention divides the gate metal layer into at least two electrically isolated gate metal regions. Each gate metal region has an independent gate pad area and is connected to the central gate signal extension area through a high-resistivity thin strip. This invention eliminates PCB-level parasitic parameters at the source by replacing discrete components with built-in high-resistivity thin strips. It innovatively adopts a gate metal partition bonding programmable structure to achieve passive and reversible dynamic resistance adjustment. Users can select and activate specific gate pad areas through bonding lines. When multiple gate pad areas are activated, the additional gate resistance is equal to the parallel resistance of the gate metal areas of each activated area, realizing programmable adjustment of the additional gate resistance to adapt to various application scenarios. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the front metal layer and electrodes of a power MOSFET.

[0027] Figure 2 This is a schematic diagram of the gate electrode region of a power MOSFET.

[0028] Figure 3 This is a schematic diagram of the gate electrode region of a power MOSFET chip with a programmable gate resistor according to Embodiment 1.

[0029] Figure 4 This is a schematic diagram of the gate electrode region of a power MOSFET chip with a programmable gate resistor according to Embodiment 2.

[0030] Figure 5 This is a schematic diagram of the gate electrode region of a power MOSFET chip with a programmable gate resistor according to Embodiment 3, wherein the gate metal region is arranged in a fan shape.

[0031] Among them, 200 is the polysilicon gate layer; 300 is the gate metal layer; 310 is the gate metal region; 311 is the gate pad region; 320 is the gate signal extension region; 330 is the high-resistivity thin strip; 340 is the isolation dielectric via; 400 is the source metal layer; and 401 is the source pad region. Detailed Implementation

[0032] The following description, in conjunction with the accompanying drawings and embodiments, further explains and illustrates a power MOSFET chip with a programmable gate resistor according to the present invention.

[0033] The embodiments are for illustrative purposes only and do not constitute a limitation on the scope of the claims. Other alternative means that can be conceived by those skilled in the art are all within the scope of the claims of this invention.

[0034] Furthermore, in the description of this invention, it should be noted that the terms "central," "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. In addition, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0035] As attached Figure 1 To be continued Figure 4 As shown, a power MOSFET chip with a programmable gate resistor according to the present invention includes:

[0036] A semiconductor substrate on which several MOSFET units are formed;

[0037] A polysilicon gate layer 200 covers the MOSFET unit cell region;

[0038] A gate metal layer 300 is located above the polysilicon gate layer 200 and is isolated by an isolation dielectric layer; the gate metal layer 300 and the polysilicon gate layer 200 are electrically connected through an isolation dielectric via 340; the gate metal layer 300 includes at least two electrically isolated gate metal regions 310 and a gate signal extension region 320.

[0039] Each gate metal region 310 corresponds to at least one high-resistivity strip 330. The high-resistivity strip 330 is on the same layer as the gate metal region 310 or on the same layer as the polysilicon gate layer 200. The gate signal extension region 320 is connected to each gate metal region 310 through the high-resistivity strip 330.

[0040] The resistance value of the high-resistance strip 330 corresponding to each gate metal region 310 is used to form the gate metal region resistor. All gate metal region resistors are used to form the additional gate resistor of the power MOSFET chip, realizing the programmable design of the gate resistor. The high-resistance strip 330 corresponding to each gate metal region 310 refers to the high-resistance strip connecting the gate metal region 310 and the gate signal extension region 320.

[0041] The built-in gate resistor of a power MOSFET device consists of two parts: one part is the distributed resistance inherent in the conventional device structure, and the other part is an additional gate resistor. This additional resistor can achieve dynamic resistance adjustment, which is the programmable gate resistor introduced by the high-resistance thin strip in this invention.

[0042] Each gate metal region 310 has an independent gate pad region 311, which serves as a PAD region;

[0043] The gate pad region 311 is connected to an external driving circuit, and the built-in gate resistor in the corresponding gate metal region 310 is activated. At this time:

[0044] When only a single gate pad region 311 is connected to an external drive circuit via a bonding lead, the gate current flows only through the high-resistance strip 330 associated with that gate metal region 310; the additional gate resistance of the power MOSFET chip is the gate metal region resistance of the gate metal region 310 through which the gate current flows; the gate metal region resistance is composed of the resistance value of the high-resistance strip 330 corresponding to that gate metal region, and the resistance values ​​of the high-resistance strip 330 are in parallel.

[0045] When at least two gate pad regions 311 are connected to an external drive circuit via bonding leads, the gate current flows in parallel through the high-resistance strips 330 of multiple gate metal regions 310. At this time, the gate metal region resistances of each activated gate metal region are in parallel. Furthermore, when K gate metal regions 310 are connected in parallel, the resistance value R of the additional gate resistor... K The following calculation formula must be satisfied:

[0046] ,

[0047] Among them, R i For the gate metal region resistance corresponding to the i-th gate metal region 310, in some embodiments of the present invention, the condition 3Ω ≤ R is also satisfied. i ≤ 60Ω.

[0048] The gate metal region resistance of each gate metal region 310 satisfies one of the following conditions:

[0049] (1) The resistance values ​​of the gate metal regions in each gate metal region are the same;

[0050] (2) The resistance values ​​of the gate metal regions of each gate metal region are different, and the ratio of the resistance values ​​of any two regions is ≥ 1.5.

[0051] The present invention sets two conditions for the gate metal region resistance, mainly to improve the programmability of the additional gate resistance or reduce the difficulty of process implementation. Under the first condition, the process difficulty of the power MOSFET chip is low, but the programmability of the additional gate resistance is low. Under the second condition, the process difficulty of the power MOSFET chip is high, but the programmability of the additional gate resistance is high. For example, under the same conditions: the power MOSFET chip has two gate metal regions. If the gate metal region resistance is 1, then under different selection methods, the additional gate resistance value of the power MOSFET chip is 0.5 or 1, and there are only two programmable results. If the gate metal region resistances are 1 and 2 respectively, then under different selection methods, the additional gate resistance value of the power MOSFET chip is 1, 2 or 0.67, and there are three programmable results. When there are more gate metal regions, it is foreseeable that the programmable results corresponding to different gate metal region resistance values ​​will be much more numerous than the programmable results corresponding to the same gate metal region resistance values.

[0052] Additional gate resistance R when activating K gate metal regions 310 K The minimum value R among the gate metal region resistances of the single gate metal region 310 that activates it. imin The following conditions must be met between R: imini / K≤R K ≤ 0.8R imin , K≥2.

[0053] The ratio of the length L to the width W of the high-resistivity thin strip 330 satisfies L / W ≥ 1; and the high-resistivity thin strip 330 satisfies one of the following conditions:

[0054] (1) It is in the same layer as the gate metal region 310 and is etched together with the metal of the gate metal region in one step. At this time, the high-resistivity strip 330 is directly connected to the gate metal region 310 and the gate signal extension region 320.

[0055] (2) The high-resistivity strip 330 is in the same layer as the polysilicon gate layer 200 and is made of the same material as the polysilicon gate layer 200. It is electrically connected to the gate metal region 310 and the gate signal extension region 320 through the isolation medium hole 340.

[0056] When the material of the high-resistivity strip 330 is polysilicon, that is, when the high-resistivity strip 330 is on the same layer as the polysilicon gate layer 200, the width W of the high-resistivity strip 330 is ≤ 100μm and the length L is ≥ 20μm, which facilitates the setting of the isolation dielectric hole 340 on the high-resistivity strip 330, thereby realizing the connection between the gate metal region 310 and the gate signal extension region 320; the isolation dielectric hole 340 is filled with metal, and the depth range of the isolation dielectric hole 340 is 0.1μm~2μm.

[0057] The gate metal region 310 is arranged in one of the following ways:

[0058] (1) Rectangular block layout: Each gate metal region is distributed in a rectangular or rounded rectangle;

[0059] (2) Sector layout: Centered on the gate signal extension region, each gate metal region is distributed according to the central angle, as shown in the attached figure. Figure 5 As shown.

[0060] The gate pad area 311 is connected to external circuitry in any of the following ways:

[0061] (1) Bonding lead connection: Metal wires are bonded to external pins;

[0062] (2) Vertical interconnect structure: Metal pillars formed by laser drilling are connected to the redistribution layer of the embedded PCB. The metal pillars penetrate the electrical isolation layer. The power MOSFET chip is packaged through the electrical isolation layer during use. Therefore, when connecting to external circuits, the connection is achieved through the metal pillars after the laser drilling penetrates the electrical isolation layer.

[0063] The structure of the present invention will be further described below with reference to the accompanying drawings.

[0064] like Figure 1As shown, the source metal layer 400 covers the unit cell region of the power MOSFET, and a source pad region 401 for subsequent external circuit connections is provided thereon. The gate metal layer 300 is isolated from the source metal layer 400 and covers the gate bus region to reduce the distributed resistance from the gate electrode to the unit cell and reduce the switching delay of unit cells in different regions. The gate metal layer has a gate pad region 311 for subsequent external circuit connections.

[0065] like Figure 2 As shown, a polysilicon gate layer 200 lies beneath the gate metal layer 300, and the polysilicon gate layer 200 is cut out in the gate pad region 311 to prevent damage to the polysilicon gate during subsequent external bonding. The polysilicon gate layer 200 covers the MOSFET unit cell region; the gate metal layer 300 and the polysilicon gate layer 200 are isolated by an isolation dielectric layer, and there is an overlapping area between the gate metal layer 300 and the polysilicon gate layer 200 along the circumference of the gate pad region 311. This area is electrically connected through an isolation dielectric via 340. When the device is operating, after the gate signal reaches the gate pad via external wire bonding, it is mainly transmitted on the gate bus through the gate metal layer 300 with extremely low on-resistance, and then reaches the corresponding polysilicon gate layer 200 through the isolation dielectric via 340.

[0066] Figure 3 This is a schematic diagram of the gate electrode region of a power MOSFET chip with a programmable gate resistor, corresponding to Embodiment 1 of the present invention. Figure 2 The difference lies in Embodiment 1, where the gate metal layer 300 is divided into a gate signal extension region 320 and two independent gate metal regions 310. The gate signal extension region 320 and each independent gate metal region 310 are connected by high-resistivity strips 330. In this embodiment, the high-resistivity strips 330 and the gate metal regions 310 are made of the same material; that is, the gate signal extension region 320, the gate metal regions 310, and the high-resistivity strips 330 are formed in a single metal etching process. In this embodiment, the gate metal layer 300 is made of aluminum with a thickness of approximately 3 μm. The two gate metal regions 310 and the high-resistivity strips are symmetrically arranged. Each high-resistivity strip is approximately 1 μm wide and 700 μm long, corresponding to an internal gate resistance of approximately 6 Ω. Therefore, when an external gate drive lead connects to any gate pad region, the chip's additional gate resistance is 6 Ω. However, when the external gate drive lead connects to two gate pad regions simultaneously, the chip's additional gate resistance becomes 3 Ω.

[0067] Figure 4 This is a schematic diagram of the gate electrode region of a power MOSFET chip with a programmable gate resistor, corresponding to Embodiment 2 of the present invention. Figure 2The difference lies in Embodiment 2, where the gate metal layer 300 is divided into a gate signal extension region 320 and three independent gate metal regions 310. The gate signal extension region 320 and each independent gate metal region 310 are connected by high-resistivity strips 330. In this embodiment, the high-resistivity strips 330 are made of the same material as the polysilicon gate layer 200, which is doped polysilicon, with a thickness of approximately 0.4 μm. Each high-resistivity strip 330 has a width of 60 μm, and the spacing of the isolation dielectric vias 340 on the strip is 100 μm. Therefore, each high-resistivity strip 330 has an effective width of 60 μm and an effective length of 100 μm, corresponding to a gate resistance of approximately 24 Ω. ​​The high-resistivity strips corresponding to each gate metal region 310 are connected in parallel, and the effective resistance is the resistance of a single high-resistivity strip (24 Ω) divided by the number of high-resistivity strips connecting that region; as shown in the attached figure. Figure 4 As shown, the gate metal region 310, where the left gate pad area is located, is connected to the gate signal extension region 320 via two high-resistivity thin strips 330, corresponding to a gate metal region resistance of 12Ω; the gate metal region 310, where the middle gate pad area is located, is connected to the gate signal extension region 320 via one high-resistivity thin strip 330, corresponding to a gate metal region resistance of 24Ω; and the gate metal region 310, where the right gate pad area is located, is connected to the gate signal extension region 320 via four high-resistivity thin strips 330, corresponding to a gate metal region resistance of 6Ω. A vertical interconnect structure is subsequently adopted, i.e., metal pillars formed by laser drilling penetrate the electrical isolation layer and connect to the redistribution layer of the embedded PCB. Table 1 shows the programmable results of the additional gate resistance of the power MOSFET chip corresponding to the metal pillar connection method of the gate pad area, with a checkmark indicating that the gate metal region is selected.

[0068] Table 1. Results of Programmable Additional Gate Resistors for Power MOSFET Chips

[0069]

[0070] As shown in the table above, by setting different metal pillar connection methods, the additional gate resistance can be adjusted in 7 modes between 3.43Ω and 24Ω, thus realizing programmable design.

[0071] Figure 5 This is a schematic diagram of the gate electrode region of a power MOSFET chip with a programmable gate resistor, corresponding to Embodiment 3 of the present invention. Figure 2The difference lies in Embodiment 3, where the gate metal layer 300 is divided into a gate signal extension region 320 and four independent gate metal regions 310, each connected by a high-resistivity strip 330. In this embodiment, the high-resistivity strip 330 and the gate metal regions 310 are made of the same material; that is, the gate signal extension region 320, the gate metal regions 310, and the high-resistivity strip 330 are formed in a single metal etching process. In this embodiment, the gate metal layer 300 is made of aluminum with a thickness of approximately 3 μm, and the four fan-shaped gate metal regions 310 are symmetrically arranged with the high-resistivity strip. Each high-resistivity strip is approximately 1 μm wide and 700 μm long, corresponding to an internal gate resistance of approximately 6 Ω. Therefore, when an external gate drive lead is connected to the gate pad in any region, the chip's additional gate resistance is 6 Ω; through different activation methods, the chip's additional gate resistance can be adjusted in four modes between 1.5 Ω and 6 Ω.

[0072] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A power MOSFET chip with a programmable gate resistor, characterized in that, include: A semiconductor substrate on which several MOSFET units are formed; A polycrystalline silicon gate layer covers the MOSFET unit cell region; A gate metal layer is located above the polysilicon gate layer and is isolated by an isolation dielectric layer; The gate metal layer and the polysilicon gate layer are electrically connected through an isolation dielectric via; The gate metal layer includes: at least two electrically isolated gate metal regions and a gate signal extension region; Each gate metal region corresponds to at least one high-resistivity strip. The high-resistivity strip is on the same layer as the gate metal region or on the same layer as the polysilicon gate layer. The gate signal extension region is connected to each gate metal region through the high-resistivity strip. The resistance value of the high-resistance strip corresponding to each gate metal region is used to form the gate metal region resistor. All gate metal region resistors are used to form the additional gate resistor of the power MOSFET chip, realizing the programmable design of the gate resistor. Each gate metal region has an independent gate pad area, which serves as a PAD area; the gate pad area is connected to an external driving circuit, and the built-in gate resistor of the corresponding gate metal region is activated. The gate metal region resistance of each gate metal region satisfies: The gate metal region resistance values ​​of each gate metal region are the same; or the gate metal region resistance values ​​of each gate metal region are different, and the ratio of the resistance values ​​of any two regions is ≥ 1.

5.

2. A power MOSFET chip with a programmable gate resistor according to claim 1, characterized in that: Additional gate resistance R when activating K gate metal regions K The minimum value R among the gate metal region resistances that activate a single gate metal region imin The following conditions must be met between R: imini / K≤R K ≤ 0.8R imin , K≥2.

3. A power MOSFET chip with a programmable gate resistor according to claim 1, characterized in that: When only a single gate pad region is connected to an external drive circuit, the gate current flows only through the high-resistivity strip associated with that gate metal region; the additional gate resistance of the power MOSFET chip is the gate metal region resistance through which the gate current flows; the gate metal region resistance is composed of the resistance value of the high-resistivity strip corresponding to that gate metal region, and the resistance values ​​of the high-resistivity strips are in parallel. When at least two gate pad regions are connected to an external driving circuit, the gate current flows in parallel through multiple high-resistance strips of gate metal regions. At this time, the gate metal region resistances of each activated gate metal region are in parallel.

4. A power MOSFET chip with a programmable gate resistor according to claim 3, characterized in that: When K gate metal regions are connected in parallel, the resistance value R of the additional gate resistor is... K satisfy: ， Among them, R i Let be the gate metal region resistance corresponding to the i-th gate metal region.

5. A power MOSFET chip with a programmable gate resistor according to claim 1, characterized in that: The ratio of the length L to the width W of the high-resistivity thin strip satisfies L / W ≥ 1.

6. A power MOSFET chip with a programmable gate resistor according to claim 1, characterized in that: When the material of the high-resistivity strip is polycrystalline silicon, the width W of the high-resistivity strip is ≤ 100μm and the length L is ≥ 20μm.

7. A power MOSFET chip with a programmable gate resistor according to claim 1, characterized in that: The gate metal region can be arranged in a rectangular block or a sector layout. In the case of a rectangular block layout, each gate metal region is distributed in a rectangular or rounded rectangle. In the case of a sector layout, each gate metal region is distributed according to the central angle with the gate signal extension region as the center.

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