SiC MOSFET device integrated with punch-through type NPN diode

Abstract

The invention discloses a SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device integrated with a punch-through NPN (Negative-Positive-Negative) diode, which is characterized in that an NPN punch-through JFET (Junction Field Effect Transistor) region is used as a reverse through-flow path, and on the premise of ensuring the reliability of a grid electrode of the device and relatively low specific on-resistance, the conduction voltage drop of reverse through-flow is further reduced, the conduction of a body diode is inhibited, and the switching loss is reduced by reducing reverse recovery charges. Compared with a traditional JFET structure, through a punch-through type breakdown electric field, the electron drift rate is increased, meanwhile, the reverse current path is increased, and the reverse flow capacity is improved. According to the invention, the bipolar degradation of the device can be effectively prevented, the reverse recovery charge is obviously reduced, the reverse through-current capability is enhanced, the switching speed is greatly improved, and the switching loss is reduced.

Description

Technical Field

[0001] This invention belongs to the field of power semiconductor device technology, specifically relating to the design of a SiCMOSFET device with an integrated punch-through NPN diode. Background Technology

[0002] Wide bandgap semiconductor material SiC is a typical material in third-generation semiconductors. Compared with traditional Si materials, it has a higher critical breakdown electric field strength, higher carrier saturation drift velocity, higher thermal conductivity and better radiation resistance. Therefore, it is an ideal material for high-power, high-voltage, high-temperature and radiation-resistant electronic devices.

[0003] To achieve high power and low loss, SiC MOSFET devices need to be developed towards higher channel density and lower on-state resistance. The trench structure of SiC MOSFET devices eliminates the JFET region and transforms the horizontal channel into a vertical channel, which can effectively reduce the cell size and integrate more cells on a chip of fixed area, thereby improving the device's integration density.

[0004] With the continuous development of power electronics, the performance requirements of power SiC MOSFETs are becoming increasingly stringent. Improving the switching frequency and reducing switching losses have become goals for many device designers. Based on this goal, some researchers have proposed SiC MOSFETs with integrated Schottky diodes or low-barrier diode structures. This type of structure uses an anti-parallel Schottky diode cell region or adds a source-controlled channel region to provide a reverse conduction path, suppressing body diode conduction and achieving reverse freewheeling integration. This reduces reverse conduction losses, increases power density, lowers switching losses, suppresses bipolar degradation effects, and improves device reliability. Summary of the Invention

[0005] The purpose of this invention is to propose a SiC MOSFET device with an integrated punch-through NPN diode, which increases the electron migration rate, improves the reverse freewheeling capability of the SiC MOSFET, reduces the conduction of the body diode, enhances the reliability of the device, and reduces switching losses.

[0006] The technical solution of the present invention is as follows: a SiC MOSFET device integrating a punch-through NPN diode, comprising an N-type substrate, an N-type epitaxial layer above the N-type substrate, and a current diffusion layer above the N-type epitaxial layer. The current diffusion layer is separated by two P-type shielding regions, both of which are L-shaped and mirror-symmetrically arranged. A polysilicon region is disposed inside the L-shape of each P-type shielding region. A P-type electron accelerating region is disposed between the two P-type shielding regions and is located above the current diffusion layer. An N+ contact region is disposed above the P-type electron accelerating region. A P-channel region is disposed on the side of each polysilicon region away from the P-type shielding region and is located above the current diffusion layer. A P+ contact region and an N+ contact region are disposed side by side above each P-channel region, and the N+ contact region above the P-channel region is adjacent to the polysilicon region. A metal layer covers the P+ contact region and the N+ contact region.

[0007] Furthermore, the metal layer forms the source of the MOSFET device through ohmic contacts with the P+ and N+ contact regions.

[0008] Furthermore, the N-type substrate and its external metal electrode form the drain of the MOSFET device through an ohmic contact.

[0009] Furthermore, the N+ contact region above the P-channel region, the P-channel region, the P-type shielding region, and the current diffusion layer together constitute the semiconductor region, and a gate oxide layer is disposed between the polysilicon region and the semiconductor region.

[0010] Furthermore, the polysilicon region contacts the gate oxide layer to form the gate of the MOSFET device.

[0011] Furthermore, the semiconductor material in the MOSFET device is SiC material.

[0012] Furthermore, the metal layer is made of aluminum.

[0013] The beneficial effects of this invention are: (1) Under the premise of ensuring the reliability of the device gate and a low specific on-resistance, the present invention further reduces the on-state voltage drop of the reverse current, suppresses the conduction of the body diode, and reduces the switching loss by reducing the reverse recovery charge.

[0014] (2) Compared with the traditional JFET structure, the present invention enhances the electron drift rate by punch-through breakdown electric field, while increasing the reverse current path and improving the reverse current carrying capacity.

[0015] (3) The present invention can effectively prevent bipolar degradation of the device, while significantly reducing reverse recovery charge, enhancing reverse current carrying capacity, greatly improving switching speed and reducing switching losses. Attached Figure Description

[0016] Figure 1 The diagram shown is a schematic diagram of a SiC MOSFET device structure with an integrated punch-through NPN diode provided in an embodiment of the present invention.

[0017] Explanation of reference numerals in the attached figures: 1-metal layer, 2-P+ contact region, 3-N+ contact region, 4-P-type electron acceleration region, 5-P-channel region, 6-polysilicon region, 7-P-type shielding region, 8-current diffusion layer, 9-N-type epitaxial layer, 10-N-type substrate, 11-gate oxide layer. Detailed Implementation

[0018] Exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be understood that the embodiments shown and described in the drawings are merely exemplary and are intended to illustrate the principles and spirit of the invention, and are not intended to limit the scope of the invention.

[0019] This invention provides a SiC MOSFET device with an integrated punch-through NPN diode, such as... Figure 1 As shown, the structure includes an N-type substrate 10, an N-type epitaxial layer 9 above the N-type substrate 10, and a current diffusion layer 8 above the N-type epitaxial layer 9. The current diffusion layer 8 is separated by two P-type shielding regions 7. Both P-type shielding regions 7 are L-shaped and arranged in a mirror symmetrical manner. A polysilicon region 6 is disposed inside the L-shape of each P-type shielding region 7. A P-type electron acceleration region 4 is disposed between the two P-type shielding regions 7, and the P-type electron acceleration region 4 is located above the current diffusion layer 8. An N+ contact region 3 is disposed above the P-type electron acceleration region 4. A P-channel region 5 is disposed on the side of each polysilicon region 6 away from the P-type shielding region 7, and the P-channel regions 5 are all located above the current diffusion layer 8. A P+ contact region 2 and an N+ contact region 3 are disposed side by side above each P-channel region 5, and the N+ contact region 3 above the P-channel region 5 is adjacent to the polysilicon region 6. A metal layer 1 covers the P+ contact region 2 and the N+ contact region 3.

[0020] In this embodiment of the invention, the metal layer 1 forms the source of the MOSFET device through an ohmic contact with the P+ contact region 2 and the N+ contact region 3; the N-type substrate 10 forms the drain of the MOSFET device through an ohmic contact with its external metal electrode.

[0021] In this embodiment of the invention, the N+ contact region 3 above the P-channel region 5, the P-channel region 5, the P-type shielding region 7, and the current diffusion layer 8 together constitute a semiconductor region, and a gate oxide layer 11 is disposed between the polysilicon region 6 and the semiconductor region; the polysilicon region 6 and the gate oxide layer 11 contact to form the gate of the MOSFET device.

[0022] In this embodiment of the invention, the semiconductor material in the MOSFET device is SiC material.

[0023] In this embodiment of the invention, the metal layer 1 is an aluminum layer.

[0024] The following is combined Figure 1 The working principle and process of the embodiments of the present invention will be described in detail below: The N+ contact region 3 above the P-channel region 5, the P-channel region 5, and the current diffusion layer 8 form an NPN diode. The polysilicon region 6 and the gate oxide layer 11 form the gate of the MOSFET device. The NPN diode and the gate together form the basic structure of the MOSFET device. The P-type shielding region 7 is used to protect the gate and reduce the gate electric field strength; the current diffusion layer 8 is used to reduce the resistance; the N-type epitaxial layer 9 is used to withstand high voltage; and the N-type substrate 10 forms an ohmic contact with the drain. The N+ contact region 3, the electron acceleration region 4, and the current diffusion layer 8 on the electron acceleration region 4 together form a punch-through diode structure. Based on the punch-through breakdown principle, the electron acceleration region 4 can generate an electron acceleration electric field; combined with the mirror-symmetric P-type shielding region 7, an integrated punch-through NPN diode is realized.

[0025] Those skilled in the art will recognize that the embodiments described herein are intended to help the reader understand the principles of the invention, and should be understood that the scope of protection of the invention is not limited to such specific statements and embodiments. Those skilled in the art can make various other specific modifications and combinations based on the technical teachings disclosed in this invention without departing from the spirit of the invention, and these modifications and combinations are still within the scope of protection of this invention.

Claims

1. A SiC MOSFET device integrated with a punch-through NPN diode, characterized in that, The application relates to a MOSFET device, which comprises an N-type substrate (10), an N-type epitaxial layer (9) above the N-type substrate (10), and a current diffusion layer (8) above the N-type epitaxial layer (9), wherein the current diffusion layer (8) is separated by two P-type shielding areas (7), the two P-type shielding areas (7) are L-shaped and mirror-symmetrically arranged, each of the P-type shielding areas (7) is provided with a polysilicon area (6) on the inner side of the L shape, a P-type electron acceleration area (4) is arranged between the two P-type shielding areas (7) and above the current diffusion layer (8), an N+ contact area (3) is arranged above the P-type electron acceleration area (4), a P-channel area (5) is arranged on the side of each of the polysilicon areas (6) away from the P-type shielding area (7) and above the current diffusion layer (8), a P+ contact area (2) and an N+ contact area (3) are arranged side by side above each of the P-channel areas (5), the N+ contact area (3) above the P-channel area (5) is arranged adjacent to the polysilicon area (6), and a metal layer (1) is arranged above the P+ contact area (2) and the N+ contact area (3).

2. The SiC MOSFET device integrated punch-through NPN diode of claim 1, wherein, The metal layer (1), the P+ contact area (2) and the N+ contact area (3) form the source of the MOSFET device through ohmic contact.

3. The SiC MOSFET device integrated punch-through NPN diode of claim 1, wherein, The N-type substrate (10) and the metal electrode connected thereto form the drain of the MOSFET device through ohmic contact.

4. The SiC MOSFET device integrated punch-through NPN diode of claim 1, wherein, The N+ contact area (3), the P-channel area (5), the P-type shielding area (7) and the current diffusion layer (8) above the P-channel area (5) jointly form a semiconductor area, and a gate oxide layer (11) is arranged between the polysilicon area (6) and the semiconductor area.

5. The SiC MOSFET device integrated punch-through NPN diode of claim 4, wherein, The polysilicon area (6) and the gate oxide layer (11) form the gate of the MOSFET device.

6. The SiC MOSFET device integrated punch-through NPN diode of claim 1, wherein, The semiconductor material in the MOSFET device is SiC material.

7. The SiC MOSFET device integrated punch-through NPN diode of claim 1, wherein, The metal layer (1) is an aluminum layer.

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