Integrated circuit with PUF
By introducing parallel PUF units into integrated circuits and utilizing the offset characteristics of operational amplifiers to generate unique chip IDs, the anti-counterfeiting problem of integrated circuits is solved, and good temperature stability and security are achieved.
Patent Information
- Application Number
- CN202511238251.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-01
- Publication Date
- 2025-12-16
AI Technical Summary
Existing integrated circuits lack effective anti-counterfeiting features, making it difficult to ensure the safety and legality of products.
At least four parallel PUF units are set inside the integrated circuit. Each unit consists of an operational amplifier and an inverter. The operational amplifier amplifies the offset voltage through a positive feedback circuit and generates a stable digital signal through rectification by the inverter. The offset characteristics of the operational amplifier are used to generate a unique chip ID.
It achieves excellent temperature stability and anti-counterfeiting functions, ensuring the safety and legality of integrated circuits and effectively preventing counterfeiting and piracy.
Smart Images
Figure CN121145271A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of microelectronics technology. Background Technology
[0003] PUF, short for Physical Unclonable Functions, is a hardware security technology. PUF utilizes the inherent properties of silicon-based semiconductors to randomly extract unclonable physical characteristics. These characteristics, similar to biometric fingerprints, serve as unique identifiers for each chip. During the manufacturing process of silicon-based chips, variations in semiconductor manufacturing processes result in differences in inherent properties such as path delay and transistor threshold voltage, making each physical chip unique after fabrication. PUF leverages these naturally occurring inherent differences to generate a unique identifier, or "digital fingerprint," for each chip.
[0004] Operational amplifiers typically consist of multiple transistors. Manufacturing limitations mean that the characteristics of these transistors, such as threshold voltage and current amplification, cannot be exactly the same. Even under the same bias conditions, these differences can lead to slight variations in the collector current or emitter voltage of the transistors, resulting in offset voltage at the output. Secondly, the resistor network inside the operational amplifier is used to set parameters such as gain. In actual production, the resistance values of these resistors will have some deviation, which can also disrupt the circuit balance and generate offset voltage. Furthermore, if the circuit layout is not perfectly symmetrical, differences in signal paths and parasitic parameters can occur, all of which can introduce offset voltage.
[0005] Positive feedback refers to the process of sending part or all of the output signal of a system (or component) back to the system's input through a certain circuit or device. This input signal is then added to the original input signal, amplifying its effect and further increasing the system's output. The result is that the system's changes become increasingly larger, deviating further and further from its equilibrium state. Summary of the Invention
[0006] The technical problem to be solved by the present invention is to provide an integrated circuit with PUF that has reliable anti-counterfeiting function.
[0007] The technical solution adopted by the present invention to solve the aforementioned technical problem is an integrated circuit with a PUF (Power Activated Function). The integrated circuit has at least four parallel PUF units inside. Each PUF unit includes an operational amplifier and an inverter. The positive input terminal and positive output terminal of the operational amplifier are connected, and the negative input terminal and negative output terminal are connected. The positive output terminal or the negative output terminal is connected to the input terminal of the inverter. The output terminal of the inverter serves as the output terminal of the PUF unit.
[0008] Furthermore, the operational amplifier consists of two differential amplifier stages. The operational amplifier includes a first differential stage... A first differential amplifier and a second differential amplifier are connected. The positive input terminal of the first differential amplifier is connected to the positive output terminal of the second differential amplifier, and the negative input terminal of the first differential amplifier is connected to the negative output terminal of the second differential amplifier. The positive input terminal of the second differential amplifier is connected to the positive output terminal of the first differential amplifier, and the negative input terminal of the second differential amplifier is connected to the negative output terminal of the first differential amplifier. The positive output terminal of the first differential amplifier is connected to the input terminal of the inverter.
[0009] The beneficial effects of this invention are that it has good temperature stability, which can effectively prevent integrated circuits from being counterfeited or pirated, and ensure the safety and legality of the product. Attached Figure Description
[0010] Figure 1 This is a schematic diagram of the PUF unit structure of the present invention.
[0011] Figure 2 This is a schematic diagram of the PUF circuit of the present invention.
[0012] Figure 3 This is a schematic diagram of the workflow of the present invention.
[0013] Figure 4 This is a structural diagram of the PUF unit according to an embodiment of the present invention.
[0014] Figure 5 This is a graph showing the statistical results of the Monte Carlo simulation of this invention.
[0015] Figure 6 It is a graph showing how the output changes with temperature when the output is high.
[0016] Figure 7 The output is a curve showing how low the temperature changes. Detailed Implementation
[0018] This invention provides a PUF technology based on the offset characteristics of operational amplifiers, characterized by good randomness (the probability of logic 0 and logic 1 is approximately 50%), good temperature stability, and unchanged output logic value when operating from -55°C to +125°C.
[0019] The working principle is as follows: the offset voltage of the operational amplifier is amplified through a positive feedback circuit, and then rectified by an inverter to obtain a stable digital signal level. If the offset result is that the voltage at the non-inverting input is greater than that at the inverting input, then a high level will be obtained after positive feedback and rectification by an inverter, which is recorded as 1; otherwise, a low level will be obtained, which is recorded as 0.
[0020] Figure 1 and Figure 2 The PUF circuit structure is shown.
[0021] The integrated circuit with PUF provided by this invention has at least four parallel PUF units disposed inside the integrated circuit, such as... Figure 2 As shown. The PUF unit includes an operational amplifier and an inverter. The positive input and positive output of the operational amplifier are connected, and the negative input and negative output are connected. Either the positive or negative output is connected to the input of the inverter. The output of the inverter serves as the output of the PUF unit, as shown below. Figure 1 .
[0022] See Figure 4 The operational amplifier consists of two differential amplifier stages. The operational amplifier includes the first... A first differential amplifier and a second differential amplifier are connected. The positive input terminal of the first differential amplifier is connected to the positive output terminal of the second differential amplifier, and the negative input terminal of the first differential amplifier is connected to the negative output terminal of the second differential amplifier. The positive input terminal of the second differential amplifier is connected to the positive output terminal of the first differential amplifier, and the negative input terminal of the second differential amplifier is connected to the negative output terminal of the first differential amplifier. The positive output terminal of the first differential amplifier is connected to the input terminal of an inverter.
[0023] See Figure 3 The workflow based on this invention includes the following steps: 1. Before chip fabrication, an anti-counterfeiting test area is added to the circuit. This involves creating multiple operational amplifier (PUF) test structures specifically for anti-counterfeiting authentication. The PUF circuit is a differential symmetrical structure, connecting the non-inverting input and output of the operational amplifier, and the negative input and output, to form positive feedback, amplifying the input offset to the output. An inverter is connected to the non-inverting output. If the offset voltage causes the non-inverting input voltage to be greater than the inverting input voltage, the inverter outputs 1; otherwise, it outputs 0. The final test result of the inverter is used as a single-bit ID.
[0024] 2. After the chip is generated, the test data in the test area is read before the product is released. Taking 16-bit as an example, the output results of 16 operational amplifiers are read and digitized (taking 3.3V LVCMOS as an example, output above 2.5V is recorded as 1, output below 1.0V is recorded as 0, and the rest are recorded as X), and finally a 16-bit code is obtained.
[0025] 3. Upload the above code as the chip ID to the server's database.
[0026] 4. After purchasing the chip, users can send a test request to obtain the 16-bit encoded result of the chip test area. By comparing the result with the information in the database, the authenticity of the chip can be verified.
[0027] 5. If the test results match the information entered in the database, the chip is a genuine product; otherwise, it is a counterfeit or substandard product.
[0028] Monte Carlo simulation using the circuit simulation tool Virtuoso was employed to simulate process-induced deviations, and statistical results were obtained. The simulation results are as follows: Figure 5 As shown, the probability of logic 0 and logic 1 is approximately 50%, indicating that this PUF circuit exhibits good randomness.
[0029] Chip IDs obtained from testing the PUF circuit under different environments were compared with data in the database. Under Monte Carlo simulation conditions with varying process angles, the output results were tested at different temperatures (-60°C to +130°C). The temperature variation of the high-level output is shown below. Figure 6 As shown, the output low level changes with temperature as follows: Figure 7 As shown in the figure. The results indicate that the temperature stability of this PUF circuit is highly reliable.
Claims
1. An integrated circuit with a PUF, characterized in that, The integrated circuit has at least four parallel PUF units. Each PUF unit includes an operational amplifier and an inverter. The positive input and positive output of the operational amplifier are connected, and the negative input and negative output are connected. The positive or negative output is connected to the input of the inverter. The output of the inverter serves as the output of the PUF unit.
2. The integrated circuit with PUF as described in claim 1, characterized in that, The operational amplifier consists of two differential amplifier stages.
3. The integrated circuit with PUF as described in claim 2, characterized in that, The operational amplifier includes a first differential amplifier and a second differential amplifier. The positive input terminal of the first differential amplifier is connected to the positive output terminal of the second differential amplifier. The negative input terminal of the first differential amplifier is connected to the negative output terminal of the second differential amplifier. The positive input terminal of the second differential amplifier is connected to the positive output terminal of the first differential amplifier. The negative input terminal of the second differential amplifier is connected to the negative output terminal of the first differential amplifier. The positive output terminal of the first differential amplifier is connected to the input terminal of the inverter.