Register header file generation method and device, electronic equipment and storage medium

Abstract

The application provides a register header file generation method and device, electronic equipment and a storage medium, relates to the chip design verification technical field, and comprises the following steps: obtaining a target configuration file; based on version information and a storage path in the target configuration file, dynamically obtaining a register description file of a specified version from a version control server; parsing the register description file and extracting register definition information of at least one functional module; and based on instantiation configuration information of at least one functional module in a chip to be developed and the register definition information of the at least one functional module, generating a register header file of the chip to be developed. The method and device provided by the application accurately manage the version information and storage path of the register description file of each functional module in the chip; can realize batch updating of the register header file to the required version, and realize fast and efficient generation of the register header file of the required version.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip design verification technical field, and particularly relates to a register header file generation method and device, electronic equipment and storage medium. BACKGROUND

[0002] In the design process of a large-scale system on chip (SoC), a large number of memory-mapped input / output (MMIO) definitions of sub-function modules are updated with the rapid iteration of register transfer level (RTL) code. As a bridge between software and hardware, the register header file defines register addresses and bit fields, and provides a structured access method, which has an important influence on software programming.

[0003] According to the related art, the register header file is generated according to a static file, and the register header file version management and generation speed cannot adapt to the requirement of rapid iteration of the register transfer level code.

[0004] Therefore, how to quickly and efficiently generate the required version of the register header file and improve the development efficiency of the chip-related software has become a technical problem to be solved in the industry. SUMMARY

[0005] The present application provides a register header file generation method and device, electronic equipment and storage medium, which are used to solve the technical problem of how to quickly and efficiently generate the required version of the register header file and improve the development efficiency of the chip-related software.

[0006] The present application provides a register header file generation method, which comprises the following steps:

[0007] Obtaining a target configuration file, wherein the target configuration file is used to store version information of a register description file of at least one function module and a storage path of the register description file corresponding to the version information in a version control server;

[0008] Based on the version information and the storage path in the target configuration file, a register description file of a specified version is dynamically obtained from the version control server;

[0009] Parsing the register description file and extracting register definition information of the at least one function module;

[0010] Based on instantiation configuration information of the at least one function module in a chip to be developed and the register definition information of the at least one function module, a register header file of the chip to be developed is generated.

[0011] In some embodiments, the file format of the register description file comprises at least one of:

[0012] a machine-readable standardized format;

[0013] a specific tool format;

[0014] a software development header file format;

[0015] a general data exchange format.

[0016] In some embodiments, the parsing of the register description file comprises:

[0017] parsing the register description file when the file format of the register description file is a preset format;

[0018] when the file format of the register description file is a non-preset format, converting the file format of the register description file into a preset format and parsing the register description file after the format conversion.

[0019] In some embodiments, the register header file comprises at least one of:

[0020] a base address definition header file;

[0021] a bit definition header file;

[0022] a command packet definition header file;

[0023] a hardware design quality data definition header file;

[0024] a register field definition header file.

[0025] In some embodiments, the generating of the register header file of the chip to be developed comprises:

[0026] generating the register header file in at least one programming language.

[0027] In some embodiments, the method further comprises:

[0028] performing a rule check on the register description file;

[0029] and / or, comparing the current version of the register description file with the previous version of the register description file, and generating register change information based on the comparison result.

[0030] The present application provides a register header file generation device, comprising:

[0031] The configuration file acquisition module is configured to acquire a target configuration file, wherein the target configuration file is used to store version information of a register description file of at least one function module and a storage path of the register description file corresponding to the version information in a version control server.

[0032] The register description file acquisition module is configured to dynamically acquire a register description file of a specified version from the version control server based on the version information and the storage path in the target configuration file.

[0033] The parsing module is configured to parse the register description file and extract register definition information of the at least one function module.

[0034] The generating module is configured to generate a register header file of the chip to be developed based on instantiation configuration information of the at least one function module in the chip to be developed and the register definition information of the at least one function module.

[0035] The present application provides an electronic device, comprising a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements the register header file generation method when executing the computer program.

[0036] The present application provides a non-transitory computer readable storage medium, which stores a computer program, wherein the computer program is executed by a processor to implement the register header file generation method.

[0037] The present application provides a computer program product comprising a computer program, wherein the computer program is executed by a processor to implement the register header file generation method.

[0038] The register header file generation method, device, electronic device and storage medium provided by the present application can accurately manage the version information and storage path of the register description file of each function module in the chip through the target configuration file, dynamically acquire the register description file of the specified version from the version control server based on the version information and the storage path in the target configuration file, and generate the register header file of the chip to be developed after parsing, so that the register header file can be updated to the required version in batches, the register header file of the required version can be quickly and efficiently generated, the synchronization efficiency and accuracy of the software and hardware interface in large-scale chip development are improved, the integration errors caused by manual version management are reduced, the development efficiency of chip-related software is improved, and the chip development of team collaboration is supported. BRIEF DESCRIPTION OF DRAWINGS

[0039] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the application.

[0040] In order to more clearly illustrate the technical solutions in the application or the prior art, the accompanying drawings needed to be used in the embodiments or prior art description will be briefly introduced. Obviously, the accompanying drawings in the following description are some embodiments of the application, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0041] Figure 1 is one of the flowcharts of the register header file generation method provided by the application.

[0042] Figure 2 is the second flowchart of the register header file generation method provided by the application.

[0043] Figure 3 is the structural schematic diagram of the register header file generation device provided by the application.

[0044] Figure 4 is the structural schematic diagram of the electronic device provided by the application. DETAILED DESCRIPTION

[0045] In order to make the person skilled in the art better understand the application scheme, the technical solutions in the embodiments of the application will be clearly and completely described below in conjunction with the drawings in the embodiments of the application. Obviously, the described embodiments are only some of the embodiments of the application, not all. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without any creative effort should be within the scope of protection of the application.

[0046] It should be noted that the terms "first", "second" and the like in the application are used to distinguish similar objects, and do not necessarily indicate specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the application described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units or modules does not have to be limited to those steps or units or modules clearly listed, but can include other steps or units or modules not clearly listed or inherent to these processes, methods, products or devices.

[0047] The related art generates a register header file according to a local fixed file (static file), and the register header file version management and generation speed cannot adapt to the demand of rapid iteration of register transfer level code, which affects the development efficiency of chip related software.

[0048] In order to solve the problems in the related art, Figure 1 is one of the flowcharts of the register header file generation method provided in the present application, as shown in the figure, the method comprises steps 110, 120, 130 and 140. Figure 1

[0049] Step 110, obtaining a target configuration file, the target configuration file is used to store version information of at least one register description file of a functional module and a storage path of the register description file corresponding to the version information in a version control server.

[0050] Specifically, the execution subject of the register header file generation method provided in the embodiments of the present application is a register header file generation device or system. The device can be implemented by software, for example, a register header file generation program running in a computer system, or by hardware, for example, a computer or a server executing the register header file generation method.

[0051] The target configuration file is used to centrally manage register configuration information of all or part of functional modules required to constitute a chip to be developed, and can include version information of register description files of each functional module and a storage path of the register description file corresponding to each version information in a version control server.

[0052] The functional module refers to an Intellectual Property Core (IP core) having an independent function in the chip to be developed, for example, including a direct memory access controller, a timer, an artificial intelligence accelerator, etc. In a chip to be developed, there can be tens or even hundreds of functional modules.

[0053] The register description file refers to a file used to define and describe all MMIO registers inside the functional module. The file contains key information such as the name of the register, the offset relative to the module base address, the name of each field in the register, the bit width, the position, the access attribute (such as read-write, read-only, write-only) and the reset value. For example, the register description file can be a register table.

[0054] Since the RTL design of the functional module is iteratively updated, the register description file is also changed. The version information is an identifier used to accurately identify which specific state the register description file is in, for example, which can be represented by a specific tag.

[0055] The version control server is used to centrally manage the code, design files and other engineering materials of the chip to be developed, for example, a Perforce server.

[0056] ​The storage path is used to specify the storage location of the register description file of the specific version on the version control server.

[0057] By reading the target configuration file, it can be determined which functional modules are needed for designing the current chip to be developed, and where to obtain the register description file of the version exactly correct for these modules.

[0058] Step 120, based on the version information and the storage path in the target configuration file, dynamically obtaining the register description file of the specified version from the version control server.

[0059] Specifically, after obtaining the target configuration file, for each functional module, the version control server can be accessed at any time according to the version information and the storage path in the target configuration file, and the register description file of the specified version is accurately downloaded (or synchronized) from the server to the local.

[0060] Unlike the related art that requires developers to manually obtain the register description file, the embodiments of the present application program the version selection and automate the action by directly interacting with the version control server, thereby fundamentally ensuring the accuracy of the register description file.

[0061] Step 130, parsing the register description file to extract register definition information of at least one functional module.

[0062] Specifically, after obtaining all the required register description files of the correct version, these files can be parsed to extract the register definition information of each functional module.

[0063] The register definition information includes but is not limited to register name, register offset address, name of each field in the register, access attribute of the field, etc.

[0064] Step 140, generating a register header file of the chip to be developed based on the instantiation configuration information of at least one functional module in the chip to be developed and the register definition information of at least one functional module.

[0065] Specifically, the instantiation configuration information of the functional module refers to a data set for describing the instantiation parameters and integration attributes of one or more reusable functional modules in the specific system-level environment of the chip to be developed, for defining how a general and independent functional module is specifically and uniquely instantiated and integrated into the final chip design, which can include base address configuration information, instance name, identifier, and system-level parameter value, etc.

[0066] In one specific embodiment, the instantiation configuration information of at least one functional module in the chip to be developed is base address configuration information, which is used to assign different base addresses to each functional module.

[0067] The base address of each functional module instance is added to the offset address of each register inside the functional module, so as to calculate the absolute address of each register in the entire chip memory space. Then, the register name, field name, absolute address and other information are formatted according to the syntax rules of a specific programming language, and written into one or more text files to form the final register header file.

[0068] The register header file generation method provided by the embodiments of the present application precisely manages the version information and storage path of the register description file of each functional module in the chip through the target configuration file; the register description file of a specified version is dynamically obtained from the version control server through the version information and storage path in the target configuration file, and the register header file of the chip to be developed is generated after parsing, which can realize batch updating of the register header file to the required version, realize fast and efficient generation of the register header file of the required version, improve the synchronization efficiency and accuracy of the software and hardware interface in large-scale chip development, reduce the integration errors introduced by manual version management, improve the development efficiency of chip-related software, and support team collaborative chip development.

[0069] It should be noted that each embodiment of the present application can be freely combined, the order can be changed or executed alone, and does not need to rely on or depend on a fixed execution order.

[0070] In some embodiments, the file format of the register description file includes at least one of the following:

[0071] a machine-readable standardized format;

[0072] a specific tool format;

[0073] a software development header file format;

[0074] a general data exchange format.

[0075] Specifically, the machine-readable standardized format can refer to a format formulated by an industry standard organization for exchanging IP core design data between different tools and companies. For example, it can be an Intellectual Property eXchange and API Configuration (IP-XACT) format. IP-XACT uses eXtensible Markup Language (XML) to describe various information of IP cores, including detailed memory mapping and register definition.

[0076] A specific tool format refers to a proprietary format defined and used by a specific commercial Electronic Design Automation (EDA) tool or in-house tool.

[0077] A software development header file format refers to a header file that can be used by programming software, such as a C language header file.

[0078] A general data exchange format refers to a general format that is not specific to hardware design but is widely used for structured data representation and exchange, such as a JSON (JavaScript Object Notation) format or a CSV (Comma-Separated Values) format.

[0079] The register header file generation method provided by the embodiments of the present application supports a plurality of register description file formats including industry standards, specific tools, software codes, and general data formats, has high flexibility and compatibility, and is suitable for various chip development work.

[0080] In some embodiments, the register description file is parsed, including:

[0081] In a case where the file format of the register description file is a preset format, the register description file is parsed.

[0082] In a case where the file format of the register description file is a non-preset format, the file format of the register description file is converted into a preset format, and the register description file after the format conversion is parsed.

[0083] Specifically, the preset format can be a data format selected according to actual needs, used for uniform processing of each register description file. For example, the preset format can be set as a JSON format. This format has a clear structure, is easy to parse by a machine, and has mature library support in various programming languages.

[0084] Before parsing the register description file, the file format of the register description file can be identified first. If the file format of the register description file is a preset format, a core parser matched with the preset format can be directly called to process the file. For example, if the preset format is a JSON format, the core parser will load the file content into the memory by using a JSON library to form a tree-shaped data object, then traverse the object to extract the definition information of all registers and fields.

[0085] If the register description file is in a non-preset format, one or more format converters need to be invoked to convert the specific non-preset format into a unified preset format. For example, when the input file is in IP-XACT format, the system will call the IP-XACT converter. This converter reads the XML file, parses its nodes and attributes according to relevant standards, and then reorganizes the extracted register definition information according to the structure of a preset format (such as JSON), generating a JSON file with equivalent content. After the format conversion is complete, regardless of the original input file's non-preset format, its output becomes a unified file conforming to the preset format. The system can directly call the core parser that matches the preset format to process the converted file.

[0086] The register header file generation method provided in this application introduces a preset format and a format conversion mechanism to parse register description files of different formats, ensuring the uniformity of subsequent processing and improving the efficiency of register header file generation.

[0087] In some embodiments, the register header file includes at least one of the following:

[0088] Base address definition header file;

[0089] Bit definition header file;

[0090] Command package definition header file;

[0091] Hardware design quality data definition header file;

[0092] Register field definition header file.

[0093] Specifically, the Base Address Definition Header File is used to define the starting address, or base address, of each instantiated functional module (IP core) in the chip's unified memory space. This file can be generated based on the instantiation configuration information of at least one functional module in the chip to be developed, and is essentially the chip's system memory mapping plan.

[0094] The Register / Field Definition Header File is primarily used by low-level drivers to directly read and write hardware registers and their internal bit fields. The generation of this file combines the base address definition with register definition information parsed from the register description file (such as register offset address, field width, and position).

[0095] The bit definition header file is a supplement to the register field definition header file, and provides meaningful names for some fields with specific enumeration meanings. The file is generated according to the description of legal values of the fields in the register description file.

[0096] For some functional modules (such as artificial intelligence accelerators) that receive complex commands through a first-in-first-out queue or shared memory, the command packet definition header file is used to define the data structure of the commands. The file is generated according to the special definition of the command packet structure in the register description file.

[0097] The hardware component quality data definition header file is used to record metadata about the quality of the hardware design itself. The file can be generated by running additional rule checking logic during the parsing of the register description file. For example, checking whether there is address overlap, whether the naming is in accordance with the specification, whether the access attribute is reasonable (such as a write-only register should not have a reset value), and the like.

[0098] The register header file generation method provided in the embodiments of the present application supports the generation of various types of header files for different purposes, and can provide accurate and customized data support for different links such as software driver development, hardware function verification, system-level debugging, and design quality assurance.

[0099] In some embodiments, the register header file of the chip to be developed is generated, including:

[0100] The register header file in at least one programming language is generated.

[0101] Specifically, the method provided in the embodiments of the present application decouples the extraction of register definition information and the generation of the register header file. After the register definition information is extracted, the register definition information (including the name, address, bit field, attribute, and the like) of all functional modules is extracted and organized into a structured intermediate data structure that is independent of the specific programming language. The data structure can be an object tree in memory, a dictionary list, or any other form that is convenient for program processing.

[0102] When generating the final header file, a template-based generation method can be used, the above-mentioned intermediate data structure is taken as data, and a syntax template for different programming languages that is written in advance is taken as a format. By filling the data into the corresponding template, a header file that conforms to the syntax specification of a specific language can be generated.

[0103] For example, a C / C++ language header file can be generated, which serves the development of embedded firmware and underlying drivers; a SystemVerilog language header file can also be generated, which mainly serves the hardware design verification team, especially when using a high-level verification platform such as Universal Verification Methodology (UVM).

[0104] The programming language can be set as needed, for example, it can also include Python and the like.

[0105] The method provided by the embodiments of the present application can be configured to generate a header file of only one specified programming language, or to generate header files of multiple programming languages at the same time and output them to the respective specified directories to meet different needs.

[0106] The register header file generation method provided by the embodiments of the present application supports generating header files of multiple programming languages, greatly improving the collaborative development efficiency of the entire chip.

[0107] In some embodiments, the method further comprises:

[0108] performing rule checking on the register description file;

[0109] and / or, comparing the current version of the register description file with the previous version of the register description file, and generating register change information based on the comparison result.

[0110] Specifically, before parsing the register description file, the design rules can be defined to perform rule checking on the register description file.

[0111] The rule checking can include address space checking, register attribute logic checking, naming specification checking, etc. The address space checking includes address overlap / conflict checking, address alignment checking, and address space range, etc. The register attribute logic checking includes access strategy and reset value conflict, reserved bit access, etc.

[0112] The result of the rule checking can have multiple output forms: it can be directly printed to the console when the automated script is executed, or it can be formatted and written to a log file.

[0113] When the hardware design is iterated, the current version of the register description file can also be compared with the previous version of the register description file to determine which changes have occurred in the register definition, so as to evaluate the impact on the existing program and the modification workload.

[0114] The system not only acquires the register description file of the current version specified in the target configuration file, but also acquires a previous version of the file for comparison according to preset logic. For example, the previous version can be the previous committed version of the file on the version control server, or the last published stable version. The system performs a parsing step on the two versions of the file respectively, to obtain two independent structured intermediate data objects. Then, the two data objects are compared at the semantic level to generate register change information. The register change information can include information such as addition, deletion, and modification of registers.

[0115] The register header file generation method provided in the embodiments of the present application can actively find and eliminate potential integration errors by adding rule checking and change comparison functions, thereby greatly reducing the communication cost and integration risk caused by interface definition changes.

[0116] Figure 2 FIG. 2 is a flowchart of a register header file generation method provided in the embodiments of the present application, as shown in FIG. 2, the method comprises the following steps. Figure 2

[0117] Step 210, reading a target configuration file (configure). The target configuration file can be in JSON format.

[0118] Step 220, dynamically acquiring a register description file of a specified version from a version control server (Perforce) according to version information and a storage path in the target configuration file.

[0119] Step 230, identifying the file format of the register description file. If it is a preset format, directly parsing the register description file to extract register definition information; if it is a non-preset format, converting the file format of the register description file into a preset format and parsing the register description file after format conversion to extract register definition information.

[0120] Step 240, generating multiple types of register header files according to the configuration information of each functional module (IP core) in the chip to be developed and the register definition information of each functional module, including base address (baseaddr) definition header file, bit definition header file, command packet definition header file, hardware design quality data (HCQD) definition header file, and register / field definition header file. The register header file can support multiple programming languages, such as C language or SystemVerilog language.

[0121] ​The register header file generation method provided in the embodiments of the present application stores the versions (the register tables of various IP cores) of all functional modules and the storage paths in the server in a target configuration file, then retrieves the corresponding versions one by one, and generates header files supported by multiple programming languages after information extraction. The above process can be automatically processed by writing a Python script to generate C language header files or SystemVerilog language header files.

[0122] The device provided in the embodiments of the present application is described below, and the device described below can be correspondingly referred to the method described above.

[0123] Figure 3 FIG. 1 is a structural schematic diagram of a register header file generation device provided in the present application, as shown in the figure, the device comprises: Figure 3

[0124] The configuration file acquisition module 310 is configured to acquire a target configuration file, and the target configuration file is configured to store version information of a register description file of at least one functional module and a storage path of the register description file corresponding to the version information in a version control server;

[0125] The register description file acquisition module 320 is configured to dynamically acquire the register description file of a specified version from the version control server based on the version information and the storage path in the target configuration file;

[0126] The analysis module 330 is configured to analyze the register description file and extract register definition information of the at least one functional module;

[0127] The generation module 340 is configured to generate a register header file of the chip to be developed based on instantiation configuration information of the at least one functional module in the chip to be developed and the register definition information of the at least one functional module.

[0128] The register header file generation device provided in the embodiments of the present application accurately manages the version information and the storage path of the register description file of each functional module in the chip through the target configuration file. The register description file of the specified version is dynamically acquired from the version control server based on the version information and the storage path in the target configuration file, and the register header file of the chip to be developed is generated after analysis, which can realize batch updating of the register header file to the required version, realize rapid and efficient generation of the register header file of the required version, improve the synchronization efficiency and accuracy of the software and hardware interface in large-scale chip development, reduce the integration errors introduced by manual version management, improve the development efficiency of chip-related software, and support team collaborative chip development.

[0129] Figure 4 FIG. 1 is a structural schematic diagram of an electronic device provided in the present application, as shown in the figure, the device comprises:​Figure 4 As shown, the electronic device can include a processor 410, a communications interface 420, a memory 430, and a communications bus 440, wherein the processor 410, the communications interface 420, and the memory 430 communicate with each other through the communications bus 440. The processor 410 can invoke a logical command in the memory 430 to execute the method described in the above embodiments, for example:

[0130] Obtain a target configuration file, the target configuration file is used to store version information of a register description file of at least one function module and a storage path of the register description file corresponding to the version information in a version control server; based on the version information and the storage path in the target configuration file, dynamically obtain the register description file of a specified version from the version control server; parse the register description file to extract register definition information of the at least one function module; and based on instantiation configuration information of the at least one function module in the chip to be developed and the register definition information of the at least one function module, generate a register header file of the chip to be developed.

[0131] In addition, the logical command in the memory described above can be implemented in the form of a software function unit and sold or used as an independent product, and can be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the present application essentially or the part that contributes to the prior art or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, including a plurality of commands to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, and various media that can store program codes.

[0132] The processor in the electronic device provided by the embodiments of the present application can invoke the logical instructions in the memory to implement the above method, and the specific implementation manners are consistent with the foregoing method implementation manners, and the same beneficial effects can be achieved, which will not be described here.

[0133] The embodiments of the present application also provide a computer-readable storage medium, which stores a computer program, and the computer program is executed by a processor to implement the method provided by each of the above embodiments.

[0134] The specific implementation is consistent with the foregoing method implementation, and the same beneficial effects can be achieved, which will not be repeated here.

[0135] The embodiment of the application provides a computer program product, comprising a computer program, and the computer program is executed by a processor to realize the method.

[0136] The device embodiments described above are only schematic, wherein the units described as separated components can or can not be physically separated, and the components displayed as units can or can not be physical units, that is, they can be located in one place, or distributed on multiple network units. Part or all of the modules can be selected according to actual needs to achieve the purpose of the embodiment scheme. Those skilled in the art can understand and implement without creative labor.

[0137] Through the description of the foregoing embodiments, those skilled in the art can clearly understand that each embodiment can be realized by means of software and a necessary universal hardware platform, and of course, can also be realized by hardware. Based on such understanding, the foregoing technical solutions can be embodied in the form of a software product in essence or in the form of a contribution to the prior art. The computer software product can be stored in a computer readable storage medium, such as a ROM / RAM, a magnetic disk, an optical disk, and the like, and includes a plurality of instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute the methods described in each embodiment or some parts of the embodiments.

[0138] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the application, and not to limit them; although the application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement to some technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the application.

Claims

1. A method for generating a register header file, characterized in that, include: Obtain a target configuration file, which stores version information of register description files for at least one functional module and the storage path of the register description files corresponding to the version information in a version control server; the version information is an identifier that identifies the status of the register description file; the version control server is a central server that stores and manages the register description files. Based on the version information and storage path in the target configuration file, the register description file of the specified version is dynamically obtained from the version control server; Parse the register description file to extract the register definition information of the at least one functional module; Based on the instantiation configuration information of at least one functional module in the chip to be developed, and the register definition information of the at least one functional module, a register header file of the chip to be developed is generated.

2. The register header file generation method according to claim 1, characterized in that, The file format of the register description file includes at least one of the following: Machine-readable standardized format; Software development header file format; Universal data exchange format.

3. The register header file generation method according to claim 1, characterized in that, The parsing of the register description file includes: If the register description file is in a preset format, the register description file is parsed. If the register description file is not in a preset format, the file format of the register description file is converted to the preset format and the converted register description file is parsed.

4. The register header file generation method according to claim 1, characterized in that, The register header file includes at least one of the following: Base address definition header file; Bit definition header file; Command package definition header file; Hardware design quality data definition header file; Register field definition header file.

5. The register header file generation method according to claim 1, characterized in that, The process of generating the register header file for the chip to be developed includes: Generate register header files for at least one programming language.

6. The register header file generation method according to claim 1, characterized in that, The method further includes: Perform rule checks on the register description file; And / or, compare the current version of the register description file with the previous version of the register description file, and generate register change information based on the comparison results.

7. A register header file generation apparatus, characterized in that, include: The configuration file acquisition module is used to acquire a target configuration file, which stores version information of register description files for at least one functional module and the storage path of the register description file corresponding to the version information in the version control server; the version information is an identifier that identifies the status of the register description file; the version control server is a central server that stores and manages the register description files. The register description file acquisition module is used to dynamically acquire a register description file of a specified version from the version control server based on the version information and storage path in the target configuration file; A parsing module is used to parse the register description file and extract the register definition information of the at least one functional module; A generation module is used to generate a register header file for the chip under development based on the instantiation configuration information of at least one functional module in the chip under development and the register definition information of the at least one functional module.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the register header file generation method according to any one of claims 1 to 6.

9. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the register header file generation method according to any one of claims 1 to 6.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the register header file generation method as described in any one of claims 1 to 6.

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