Method and system for parsing multi-dimensional data

Abstract

Methods and systems for parsing multi-dimensional data. A computer-implemented method of parsing multi-dimensional data to identify a work package to be processed is provided in which the multi-dimensional data is mapped into one-dimensional data using a Z-ranking function. The method comprises the following steps: obtaining dimensions of the multi-dimensional data; and obtaining information identifying an active area of the multi-dimensional data, wherein the active area identifies a work package. The method includes determining at least a portion of a sequence within the one-dimensional data corresponding to a location within the multi-dimensional data located in the active area by: determining, from the Z-ranking function, whether a location defined by a first value of the one-dimensional data is located within the active area; and in response to determining that the location defined by the first value is not within the active region: calculating an overflow value that, when added to the first value, flips a least significant bit that is 1 in a binary representation of the first value to 0.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority from UK patent application GB2408595.3 filed on 14 June 2024, which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0003] The present disclosure relates to processing multi-dimensional data mapped onto one dimension in a computing environment, and more particularly to determining an effective sequence of one-dimensional data mapped from multi-dimensional data. BACKGROUND

[0004] In graphics processing systems, particularly graphics processing systems that perform rasterization and ray tracing, scene data for rendering an image of a 2D or 3D scene is stored in memory. The scene data is typically represented by tiles representing 2D regions (e.g. a grid). When processing the scene data, the grid is scanned by a portion of the graphics processing system and work items corresponding to cells of the grid are sent to relevant portions of the graphics processing system for scheduling and / or further processing.

[0005] One method of scanning the scene data using a grid representation is to scan across each row from left to right, one row at a time, until all rows of the grid have been scanned. This order is referred to as a ‘stride’ order or a ‘raster scan’ order. However, the amount of scene data stored is often very large and co-located regions of the scene data (e.g. data within a rectangular tile) are frequently accessed. Therefore, scanning in a stride order can not be the most efficient way of obtaining scene data stored in a tiled region. Furthermore, the scene data must be stored in memory lines (such as a cache). Therefore, if rows of the scene data are stored in corresponding lines of (approximately) cache memory, then accessing a rectangular data tile using a stride order that scans over rows rather than over a rectangular region can become inefficient. In particular, scanning in a stride order increases the probability of cache misses or page faults.

[0006] Accordingly, in graphics processing systems, scene data can be stored (i.e. in data tiles) in a format that better reflects the spatial location of scene data that is frequently accessed. One such order is the Z-order, also known as the Morton order, which maps multi-dimensional scene data into a one-dimensional sequence. Z-order functions and other many-to-one mapping functions are useful because they increase the spatial locality of references to scene data and therefore allow cache lines to represent rectangular regions of scene data. Therefore, this ordering reduces the probability of cache misses, which can introduce inefficiencies in the process.

[0007] Accordingly, the Z-order function provides advantages over the standard raster scan order in graphics processing systems. However, using Z-order can also result in other inefficiencies that depend on the size of the grid. Z-order functions and other many-to-one dimensional mapping functions are characterized in that they can be implemented using a single counter value. Accordingly, the binary representation of a single number can be used to encode both the x and y coordinates representing a 2D grid location. Accordingly, the total representable dimension of a grid region (sometimes referred to as the 'launch size' of the grid) is typically a power of two.

[0008] Accordingly, problems arise when the portion of the grid containing work items or work packets to be processed is not an exact power of two. Using the Z-ordering function when the active region of the grid is not an exact power of two results in the generation of invalid coordinates in the grid. This can result in a significant number of wasted cycles corresponding to the invalid grid coordinates being generated. Unlike using the step order, it is not possible to simply determine the next valid grid value of the Z-order sequence. Accordingly, using Z-order can introduce unacceptable inefficiencies in graphics processing algorithms or systems.

[0009] The present disclosure is directed, at least in part, to addressing issues associated with using Z-order to represent multi-dimensional scene data. SUMMARY

[0010] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

[0011] A computer-implemented method of parsing multi-dimensional data to identify work packets to be processed, wherein the multi-dimensional data is mapped into one-dimensional data using a Z-ordering function, the method comprising:

[0012] obtaining a dimension of the multi-dimensional data;

[0013] obtaining information identifying an active region of the multi-dimensional data, the active region identifying work packets;

[0014] determining at least a portion of a sequence within the one-dimensional data corresponding to locations within the multi-dimensional data that are located in the active region, the determining comprising:

[0015] determining, in accordance with the Z-ordering function, whether a location defined by a first value of the one-dimensional data is located within the active region;

[0016] in response to determining that the location defined by the first value is not located within the active region: calculating an overflow value that, when added to the first value, causes the least significant bit that is one in the binary representation of the first value to flip to zero;

[0017] summing the first value and the overflow value to obtain a trial value;

[0018] determining whether a position defined by the trial value lies within the valid region, thereby determining whether the trial value forms part of the sequence, wherein the sequence identifies work packages to be processed.

[0019] In example embodiments, the overflow value is a lowest possible value that flips the least significant bit (in the binary representation of the first value) that is 1 to 0. The least significant bit of the first value can be zero. In example embodiments, in response to determining whether a position defined by the trial value lies within the valid region, the method thereby determines that the sequence does not include the first value and does not include values that lie between the first value and the trial value and do not include the first value and the trial value.

[0020] In example embodiments, the work packages to be processed are used to render a scene, and the multi-dimensional data represents a region of the scene. In example embodiments, the overflow value is equal to a power of 2.

[0021] In example embodiments, calculating the overflow value includes: identifying the least significant bit that is 1 in the binary representation of the first value; and generating the overflow value that has a magnitude equal to a power of 2 represented by the least significant bit that is 1. Thus, calculating the overflow value can be conceptually equivalent to determining a number of consecutive zeros in the binary representation of the first value, where the consecutive zeros include the least significant bit of the binary representation. Thus, the method can be conceptually equivalent to or involve obtaining a value equal to an exponential power of 2, the exponent equaling the number of consecutive zeros.

[0022] In example embodiments, the valid region is defined by a plurality of boundary values, each respective dimension of the multi-dimensional data having one boundary value, and wherein determining whether the position defined by the first value of the one-dimensional data lies within the valid region includes: converting the first value to a multi-dimensional coordinate using a mapping defined by the Z-order function; and determining whether the multi-dimensional coordinate falls within a range defined by the plurality of boundary values.

[0023] In example embodiments, each boundary value is a maximum value, and determining whether the multi-dimensional coordinate falls within a range defined by the plurality of boundary values includes determining whether at least one coordinate value of the multi-dimensional coordinate exceeds a maximum value for a corresponding dimension. A boundary value can be a maximum value, for example, a maximum value for each of an X-dimension and a Y-dimension of 2-dimensional data. In general, a boundary value can indicate a range, where a start or end of the range is known, such that a degree of the range can be determined and thus a valid region can be determined.

[0024] In an example implementation, the method further includes determining, according to the Z ordering function, that a position defined by the trial value does not lie within the valid region, thereby determining that the trial value does not form part of the sequence, and in response to the determination: identifying a least significant bit that is one in a binary representation of the trial value; calculating a further overflow value that is at least as large in magnitude as a value represented by the least significant bit of the trial value that is one, and that, when added to the trial value, flips the least significant bit of the trial value that is one to zero; summing the trial value and the further overflow value to obtain a further trial value; and determining whether a position defined by the further trial value lies within the valid region, thereby determining whether the further trial value forms part of the sequence.

[0025] In an example, the further overflow value can be at least twice the size of the overflow value. Thus, the further overflow value can be larger than the overflow value by a value equal to a power of two.

[0026] In an example implementation, calculating the overflow value includes performing a bit- inversion operation, an addition operation, and at least one bitwise comparison operation on the binary representation of the first value, thereby obtaining the overflow value. For example, the bitwise comparison is an AND operation.

[0027] In an example implementation, the first value is a first entry in the one-dimensional data, and wherein the method includes iterating entries of the one-dimensional data in a sequential order, thereby determining the at least a portion of the sequence that corresponds to positions within the multi-dimensional data that lie within the valid region.

[0028] In an example implementation, the at least a portion of a sequence is determined without testing a subset of values within the one-dimensional data to determine whether the subset of values defines a position that lies within the valid region.

[0029] In an example implementation, the subset of values includes at least values that lie between the first value of the one-dimensional data and the trial value, and that do not include the first value and the trial value. Thus, values in the one-dimensional data that lie between the first value and the trial value can be skipped.

[0030] In an example implementation, none of the values of the one-dimensional data that lie between the first value of the one-dimensional data and the trial value, and that do not include the first value and the trial value, represent a position that lies within the valid region.

[0031] In an example implementation, each dimension of the multi-dimensional data is equal to a power of two, and wherein at least one dimension of the valid region is not equal to a power of two.

[0032] In an example embodiment, the multi-dimensional data represents a region of a scene, and the method further includes outputting at least some of the work packets identified by the sequence for processing, wherein the output work packets are used to render at least a portion of the scene.

[0033] In an example embodiment, for each mapped value of the one-dimensional data, the Z ordering function maps alternating bits of a binary representation of the mapped value to respective coordinate values of the multi-dimensional data.

[0034] In an example embodiment, the Z ordering function represents a Morton order function, and wherein the multi-dimensional data is 2D.

[0035] In an example embodiment, the computer-implemented method is part of a ray tracing system, and wherein the work packets identify ray tracing or shading operations.

[0036] In an example embodiment, the computer-implemented method is performed by a graphics processing unit (GPU).

[0037] In an example embodiment, the multi-dimensional data represents a multi-dimensional array space for storing thread groups, and wherein the active region represents an array of thread groups within the multi-dimensional array space, each thread group containing an identification of a plurality of work packets.

[0038] There is also provided a processing unit for parsing multi-dimensional data to identify work packets to be processed, wherein the multi-dimensional data is mapped into one-dimensional data using a Z ordering function, the processing unit being configured to:

[0039] obtain a dimensionality of the multi-dimensional data;

[0040] obtain information identifying an active region of the multi-dimensional data, the active region identifying work packets;

[0041] determine at least a portion of a sequence within the one-dimensional data corresponding to a location within the multi-dimensional data that is located in the active region, the processing unit being configured to perform the determining by:

[0042] determining, in accordance with the Z ordering function, whether a location defined by a first value of the one-dimensional data is located within the active region;

[0043] in response to determining that the location defined by the first value is not located within the active region: calculating an overflow value that, when added to the first value, causes a least significant bit that is one in a binary representation of the first value to flip to zero;

[0044] summing the first value and the overflow value to obtain a trial value; and

[0045] determining whether the position defined by the trial value lies within the valid region, thereby determining whether the trial value forms part of the sequence, wherein the sequence identifies a work package to be processed.

[0046] In an example embodiment, the processing unit is a graphics processing unit, GPU. The processing unit can be comprised in hardware on an integrated circuit.

[0047] In an example embodiment, the processing unit is configured to calculate the overflow value using an operation selected from the group consisting of: a unary bitwise operation; a bitwise comparison operation; and an addition operation. Thereby the overflow value can advantageously be calculated without using multiplication logic and without using exponential logic within the hardware unit.

[0048] There is also provided a graphics processing system configured to perform any of the methods described herein.

[0049] There is also provided an integrated circuit definition data set which, when processed in an integrated circuit manufacturing system, configures the integrated circuit manufacturing system to manufacture a processing unit as described herein.

[0050] There is also provided computer readable code configured so as when the code is run to cause any of the methods described herein to be performed.

[0051] There is also provided a non-transitory computer readable storage medium having stored thereon a computer readable description of a graphics processing unit as described herein, which, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture an integrated circuit comprising the graphics processing unit.

[0052] The processing unit can be comprised in hardware on an integrated circuit. There can be provided a method of manufacturing a processing unit at an integrated circuit manufacturing system. There can be provided an integrated circuit definition data set which, when processed in an integrated circuit manufacturing system, configures the system to manufacture a processing unit. There can be provided a non-transitory computer readable storage medium having stored thereon a computer readable description of a processing unit, which, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture an integrated circuit comprising the processing unit.

[0053] An integrated circuit manufacturing system can be provided, the integrated circuit manufacturing system comprising: a non-transitory computer readable storage medium having stored thereon a computer readable description of a processing unit; a layout processing system configured to process the computer readable description so as to generate a circuit layout description of an integrated circuit comprising the processing unit; and an integrated circuit generation system configured to manufacture the processing unit in accordance with the circuit layout description.

[0054] Computer program code for performing any of the methods described herein can be provided. A non-transitory computer readable storage medium having stored thereon computer readable instructions which, when executed in a computer system, cause the computer system to perform any of the methods described herein can be provided.

[0055] As will be apparent to a skilled person, the above features can be combined as appropriate, and can be combined with any of the aspects of the examples described herein. BRIEF DESCRIPTION OF DRAWINGS

[0056] Examples will now be described in detail with reference to the accompanying drawings, in which:

[0057] Figure 1 A ray tracing system according to examples described herein is shown;

[0058] Figure 2A A thread grid using Z-order scan is shown;

[0059] Figure 2B A thread grid using reverse N-order scan is shown;

[0060] Figure 3 An example of a full-size thread grid using Z-order scan is shown, including the active area of the thread grid;

[0061] Figure 4 A table showing binary representations and coordinates of counter values and corresponding skip values for Z-order applied according to embodiments of the disclosure is shown;

[0062] Figure 5 A grid and Z-order sequence corresponding to Figure 4 An example of is shown, including a visualization of overflow values;

[0063] Figure 6 A 3D embodiment of Z-order, referred to as Lebesgue 3D curve, is shown;

[0064] Figure 7 A flowchart showing an algorithm for determining overflow values according to embodiments of the disclosure is shown;

[0065] Figure 8 A flowchart illustrating an algorithm for determining overflow values using bitwise operations is shown, in accordance with an embodiment of the present disclosure;

[0066] Figure 9 A computer system in which a graphics processing system is implemented is shown; and

[0067] Figure 10 An integrated circuit manufacturing system for generating an integrated circuit containing a graphics processing system is shown.

[0068] The drawings illustrate various examples. A skilled artisan will understand that the boundaries shown around elements in the drawings represent one example of a boundary. In some examples, it can be the case that an element can be designed to be a plurality of elements, or that a plurality of elements can be designed to be one element. Where appropriate, common reference numerals have been used throughout the various drawing figures to designate similar features. DETAILED DESCRIPTION

[0069] The following description presents examples by way of example only to enable a person skilled in the art to make and use the application. The application is not limited to the embodiments described herein, and various modifications to the disclosed embodiments will be apparent to those skilled in the art.

[0070] Embodiments will now be described by way of example only.

[0071] As mentioned above, Z-order (also known as Morton order) is a good choice for ordering scene data in a graphics processing system as it increases the spatial locality of references to scene data and thus allows cache lines to represent rectangular regions of scene data. Thus, Z-order provides an advantage over standard raster scan order in a graphics processing system. Morton order can be applied to store scene data 2D or 3D for rendering images for rasterization and ray tracing purposes. However, using Morton order can introduce unacceptable inefficiencies in the processing system as a large number of invalid coordinates can be generated for the multi-dimensional data when the active region of the multi-dimensional data set to be resolved is not a precise power of two. This can result in a large number of wasted cycles corresponding to invalid coordinates of the multi-dimensional data being generated. Although it is theoretically possible to mathematically pre-determine the values of the active sequence for a given multi-dimensional data grid and a given ‘active region’ of the grid, the mathematical operations required to determine the values would be extremely expensive in terms of chip area as they would involve multiplication logic. Furthermore, pre-determining which regions of the scene grid to ‘skip’ and storing an indication of this prior to run for all different possible grid sizes / dimensions would involve a large amount of work and storage and is therefore generally not feasible.

[0072] The following examples describe ray tracing methods primarily by way of example. However, it should be understood that the presently described embodiments are applicable to other types of graphics processing algorithms and systems (e.g., rasterization techniques) and indeed to other types of processes involving the mapping of multi-dimensional data to a one-dimensional sequence using a Z-order function (such as image processing or general computing processes).

[0073] References to a 'Z-order function' or'multi-to-one dimensional mapping function' should be understood to encompass a variety of functions that encode multi-dimensional data as one-dimensional data in a manner that preserves the spatial location of the multi-dimensional data points. A 'Z-order' function can also be referred to as a 'twiddle' function or an 'interleaved bits' function. Thus, references to a 'Z-order function' include Z- sequence functions (known as Morton sequence) and variations such as the reverse N-sequence shown in Figure 2B and the 3D Lebesgue curve shown in Figure 6 More alternatives will be apparent to the skilled person and can be applied to the functionality described in the present disclosure on an equivalent basis.

[0074] References to 'threads' in the present disclosure generally describe some work to be performed as part of a ray tracing or graphics processing process. In other words, a 'thread' is an operation performed in relation to a particular input data. Threads can also be referred to as 'invocations' or 'work items'. Groups of threads can be referred to as work packets. In the present disclosure, unless otherwise stated, a thread refers to a work item of the present specification. In the specific context of ray tracing, a thread typically relates to a single work item of work load that generally corresponds to a single ray. Once a thread has been sent for scheduling, the thread can be launched as a work item. For example, a thread can be a code module or shader module that identifies a single ray. In other contexts, a 'thread' can alternatively refer to a part of a multi-threaded processing environment (such as a graphics processing unit GPU), i.e. a part of the hardware that executes instructions (possibly in parallel with other threads). Generally speaking, the embodiments described in the present disclosure can be applicable to graphics processing methods and systems. While the following examples relate to ray tracing, they are not intended to limit the applicability of the methods and algorithms of the ray tracing methods and systems described herein.

[0075] Figure 1A ray tracing system 100 is shown that includes a ray tracing unit 102 and a memory 104. The ray tracing unit 102 includes a processing module 106, a resolver module 108, and a scheduler module 110. In operation, the ray tracing unit 102 receives scene data, which can include ray data, geometry data, object data, etc. that define aspects of a scene. Although the scene data is indicated as being received from an external source, in implementations, the scene data can be received from the memory 104. The processing module 106 is configured to generate acceleration structures based on the geometry data, and send the acceleration structures to the memory 104 for storage therein. Alternatively, the acceleration structures can be predetermined and form part of the scene data. The processing logic 112 can retrieve nodes of the acceleration structures (including data defining bounding volumes, e.g., axis-aligned boxes corresponding to the nodes) from the memory 104 to perform intersection tests of rays with respect to the retrieved nodes. The resolver module is configured to implement initial stages of a ray tracing pipeline. The resolver module 108 is configured to resolve the scene data, specifically multi-dimensional data containing threads that identify work packets for processing portions of the scene, and thus forward the threads onward to the scheduler module 110 for scheduling and further processing. The resolver module can also be referred to as a ray tracing data master (RDM) or command engine. In some ray tracing implementations, the scene data is also referred to as a ‘control flow’ (which is stored in the memory 104) and determines the configuration of the ray tracing pipeline. Thus, the resolver (i.e., RDM) is configured to receive the control flow. The control flow can be processed in packets of a predetermined size (e.g., 64 bits each). Each packet of the control flow can be referred to as a ‘tile header’, and each tile header can contain information indicating a tile header type, and optionally can contain a payload. The control flow can also contain pointers to other structures in memory. In some instances, the tile header contains a thread grid, which the RDM splits into thread groups.

[0076] In the context of ray tracing, the ray tracing work is received as a grid, sometimes referred to as a thread grid. The resolver module iterates through the threads (also referred to as work packets) within the thread grid in a serial fashion (i.e., one after another, rather than in parallel). Thus, the resolver module 108 can generate coordinates for groups of threads (smaller 1D or 2D portions of the thread grid), which are then sent by the resolver module to the scheduler module 110. In other words, the resolver module 108 can divide the thread grid into groups of threads and provide X and Y coordinates (for thread grids with two dimensions) for each of these groups. All threads that exist within the identified thread group are passed along for further processing at the scheduler module 110, which is referred to in some instances as a ray tracing scheduler (RTS) or a ray acceleration cluster (RAC). Once received at the scheduler module 110, the scheduler module 110 can divide the thread group into work items for further processing. The resolver module 108 iterates through the thread groups in one of two sequences: a step / raster sequence or a rotate / morton / Z sequence. Typically, for data that is multi-dimensional, the RDM will select a Z ordering function to obtain the cache-related benefits described above.

[0077] In the present disclosure, a thread grid generally refers to an area of a scene that identifies and schedules work packets (containing threads, which can correspond to rays in the context of ray tracing) to be processed. The thread grid can be 2D or 3D, and can even contain higher dimensions. Thus, in the present disclosure, a thread grid is more generally referred to as multi-dimensional data used to render a scene. In the present disclosure, a thread group is a 1D or 2D slice of the thread grid that is sent by the resolver module 110 (which can be a command engine or ray data master in the context of ray tracing) to the scheduler module 110. Thus, more generally, a thread group identifies a plurality of threads or work packets to be processed. In the present disclosure, a thread or ‘work item’ is a program executed by a portion of a processing unit (e.g., a core of a processing unit, such as a graphics processing unit, GPU). A work item can operate in parallel on multiple pieces of data, referred to as instances. Typically, a work item is a single instance, i.e., corresponds to a single ray. A ray is a construct that moves through a scene a fixed distance in a straight line from an origin (not necessarily the origin of the scene’s spatial coordinate system). Rays can interact with objects that they intersect. The scheduler module 112 generates work items that launch rays and model their interactions with objects.

[0078] Figure 2AAn instance of a thread grid 200 composed of 64 thread groups and a Z-sequence (i.e. a Morton sequence) for scanning the thread groups 204 is shown. Each thread group contains a plurality of individual threads (not shown). The thread grid thus represents a multi-dimensional data representing a region of a scene to be rendered. A counter value 206 (also referred to as a sequence value) from 0 to 63 labels each thread group with its corresponding position in the Morton sequence 202. The shown Morton sequence thus represents a one-dimensional data that has been mapped from the 2-dimensional coordinate data defining the thread grid. In this case, the one-dimensional data is simply a list of integers defining positions on the thread grid. The Z-sequence is one-dimensional in that it can be encoded using a single counter value. The X and Y coordinate positions of the thread grid 200 are labelled on the axes of the thread grid (i.e. the X coordinate on the upper side of the grid and the Y coordinate on the left side of the grid) with indices starting from zero. The method of encoding the multi-dimensional data (2D in this instance) of the thread grid data into a 1D sequence in Figure 2A

[0079]

[0080] As can be seen from the table, the alternating bits of the binary representation of the sequence value encode the bits of the X coordinate and the Y coordinate respectively. The underlined values in the binary representation of the counter value indicate the bits that encode the X coordinate. The scan pattern produced by the ‘YxYx YxYx’ function thus produces a Z pattern that is essentially fractal in nature, as it recursively fills the space of the thread grid with a Z pattern that repeats over increasingly larger scales.

[0081] Figure 2B An alternative instance of a Z-ordering function is shown, in this case, an inverse N-sequence 208. Similar to the Figure 2A Figure 2B A thread grid 200 composed of 64 thread groups and an inverse N-sequence for scanning the thread groups is shown, and the X and Y coordinate positions (with indices starting from zero) are labelled as well as the upper and lower axes of the thread grid. The inverse N-sequence 208 produced is effectively a diagonal mirror image of the Z-sequence / Morton function. This inverse N-sequence can be obtained by using the following bit-format function: xYxY xYxY xYxY xYxY. Thus, in the inverse N-sequence, the X coordinate is encoded in the first bit of the binary representation of the counter value, and the Y coordinate is encoded in the second bit of the binary representation of the counter value. The third bit of the binary representation of the counter value is thus the inverse N-sequence value of the thread group at position (1, 1) of the thread grid. The fourth bit of the binary representation of the counter value is thus the inverse N-sequence value of the thread group at position (2, 1) of the thread grid, and so on. Figure 2B ​​the bit encoding of the Y coordinate (and vice versa for the Y coordinate and the X coordinate). Advantageously, as will be described in detail in the following examples, the method for determining the active position along the Morton order sequence is equally applicable to both the Morton order shown in Figure 2A Figure 2B the reverse N-order example shown in

[0082] In general, the nature of the bit pattern used to encode the Z ordering function (i.e. the many-to-one dimensional function) means that the maximum representable value for each of the X coordinate and the Y coordinate is a power of two. However, the ‘launch size’ of the thread grid is different to the grid that actually contains threads (i.e. work items or work groups) that contain active work to be performed. In this specification, the area of the grid that contains work groups that contain work to be performed is referred to as the ‘active area’. In other words, the area of the grid that contains work groups / threads that are to be processed to render a scene is referred to as the ‘active area’. Thus, the part of the grid that is not within the active area does not contain threads or work groups that define or identify processing instructions. A work group can identify multiple threads, and each thread can involve operations such as shading operations for a ray trace or a ray.

[0083] The dimensions of the launch size of a thread grid formed by using a Z order are typically equal to a power of two. Thus, in the case that the active area has exactly a power of two dimensions, the Z ordering function works effectively because the entire thread grid will be active. When the dimensions of the active area are only slightly less than exactly a power of two, the Z ordering function also works effectively because this only results in a small portion of the thread grid being inactive. However, problems can arise when the dimensions of the active area of the thread grid are slightly greater than exactly a power of two. Applying a Z ordering when the active area is slightly greater than exactly a power of two results in a large number of inactive coordinates being generated in the thread grid. In particular, the inactive coordinates are those coordinates that are allowed by the bit function that can use the Z ordering but are not contained within the active area. This problem arises whenever the active area does not have exactly a power of two dimensions. However, the problem is exacerbated in the case that the active area is only slightly greater than a power of two because this means that a large portion of the representable thread grid (which has dimensions equal to a power of two) contains inactive coordinates.

[0084] Figure 3 ​A representative example of a full-sized thread grid 300 is shown, and a Z- / Morton order sequence 202 for the thread groups of the iteration grid is shown. Individual thread groups are not shown in this diagram. The active area 302 is indicated as the shaded area. In this example, the maximum width of the thread grid is equal to 512, i.e. contains 512 thread groups, and the maximum height of the thread groups is equal to 4096, i.e. contains 4096 thread groups. The full height of the thread grid is not shown in this example. In this example, the dimensions of the thread grid are thus 512 x 4096. These dimensions represent the launch size of the grid as the maximum representable dimensions within the thread grid. As shown, the indices of the thread groups in both dimensions start at zero. However, the number of threads per thread group can vary, and does not directly affect the operation of the presently described embodiments. The number of threads per thread group can define the maximum dimensions of the thread grid.

[0085] In this case, the active area 302 contains thread group width 257 (i.e. positions 0 to 256 in the X dimension) and thread group height 2049 (i.e. positions 0 to 2048 in the Y dimension). This particular case thus represents a particularly problematic instance of a real-world scenario, as a substantial portion of the thread grid is inactive, i.e. the dimensions of the representable thread grid just exceed the power-of-two boundary (e.g. 257 width and 2049 height). Thus, when the Z-seq function 202 (shown in Figure 3 , although not drawn to scale) scans through the thread grid, a large number of "skip cycles" or "empty cycles" corresponding to coordinates of the thread grid that do not contain work packets will be generated. For example, it can be seen that the rightmost portion of the Z-seq scan 202 occupies the inactive portion of the thread grid.

[0086] If, in a real-world instance, the thread grid 300 and active area 302 are used by the ray-tracing data master (RDM) or resolver module 108 as described above, the Z-seq function 202 (shown in Figure 3If the unmodified Morton 202 were to be processed as shown in the middle, then approximately 41,000 skip cycles would occur, reaching only the final valid position 304 of the thread grid marked on the valid region. For each value of the one-dimensional data in the Z-order sequence considered by the RDM, the RDM determines whether the coordinate position defined by the sequence value lies within the valid region. This can be determined by converting the sequence value to a coordinate using the bit function that defines the Z-order. If the RDM determines that the counter value corresponds to an invalid position, it simply skips the value and does not send the thread group / work packet identified by the coordinate for processing. Specifically, the skipped coordinate is not sent down for scheduling / processing at the scheduler module 110 (which in some instances is a ray acceleration cluster, RAC). After a Z-order scan under the normal resolution mechanism, the counter value would then be incremented by 1 and the process repeated. Thus, the repeated determination of coordinate values from the counter value and the subsequent repeated determination of whether the coordinate is valid (i.e., by comparing each coordinate value to the corresponding maximum dimension defining the valid region) can waste a significant amount of time when there are a large number of invalid coordinate positions within the thread grid.

[0087] Thus, the normal resolution mechanism of incrementing the counter value defining the Z-order sequence by 1 can be inefficient. Accordingly, it would be advantageous to implement a method by which the next valid position along the Z-order can be efficiently reached or determined. In other words, it would be beneficial if invalid coordinate positions defining invalid thread groups could be efficiently skipped over. It would also be advantageous if an algorithm could be applied in the same manner to'skip' over invalid coordinate positions for various grid sizes and various dimensions (e.g., 2D, 3D, or higher dimensions) and for valid regions of arbitrary size. The foregoing embodiments and examples of the present description describe such advantageous methods.

[0088] The inventors have determined that by targeting the appropriate bit of the one-dimensional sequence value of the Z-order encoding the multi-dimensional data, it is possible to determine how to skip over a large number of invalid coordinates of a given multi-dimensional data set (e.g., a 2D thread grid). The goal is to jump forward within the one-dimensional data sequence by a'skip value' that i) has the potential to skip over at least one sequence value defining an invalid position, and ii) reaches the next valid coordinate in the sequence without skipping it. The number of values in the sequence to skip over for a given value in the one-dimensional data can be referred to as a'spill value','skip value', or'skip-over value'. For a given counter value, when represented in binary, each bit represents one dimension / coordinate component of the multi-dimensional data. In the present example, the valid region always occupies the lowest dimension (i.e., Figure 3the upper left corner of the thread grid). Thus, to determine the overflow value, a binary value is selected to add to the sequence value to obtain a new (or trial) sequence value. Ideally, at least one dimension of the new coordinate represented by the trial value will be decreased. In other words, the goal is to effectively jump ahead to a sequence value that represents the next valid location in the grid (one or more steps). Thus, the goal is to jump ahead to the next valid location without testing at least some of the intermediate sequence values. Thus, at the binary representation level, determining the overflow value corresponds to calculating an overflow value that, when added to the value of the Z-ordered sequence under consideration, flips a bit that is '1' to a '0' that defines a coordinate value that is out of bounds.

[0089] For ease of explanation, a 2D instance of a thread grid is used in the following examples. In general, it is assumed that the valid region is located at the upper left corner of the thread grid. In general, it is also assumed in this disclosure that the valid region of multi-dimensional data starts at the lowest position in each dimension, and only coordinate positions towards the maximum dimension values are invalid. Given this assumption, it is thus guaranteed that a 'out of bounds' (i.e. invalid) coordinate value will contain at least one coordinate component value that is greater than the corresponding maximum dimension of the valid region. In the 2D grid instance, each bit of the Z-sequence counter represents either the X coordinate or the Y coordinate. It should be apparent that adding a value that only increases a '0' bit to a '1' bit will increase exactly one of the X coordinate value or the Y coordinate value, and leave the other coordinate value unchanged. Thus, increasing the coordinate value in an attempt to return to the valid region would be futile, and in fact would guarantee that the new coordinate value is in an invalid position. Thus, the goal of the presently disclosed method is to target a bit of the sequence value that is '1' in order to cause an overflow, thereby causing the '1' bit to 'flip' to a '0'. Thus, this allows the possibility of decreasing at least one coordinate value, and possibly two coordinate values, in order to produce a new counter value that will represent a valid coordinate position.

[0090] The inventors have determined that this overflow value can be determined according to determining the least significant bit (LSB) of the binary representation of the one-dimensional data value that is '1'. In one example, the magnitude of the overflow value is equal to the power of two represented by the LSB that is 1. For example, in the binary number 0b01100100, the least significant '1' bit is the third bit from the right, which represents the value 2 2 In concept, this corresponds to counting the number of consecutive zeros in the least significant bit position of the binary representation of the sequence value. Thus, the overflow value is equal to 2 raised to the power of the number of consecutive zeros, i.e. in the above example, 2 2 .

[0091] Figure 4is Table 400, which contains a working example of the use of a portion of a Z-sequence Morton sequence to skip over invalid grid values. In this example, the bit format of the Morton sequence is YxYx YxYx, so the X coordinate and the Y coordinate are each represented by a 4-bit value. For completeness, in this disclosure, the notation ‘YxYx YxYx’ defines a counter value in the following way: Y (3) x (3) Y (2) x (2) Y (1) x (1) Y (0) x (0) which thus encodes the X coordinate value: x (3) x (2) x (1) x (0) and the Y coordinate value: Y (3) Y (2) Y (1) Y (0) . The counter value represents a value of a one-dimensional Z-sequence sequence under consideration. The counter value is represented by an 8-bit value that interleaves the binary representations of the X coordinate and the Y coordinate. Thus, the starting size of the grid is a 16 x 16 grid. The valid region in this example is considered to have dimensions 9 x 15. Thus, the maximum valid dimensions are X = 8 and Y = 14 (where the indices are zero-based). Figure 4 in Table 400. This value corresponds to the coordinate (8, 2), and is thus valid. Thus, the counter value is incremented by 1 normally. The next value 73 is invalid, because its X coordinate is 9, and thus exceeds the boundary. The binary representation of 73, 0b01001001, has no zeroes in the least significant positions. In this case, the conservative overflow value that can be added to the counter / sequence value and that guarantees no risk of skipping over subsequent valid counter values is 1. In other words, when the LSB of the counter value is 1, the jump value that is added is 1. This corresponds to adding 2 0 where the exponent value is equal to the number of consecutive zeroes in the least significant bit positions.

[0092] The next invalid counter value reached is 75. This also has a ‘1’ bit in the least significant positions, and thus the jump value that is added is 1, as indicated on the right side of the table. The next counter value 76 is also invalid (its X coordinate is 10, and the maximum allowed X coordinate is 8) and has exactly two consecutive zeroes starting from the least significant bit position (i.e., 010011 00 where the underlined zeroes indicate the consecutive zeroes in the least significant bit positions 402). Thus, the maximum jump value that can be added is equal to 2 raised to the power of the number of consecutive zeroes (two), i.e., 2 2i.e. 4. Adding the value '4' corresponds to adding the binary value 100, which thus causes the '1' bit in the least significant position (third from the right) to overflow. As can be seen from the table, the skipped counter values (i.e. 77, 78, 79) all represent Z-sequence coordinate positions that are out of bounds (i.e. the X coordinate is still greater than 8). The next value obtained using this method is 80, which is another invalid value (its X coordinate is 12) and its binary representation is 01010000. Thus, the least significant bit that is '1' is the fifth from the right and it represents the value 2 to the power of 2 4 . In another way, as indicated in Figure 4 , the value has four consecutive zeros 404 starting from the least significant bit position (i.e. 0101 0000 ). Thus, the determined overflow value is equal to 2 to the power of the number of consecutive zeros (two), i.e. 2 4 , i.e. 16. Adding the value '16' corresponds to adding the binary value 10000, which thus causes the '1' bit in the least significant position (fifth from the right) to overflow.

[0093] The above illustrated method of determining an overflow value can be summarized in terms of the following steps:

[0094] 1. Determine the X coordinate value and the Y coordinate value represented by the counter value using the Z-sequence function YxYx YxYx;

[0095] 2. Determine whether the coordinates are valid by determining:

[0096] a. whether the X coordinate value is greater than the maximum valid area width:

[0097] b. whether the Y coordinate value is greater than the maximum valid area height:

[0098] 3. If the coordinates correspond to a valid position, increment the counter value by 1 and return to step 1;

[0099] 4. Otherwise, if the coordinates correspond to an invalid position: determine the overflow value by generating an overflow value with a magnitude equal to 2 to the power of the least significant bit of (the binary representation of the sequence value) that is 1 (which conceptually corresponds to counting the number of consecutive zeros starting from (and including) the LSB in the binary representation of the counter / sequence value, and raising 2 to the power of the counted number of consecutive zeros);

[0100] 5. Add the overflow value to the counter value and return to step 1.

[0101] As mentioned above, the determined overflow value is conservatively chosen to be equal to a power of 2 represented by the least significant bit (LSB) being 1. This is a conservative value because adding the value guarantees that there is no risk of skipping a subsequent valid counter value. To demonstrate this, consider the binary value 0b01010000 (80, decimal). Applying the algorithm, the overflow value calculated for this number is 0b10000 (16, decimal) because this value represents the value of the least significant bit 1. If the overflow value were any (positive) integer less than 16, then adding the overflow value would guarantee that the next sequential value would also be invalid because any number less than 16 cannot flip the least significant value of 1 bit. Thus, it is guaranteed that the value represented by the least significant bit is 1 bit (16 in this case) and it is impossible to exceed the next ‘valid’ coordinate in the sequence. Thus, the overflow value is typically conservatively chosen in this way, i.e. the least possible value that flips the least significant bit (in the binary representation of the sequence value under consideration) from 1 to 0.

[0102] However, there can be instances in which a larger overflow value is chosen which still causes the least significant bit of 1 to be flipped. For example, with the example of the counter value 75 in Figure 4 , it can be predetermined that the next two ‘overflow values’ are 1 and 4, and thus the overflow value of ‘5’ can be added in one step. For example, it can be determined that adding ‘1’ to the counter value 75 will increase the X coordinate value because 3 least significant bits are ‘..011’ and thus the next value will end in ‘..101’. Thus, in some instances, the pattern of ‘..011’ in the 3 least significant bits of the counter value can be recognised as a signal that ‘5’ can be added in one step rather than ‘1’ and then ‘4’ in two steps.

[0103] Figure 5 A portion of the grid 500 is shown along with the Z-sequence 202 corresponding to the table shown in 4. For brevity, only the top right quadrant of the full 16x16 grid is shown in Figure 5 , and thus only X coordinate values of 8 to 15 and Y coordinate values of 0 to 7 are shown. All coordinate positions forming part of the valid region are indicated by shading. In particular, of the coordinate positions shown in Figure 5 , coordinate positions 64, 66, 72, 74, 96, 98, 104, 106 are valid coordinate positions and the remaining positions are invalid. Reference is made to Figure 4 for an explanation of the mathematical logic. The mathematical logic is demonstrated graphically in Figure 5 . For example, it can be seen that at position 76, the next three values in the sequence (77, 78, 79) all belong to the same ‘Z’ structure, the structure forming a diamond shape with Figure 5The dashed area in the diagram indicates a 2x2 unit square 502. Within this 2x2 unit square, it can be seen that at positions 77, 78, and 79, the X-coordinate is guaranteed to be at least as large as the X-coordinate at position 76 at the start of the 'Z' structure. Therefore, testing positions 77, 78, and 79 would be wasteful, as it can be determined that none of these positions are valid. Therefore, the jump value of 4 can be added to 76 to reach position 80.

[0104] Position 80 also forms the beginning of another 'Z' structure pattern occupying a 2x2 unit square. However, position 80 also forms the beginning of a macro 'Z' structure pattern occupying a 4x4 unit square 504 indicated by another dashed area. In each cell of the macro 4x4 square following the Z-order starting from position 80, the X-coordinate is also at least as large as the X-coordinate of position 80. Therefore, testing positions within the 4x4 unit square 504 outside of position 80 would be wasteful. Therefore, as indicated, an overflow value of 16 can be added to 'escape' the 4x4 unit square, thus reaching the next potential coordinate position. In this case, position 96, located within the valid region, is reached. Advantageously, applying the overflow value at positions 74 to 96 in the above example only requires testing the validity of the coordinate positions four times. Apart from position 80, it is not necessary to test the one-dimensional sequence values ​​in the 4x4 unit square 504 to determine whether the value defines a position within the valid region. In contrast, if the normal Z-order resolution mechanism is followed, each coordinate position will be tested, resulting in 22 validity tests (including positions 74 to 95). Therefore, this algorithm enables the skipping of most, in fact, invalid coordinates, thus saving a significant amount of computation time.

[0105] More specifically, the method described here allows skipping an exponentially increasing subset of the thread grid. This can be seen by considering the bits of the binary representation of the counter value 'flipped' by the algorithm. This takes into account scenarios where the X coordinate exceeds the boundaries (such as...). Figure 5 As shown in the diagram, the bit representing the counter value of the 'X' coordinate is located in the 'even' position in the binary representation, counting from right to left (and indexed starting from zero). Therefore, for the Z-order function YxYx YxYx, when the X coordinate exceeds the boundary, the amount of overflow applied will be an even power of two: that is, 2 0 =1,2 2 =4,2 4 =16, 2 6 =64, etc. Therefore, even if the overflow value is determined at runtime in a trial-and-error fashion (i.e., the opposite of all overflow values ​​being calculated and stored before runtime, but this is also possible), the size of successive overflow values ​​increases exponentially, for example, as... Figure 4 and Figure 5the counter values 75, 76 and 80 in the case of the Z-sequence pattern. Furthermore, the overflow value can be determined using a computationally efficient bitwise operation (specific examples of which are described in more detail below) so as to avoid the use of expensive multiplication logic that would introduce undesirable latency. In some examples, the overflow value can be computed using an operation selected from the group consisting of: a unary bitwise operation (an operation that requires only one binary number as input, such as a NOT operation); a bitwise comparison operation (an operation that requires only two binary numbers as input, such as an 'AND' or 'XNOR' operation); and an addition operation. Thus, a general advantage of the algorithms disclosed herein is that they can quickly reach the next coordinate position within the valid region of the grid.

[0106] It will be appreciated that an equivalent approach can be applied when the 'Y' coordinate exceeds the boundary. In this case, when using the Z-sequence function YxYx YxYx YxYx etc. (counting from the LSB, and indexed from zero), the 'odd' bits of the binary representation of the counter value encode the Y coordinate. Thus, to 'flip' the correct Y bits, powers of two whose odd indices will be added to the sequence value, i.e. 2 1 = 2, 2 3 = 8, 2 5 = 32 etc. As before, the overflow value can be regenerated by making it equal to the power of two represented by the least significant bit that is '1'. Again, this corresponds conceptually to counting the number of consecutive zeros starting from the LSB.

[0107] Reverse N instance

[0108] The Z-sequence pattern encompasses a range of different functions that map multi-dimensional data into a one-dimensional sequence. The resulting Figure 2A An alternative bit function to the YxYx YxYx function that produces the Z-pattern shown in Figure 1 is the reverse N-sequence sequence 208, which is effectively a diagonal mirror image of the Z-sequence pattern. Figure 2B An example of this is shown in Figure 2. The N-sequence can be obtained by using the bit format function xYxY xYxY xYxY xYxY.

[0109] Advantageously, the above algorithms for providing an efficient lookahead for the next valid coordinate of a Z-type bit format function can be applied in unmodified form to the reverse N function. Similarly, the magnitude of the overflow value produced using the algorithms for the reverse N-type function also increases exponentially in size. Thus, in general, the algorithms presently described again enable a large number of invalid positions or 'empty periods' to be skipped entirely.

[0110] To give a working example of an inverse N-type function using the bit format function Y x Y x Y x Y, suppose that a grid size of 16 x 32 can be represented, where the dimensions of the active area are 10 x 19 (so, from zero-based indexing, X value 10 is invalid and Y value 19 is invalid). The format means that the X coordinate is encoded using 4 bits and the Y coordinate is encoded using 5 bits. The table below shows the overflow values (i.e. the hop values) that can be obtained from a sequence value of 300. The underscored values in the binary representation of the counter value indicate the bits that encode the X value:

[0111]

[0112] Thus, the sequence of overflow values from sequence value 303 to 384 is 1, 16 and 64. This sequence of overflow values forms a different pattern to that observed for the Z sequence example shown in Figure 4 and Figure 5 The principle remains the same, however, that the magnitude of the successive overflow values increases exponentially in size.

[0113] The method described above has been described with reference to a 2-dimensional example grid. However, the principles and algorithms can be applied in exactly the same way to 3D multi-dimensional data, for example, where a Z ordering function maps 3D data into one dimension.

[0114] Figure 6 An example of a 3D Z ordering function 600, known as the Menger 3D curve, is shown. The function iteratively fills a 3D volume in a 3D fractal pattern. In Figure 6 The first eight values of the one-dimensional sequence mapped by the Menger 3D function are shown in the volume 602 shown in Figure 6 The dashed lines in also serve to indicate the eight spatial locations within the cube. Thus, in some examples, the volume 602 can represent a grid of threads, for example, where the volume 602 represents a 3D region of a 3D scene. The Menger 3D curve is mapped using a Z ordering bit format of ‘Zyx Zyx Zyx Zyx’. The table below shows the correspondence between the one-dimensional sequence data and the 3D coordinates of the first 8 values of the sequence:

[0115]

[0116] To show that the same concept of overflow values can be applied to 3D examples, consider an example where the starting size of the 3D grid is 4 x 4 x 4, and where a 6-bit Z ordering format of Zyx Zyx is used to map the Menger 3D curve. This 4 x 4 x 4 example would correspond to a volume of 64 x 64 x 64. Figure 6The eight cubes shown in the middle form a cube, i.e. such that the counter counts from 0 to 63. Thus, each of the X coordinate value, the Y coordinate value and the Z coordinate value is represented by a 2-bit binary value. Let the active area of this thread grid extend to Z=1, Y=3, X=1, i.e. to a quarter of the 'launch size' of the cube formed by the 3D grid. Thus, the length of the one-dimensional sequence will be 64 values (0 to 63). Of these values, the sequence values that define positions within the active area defined by the maximum values Z=1, Y=3, X=1 are [0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 23] and no other values. As mentioned before, the goal of the modified algorithm is to iterate over the one-dimensional sequence values (0 to 63) by skipping as many invalid sequence values as possible.

[0117] Based on the active sequence values listed above, it can be seen that the first invalid sequence value is 8, whose binary representation is 0b001000, corresponding to the coordinate values Z=0, Y=0, X=2 (i.e. the X coordinate is out of bounds). Using the same algorithm as before, the least significant bit that is '1' is in the fourth position and represents the value 2 3 . Thus, the overflow value 8 can be added to the sequence value 8 to get 8+8=16. As can be seen from the list above, the next active sequence value in the list is 16, thus, in this case, the algorithm successfully skipped all invalid sequence values 9 to 15 (inclusive). The next invalid sequence value in the 1D sequence is 24, whose binary representation is 0b011000, and which corresponds to the coordinate values Z=0, Y=2, X=2 (i.e. the X coordinate is again out of bounds). As before, the least significant bit that is '1' is in the fourth position and represents the value 2 3 . Thus, the overflow value 8 can be added to the sequence value 24 to get 8+24=32, whose binary representation is 0b100000. Once 32 is reached, the rest of the sequence will be completed in one go, since the least significant bit that is '1' in the binary representation 32 is 32 itself. Thus, the overflow value 32 can be added to 32, thereby reaching the end of the sequence (63), without having to test any invalid values starting from 33.

[0118] Figure 7 A flowchart showing a method for iterating over a one-dimensional sequence of data representing a multi-dimensional grid data in order to determine as efficiently as possible the values of the one-dimensional data that define the active area of the grid. The method thus determines a sequence that identifies the workpacks to be processed to render the scene (since the 'active area' is defined as the area of the grid that contains the workpacks).

[0119] Step S100 comprises identifying a launch size of the grid and dimensions of a valid region within the grid. The grid represents multi-dimensional data representing a portion of a scene and can be 2D or 3D or have higher dimensions. The launch size of the grid can be identified by the bit format of the Z-order function used to map the multi-dimensional data into a 1 -dimensional sequence. In practice, the launch size of the grid need not be explicitly determined or identified as the launch size is defined by the bit format of the Z-order function. In other words, a Z-sequence function of YxYx YxYx represents a launch size of 16x16 as each of the X and Y coordinate values is represented by a 4-bit value giving a maximum X and Y dimension of 16 grid cells (e.g. thread groups) each.

[0120] Step S102 comprises determining a position defined by the current sequence value. When starting to scan the grid, the first sequence value will typically be 0, i.e. the first value in the 1 -dimensional sequence, e.g. corresponding to the coordinate (0,0). The position can be determined by converting the sequence value to a multi-dimensional coordinate using the mapping defined by the Z-order function. Thus, for a 2D grid, the X and Y coordinates are extracted from the interleaved bits of the binary representation of the sequence value as defined by the Z-order function.

[0121] Step S104 comprises determining whether the position determined in S102 is located within the valid region. This can comprise determining whether the multi-dimensional coordinate determined in S104 falls within the identified dimensions of the valid region. For example, the valid region can be defined by a boundary value, one for each coordinate, where the boundary value can be a maximum value. For example, in Figure 5 , the boundary values of the valid region are the maximum values of X=8 and Y=14 (where the indices are zero-based). Thus, each coordinate value of the position determined in S102 can be compared to its respective maximum boundary value. In a practical instance, it can not be necessary to test all coordinates against their respective boundary values as the validity of the position can be determined based on determining that at least one coordinate value exceeds the boundary. For example, if the X coordinate exceeds the boundary, then the Y coordinate need not be tested.

[0122] If at step S104 it is determined that the position is located within the valid region, then the sequence is incremented by 1 (i.e. a counter corresponding to the sequence is incremented by 1) at step S106 and the next value in the 1 -dimensional sequence is tested at step S102.

[0123] If at step S104 it is determined that the identified position does not lie within the valid region, then the method proceeds to step S108. As step S108, an overflow value is determined, which when added to the sequence value causes the least significant bit 1 to flip to 0. By flipping the least significant bit 1, adding the overflow value to the sequence value provides a possibility that at least one coordinate value will be decreased. Thus, the next value that can be reached (e.g. the ‘trial’ value) can define a valid position within the grid. In some instances, the overflow value selected can be the most conservative value: the most conservative overflow value is equal to the value of 2 raised to the power represented by the least significant bit 1 of the binary representation of the sequence value. Advantageously, this conservative value is also a very effective overflow value to calculate. As mentioned previously, the conservative overflow value is the lowest possible value that causes the least significant bit 1 (in the binary representation of the sequence value under consideration) to flip to 0.

[0124] Step 110 involves incrementing the sequence value by the overflow value, i.e. adding the calculated overflow value to the sequence value. In the present disclosure, the sum of the sequence value under consideration and the overflow value can be referred to as the ‘trial value’. Without performing a test, it is not possible to know whether the trial value defines a valid position within the grid. Thus, the method returns to S102, at which point the trial value calculated at step S110 is tested by steps S102 and S104 to determine whether the trial value defines a position within the valid region.

[0125] Figure 7 The method is merely intended to demonstrate a way of efficiently determining portions of 1 -dimensional sequence data identifying work-packets to be processed to render a scene. However, once a work-packet (corresponding to a thread-group) is identified, Figure 7 it is not indicative of what operation is performed on the work-packet. As mentioned above, in the context of a ray-tracing system, Figure 7 The method of can correspond to iterating a thread grid to determine valid thread-groups. Upon determining that a sequence value (corresponding to a thread-group) is valid, an entity iterating the grid sends the thread-group for scheduling and / or further processing at a scheduler module 110 (e.g. a ray-tracing scheduler), which can be a ray-tracing data master (RDM) or more generally the resolver module 108. Thus, at S106, in a ray-tracing or other graphics processing instance, in response to determining that the thread-group position does lie within the valid region, the thread-group will be sent for scheduling and / or processing, e.g. by the resolver module 108 to the scheduler module 110.

[0126] Embodiment example

[0127] A portion of the algorithms described in this disclosure have the advantage that they can be implemented using only bitwise operations, thereby avoiding computationally expensive multiplication logic. The above explanation of the algorithm refers to powers of two, and other references involve counting the number of consecutive zeros. However, the references to exponents and bit counts are primarily for explanatory purposes. Computing exponents is a computationally expensive operation for a processor, and thus is avoided in actual implementations of the method when computing the overflow value. Instead, the algorithm can advantageously compute the overflow value without having to compute the exponent. Furthermore, the algorithm does not actually require 'counting' the number of consecutive zeros starting from the least significant bit. Instead, the overflow value can be determined using bitwise operations and additions.

[0128] Figure 8 is a flowchart illustrating an example algorithm for obtaining an overflow value from a sequence value, where the overflow value is a conservative value equal to a power of two represented by the least significant bit of one being the binary representation of the sequence value. The steps of the flowchart are demonstrated with respect to an actual example where the sequence value under consideration is 0b110011110000 (3312 in decimal):

[0129]

[0130] As can be seen from the table, the only operations required to obtain the overflow value are bitwise operations and additions. Specifically, the only operations required involve a unary bitwise operation; a bitwise comparison operation; and an addition operation. In this case, the operations involve a bitwise inversion at step S202 (corresponding to a logical NOT), an addition at step S204, a bitwise 'AND' comparison at step S206, and another addition at step S208 to obtain the trial value. Furthermore, it will be appreciated that the combination of i) the bits of the inverted value and ii) the addition of one corresponds to computing the 'two's complement' of the binary representation. Thus, in some examples, the two's complement of a number can be simply computed using logic in order to perform the operations of steps S202 and S204.

[0131] Generally, Figure 8 The advantage of the bitwise operations described in the above is that they eliminate the need to use computationally expensive multiplication logic or other computationally expensive operators such as computing exponents. Thus, at the bit representation level, the processor, logic or hardware computing the overflow value does not need to 'count' the number of consecutive zeros in the least significant positions, and does not need to 'identify' the position of the least significant bit of one. Instead, the bitwise operations described above are performed, which can actually determine the overflow value whose magnitude is equal to the magnitude of the value represented by the least significant bit of one (of the binary representation of the sequence value).

[0132] Figure 9A computer system in which the graphics processing system described herein can be implemented is shown. The computer system includes a CPU 902, a GPU 904, a memory 906, a neural network accelerator (NNA) 908, and other devices 914, such as a display 916, speakers 918, and a camera 922. The processing block 910 is implemented on the GPU 904. In other examples, one or more of the depicted components can be omitted from the system, and / or the processing block 910 can be implemented on the CPU 902 or within the NNA 908. The components of the computer system can communicate with one another by way of a communication bus 920. The storage 912 is implemented as part of the memory 906.

[0133] Figure 1 The ray tracing unit of FIG. 1 is shown as including a number of functional blocks. This is merely illustrative and is not intended to define a strict partitioning between the different logical elements of such an entity. Each functional block can be provided in any suitable manner. It will be appreciated that the intermediate values described herein as being formed by the ray tracing unit or processing unit need not be physically generated at any point by the ray tracing unit or processing unit and can merely represent logical values that conveniently describe the processing performed by the ray tracing unit or processing unit between its inputs and outputs.

[0134] The ray tracing unit or processing unit described herein can be included in hardware on an integrated circuit. The ray tracing unit or processing unit described herein can be configured to perform any of the methods described herein. In general, any of the functions, methods, techniques, or components described above can be implemented in software, firmware, hardware (e.g., fixed logic circuitry), or any combination thereof. The terms “module,” “functionality,” “component,” “element,” “unit,” “block,” and “logic” can be used generically herein to represent software, firmware, hardware, or any combination thereof. In the case of a software implementation, the module, functionality, component, element, unit, block, or logic represents program code that performs specified tasks when executed on a processor. The algorithms and methods described herein can be performed by one or more processors executing code, the code causing the processor(s) to perform the algorithms / methods. Examples of computer-readable storage media include random access memory (RAM), read-only memory (ROM), optical disc drives, flash memory devices, hard drives, and other storage devices that can use magnetic, optical, and other technologies to store instructions or other data and that can be accessed by a machine.

[0135] The terms computer program code and computer readable instructions as used herein refer to any kind of executable code for a processor, including code expressed in a machine language, an interpreted language, or a scripting language. Executable code includes binary code, machine code, byte code, code defining integrated circuits, such as a hardware description language or a netlist, and code expressed in a programming language such as C, Java, or OpenCL. Executable code can be, for example, any kind of software, firmware, script, module, or library, which, when executed, processed, interpreted, compiled, run, in a virtual machine or other software environment, causes a processor of a computer system supporting the executable code to perform tasks specified by the code.

[0136] A processor, computer, or computer system can be any kind of device, machine, or special-purpose circuit, or a collection or part thereof, having processing capabilities such that it can execute instructions. A processor can be or include any kind of general- or special-purpose processor, such as a CPU, GPU, NNA, system-on-a-chip, state machine, media processor, application-specific integrated circuit (ASIC), programmable logic array, field-programmable gate array (FPGA), etc. A computer or computer system can include one or more processors.

[0137] The present application is also intended to cover software, such as HDL (hardware description language) software, such as that used to design integrated circuits or to configure programmable chips to perform desired functions, defining hardware configurations as described herein. That is, a computer-readable storage medium can be provided having encoded thereon a computer-readable program code in the form of an integrated circuit definition data set that, when processed (i.e., run) in an integrated circuit manufacturing system, configures the system to manufacture a ray tracing unit or processing unit configured to perform any of the methods described herein or to manufacture a ray tracing unit or processing unit containing any of the apparatuses described herein. The integrated circuit definition data set can be, for example, an integrated circuit description.

[0138] Accordingly, a method of manufacturing a ray tracing unit or processing unit as described herein at an integrated circuit manufacturing system can be provided. Furthermore, an integrated circuit definition data set can be provided that, when processed in an integrated circuit manufacturing system, causes the method of manufacturing a ray tracing unit or processing unit to be performed.

[0139] The integrated circuit definition data set can be in the form of computer code, for example as a netlist, code for configuring a programmable chip, as a hardware description language defining hardware suitable for fabrication in an integrated circuit at any level, including as register transfer level (RTL) code, as a high level circuit representation (such as Verilog or VHDL), and as a low level circuit representation (such as OASIS (RTM) and GDSII). Higher level representations of hardware suitable for fabrication in an integrated circuit (such as RTL) can be processed at a computer system configured to generate a fabrication definition of an integrated circuit in the context of a software environment containing definitions of circuit elements and rules for combining those elements to generate a fabrication definition representing an integrated circuit defined as such. As is the case with software generally executed at a computer system to define a machine, one or more intermediate user steps (e.g., providing commands, variables, etc.) can be required to configure the computer system to generate a fabrication definition of an integrated circuit, to execute code defining an integrated circuit to generate a fabrication definition of the integrated circuit.

[0140] Reference will now be made to Figure 10 Examples of processing integrated circuit definition data sets in an integrated circuit fabrication system to configure the system to fabricate a ray tracing unit or processing unit are described.

[0141] Figure 10 An example of an integrated circuit (IC) fabrication system 1002 is shown, which is configured to fabricate a ray tracing unit or processing unit as described in any of the examples herein. In particular, the IC fabrication system 1002 includes a layout processing system 1004 and an integrated circuit generation system 1006. The IC fabrication system 1002 is configured to receive an IC definition data set (e.g., defining a ray tracing unit or processing unit as described in any of the examples herein), process the IC definition data set, and generate an IC (e.g., including a ray tracing unit or processing unit as described in any of the examples herein) from the IC definition data set. The processing of the IC definition data set configures the IC fabrication system 1002 to fabricate an integrated circuit including a ray tracing unit or processing unit as described in any of the examples herein.

[0142] The layout processing system 1004 is configured to receive and process the IC definition data set to determine a circuit layout. Methods of determining a circuit layout from an IC definition data set are known in the art and can involve, for example, synthesizing RTL code to determine a gate level representation of the circuit to be generated, e.g. in terms of logic components (e.g. NAND, NOR, AND, OR, MUX and FLIP-FLOP components). By determining the position information of the logic components, the circuit layout can be determined from the gate level representation of the circuit. This can be done automatically or with user involvement in order to optimize the circuit layout. When the layout processing system 1004 has determined the circuit layout, it can output a circuit layout definition to the IC generation system 1006. The circuit layout definition can be, for example, a circuit layout description.

[0143] As is known in the art, the IC generation system 1006 generates an IC from the circuit layout definition. For example, the IC generation system 1006 can implement a semiconductor device manufacturing process to generate the IC, which can involve a multi-step sequence of photolithographic and chemical processing steps during which an electronic circuit is gradually formed on a wafer made of semiconductor material. The circuit layout definition can be in the form of a mask which can be used in a photolithographic process to generate the IC according to the circuit definition. Alternatively, the circuit layout definition provided to the IC generation system 1006 can be in the form of computer readable code which can be used by the IC generation system 1006 to form a suitable mask for generating the IC.

[0144] The different processes performed by the IC manufacturing system 1002 can all be implemented at one location, e.g. by one party. Alternatively, the IC manufacturing system 1002 can be a distributed system such that some processes can be performed at different locations and can be performed by different parties. For example, some of the following stages can be performed at different locations and / or by different parties: (i) synthesizing RTL code representing the IC definition data set to form a gate level representation of the circuit to be generated; (ii) generating a circuit layout based on the gate level representation; (iii) forming a mask from the circuit layout; and (iv) using the mask to manufacture an integrated circuit.

[0145] In other examples, processing of an integrated circuit definition data set at an integrated circuit manufacturing system can configure the system to manufacture a ray tracing unit or processing unit without processing the IC definition data set in order to determine a circuit layout. For example, the integrated circuit definition data set can define a configuration of a reconfigurable processor (such as an FPGA) and processing of the data set can configure the IC manufacturing system to generate a reconfigurable processor having the defined configuration (e.g. by loading configuration data to the FPGA).

[0146] In some embodiments, when processed in an integrated circuit fabrication system, the integrated circuit fabrication definition data set can cause the integrated circuit fabrication system to generate an apparatus as described herein. For example, by the integrated circuit fabrication definition data set, the above-described apparatus can be configured in the manner described above with reference to Figure 10 The described manner of configuring the integrated circuit fabrication system can result in the manufacture of an apparatus as described herein.

[0147] In some instances, the integrated circuit definition data set can include software that runs on hardware defined at the data set, or in combination with hardware defined at the data set. In Figure 10 In the example shown in FIG. 1, the IC production system can be further configured by the integrated circuit definition data set to load firmware onto an integrated circuit being manufactured according to program code defined at the integrated circuit definition data set, or otherwise provide program code for use with the integrated circuit, when the integrated circuit is manufactured.

[0148] Compared to known implementations, embodiments of the concepts set forth in this application can improve performance in apparatuses, devices, modules, and / or systems (as well as in methods implemented herein). Performance improvements can include one or more of improved computational performance, reduced latency, increased throughput, and / or reduced power consumption. During the manufacture of such apparatuses, devices, modules, and systems (e.g., in integrated circuits), a tradeoff can be made between performance improvements and physical implementation, thereby improving manufacturing methods. For example, a tradeoff can be made between performance improvements and layout area, thereby matching the performance of known implementations but using less silicon. This can be done, for example, by reusing functional blocks in a serial fashion or sharing functional blocks among elements of the apparatus, device, module, and / or system. Conversely, concepts set forth in this application that result in improvements in the physical implementation of apparatuses, devices, modules, and systems (e.g., reduced silicon area) can be traded off for performance improvements. This can be done, for example, by manufacturing multiple instances of a module within a predefined area budget.

[0149] The applicant hereby expressly incorporates by reference the entire disclosure of each and every U.S. and International patent and / or application cited in this application. Each and every patent and / or application cited in this application is incorporated herein by reference for the purpose of describing in full the disclosure of the cited patent and / or application and for the purpose of disclosing the teachings contained therein that are relevant to the disclosure of this application. Applicant hereby discloses the content of every patent and / or application cited in this application, whether or not the content is repeated herein. The content of every patent and / or application cited in this application is expressly incorporated herein by reference for the purpose of disclosing the teachings contained therein that are relevant to the disclosure of this application. The content of every patent and / or application cited in this application is expressly incorporated herein by reference for the purpose of describing in full the disclosure of the cited patent and / or application. Applicant hereby discloses the content of every patent and / or application cited in this application, whether or not the content is repeated herein. The content of every patent and / or application cited in this application is expressly incorporated herein by reference for the purpose of disclosing the teachings contained therein that are relevant to the disclosure of this application. The content of every patent and / or application cited in this application is expressly incorporated herein by reference for the purpose of describing in full the disclosure of the cited patent and / or application. Applicant hereby discloses the content of every patent and / or application cited in this application, whether or not the content is repeated herein. The content of every patent and / or application cited in this application is expressly incorporated herein by reference for the purpose of disclosing the teachings contained therein that are relevant to the disclosure of this application. The content of every patent and / or application cited in this application is expressly incorporated herein by reference for the purpose of describing in full the disclosure of the cited patent and / or application.

Claims

1. A computer-implemented method of parsing multi-dimensional data to identify a work package to be processed, wherein the multi-dimensional data is mapped into one-dimensional data using a Z-order function, the method comprising: obtaining dimensions of the multi-dimensional data; obtaining information identifying a valid region of the multi-dimensional data, the valid region identifying a work package; determining at least a portion of a sequence within the one-dimensional data corresponding to a location within the multi-dimensional data that lies within the valid region, the determining comprising: determining, in accordance with the Z-order function, whether a location defined by a first value of the one-dimensional data lies within the valid region; in response to determining that the location defined by the first value does not lie within the valid region: calculating an overflow value that, when added to the first value, causes a least significant bit that is one in a binary representation of the first value to flip to zero; summing the first value and the overflow value to obtain a trial value; determining whether a location defined by the trial value lies within the valid region, thereby determining whether the trial value forms part of the sequence, wherein the sequence identifies a work package to be processed.

2. The method of claim 1, wherein the overflow value is equal to a power of two.

3. The method of claim 2, wherein calculating the overflow value comprises: identifying the least significant bit that is one in the binary representation of the first value; and generating the overflow value having a magnitude equal to a power of two represented by the least significant bit that is one.

4. The method of any one of the preceding claims, wherein the valid region is defined by a plurality of boundary values, one for each respective dimension of the multi-dimensional data, and wherein determining whether the location defined by the first value of the one-dimensional data lies within the valid region comprises: converting the first value to a multi-dimensional coordinate using a mapping defined by the Z-order function; and determining whether the multi-dimensional coordinate falls within a range defined by the plurality of boundary values.

5. The method of any one of claims 1 to 3, further comprising determining, in accordance with the Z-order function, that the location defined by the trial value does not lie within the valid region, thereby determining that the trial value does not form part of the sequence, and in response to the determining: identifying a least significant bit that is one in a binary representation of the trial value; calculating a further overflow value having a magnitude at least as great as a value represented by the least significant bit that is one of the trial value, and which, when added to the trial value, causes the least significant bit that is one of the trial value to flip to zero; summing the trial value and the further overflow value to obtain a further trial value; and determining whether a location defined by the further trial value lies within the valid region, thereby determining whether the further trial value forms part of the sequence.

6. The method of any one of claims 1 to 3, wherein calculating the overflow value comprises performing a bit inversion operation, an addition operation, and at least one bitwise comparison operation on the binary representation of the first value, thereby obtaining the overflow value. ​ 7. The method of any one of claims 1-3, wherein the first value is a first entry in the one-dimensional data, and wherein the method includes iterating through entries of the one-dimensional data in a sequential order, thereby determining the at least a portion of the sequence corresponding to locations within the multi-dimensional data that are within the active region.

8. The method of claim 7, wherein the at least a portion of the sequence is determined without testing a subset of values within the one-dimensional data to determine whether the subset of values define a location that is within the active region, wherein the subset of values includes at least values between the first value of the one-dimensional data and the trial value, exclusive of the first value and the trial value.

9. The method of any one of claims 1-3, wherein none of the values of the one-dimensional data between the first value of the one-dimensional data and the trial value, exclusive of the first value and the trial value, represent a location that is within the active region.

10. The method of any one of claims 1-3, wherein each dimension of the multi-dimensional data is equal to a power of two, and wherein at least one dimension of the active region is not equal to a power of two.

11. The method of any one of claims 1-3, wherein the multi-dimensional data represents a region of a scene, and the method further includes outputting at least some of the work packets identified by the sequence for processing, wherein the output work packets are used to render at least a portion of the scene.

12. The method of any one of claims 1-3, wherein for each mapped value of the one-dimensional data, the Z-order function maps alternating bits of a binary representation of the mapped value to corresponding coordinate values of the multi-dimensional data.

13. The method of any one of claims 1-3, wherein the Z-order function represents a Morton order function, and wherein the multi-dimensional data is 2D.

14. The method of any one of claims 1-3, wherein the computer-implemented method is part of a ray tracing system, and wherein the work packets identify ray tracing or shading operations.

15. The method of any one of claims 1-3, wherein the computer-implemented method is executed by a graphics processing unit (GPU).

16. The method of any one of claims 1-3, wherein the multi-dimensional data represents a multi-dimensional array space for storing thread groups, and wherein the active region represents an array of thread groups within the multi-dimensional array space, each thread group including identifying a plurality of work packets.

17. A processing unit for parsing multi-dimensional data to identify work packets to be processed, wherein the multi-dimensional data is mapped into one-dimensional data using a Z-order function, the processing unit configured to: obtain dimensions of the multi-dimensional data; obtain information identifying an active region of the multi-dimensional data, the active region identifying work packets; ​ ​ determining at least a portion of a sequence within the one-dimensional data corresponding to locations within the multi-dimensional data that lie in the active area, the processing unit being configured to perform the determining by: determining, in accordance with the Z-order function, whether a location defined by a first value of the one-dimensional data lies within the active area; in response to determining that the location defined by the first value does not lie within the active area: calculating an overflow value that, when added to the first value, causes a least significant bit that is one in a binary representation of the first value to flip to zero; summing the first value and the overflow value to obtain a trial value; and determining whether a location defined by the trial value lies within the active area, thereby determining whether the trial value forms part of the sequence, wherein the sequence identifies work packets to be processed.

18. The processing unit of claim 17, wherein the processing unit is a graphics processing unit, GPU, wherein the processing unit is included in hardware on an integrated circuit.

19. The processing unit of claim 17 or 18, wherein the processing unit is configured to calculate the overflow value using an operation selected from the group consisting of: a unary bitwise operation; a bitwise comparison operation; and an addition operation.

20. A non-transitory computer readable storage medium having stored thereon a computer readable description of a processing unit according to claim 17 or 18, the computer readable description, when processed in an integrated circuit manufacturing system, causing the integrated circuit manufacturing system to manufacture an integrated circuit embodying the processing unit.

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