Driving circuit, scanning circuit, display panel and electronic equipment

Abstract

The invention provides a driving circuit, a scanning circuit, a display panel and electronic equipment, and relates to the technical field of display driving. The driving circuit comprises a driving unit and a gating unit; the driving unit comprises a first driving input module, a second driving input module, a first driving pull-down module, a second driving pull-down module, a first driving output module and a second driving output module; and the gating unit comprises a gating control module, a gating pull-down module, a first gating output module and a second gating output module, so that the work of the driving circuit is completed through the cooperation of the driving unit and the gating unit, the circuit structure of the driving circuit is simplified, the occupied area of the scanning circuit is reduced, and the narrow frame design of the display panel is facilitated.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display driving, more particularly to a driving circuit, a scanning circuit, a display panel and an electronic device. BACKGROUND

[0002] An organic light-emitting display panel has the advantages of self-illumination, low driving voltage, high luminous efficiency, fast response speed, thinness, high contrast ratio and the like, and is widely used in mobile phones, computers, televisions, vehicle-mounted display devices, wearable devices and other display devices with display functions. The organic light-emitting display panel usually has a scanning circuit and a plurality of pixel units. The scanning circuit includes a plurality of driving circuits, and the pixel unit includes a pixel circuit and a light-emitting element. During the operation of the organic light-emitting display panel, the driving circuit generates a driving signal to drive the pixel circuit to work. The pixel circuit generates a driving current through an internal driving transistor, and the light-emitting element emits light in response to the driving current. The circuit structure of the existing driving circuit is relatively complex, which occupies a large area and is not conducive to the narrow-frame design of the display panel. SUMMARY

[0003] Therefore, the present application provides a driving circuit, a scanning circuit, a display panel and an electronic device, which effectively solve the technical problems existing in the prior art, simplify the circuit structure of the driving circuit, thereby reducing the occupied area of the scanning circuit, and are conducive to the narrow-frame design of the display panel.

[0004] To achieve the above object, the technical scheme provided by the present application is as follows:

[0005] A driving circuit, comprising a driving unit and a gating unit;

[0006] The driving unit comprises:

[0007] A first driving input module, which is electrically connected to at least an input signal terminal and a first clock signal terminal, and is connected in communication with a first node based on at least the signal control of the first clock signal terminal;

[0008] A second driving input module, which is electrically connected to at least the first node or the input signal terminal, and inputs a first level signal, and transmits the first level signal to a second node based on at least the signal control of the first node or the input signal terminal;

[0009] The first driving pull-down module is electrically connected with at least the first node and a second clock signal terminal, and couples a signal of the second clock signal terminal to the first node based on at least a signal control of the first node; the clock signals output by the first clock signal terminal and the second clock signal terminal have the same period and duty cycle and have a set phase difference;

[0010] The second driving pull-down module is electrically connected with at least the first node and the first clock signal terminal, and connects the first clock signal terminal and the second node based on at least a signal control of the first node.

[0011] The first driving output module is electrically connected with at least the first node and a first level terminal, and connects the first level terminal and a cascade output terminal of the driving circuit based on at least a signal control of the first node, wherein the first level signal and the first level terminal have the same level.

[0012] The second driving output module is electrically connected with at least the second node and the first clock signal terminal, and connects the first clock signal terminal and the cascade output terminal based on at least a signal control of the second node.

[0013] The gating unit comprises:

[0014] The gating control module is electrically connected with at least a gating control terminal and the second node, and connects the second node and a third node based on at least a signal control of the gating control terminal.

[0015] The gating pull-down module is electrically connected with at least the first clock signal terminal, and connects the first clock signal terminal and the third node at an end time of outputting a valid level by the cascade output terminal.

[0016] The first gating output module is electrically connected with at least the first clock signal terminal and the third node, and connects the first clock signal terminal and a gating output terminal of the gating unit based on at least a signal control of the third node.

[0017] The second gating output module is electrically connected with at least the first node and a first level terminal, and connects the first level terminal and the gating output terminal based on at least a signal control of the first node.

[0018] Based on the same inventive concept, the application further provides a scanning circuit, which comprises the above-described driving circuit.

[0019] Based on the same inventive concept, the present application also provides a display panel comprising the scanning circuit described above.

[0020] Based on the same inventive concept, the present application also provides an electronic device comprising the display panel described above.

[0021] Compared with the prior art, the technical solution provided by the present application has at least the following advantages:

[0022] The present application provides a driving circuit, a scanning circuit, a display panel and an electronic device. The driving circuit comprises a driving unit and a gating unit. The driving unit comprises a first driving input module, a second driving input module, a first driving pull-down module, a second driving pull-down module, a first driving output module and a second driving output module. The gating unit comprises a gating control module, a gating pull-down module, a first gating output module and a second gating output module. Thus, the work of the driving circuit is completed by the cooperation of the driving unit and the gating unit, the circuit structure of the driving circuit is simplified, thereby reducing the occupied area of the scanning circuit, which is conducive to the narrow frame design of the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced below. Obviously, the drawings in the following description are only embodiments of the present application, and those skilled in the art can obtain other drawings according to the provided drawings without creative labor.

[0024] Figure 1 A circuit diagram of a driving circuit provided for an embodiment of the present application;

[0025] Figure 2 Another circuit diagram of a driving circuit provided for an embodiment of the present application;

[0026] Figure 3 Another circuit diagram of a driving circuit provided for an embodiment of the present application;

[0027] Figure 4 Another circuit diagram of a driving circuit provided for an embodiment of the present application;

[0028] Figure 5 Another circuit diagram of a driving circuit provided for an embodiment of the present application;

[0029] Figure 6a A timing diagram provided for an embodiment of the present application;

[0030] Figure 6b Another timing diagram provided for an embodiment of the present application;

[0031] Figure 7 A circuit diagram of yet another drive circuit provided for embodiments of the present application;

[0032] Figure 8 A circuit diagram of yet another drive circuit provided for embodiments of the present application;

[0033] Figure 9 A circuit diagram of yet another drive circuit provided for embodiments of the present application;

[0034] Figure 10 A circuit diagram of yet another drive circuit provided for embodiments of the present application;

[0035] Figure 11 A circuit diagram of yet another drive circuit provided for embodiments of the present application;

[0036] Figure 12 A circuit diagram of yet another drive circuit provided for embodiments of the present application;

[0037] Figure 13 A circuit diagram of yet another drive circuit provided for embodiments of the present application;

[0038] Figure 14 A circuit diagram of yet another drive circuit provided for embodiments of the present application;

[0039] Figure 15 A circuit diagram of yet another drive circuit provided for embodiments of the present application;

[0040] Figure 16 A circuit diagram of yet another drive circuit provided for embodiments of the present application;

[0041] Figure 17 A circuit diagram of yet another drive circuit provided for embodiments of the present application;

[0042] Figure 18 A circuit diagram of yet another drive circuit provided for embodiments of the present application;

[0043] Figure 19 A circuit diagram of yet another drive circuit provided for embodiments of the present application;

[0044] Figure 20 A circuit diagram of yet another drive circuit provided for embodiments of the present application;

[0045] Figure 21 A circuit diagram of yet another drive circuit provided for embodiments of the present application;

[0046] Figure 22 A circuit diagram of yet another drive circuit provided for embodiments of the present application;

[0047] Figure 23 A circuit diagram of another driving circuit provided for an embodiment of the present application;

[0048] Figure 24 A circuit diagram of a scanning circuit provided for an embodiment of the present application;

[0049] Figure 25 A timing diagram of each clock signal line provided for an embodiment of the present application;

[0050] Figure 26 A partial structural schematic diagram of a display panel provided for an embodiment of the present application;

[0051] Figure 27 A partial structural schematic diagram of another display panel provided for an embodiment of the present application;

[0052] Figure 28 A structural schematic diagram of an electronic device provided for an embodiment of the present application.

[0053] Reference signs:

[0054] 1-electronic device; 10-scanning circuit; 11-repetition circuit unit; 100-driving circuit; 100a-driving unit; 100b-gating unit; 101-first driving circuit; 102-second driving circuit; 103-third driving circuit; 104-fourth driving circuit; 1000-display panel; 111-first driving input module; 112-second driving input module; 121-first driving pull-down module; 122-second driving pull-down module; 131-first driving output module; 132-second driving output module; 140-coupling module; 150-gating control module; 160-gating pull-down module; 171-first gating output module; 172-second gating output module; IN-input signal terminal; CK-first clock signal terminal; XCK-second clock signal terminal; Ctrl-gating control terminal; N1-first node; N2-second node; N3-third node; VG1-first level signal; VGL-first level terminal; VGK-constant open level terminal; OUT-cascaded output terminal; OUTx-gating output terminal; T1-first transistor; T2-second transistor; T3-third transistor; T4-fourth transistor; T5-fifth transistor; T6-sixth transistor; T7-seventh transistor; T8-eighth transistor; T9-ninth transistor; T10-tenth transistor; T11-eleventh transistor; T12-twelfth transistor; T13-thirteenth transistor; T14-fourteenth transistor; T15-fifteenth transistor; T16-sixteenth transistor; M1-first voltage stabilizing transistor; M2-second voltage stabilizing transistor; M3-third voltage stabilizing transistor; M4-fourth voltage stabilizing transistor; M5-fifth voltage stabilizing transistor; C1-first capacitor; C2-second capacitor; C3-third capacitor; Cw-maintenance capacitor; S1-pull-down stage; S2-input stage; S3-output stage; S4-maintenance stage; S5-transition stage; S6-end stage; VCK1-first clock signal line; VCK2-second clock signal line; VCK3-third clock signal line; VCK4-fourth clock signal line. DETAILED DESCRIPTION

[0055] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0056] As described in the background, the organic light-emitting display panel has the advantages of self-illumination, low driving voltage, high luminous efficiency, fast response speed, thinness, high contrast ratio and the like, and is widely used in mobile phones, computers, televisions, vehicle-mounted display devices, wearable devices and other display devices with display functions. The organic light-emitting display panel usually has a scanning circuit and a plurality of pixel units, the scanning circuit includes a plurality of driving circuits, and the pixel unit includes a pixel circuit and a light-emitting element. During the working process of the organic light-emitting display panel, the driving circuit generates a driving signal to drive the pixel circuit to work; the pixel circuit generates a driving current through an internal driving transistor, and the light-emitting element emits light in response to the driving current. The circuit structure of the existing driving circuit is relatively complex, which occupies a large area and is not conducive to the narrow frame design of the display panel.

[0057] Based on this, the embodiments of the present application provide a driving circuit, a scanning circuit, a display panel and an electronic device, which effectively solve the technical problems existing in the prior art, simplify the circuit structure of the driving circuit, thereby reducing the occupied area of the scanning circuit, and are conducive to the narrow frame design of the display panel.

[0058] To achieve the above-mentioned purpose, the technical solutions provided by the embodiments of the present application are as follows, which are specifically combined Figures 1 to 28 The technical solutions provided by the embodiments of the present application are described in detail.

[0059] Combined with Figure 1 and Figure 2 As shown in Figure 1 A circuit diagram of a driving circuit provided by an embodiment of the present application, Figure 2 A circuit diagram of another driving circuit provided by an embodiment of the present application. The embodiment of the present application provides a driving circuit 100, which includes a driving unit 100a and a gating unit 100b; the driving unit 100a includes: a first driving input module 111, which is electrically connected with at least an input signal end IN and a first clock signal end CK, and is connected in communication with a first node N1 based on at least the signal control of the first clock signal end CK. A second driving input module 112, which is electrically connected with at least the first node N1 (as shown in Figure 1 ) or the input signal end IN (as shown in Figure 2The first node N1 and the input signal terminal IN are electrically connected, and the first level signal VG1 is input into the second node N2 based on the signal of the first node N1 or the input signal terminal IN. The first driving pull-down module 121 is electrically connected to the first node N1 and the second clock signal terminal XCK, and the signal of the second clock signal terminal XCK is coupled to the first node N1 based on the signal of the first node N1. The first clock signal terminal CK and the second clock signal terminal XCK output clock signals with the same period and duty cycle and a set phase difference. The second driving pull-down module 122 is electrically connected to the first node N1 and the first clock signal terminal CK, and the first clock signal terminal CK is connected to the second node N2 based on the signal of the first node N1. The first driving output module 131 is electrically connected to the first node N1 and the first level terminal VGL, and the first level terminal VGL is connected to the cascade output terminal OUT of the driving circuit 100 based on the signal of the first node N1. The first level signal VG1 and the first level terminal VGL have the same level, and the first level signal VG1 can be the first level terminal VGL or the corresponding level signal output by the second clock signal terminal XCK. The second driving output module 132 is electrically connected to the second node N2 and the first clock signal terminal CK, and the first clock signal terminal CK is connected to the cascade output terminal OUT based on the signal of the second node N2.

[0060] The gate unit 100b provided by the embodiment of the application comprises: a gate control module 150, which is electrically connected to at least a gate control end Ctrl and the second node N2, and is connected between the second node N2 and the third node N3 based on at least the signal control of the gate control end Ctrl; a gate pull-down module 160, which is electrically connected to at least the first clock signal end CK, and is connected between the first clock signal end CK and the third node N3 at the end of the output of the valid level of the cascade output end OUT; a first gate output module 171, which is electrically connected to at least the first clock signal end CK and the third node N3, and is connected between the first clock signal end CK and the gate output end OUTx of the gate unit 100b based on at least the signal control of the third node N3; and a second gate output module 172, which is electrically connected to at least the first node N1 and the first level end VGL, and is connected between the first level end VGL and the gate output end OUTx based on at least the signal control of the first node N1. Thus, the driving circuit 100 cooperates with the first driving input module 111, the second driving input module 112, the first driving pull-down module 121, the second driving pull-down module 122, the first driving output module 131, the second driving output module 132, the gate control module 150, the gate pull-down module 160, the first gate output module 171, and the second gate output module 172 to complete the work, which simplifies the circuit structure of the driving circuit 100, thereby reducing the occupied area of the scanning circuit and being conducive to the narrow-frame design of the display panel.

[0061] Reference Figure 3As shown in the circuit diagram of another driving circuit provided by the embodiment of the present application, the driving circuit 100 provided by the embodiment of the present application further comprises a coupling module 140, which is electrically connected with the second node N2 and the first clock signal terminal CK, and is configured to couple the voltage level output by the first clock signal terminal CK to the second node N2 at the end of the output of the effective level by the cascaded output terminal OUT, so as to control the voltage adjustment direction of the second node N2 to be the same as the polarity of the level output by the first clock signal terminal CK. That is, when the level output by the first clock signal terminal CK is a low level, the coupling module 140 couples the low level voltage output by the first clock signal terminal CK to the second node N2 at the end of the output of the effective level by the cascaded output terminal OUT, the level of the second node N2 remains the same as that in the output stage, that is, a low level, and the voltage of the second node N2 is adjusted to a lower voltage; or, when the level output by the first clock signal terminal CK is a high level, the coupling module 140 couples the high level voltage output by the first clock signal terminal CK to the second node N2 at the end of the output of the effective level by the cascaded output terminal OUT, the level of the second node N2 remains the same as that in the output stage, that is, a high level, and the voltage of the second node N2 is adjusted to a higher voltage. In this way, the second node N2 can control the second driving output module 132 to better connect the first clock signal terminal CK and the cascaded output terminal OUT, so as to more fully output the voltage output by the first clock signal terminal CK to the cascaded output terminal OUT, thereby avoiding the problem of step voltage when the cascaded output terminal OUT outputs an invalid level. The "step voltage" is the voltage between the voltage of the effective level and the voltage of the invalid level output by the cascaded output terminal OUT.

[0062] In some embodiments, the operation of the driving circuit 100 provided by the embodiment of the present application can be divided into six stages in time sequence, which are a pull-down stage, an input stage, an output stage, a maintenance stage, a transition stage and an end stage. Based on the above description of the driving circuit 100 provided by the embodiment of the present application, the working processes of the pull-down stage, the input stage, the output stage, the maintenance stage, the transition stage and the end stage of the driving circuit 100 are as follows. Figure 3 As shown in the driving circuit 100, when the second driving input module 112 is electrically connected with the first node N1, and the control signal terminal Ctrl is in a state of controlling the gating control module 150 to connect the second node N2 and the third node N3, the scanning circuit is in a high-frequency refreshing state (at this time, the output waveforms of the cascaded output terminal OUT and the gating output terminal OUTx are consistent), and the working processes of the pull-down stage, the input stage, the output stage, the maintenance stage, the transition stage and the end stage of the driving circuit 100 are as follows.

[0063] In the pull-down phase, the first driving input module 111 connects the input signal end IN with the first node N1 based on the signal control of the first clock signal end CK; the second driving pull-down module 122 connects the first clock signal end CK with the second node N2 based on the signal control of the first node N1. The second driving output module 132 connects the first clock signal end CK with the cascade output end OUT based on the signal control of the second node N2, and the cascade output end OUT outputs an invalid level at this time. Meanwhile, since the second node N2 and the third node N3 are connected, the first gating output module 171 connects the first clock signal end CK with the gating output end OUTx based on the signal control of the third node N3, and the gating output end OUTx outputs an invalid level at this time. It should be noted that the level output by the cascade output end OUT is an effective level or an invalid level, which is determined by the state of the transistor in the next stage driving circuit 100 connected thereto. The level output by the cascade output end OUT is an effective level when it controls the transistor connected in the next stage driving circuit 100 to be turned on, and is an invalid level when it controls the transistor connected in the next stage driving circuit 100 to be turned off. In addition, the level output by the gating output end OUTx is an effective level or an invalid level, which is determined by the pixel circuit connected to the driving circuit 100. The level output by the gating output end OUTx is an effective level when it drives the transistor connected in the pixel circuit to be turned on, and is an invalid level when it drives the transistor connected in the pixel circuit to be turned off.

[0064] In the input phase, the first driving input module 111 connects the input signal end IN with the first node N1 based on the signal control of the first clock signal end CK; the second driving input module 112 transmits the first level signal VG1 to the second node N2 based on the signal control of the first node N1; the second driving output module 132 connects the first clock signal end CK with the cascade output end OUT based on the signal control of the second node N2, and the cascade output end OUT outputs an invalid level at this time. Meanwhile, since the second node N2 and the third node N3 are connected, the first gating output module 171 connects the first clock signal end CK with the gating output end OUTx based on the signal control of the third node N3, and the gating output end OUTx outputs an invalid level at this time.

[0065] In the output phase, the first driving input module 111 disconnects the input signal terminal IN from the first node N1 based on the signal control of the first clock signal terminal CK, and the first node N1 keeps the voltage in the input phase without voltage input; thus, the second driving input module 112 transmits the first level signal VG1 to the second node N2 based on the signal control of the first node N1; the second driving output module 132 connects the first clock signal terminal CK and the cascade output terminal OUT based on the signal control of the second node N2, and the cascade output terminal OUT outputs the effective level at this time. At the same time, since the second node N2 and the third node N3 are connected, the first gating output module 171 connects the first clock signal terminal CK and the gating output terminal OUTx based on the signal control of the third node N3, and the gating output terminal OUTx outputs the effective level at this time.

[0066] In the holding phase, the first node N1 keeps the voltage in the output phase without other voltage input, thus the second driving input module 112 transmits the first level signal VG1 to the second node N2 based on the signal control of the first node N1; the second driving output module 132 connects the first clock signal terminal CK and the cascade output terminal OUT based on the signal control of the second node N2, and the cascade output terminal OUT maintains the output effective level at this time. At the same time, since the second node N2 and the third node N3 are connected, the first gating output module 171 connects the first clock signal terminal CK and the gating output terminal OUTx based on the signal control of the third node N3, and the gating output terminal OUTx maintains the output effective level at this time.

[0067] In the transition stage, the first driving input module 111 controls the input signal terminal IN to be connected with the first node N1 based on the signal of the first clock signal terminal CK, at this time, the level of the input signal terminal IN is opposite to the level in the input stage; the second driving pull-down module 122 controls the first clock signal terminal CK to be connected with the second node N2 based on the signal of the first node N1; the second driving output module 132 controls the first clock signal terminal CK to be connected with the cascade output terminal OUT based on the signal of the second node N2, at this time, the cascade output terminal OUT outputs invalid level. At the same time, the first gating output module 171 controls the first clock signal terminal CK to be connected with the gating output terminal OUTx based on the signal of the third node N3, at this time, the gating output terminal OUTx outputs invalid level. In addition, the coupling module 140 couples the voltage level output by the first clock signal terminal CK to the second node N2 to adjust the voltage of the second node N2, wherein when the first clock signal terminal CK outputs low voltage to the second node N2, the voltage of the second node N2 is adjusted to be lower; or when the first clock signal terminal CK outputs high voltage to the second node N2, the voltage of the second node N2 is adjusted to be higher, thereby the second driving output module 132 can be better controlled by the second node N2 to connect the first clock signal terminal CK and the cascade output terminal OUT, so that the voltage output by the first clock signal terminal CK can be more fully output to the cascade output terminal OUT, to avoid the problem of step voltage when the cascade output terminal OUT outputs invalid level.

[0068] In the end stage, the first driving pull-down module 121 controls the signal of the second clock signal terminal XCK to be coupled to the first node N1 based on the signal of the first node N1, to adjust the voltage of the first node N1, the adjustment direction of the voltage of the first node N1 is the same as the polarity of the level of the first node N1 in the transition stage, thereby ensuring that the second driving input module 112 is in a completely stopped working state, and ensuring that the first driving pull-down module 121, the second driving pull-down module 122, the first driving output module 131 and the second gating output module 172 are fully working, and the cascade output terminal OUT and the gating output terminal OUTx maintain invalid level. That is, when the level of the first node N1 in the transition stage is low, the signal of the second clock signal terminal XCK is coupled to the first node N1, which can adjust the voltage of the first node N1 to be lower; or when the level of the first node N1 in the transition stage is high, the signal of the second clock signal terminal XCK is coupled to the first node N1, which can adjust the voltage of the first node N1 to be higher.

[0069] Continuing to refer to Figure 3The driving circuit 100 shown, when the second driving input module 112 is electrically connected with the first node N1, and the control end Ctrl is in a state of controlling the gating control module 150 to disconnect the second node N2 and the third node N3, the scanning circuit is in a low-frequency refreshing state (at this time, the gating output end OUTx keeps outputting an invalid level), wherein the working processes of the pull-down stage, the input stage, the output stage, the maintaining stage, the transition stage and the end stage of the driving circuit 100 are respectively as follows:

[0070] In the pull-down stage, the first driving input module 111 connects the input signal end IN with the first node N1 based on the signal control of the first clock signal end CK; the second driving pull-down module 122 connects the first clock signal end CK with the second node N2 based on the signal control of the first node N1. The second driving output module 132 connects the first clock signal end CK with the cascade output end OUT based on the signal control of the second node N2, and the cascade output end OUT outputs an invalid level at this time. Meanwhile, the gating pull-down module 160 connects the first clock signal end CK with the third node N3 to make the third node N3 control the first gating output module 171 to connect the first clock signal end CK with the gating output end OUTx; and the second gating output module 172 connects the first level end VGL with the gating output end OUTx based on the signal control of the first node N1, so that the gating output end OUTx outputs an invalid level at this time.

[0071] In the input stage, the first driving input module 111 connects the input signal end IN with the first node N1 based on the signal control of the first clock signal end CK; the second driving input module 112 transmits the first level signal VG1 to the second node N2 based on the signal control of the first node N1; the second driving output module 132 connects the first clock signal end CK with the cascade output end OUT based on the signal control of the second node N2, and the cascade output end OUT outputs an invalid level at this time. Meanwhile, the gating pull-down module 160 disconnects the first clock signal end CK and the third node N3, the third node N3 keeps the same voltage as in the pull-down stage without voltage input, the third node N3 controls the first gating output module 171 to connect the first clock signal end CK with the gating output end OUTx, and the gating output end OUTx outputs an invalid level at this time.

[0072] In the output stage, the first driving input module 111 disconnects the input signal terminal IN from the first node N1 based on the signal control of the first clock signal terminal CK, and the first node N1 keeps the voltage in the input stage without voltage input; thus, the second driving input module 112 transmits the first level signal VG1 to the second node N2 based on the signal control of the first node N1; the second driving output module 132 connects the first clock signal terminal CK and the cascade output terminal OUT based on the signal control of the second node N2, and the cascade output terminal OUT outputs the effective level at this time. Meanwhile, the gate output terminal OUTx keeps the same voltage as in the input stage without voltage input, and the gate output terminal OUTx continues to output the ineffective level at this time.

[0073] In the maintenance stage, the first node N1 keeps the voltage in the output stage without other voltage input, thus, the second driving input module 112 transmits the first level signal VG1 to the second node N2 based on the signal control of the first node N1; the second driving output module 132 connects the first clock signal terminal CK and the cascade output terminal OUT based on the signal control of the second node N2, and the cascade output terminal OUT maintains the output of the effective level at this time. Meanwhile, the gate output terminal OUTx keeps the same voltage as in the output stage without voltage input, and the gate output terminal OUTx maintains the output of the ineffective level at this time.

[0074] In the transition stage, the first driving input module 111 controls the input signal terminal IN to be connected with the first node N1 based on the signal of the first clock signal terminal CK, at this time, the level of the input signal terminal IN is opposite to the level in the input stage; the second driving pull-down module 122 controls the first clock signal terminal CK to be connected with the second node N2 based on the signal of the first node N1; the second driving output module 132 controls the first clock signal terminal CK to be connected with the cascade output terminal OUT based on the signal of the second node N2, at this time, the cascade output terminal OUT outputs an invalid level. At the same time, the second gating output module 172 controls the first level terminal VGL to be connected with the gating output terminal OUTx based on the signal of the first node N1, so that the gating output terminal OUTx continues to output an invalid level at this time. And the coupling module 140 couples the level voltage output by the first clock signal terminal CK to the second node N2 to adjust the voltage of the second node N2, wherein when the first clock signal terminal CK outputs a low level voltage to the second node N2, the voltage of the second node N2 is adjusted to a lower voltage; or when the first clock signal terminal CK outputs a high level voltage to the second node N2, the voltage of the second node N2 is adjusted to a higher voltage, thereby the second driving output module 132 can be better controlled by the second node N2 to connect the first clock signal terminal CK and the cascade output terminal OUT, so that the voltage output by the first clock signal terminal CK can be more fully output to the cascade output terminal OUT, to avoid the problem of step voltage when the cascade output terminal OUT outputs an invalid level.

[0075] In the end stage, the first driving pull-down module 121 controls the signal of the second clock signal terminal XCK to be coupled to the first node N1 based on the signal of the first node N1, to adjust the voltage of the first node N1, the adjustment direction of the voltage of the first node N1 is the same as the polarity of the level of the first node N1 in the transition stage, thereby ensuring that the second driving input module 112 is in a completely stopped working state, and ensuring that the first driving pull-down module 121, the second driving pull-down module 122, the first driving output module 131 and the second gating output module 172 are fully working, and the cascade output terminal OUT and the gating output terminal OUTx both maintain an invalid level. That is, when the level of the first node N1 in the transition stage is a low level, the signal of the second clock signal terminal XCK is coupled to the first node N1, which can adjust the voltage of the first node N1 to be lower; or when the level of the first node N1 in the transition stage is a high level, the signal of the second clock signal terminal XCK is coupled to the first node N1, which can adjust the voltage of the first node N1 to be higher. Thereby, the state of the gating control module 150 is controlled by the gating control terminal Ctrl to adjust the timing of the connection between the second node N2 and the third node N3, to complete the switching of high-frequency refresh and low-frequency refresh of the scan circuit.

[0076] ReferenceFigure 4 Fig. 19 is a circuit diagram of another driving circuit provided by the embodiments of the present application, wherein when the second driving input module 112 is electrically connected with the input signal terminal IN, and the control signal terminal Ctrl is in a state of controlling the gating control module 150 to connect the second node N2 and the third node N3, the scanning circuit is in a high-frequency refreshing state (at this time, the output waveforms of the cascade output terminal OUT and the gating output terminal OUTx are consistent), and the working processes of the pull-down stage, the input stage, the output stage, the maintaining stage, the transition stage and the end stage of the driving circuit 100 are as follows:

[0077] In the pull-down stage, the first driving input module 111 controls the input signal terminal IN to be connected with the first node N1 based on the signal of the first clock signal terminal CK. The second driving pull-down module 122 controls the first clock signal terminal CK to be connected between the second node N2 based on the signal of the first node N1. The second driving output module 132 controls the first clock signal terminal CK to be connected with the cascade output terminal OUT based on the signal of the second node N2, and the cascade output terminal OUT outputs an invalid level at this time. Meanwhile, since the second node N2 and the third node N3 are connected, the first gating output module 171 controls the first clock signal terminal CK to be connected with the gating output terminal OUTx based on the signal of the third node N3, and the gating output terminal OUTx outputs an invalid level at this time.

[0078] In the input stage, the first driving input module 111 controls the input signal terminal IN to be connected with the first node N1 based on the signal of the first clock signal terminal CK. Meanwhile, the second driving input module 112 controls the first voltage signal VG1 to be transmitted to the second node N2 based on the signal of the input signal terminal IN. The second driving output module 132 controls the first clock signal terminal CK to be connected with the cascade output terminal OUT based on the signal of the second node N2, and the cascade output terminal OUT outputs an invalid level at this time. Alternatively, in the input stage, the first driving input module 111 controls the input signal terminal IN to be connected with the first node N1 based on the signal of the first clock signal terminal CK. The second node N2 maintains the same voltage as that in the pull-down stage without voltage input. The second driving output module 132 controls the first clock signal terminal CK to be connected with the cascade output terminal OUT based on the signal of the second node N2, and the cascade output terminal OUT outputs an invalid level at this time. Meanwhile, since the second node N2 and the third node N3 are connected, the first gating output module 171 controls the first clock signal terminal CK to be connected with the gating output terminal OUTx based on the signal of the third node N3, and the gating output terminal OUTx outputs an invalid level at this time.

[0079] In the output phase, the first driving input module 111 disconnects the input signal terminal IN from the first node N1 based on the signal control of the first clock signal terminal CK, and the first node N1 keeps the voltage in the input phase without voltage input. The second driving input module 112 transmits the first level signal VG1 to the second node N2 based on the signal control of the input signal terminal IN; the second driving output module 132 connects the first clock signal terminal CK and the cascade output terminal OUT based on the signal control of the second node N2, and the cascade output terminal OUT outputs the effective level at this time. At the same time, since the second node N2 and the third node N3 are connected, the first gating output module 171 connects the first clock signal terminal CK and the gating output terminal OUTx based on the signal control of the third node N3, and the gating output terminal OUTx outputs the effective level at this time.

[0080] In the maintenance phase, the first node N1 keeps the voltage in the output phase without other voltage input, and the second driving input module 112 stops transmitting the first level signal VG1 to the second node N2 based on the signal control of the input signal terminal IN at this time, and the second node N2 keeps the same voltage as that in the output phase without voltage input; the second driving output module 132 connects the first clock signal terminal CK and the cascade output terminal OUT based on the signal control of the second node N2, and the cascade output terminal OUT keeps outputting the effective level at this time. At the same time, since the second node N2 and the third node N3 are connected, the first gating output module 171 connects the first clock signal terminal CK and the gating output terminal OUTx based on the signal control of the third node N3, and the gating output terminal OUTx keeps outputting the effective level at this time.

[0081] In the transition stage, the first driving input module 111 controls the input signal terminal IN to be connected with the first node N1 based on the signal of the first clock signal terminal CK, at this time, the level of the input signal terminal IN is opposite to the level in the input stage; the second driving pull-down module 122 controls the first clock signal terminal CK to be connected with the second node N2 based on the signal of the first node N1; the second driving output module 132 controls the first clock signal terminal CK to be connected with the cascade output terminal OUT based on the signal of the second node N2, at this time, the cascade output terminal OUT outputs invalid level. At the same time, since the second node N2 and the third node N3 are connected, the first gating output module 171 controls the first clock signal terminal CK to be connected with the gating output terminal OUTx based on the signal of the third node N3, at this time, the gating output terminal OUTx outputs invalid level. In addition, the coupling module 140 couples the voltage level output by the first clock signal terminal CK to the second node N2 to adjust the voltage of the second node N2, wherein when the first clock signal terminal CK outputs low voltage to the second node N2, the voltage of the second node N2 is adjusted to be lower; or when the first clock signal terminal CK outputs high voltage to the second node N2, the voltage of the second node N2 is adjusted to be higher, thereby the second driving output module 132 can be better controlled by the second node N2 to connect the first clock signal terminal CK and the cascade output terminal OUT, so that the voltage output by the first clock signal terminal CK can be more fully output to the cascade output terminal OUT, to avoid the problem of step voltage when the cascade output terminal OUT outputs invalid level.

[0082] In the end stage, the first driving pull-down module 121 controls the signal of the second clock signal terminal XCK to be coupled to the first node N1 based on the signal of the first node N1, to adjust the voltage of the first node N1, the adjustment direction of the voltage of the first node N1 is the same as the polarity of the level of the first node N1 in the transition stage, thereby ensuring the sufficient work of the first driving pull-down module 121, the second driving pull-down module 122, the first driving output module 131 and the second gating output module 172, the cascade output terminal OUT and the gating output terminal OUTx maintain invalid level. That is, when the level of the first node N1 in the transition stage is low, the signal of the second clock signal terminal XCK is coupled to the first node N1, which can adjust the voltage of the first node N1 to be lower; or, when the level of the first node N1 in the transition stage is high, the signal of the second clock signal terminal XCK is coupled to the first node N1, which can adjust the voltage of the first node N1 to be higher.

[0083] Continuing to refer to Figure 4The driving circuit 100 shown, when the second driving input module 112 is electrically connected with the first node N1, and the control end Ctrl is in a state of controlling the gating control module 150 to disconnect the second node N2 and the third node N3, the scanning circuit is in a low-frequency refreshing state (at this time, the gating output end OUTx keeps outputting an invalid level), wherein the working processes of the pull-down stage, the input stage, the output stage, the maintaining stage, the transition stage and the end stage of the driving circuit 100 are respectively as follows:

[0084] In the pull-down stage, the first driving input module 111 is connected with the first node N1 based on the signal control of the first clock signal end CK. The second driving pull-down module 122 is connected between the first clock signal end CK and the second node N2 based on the signal control of the first node N1. The second driving output module 132 is connected between the first clock signal end CK and the cascade output end OUT based on the signal control of the second node N2, and the cascade output end OUT outputs an invalid level at this time. At the same time, the gating pull-down module 160 is connected between the first clock signal end CK and the third node N3, so that the third node N3 controls the first gating output module 171 to connect the first clock signal end CK and the gating output end OUTx; and the second gating output module 172 is connected between the first level end VGL and the gating output end OUTx based on the signal control of the first node N1, so that the gating output end OUTx outputs an invalid level at this time.

[0085] In the input stage, the first driving input module 111 is connected with the first node N1 based on the signal control of the first clock signal end CK; at the same time, the second driving input module 112 transmits the first level signal VG1 to the second node N2 based on the signal control of the input signal end IN. The second driving output module 132 is connected between the first clock signal end CK and the cascade output end OUT based on the signal control of the second node N2, and the cascade output end OUT outputs an invalid level at this time. Alternatively, in the input stage, the first driving input module 111 is connected with the first node N1 based on the signal control of the first clock signal end CK; the second node N2 has no voltage input and maintains the same voltage as in the pull-down stage. The second driving output module 132 is connected between the first clock signal end CK and the cascade output end OUT based on the signal control of the second node N2, and the cascade output end OUT outputs an invalid level at this time. At the same time, since the second node N2 and the third node N3 are connected, the first gating output module 171 is connected between the first clock signal end CK and the gating output end OUTx based on the signal control of the third node N3, and the gating output end OUTx outputs an invalid level at this time.

[0086] In the output phase, the first driving input module 111 disconnects the input signal terminal IN from the first node N1 based on the signal control of the first clock signal terminal CK, and the first node N1 keeps the voltage in the input phase without voltage input. The second driving input module 112 transmits the first level signal VG1 to the second node N2 based on the signal control of the input signal terminal IN; the second driving output module 132 connects the first clock signal terminal CK and the cascade output terminal OUT based on the signal control of the second node N2, and the cascade output terminal OUT outputs the effective level at this time. Meanwhile, the gate output terminal OUTx keeps the same voltage as in the input phase without voltage input, and the gate output terminal OUTx continues to output the ineffective level at this time.

[0087] In the maintenance phase, the first node N1 keeps the voltage in the output phase without other voltage input, and the second driving input module 112 stops transmitting the first level signal VG1 to the second node N2 based on the signal control of the input signal terminal IN at this time, and the second node N2 keeps the same voltage as in the output phase without voltage input; the second driving output module 132 connects the first clock signal terminal CK and the cascade output terminal OUT based on the signal control of the second node N2, and the cascade output terminal OUT keeps outputting the effective level at this time. Meanwhile, the gate output terminal OUTx keeps the same voltage as in the output phase without voltage input, and the gate output terminal OUTx keeps outputting the ineffective level at this time.

[0088] In the transition stage, the first driving input module 111 controls the input signal terminal IN to be connected with the first node N1 based on the signal of the first clock signal terminal CK, at this time, the level of the input signal terminal IN is opposite to the level in the input stage; the second driving pull-down module 122 controls the first clock signal terminal CK to be connected with the second node N2 based on the signal of the first node N1; the second driving output module 132 controls the first clock signal terminal CK to be connected with the cascade output terminal OUT based on the signal of the second node N2, at this time, the cascade output terminal OUT outputs invalid level. At the same time, the second gating output module 172 controls the first level terminal VGL to be connected with the gating output terminal OUTx based on the signal of the first node N1, so that the gating output terminal OUTx continues to output invalid level at this time. And the coupling module 140 couples the level voltage output by the first clock signal terminal CK to the second node N2 to adjust the voltage of the second node N2, wherein when the first clock signal terminal CK outputs low level voltage to the second node N2, the voltage of the second node N2 is adjusted to be lower voltage; or when the first clock signal terminal CK outputs high level voltage to the second node N2, the voltage of the second node N2 is adjusted to be higher voltage, thereby the second driving output module 132 can be better controlled by the second node N2 to connect the first clock signal terminal CK and the cascade output terminal OUT, so that the voltage output by the first clock signal terminal CK can be more fully output to the cascade output terminal OUT, to avoid the problem of step voltage when the cascade output terminal OUT outputs invalid level.

[0089] In the end stage, the first driving pull-down module 121 controls the signal of the second clock signal terminal XCK to be coupled to the first node N1 based on the signal of the first node N1, to adjust the voltage of the first node N1, the adjustment direction of the voltage of the first node N1 is the same as the polarity of the level of the first node N1 in the transition stage, thereby ensuring the sufficient work of the first driving pull-down module 121, the second driving pull-down module 122, the first driving output module 131 and the second gating output module 172, the cascade output terminal OUT and the gating output terminal OUT maintain output invalid level. That is, when the level of the first node N1 in the transition stage is low, the signal of the second clock signal terminal XCK is coupled to the first node N1, which can adjust the voltage of the first node N1 to be lower; or, when the level of the first node N1 in the transition stage is high, the signal of the second clock signal terminal XCK is coupled to the first node N1, which can adjust the voltage of the first node N1 to be higher.

[0090] Reference Figure 5As shown in FIG. 1, the first driving input module 111 provided by the embodiment of the present application includes a first transistor T1, a gate of the first transistor T1 is electrically connected with the first clock signal end CK, a first end of the first transistor T1 is electrically connected with the input signal end IN, and a second end of the first transistor T1 is electrically connected with the first node N1. The first driving pull-down module 121 provided by the embodiment of the present application includes a second transistor T2 and a second capacitor C2, a gate of the second transistor T2 is electrically connected with the first node N1, a first end of the second transistor T2 is electrically connected with the second clock signal end XCK, a second end of the second transistor T2 is electrically connected with a first plate of the second capacitor C2, and a second plate of the second capacitor C2 is electrically connected with the first node N1. The first driving output module 131 provided by the embodiment of the present application includes a fourth transistor T4, a gate of the fourth transistor T4 is electrically connected with the first node N1, a first end of the fourth transistor T4 is electrically connected with the first level end VGL, and a second end of the fourth transistor T4 is electrically connected with the cascade output end OUT.

[0091] The second driving input module 112 provided by the embodiment of the present application includes a fifth transistor T5, a gate of the fifth transistor T5 is electrically connected with the input signal end IN, a first end of the fifth transistor T5 is connected with the first level signal VG1, and a second end of the fifth transistor T5 is electrically connected with the second node N2. The second driving pull-down module 122 provided by the embodiment of the present application includes an eleventh transistor T11, a gate of the eleventh transistor T11 is electrically connected with the first node N1, a first end of the eleventh transistor T11 is electrically connected with the first clock signal end CK, and a second end of the eleventh transistor T11 is electrically connected with the second node N2. The second driving output module 132 provided by the embodiment of the present application includes a twelfth transistor T12, a gate of the twelfth transistor T12 is electrically connected with the second node N2, a first end of the twelfth transistor T12 is electrically connected with the first clock signal end CK, and a second end of the twelfth transistor T12 is electrically connected with the cascade output end OUT. In addition, the coupling module 140 provided by the embodiment of the present application includes a first capacitor C1, a first plate of the first capacitor C1 is electrically connected with the first clock signal end CK, and a second plate of the first capacitor C1 is electrically connected with the second node N2.

[0092] Continue as Figure 5As shown, the gate of the thirteenth transistor T13 is electrically connected with the gate control end Ctrl, the first end of the thirteenth transistor T13 is electrically connected with the second node N2, and the second end of the thirteenth transistor T13 is electrically connected with the third node N3. The gate of the fourteenth transistor T14 is electrically connected with the first node N1, the first end of the fourteenth transistor T14 is electrically connected with the first clock signal end CK, and the second end of the fourteenth transistor T14 is electrically connected with the third node N3. The gate of the fifteenth transistor T15 is electrically connected with the third node N3, the first end of the fifteenth transistor T15 is electrically connected with the first clock signal end CK, the second end of the fifteenth transistor T15 is electrically connected with the gate control end OUTx, the first plate of the third capacitor C3 is electrically connected with the first clock signal end CK, and the second plate of the third capacitor C3 is electrically connected with the third node N3. In addition, the gate of the sixteenth transistor T16 is electrically connected with the first node N1, one end of the sixteenth transistor T16 is electrically connected with the first voltage level end VGL, and the second end of the sixteenth transistor T16 is electrically connected with the gate control end OUTx.

[0093] In some embodiments, the signal control state of the fifth transistor T5 in the second drive input module 112 provided in this application embodiment based on the first node N1 or the input signal terminal IN is opposite to the signal control state of the transistors (transistors electrically connected to the first node N1) in the second drive pull-down module 122, the first drive pull-down module 121, and the first drive output module 131 based on the first node N1. Specifically, when the fifth transistor T5 in the second drive input module 112 starts working based on the signal control of the first node N1, the transistors in the second drive pull-down module 122, the first drive pull-down module 121, and the first drive output module 131 stop working based on the signal control of the first node N1; or, when the fifth transistor T5 in the second drive input module 112 stops working based on the signal control of the first node N1, the transistors in the second drive pull-down module 122, the first drive pull-down module 121, and the first drive output module 131 start working based on the signal control of the first node N1. Optionally, the conduction type of the fifth transistor T5 provided in this application embodiment is the opposite of the conduction types of the first transistors T1 to the fourth transistor T4, the eleventh transistor T11, and the twelfth transistor T12. The following description uses an example where the fifth transistor T5 is an N-type transistor, and the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the fourteenth transistor T14, the fifteenth transistor T15, and the sixteenth transistor T16 are all P-type transistors, to provide a more detailed description of the technical solution provided in this application embodiment.

[0094] Combination Figure 5 The schematic drive circuit 100 and Figure 6a The schematic timing diagram provides a detailed description of the operation of the drive circuit 100 provided in the embodiments of this application. Figure 5 The fifth transistor T5 shown is an N-type transistor, while the first transistor T1, the second transistor T2, the fourth transistor T4, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the fourteenth transistor T14, the fifteenth transistor T15, and the sixteenth transistor T16 are all P-type transistors. The first level terminal VGL is a low-level terminal, and the first level signal VG1 is a low-level signal. Figure 5 The gate of the fifth transistor T5 is electrically connected to the input signal terminal IN. When the gating control terminal Ctrl is a low-level signal, the thirteenth transistor T13 is turned on, connecting the second node N2 and the third node N3. At this time, the scanning circuit is in a high-frequency refresh state (the output waveforms of the cascaded output terminal OUT and the gating output terminal OUTx are consistent). The working processes of the pull-down stage S1, input stage S2, output stage S3, sustain stage S4, transition stage S5 and end stage S6 of the driving circuit 100 are as follows:

[0095] In the pull-down phase S1, the first clock signal end CK controls the first transistor T1 to be turned on, so as to transmit the low level signal of the input signal end IN at this time to the first node N1. The low level signal of the first node N1 can control the eleventh transistor T11 to be turned on, and the eleventh transistor T11 transmits the low level signal of the first clock signal end CK at this time to the second node N2. The low level signal of the second node N2 can control the twelfth transistor T12 to be turned on, and the twelfth transistor T12 transmits the low level signal of the first clock signal end CK at this time to the cascade output end OUT, and the cascade output end OUT outputs an invalid level. At the same time, since the second node N2 and the third node N3 are connected in communication, the fifteenth transistor T15 is turned on based on the signal control of the third node N3, and transmits the low level signal of the first clock signal end CK at this time to the gating output end OUTx, and the gating output end OUTx outputs an invalid level.

[0096] In the input phase S2, the first clock signal end CK controls the first transistor T1 to be turned on, so as to transmit the high level signal of the input signal end IN at this time to the first node N1. At the same time, the fifth transistor T5 is turned on based on the high level signal control of the input signal end IN at this time, and transmits the low level signal of the first level signal VG1 to the second node N2. The low level signal of the second node N2 can control the twelfth transistor T12 to be turned on, and the twelfth transistor T12 transmits the low level signal of the first clock signal end CK at this time to the cascade output end OUT, and the cascade output end OUT outputs an invalid level. At the same time, since the second node N2 and the third node N3 are connected in communication, the fifteenth transistor T15 is turned on based on the signal control of the third node N3, and transmits the low level signal of the first clock signal end CK at this time to the gating output end OUTx, and the gating output end OUTx outputs an invalid level.

[0097] In the output phase S3, the first clock signal end CK at this time is high level to control the first transistor T1 to be turned off, and the first node N1 keeps the high level signal in the input phase S2 without voltage input. At the same time, the fifth transistor T5 is turned on based on the high level signal control of the input signal end IN at this time, and transmits the low level signal of the first level signal VG1 to the second node N2. The low level signal of the second node N2 can control the twelfth transistor T12 to be turned on, and the twelfth transistor T12 transmits the high level signal of the first clock signal end CK at this time to the cascade output end OUT, and the cascade output end OUT outputs a valid level. At the same time, since the second node N2 and the third node N3 are connected in communication, the fifteenth transistor T15 is turned on based on the signal control of the third node N3, and transmits the high level signal of the first clock signal end CK at this time to the gating output end OUTx, and the gating output end OUTx outputs a valid level.

[0098] In the maintaining stage S4, the first node N1 keeps the high level signal without other voltage input in the output stage S3. Meanwhile, the fifth transistor T5 is turned off based on the low level signal of the input signal terminal IN at this time, and the second node N2 keeps the low level signal without voltage input, which is the same as that in the output stage S3. The low level signal of the second node N2 can control the twelfth transistor T12 to be turned on, and the twelfth transistor T12 transmits the high level signal of the first clock signal terminal CK at this time to the cascade output terminal OUT, and the cascade output terminal OUT keeps the output active level at this time. Meanwhile, since the second node N2 and the third node N3 are connected, the fifteenth transistor T15 is turned on based on the signal control of the third node N3, and transmits the high level signal of the first clock signal terminal CK at this time to the gating output terminal OUTx, and the gating output terminal OUTx outputs the active level.

[0099] In the transition stage S5, the first clock signal terminal CK is low level signal at this time to control the first transistor T1 to be turned on, so as to transmit the low level signal of the input signal terminal IN at this time to the first node N1. The low level signal of the first node N1 can control the eleventh transistor T11 to be turned on, and the eleventh transistor T11 transmits the low level signal of the first clock signal terminal CK to the second node N2. The twelfth transistor T12 is turned on based on the low level signal control of the second node N2, and transmits the low level signal of the first clock signal terminal CK to the cascade output terminal OUT, and the cascade output terminal OUT outputs the inactive level. Meanwhile, since the second node N2 and the third node N3 are connected, the fifteenth transistor T15 is turned on based on the signal control of the third node N3, and transmits the low level signal of the first clock signal terminal CK at this time to the gating output terminal OUTx, and the gating output terminal OUTx outputs the inactive level. In addition, the first capacitor C1 couples the low level signal of the first clock signal terminal CK to the second node N2, so as to adjust the low level voltage of the second node N2 to be less than the level voltage of the first level terminal VGL, thereby enabling the low level signal of the first clock signal terminal CK to be more fully transmitted to the cascade output terminal OUT, so as to avoid the problem of step voltage when the cascade output terminal OUT outputs the inactive level.

[0100] At the end stage S6, the first node N1 low level signal controls the second transistor T2 to turn on, and the low level signal of the second clock signal end XCK is coupled to the first node N1 through the second capacitor C2, so as to adjust the voltage of the first node N1 to a lower voltage, thereby being able to better control the sufficient conduction of the fourth transistor T4, the eleventh transistor T11 and the sixteenth transistor T16 through the low level of the first node N1, the fourth transistor T4 transmits the low level signal of the first level end VGL to the cascade output end OUT, and the cascade output end OUT outputs an invalid level; at the same time, the sixteenth transistor T16 transmits the low level signal of the first level end VGL to the gating output end OUTx, and the gating output end OUTx outputs an invalid level.

[0101] With reference to the Figure 5 timing diagram shown, and in combination with Figure 6b the working process of the driving circuit 100 provided by the embodiment of the present application is described in detail. Figure 5 The fifth transistor T5 shown in the schematic is an N-type transistor, and the first transistor T1, the second transistor T2, the fourth transistor T4, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the fourteenth transistor T14, the fifteenth transistor T15 and the sixteenth transistor T16 are all P-type transistors. Among them, the first level end VGL is a low level end, and the first level signal VG1 is a low level signal. Figure 5 The gate of the fifth transistor T5 shown in the schematic is electrically connected with the input signal end IN, and when the gating control end Ctrl is a high level signal to control the thirteenth transistor T13 to be cut off, the second node N2 and the third node N3 are disconnected, and the scanning circuit is in a low frequency refreshing state (at this time, the gating output end OUTx continuously outputs an invalid level), wherein the working processes of the pull-down stage S1, the input stage S2, the output stage S3, the maintaining stage S4, the transition stage S5 and the end stage S6 of the driving circuit 100 are respectively as follows:

[0102] In the pull-down phase S1, the first clock signal end CK controls the first transistor T1 to be turned on, so as to transmit the low level signal of the input signal end IN at this time to the first node N1. The low level signal of the first node N1 can control the eleventh transistor T11 to be turned on, and the eleventh transistor T11 transmits the low level signal of the first clock signal end CK at this time to the second node N2. The low level signal of the second node N2 can control the twelfth transistor T12 to be turned on, and the twelfth transistor T12 transmits the low level signal of the first clock signal end CK at this time to the cascade output end OUT, and the cascade output end OUT outputs an invalid level. Meanwhile, the fourteenth transistor T14 is turned on based on the signal control of the first node N1, and transmits the low level signal of the first clock signal end CK to the third node N3. The fifteenth transistor T15 is turned on based on the signal control of the third node N3, and transmits the low level signal of the first clock signal end CK at this time to the gating output end OUTx. The sixteenth transistor T16 is turned on based on the signal control of the first node N1, and transmits the low level signal of the first level end VGL to the gating output end OUTx, and the gating output end OUTx outputs an invalid level.

[0103] In the input phase S2, the first clock signal end CK controls the first transistor T1 to be turned on, so as to transmit the high level signal of the input signal end IN at this time to the first node N1. Meanwhile, the fifth transistor T5 is turned on based on the high level signal control of the input signal end IN at this time, and transmits the low level signal of the first level signal VG1 to the second node N2. The low level signal of the second node N2 can control the twelfth transistor T12 to be turned on, and the twelfth transistor T12 transmits the low level signal of the first clock signal end CK at this time to the cascade output end OUT, and the cascade output end OUT outputs an invalid level. Meanwhile, the fourteenth transistor T14 is turned off based on the signal control of the first node N1, and the third node N3 has no voltage input and remains the same voltage as in the pull-down phase S1. The third node N3 controls the fifteenth transistor T15 to be turned on, and transmits the low level signal of the first clock signal end CK at this time to the gating output end OUTx, and the gating output end OUTx outputs an invalid level.

[0104] In the output stage S3, the first clock signal end CK is high at this time to control the first transistor T1 to be off, and the first node N1 has no voltage input to keep the high level signal in the input stage S2. Meanwhile, the fifth transistor T5 is turned on based on the high level signal of the input signal end IN at this time to transmit the low level signal of the first level signal VG1 to the second node N2. The low level signal of the second node N2 can control the twelfth transistor T12 to be turned on, and the twelfth transistor T12 transmits the high level signal of the first clock signal end CK at this time to the cascade output end OUT, and the cascade output end OUT outputs the effective level. Meanwhile, the fourteenth transistor T14 is off based on the signal control of the first node N1, and the high level signal of the first clock signal end CK is coupled to the third node N3 through the third capacitor C3 to make the third node N3 high, and the third node N3 controls the fifteenth transistor T15 to be off, and the gating output end OUTx has no other voltage input to keep the same voltage as that in the input stage S2, and the gating output end OUTx outputs the ineffective level.

[0105] In the holding stage S4, the first node N1 has no other voltage input to keep the high level signal in the output stage S3. Meanwhile, the fifth transistor T5 is off based on the low level signal of the input signal end IN at this time, and the second node N2 has no voltage input to maintain the low level signal as that in the output stage S3. The low level signal of the second node N2 can control the twelfth transistor T12 to be turned on, and the twelfth transistor T12 transmits the high level signal of the first clock signal end CK at this time to the cascade output end OUT, and the cascade output end OUT maintains the output effective level at this time. Meanwhile, the fourteenth transistor T14 is off based on the signal control of the first node N1, and the high level signal of the first clock signal end CK is coupled to the third node N3 through the third capacitor C3 to make the third node N3 high, and the third node N3 controls the fifteenth transistor T15 to be off, and the gating output end OUTx has no other voltage input to keep the same voltage as that in the output stage S3, and the gating output end OUTx outputs the ineffective level.

[0106] In the transition stage S5, the first clock signal terminal CK is a low level signal at this time, and controls the first transistor T1 to be turned on, so as to transmit the low level signal of the input signal terminal IN at this time to the first node N1. The low level signal of the first node N1 can control the eleventh transistor T11 to be turned on, and the eleventh transistor T11 transmits the low level signal of the first clock signal terminal CK to the second node N2. The twelfth transistor T12 controls to be turned on based on the low level signal of the second node N2, and transmits the low level signal of the first clock signal terminal CK to the cascade output terminal OUT, and the cascade output terminal OUT outputs an invalid level. The fourteenth transistor T14 is turned on based on the signal control of the first node N1, and transmits the low level signal of the first clock signal terminal CK to the third node N3, the fifteenth transistor T15 is turned on based on the signal control of the third node N3, and transmits the low level signal of the first clock signal terminal CK at this time to the gating output terminal OUTx; and the sixteenth transistor T16 is turned on based on the signal control of the first node N1, and transmits the low level signal of the first level terminal VGL to the gating output terminal OUTx, and the gating output terminal OUTx outputs an invalid level. In addition, the first capacitor C1 couples the low level signal of the first clock signal terminal CK to the second node N2, so as to adjust the low level voltage of the second node N2 to be less than the level voltage of the first level terminal VGL, thereby enabling the low level signal of the first clock signal terminal CK to be more fully transmitted to the cascade output terminal OUT, so as to avoid the problem of step voltage when the cascade output terminal OUT outputs an invalid level.

[0107] In the end stage S6, the low level signal of the first node N1 controls the second transistor T2 to be turned on, and the low level signal of the second clock signal terminal XCK is coupled to the first node N1 through the second capacitor C2, so as to adjust the voltage of the first node N1 to be a lower voltage, thereby enabling the low level of the first node N1 to better control the sufficient turn-on of the fourth transistor T4, the eleventh transistor T11 and the sixteenth transistor T16, the fourth transistor T4 transmits the low level signal of the first level terminal VGL to the cascade output terminal OUT, and the cascade output terminal OUT outputs an invalid level; at the same time, the sixteenth transistor T16 transmits the low level signal of the first level terminal VGL to the gating output terminal OUTx, and the gating output terminal OUTx outputs an invalid level. Thus, the turn-on or turn-off state of the thirteenth transistor T13 is controlled by the gating control terminal Ctrl, the timing of the connection between the second node N2 and the third node N3 is adjusted, and the switching of the high frequency refresh and the low frequency refresh of the scan circuit is completed.

[0108] It should be noted that the application Figure 5 The second capacitor C2 in the schematic drive circuit 100 is directly electrically connected with the first node N1, so that the first node N1 is greatly affected by the coupling of the second clock signal terminal XCK, Figure 5The fifth transistor T5 has a gate electrode electrically connected to the first node N1. When the gate electrode of the fifth transistor T5 is electrically connected to the first node N1, the fifth transistor T5 is controlled by the signal of the first node N1.

[0109] Reference Figure 7 As shown in the circuit diagram of another driving circuit provided by the embodiment of the present application, the first driving pull-down module 121 provided by the embodiment of the present application further includes a third transistor T3 electrically connected between the second plate of the second capacitor C2 and the first node N1. The second plate of the second capacitor C2 is electrically connected to the gate electrode of the third transistor T3. The gate electrode of the third transistor T3 and the first end of the third transistor T3 are both electrically connected to the output end of the first driving input module 111 (i.e., the gate electrode of the third transistor T3 and the first end of the third transistor T3 are both electrically connected to the second end of the first transistor T1). The second end of the third transistor T3 is electrically connected to the first node N1. Optionally, the second driving input module 112 provided by the embodiment of the present application includes a fifth transistor T5. The gate electrode of the fifth transistor T5 is electrically connected to the first node N1. The first end of the fifth transistor T5 is connected to the first voltage level signal VG1. The second end of the fifth transistor T5 is electrically connected to the second node N2.

[0110] The working process of the driving circuit 100 provided by the embodiment of the present application is described in detail below. Figure 7 The driving circuit 100 and Figure 6a The working process of the driving circuit 100 provided by the embodiment of the present application is described in detail below. Figure 7 The fifth transistor T5 is an N-type transistor. The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the fourteenth transistor T14, the fifteenth transistor T15, and the sixteenth transistor T16 are P-type transistors. The first voltage level end VGL is a low voltage level end. The first voltage level signal VG1 is a low voltage level signal. Figure 7 The gate electrode of the fifth transistor T5 is electrically connected to the first node N1. When the gate electrode of the fifth transistor T5 is electrically connected to the first node N1, the fifth transistor T5 is controlled by the signal of the first node N1. When the gate electrode of the thirteenth transistor T13 is a low voltage level signal and the thirteenth transistor T13 is turned on, the second node N2 and the third node N3 are connected. At this time, the scanning circuit is in a high-frequency refreshing state (at this time, the output waveforms of the cascade output end OUT and the gating output end OUTx are consistent). The working processes of the pull-down stage S1, the input stage S2, the output stage S3, the maintaining stage S4, the transition stage S5, and the end stage S6 of the driving circuit 100 are as follows.

[0111] In the pull-down phase S1, the first clock signal end CK controls the first transistor T1 to be turned on, so as to transmit the low level signal of the input signal end IN at this time to the first node N1. The low level signal of the first node N1 can control the eleventh transistor T11 to be turned on, and the eleventh transistor T11 transmits the low level signal of the first clock signal end CK at this time to the second node N2. The low level signal of the second node N2 can control the twelfth transistor T12 to be turned on, and the twelfth transistor T12 transmits the low level signal of the first clock signal end CK at this time to the cascade output end OUT, and the cascade output end OUT outputs an invalid level. At the same time, since the second node N2 and the third node N3 are connected in communication, the fifteenth transistor T15 is turned on based on the signal control of the third node N3, and transmits the low level signal of the first clock signal end CK at this time to the gating output end OUTx, and the gating output end OUTx outputs an invalid level.

[0112] In the input phase S2, the first clock signal end CK controls the first transistor T1 to be turned on, so as to transmit the high level signal of the input signal end IN at this time to the first node N1. The high level signal of the first node N1 can control the fifth transistor T5 to be turned on, and the fifth transistor T5 transmits the low level signal of the first level signal VG1 to the second node N2. The low level signal of the second node N2 can control the twelfth transistor T12 to be turned on, and the twelfth transistor T12 transmits the low level signal of the first clock signal end CK at this time to the cascade output end OUT, and the cascade output end OUT outputs an invalid level. At the same time, since the second node N2 and the third node N3 are connected in communication, the fifteenth transistor T15 is turned on based on the signal control of the third node N3, and transmits the low level signal of the first clock signal end CK at this time to the gating output end OUTx, and the gating output end OUTx outputs an invalid level.

[0113] In the output phase S3, the first clock signal end CK at this time is high level to control the first transistor T1 to be turned off, and the first node N1 keeps the high level signal in the input phase S2 without voltage input. Thus, the high level signal of the first node N1 can control the fifth transistor T5 to be turned on, and the fifth transistor T5 transmits the low level signal of the first level signal VG1 to the second node N2. The low level signal of the second node N2 can control the twelfth transistor T12 to be turned on, and the twelfth transistor T12 transmits the high level signal of the first clock signal end CK at this time to the cascade output end OUT, and the cascade output end OUT outputs a valid level. At the same time, since the second node N2 and the third node N3 are connected in communication, the fifteenth transistor T15 is turned on based on the signal control of the third node N3, and transmits the high level signal of the first clock signal end CK at this time to the gating output end OUTx, and the gating output end OUTx outputs a valid level.

[0114] In the maintaining stage S4, the first node N1 keeps the high level signal without other voltage input in the outputting stage S3, thus the high level signal of the first node N1 can control the fifth transistor T5 to be turned on, and the fifth transistor T5 transmits the low level signal of the first level signal VG1 to the second node N2. The low level signal of the second node N2 can control the twelfth transistor T12 to be turned on, and the twelfth transistor T12 transmits the high level signal of the first clock signal end CK to the cascade output end OUT at this time, and the cascade output end OUT keeps outputting the effective level at this time. Meanwhile, since the second node N2 and the third node N3 are connected, the fifteenth transistor T15 is turned on based on the signal control of the third node N3, and transmits the high level signal of the first clock signal end CK to the gating output end OUTx, and the gating output end OUTx outputs the effective level.

[0115] In the transition stage S5, the first clock signal end CK is low level signal at this time to control the first transistor T1 to be turned on, so as to transmit the low level signal of the input signal end IN at this time to the first node N1. The low level signal of the first node N1 can control the eleventh transistor T11 to be turned on, and the eleventh transistor T11 transmits the low level signal of the first clock signal end CK to the second node N2. The twelfth transistor T12 is turned on based on the low level signal of the second node N2, and transmits the low level signal of the first clock signal end CK to the cascade output end OUT, and the cascade output end OUT outputs the ineffective level. Meanwhile, since the second node N2 and the third node N3 are connected, the fifteenth transistor T15 is turned on based on the signal control of the third node N3, and transmits the low level signal of the first clock signal end CK at this time to the gating output end OUTx, and the gating output end OUTx outputs the ineffective level. In addition, the first capacitor C1 couples the low level signal of the first clock signal end CK to the second node N2, so as to adjust the low level voltage of the second node N2 to be less than the level voltage of the first level end VGL, thereby making the low level signal of the first clock signal end CK more fully transmitted to the cascade output end OUT, so as to avoid the problem of step voltage when the cascade output end OUT outputs the ineffective level.

[0116] At the end stage S6, the first node N1 low level signal controls the second transistor T2 to turn on, and the low level signal of the second clock signal end XCK is coupled to the first node N1 through the second capacitor C2, so as to adjust the voltage of the first node N1 to a lower voltage, thereby better controlling the fifth transistor T5 to be turned off through the low level of the first node N1, and better controlling the fourth transistor T4, the eleventh transistor T11 and the sixteenth transistor T16 to be fully turned on. The fourth transistor T4 transmits the low level signal of the first level end VGL to the cascade output end OUT, and the cascade output end OUT outputs an invalid level; at the same time, the sixteenth transistor T16 transmits the low level signal of the first level end VGL to the gating output end OUTx, and the gating output end OUTx outputs an invalid level.

[0117] With reference to the Figure 7 timing diagram shown, and in combination with Figure 6b the working process of the driving circuit 100 provided by the embodiment of the present application is described in detail. Figure 7 The fifth transistor T5 shown in the schematic is an N-type transistor, and the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the fourteenth transistor T14, the fifteenth transistor T15 and the sixteenth transistor T16 are all P-type transistors. Among them, the first level end VGL is a low level end, and the first level signal VG1 is a low level signal. Figure 7 The gate of the fifth transistor T5 shown in the schematic is electrically connected with the first node N1. When the gating control end Ctrl is a high level signal to control the thirteenth transistor T13 to be turned off, and the second node N2 and the third node N3 are disconnected, the scanning circuit is in a low frequency refresh state (at this time, the gating output end OUTx continuously outputs an invalid level), and the working processes of the pull-down stage S1, the input stage S2, the output stage S3, the maintenance stage S4, the transition stage S5 and the end stage S6 of the driving circuit 100 are as follows:

[0118] In the pull-down phase S1, the first clock signal end CK controls the first transistor T1 to be turned on, so as to transmit the low level signal of the input signal end IN at this time to the first node N1. The low level signal of the first node N1 can control the eleventh transistor T11 to be turned on, and the eleventh transistor T11 transmits the low level signal of the first clock signal end CK at this time to the second node N2. The low level signal of the second node N2 can control the twelfth transistor T12 to be turned on, and the twelfth transistor T12 transmits the low level signal of the first clock signal end CK at this time to the cascade output end OUT, and the cascade output end OUT outputs an invalid level. At the same time, the fourteenth transistor T14 is turned on based on the signal control of the first node N1, and transmits the low level signal of the first clock signal end CK to the third node N3. The fifteenth transistor T15 is turned on based on the signal control of the third node N3, and transmits the low level signal of the first clock signal end CK at this time to the gating output end OUTx; and the sixteenth transistor T16 is turned on based on the signal control of the first node N1, and transmits the low level signal of the first level end VGL to the gating output end OUTx, and the gating output end OUTx outputs an invalid level.

[0119] In the input phase S2, the first clock signal end CK controls the first transistor T1 to be turned on, so as to transmit the high level signal of the input signal end IN at this time to the first node N1. The high level signal of the first node N1 can control the fifth transistor T5 to be turned on, and the fifth transistor T5 transmits the low level signal of the first level signal VG1 to the second node N2. The low level signal of the second node N2 can control the twelfth transistor T12 to be turned on, and the twelfth transistor T12 transmits the low level signal of the first clock signal end CK at this time to the cascade output end OUT, and the cascade output end OUT outputs an invalid level. At the same time, the fourteenth transistor T14 is turned off based on the signal control of the first node N1, the third node N3 has no voltage input and keeps the same voltage as in the pull-down phase S1, the third node N3 controls the fifteenth transistor T15 to be turned on, and transmits the low level signal of the first clock signal end CK at this time to the gating output end OUTx, and the gating output end OUTx outputs an invalid level.

[0120] In the output stage S3, the first clock signal end CK is high at this time, the first transistor T1 is controlled to be off, the first node N1 has no voltage input and keeps the high level signal in the input stage S2; thus, the high level signal of the first node N1 can control the fifth transistor T5 to be on, and the fifth transistor T5 transmits the low level signal of the first level signal VG1 to the second node N2. The low level signal of the second node N2 can control the twelfth transistor T12 to be on, and the twelfth transistor T12 transmits the high level signal of the first clock signal end CK at this time to the cascade output end OUT, and the cascade output end OUT outputs the effective level. At the same time, the fourteenth transistor T14 is controlled to be off based on the signal of the first node N1, the high level signal of the first clock signal end CK is coupled to the third node N3 through the third capacitor C3, so that the third node N3 is high, the third node N3 controls the fifteenth transistor T15 to be off, the gating output end OUTx has no other voltage input and keeps the same voltage as that in the input stage S2, and the gating output end OUTx outputs the invalid level.

[0121] In the output stage S3, the first clock signal end CK is high at this time, the first transistor T1 is controlled to be off, the first node N1 has no voltage input and keeps the high level signal in the input stage S2; thus, the high level signal of the first node N1 can control the fifth transistor T5 to be on, and the fifth transistor T5 transmits the low level signal of the first level signal VG1 to the second node N2. The low level signal of the second node N2 can control the twelfth transistor T12 to be on, and the twelfth transistor T12 transmits the high level signal of the first clock signal end CK at this time to the cascade output end OUT, and the cascade output end OUT outputs the effective level. At the same time, the fourteenth transistor T14 is controlled to be off based on the signal of the first node N1, the high level signal of the first clock signal end CK is coupled to the third node N3 through the third capacitor C3, so that the third node N3 is high, the third node N3 controls the fifteenth transistor T15 to be off, the gating output end OUTx has no other voltage input and keeps the same voltage as that in the input stage S2, and the gating output end OUTx outputs the invalid level.

[0122] In the transition stage S5, the first clock signal end CK is a low level signal at this time, and the first transistor T1 is controlled to be turned on by the low level signal, so as to transmit the low level signal of the input signal end IN to the first node N1. The low level signal of the first node N1 can control the eleventh transistor T11 to be turned on, and the eleventh transistor T11 transmits the low level signal of the first clock signal end CK to the second node N2. The twelfth transistor T12 is controlled to be turned on based on the low level signal of the second node N2, and transmits the low level signal of the first clock signal end CK to the cascade output end OUT, and the cascade output end OUT outputs an invalid level. The fourteenth transistor T14 is turned on based on the signal control of the first node N1, and transmits the low level signal of the first clock signal end CK to the third node N3. The fifteenth transistor T15 is turned on based on the signal control of the third node N3, and transmits the low level signal of the first clock signal end CK at this time to the gating output end OUTx. The sixteenth transistor T16 is turned on based on the signal control of the first node N1, and transmits the low level signal of the first level end VGL to the gating output end OUTx, and the gating output end OUTx outputs an invalid level. In addition, the first capacitor C1 couples the low level signal of the first clock signal end CK to the second node N2, so as to adjust the low level voltage of the second node N2 to a voltage smaller than the level voltage of the first level end VGL, thereby enabling the low level signal of the first clock signal end CK to be more fully transmitted to the cascade output end OUT, so as to avoid the problem of step voltage when the cascade output end OUT outputs an invalid level.

[0123] In the end stage S6, the low level signal of the first node N1 controls the second transistor T2 to be turned on, and the low level signal of the second clock signal end XCK is coupled to the first node N1 through the second capacitor C2, so as to adjust the voltage of the first node N1 to a lower voltage, thereby enabling the low level of the first node N1 to better control the turn-off of the fifth transistor T5 and better control the full turn-on of the fourth transistor T4, the eleventh transistor T11 and the sixteenth transistor T16. The fourth transistor T4 transmits the low level signal of the first level end VGL to the cascade output end OUT, and the cascade output end OUT outputs an invalid level. At the same time, the sixteenth transistor T16 transmits the low level signal of the first level end VGL to the gating output end OUTx, and the gating output end OUTx outputs an invalid level.

[0124] Figure 7 The technical scheme is illustrated when the first driving pull-down module 121 includes the second transistor T2, the third transistor T3 and the second capacitor C2, and the fifth transistor T5 is electrically connected with the first node N1. In some embodiments of the present application, when the first driving pull-down module 121 provided by the embodiments of the present application includes the second transistor T2, the third transistor T3 and the second capacitor C2, the fifth transistor T5 can also be electrically connected with the input signal end IN. For details, please refer toFigure 8 Fig. 6 is a circuit diagram of another driving circuit provided by the embodiment of the present application, and the gate of the fifth transistor T5 is electrically connected with the input signal terminal IN in the first driving pull-down module 121, the second transistor T2, the third transistor T3 and the second capacitor C2 provided by the embodiment of the present application. In combination with Figure 8 Fig. 6 is a timing diagram of the driving circuit 100 and Fig. 6, and the working process of the driving circuit 100 provided by the embodiment of the present application is described in detail. Figure 8 The fifth transistor T5 is an N-type transistor, and the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the fourteenth transistor T14, the fifteenth transistor T15 and the sixteenth transistor T16 are all P-type transistors. Among them, the first level terminal VGL is a low level terminal, and the first level signal VG1 is a low level signal. Figure 8 The gate of the fifth transistor T5 is electrically connected with the input signal terminal IN, and when the control terminal Ctrl is a low level signal to control the thirteenth transistor T13 to be turned on, the second node N2 and the third node N3 are connected, and the scanning circuit is in a high frequency refresh state (at this time, the output waveforms of the cascade output terminal OUT and the gating output terminal OUTx are consistent), wherein the working processes of the pull-down stage S1, the input stage S2, the output stage S3, the maintenance stage S4, the transition stage S5 and the end stage S6 of the driving circuit 100 are as follows:

[0125] In the pull-down stage S1, the first clock signal terminal CK controls the first transistor T1 to be turned on, so as to transmit the low level signal of the input signal terminal IN at this time to the first node N1. The low level signal of the first node N1 can control the eleventh transistor T11 to be turned on, and the eleventh transistor T11 transmits the low level signal of the first clock signal terminal CK at this time to the second node N2. The low level signal of the second node N2 can control the twelfth transistor T12 to be turned on, and the twelfth transistor T12 transmits the low level signal of the first clock signal terminal CK at this time to the cascade output terminal OUT, and the cascade output terminal OUT outputs an invalid level. At the same time, since the second node N2 and the third node N3 are connected, the fifteenth transistor T15 is turned on based on the signal control of the third node N3, and transmits the low level signal of the first clock signal terminal CK at this time to the gating output terminal OUTx, and the gating output terminal OUTx outputs an invalid level.

[0126] In the input stage S2, the first clock signal end CK controls the first transistor T1 to be turned on, so as to transmit the high level signal of the input signal end IN at this time to the first node N1. Meanwhile, the fifth transistor T5 is turned on based on the high level signal of the input signal end IN at this time, so as to transmit the low level signal of the first level signal VG1 to the second node N2. The low level signal of the second node N2 can control the twelfth transistor T12 to be turned on, and the twelfth transistor T12 transmits the low level signal of the first clock signal end CK at this time to the cascade output end OUT, and the cascade output end OUT outputs an invalid level. Meanwhile, since the second node N2 and the third node N3 are connected, the fifteenth transistor T15 is turned on based on the signal control of the third node N3, so as to transmit the low level signal of the first clock signal end CK at this time to the gating output end OUTx, and the gating output end OUTx outputs an invalid level.

[0127] In the output stage S3, the first clock signal end CK at this time is high level, so as to control the first transistor T1 to be turned off, and the first node N1 keeps the high level signal in the input stage S2 without voltage input. Meanwhile, the fifth transistor T5 is turned on based on the high level signal of the input signal end IN at this time, so as to transmit the low level signal of the first level signal VG1 to the second node N2. The low level signal of the second node N2 can control the twelfth transistor T12 to be turned on, and the twelfth transistor T12 transmits the high level signal of the first clock signal end CK at this time to the cascade output end OUT, and the cascade output end OUT outputs a valid level. Meanwhile, since the second node N2 and the third node N3 are connected, the fifteenth transistor T15 is turned on based on the signal control of the third node N3, so as to transmit the high level signal of the first clock signal end CK at this time to the gating output end OUTx, and the gating output end OUTx outputs a valid level.

[0128] In the maintaining stage S4, the first node N1 keeps the high level signal in the output stage S3 without other voltage input. Meanwhile, the fifth transistor T5 is turned off based on the low level signal of the input signal end IN at this time, and the second node N2 keeps the low level signal in the output stage S3 without voltage input. The low level signal of the second node N2 can control the twelfth transistor T12 to be turned on, and the twelfth transistor T12 transmits the high level signal of the first clock signal end CK at this time to the cascade output end OUT, and the cascade output end OUT keeps outputting a valid level at this time. Meanwhile, since the second node N2 and the third node N3 are connected, the fifteenth transistor T15 is turned on based on the signal control of the third node N3, so as to transmit the high level signal of the first clock signal end CK at this time to the gating output end OUTx, and the gating output end OUTx outputs a valid level.

[0129] During transition phase S5, the first clock signal terminal CK is low, controlling the first transistor T1 to turn on, transmitting the low-level signal at the input signal terminal IN to the first node N1. The low-level signal at the first node N1 controls the eleventh transistor T11 to turn on, transmitting the low-level signal of the first clock signal terminal CK to the second node N2. The twelfth transistor T12 is turned on based on the low-level signal at the second node N2, transmitting the low-level signal of the first clock signal terminal CK to the cascaded output terminal OUT, which outputs an invalid level. Simultaneously, since the second node N2 and the third node N3 are connected, the fifteenth transistor T15 is turned on based on the signal control of the third node N3, transmitting the low-level signal of the first clock signal terminal CK to the gating output terminal OUTx, which outputs an invalid level. In addition, the first capacitor C1 couples the low-level signal of the first clock signal terminal CK to the second node N2, so as to adjust the low-level voltage of the second node N2 down to a level voltage lower than that of the first level terminal VGL. This allows the low-level signal of the first clock signal terminal CK to be transmitted more fully to the cascaded output terminal OUT, so as to avoid the problem of step voltage when the cascaded output terminal OUT outputs an invalid level.

[0130] During the final stage S6, the low-level signal of the first node N1 controls the second transistor T2 to turn on, coupling the low-level signal of the second clock signal terminal XCK to the first node N1 through the second capacitor C2, thereby adjusting the voltage of the first node N1 downward to a lower voltage. This allows the low level of the first node N1 to better control the full conduction of the fourth transistor T4, the eleventh transistor T11, and the sixteenth transistor T16. The fourth transistor T4 transmits the low-level signal of the first level terminal VGL to the cascaded output terminal OUT, which outputs an invalid level. At the same time, the sixteenth transistor T16 transmits the low-level signal of the first level terminal VGL to the gating output terminal OUTx, which outputs an invalid level.

[0131] Continue to refer to Figure 8 As shown, and in combination Figure 6b The timing diagram shown describes in detail the operation of the drive circuit 100 provided in the embodiments of this application. Figure 8 The fifth transistor T5 is shown as an N-type transistor, while the first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, eleventh transistor T11, twelfth transistor T12, thirteenth transistor T13, fourteenth transistor T14, fifteenth transistor T15, and sixteenth transistor T16 are all P-type transistors. The first level terminal VGL is a low-level terminal, and the first level signal VG1 is a low-level signal. Figure 8The gate of the fifth transistor T5 is electrically connected with the first node N1. When the thirteenth transistor T13 is turned off by the high level signal of the control terminal Ctrl, the second node N2 and the third node N3 are disconnected, the scanning circuit is in the low frequency refresh state (at this time, the invalid level is continuously outputted from the selection output terminal OUTx), and the working processes of the pull-down stage S1, the input stage S2, the output stage S3, the maintaining stage S4, the transition stage S5 and the end stage S6 of the driving circuit 100 are respectively as follows:

[0132] In the pull-down stage S1, the first clock signal terminal CK controls the first transistor T1 to be turned on, so as to transmit the low level signal of the input signal terminal IN to the first node N1. The low level signal of the first node N1 can control the eleventh transistor T11 to be turned on, and the eleventh transistor T11 transmits the low level signal of the first clock signal terminal CK to the second node N2. The low level signal of the second node N2 can control the twelfth transistor T12 to be turned on, and the twelfth transistor T12 transmits the low level signal of the first clock signal terminal CK to the cascade output terminal OUT, and the cascade output terminal OUT outputs the invalid level. Meanwhile, the fourteenth transistor T14 is turned on based on the signal control of the first node N1, the low level signal of the first clock signal terminal CK is transmitted to the third node N3, the fifteenth transistor T15 is turned on based on the signal control of the third node N3, the low level signal of the first clock signal terminal CK is transmitted to the selection output terminal OUTx, and the sixteenth transistor T16 is turned on based on the signal control of the first node N1, the low level signal of the first level terminal VGL is transmitted to the selection output terminal OUTx, and the selection output terminal OUTx outputs the invalid level.

[0133] In the input stage S2, the first clock signal terminal CK controls the first transistor T1 to be turned on, so as to transmit the high level signal of the input signal terminal IN to the first node N1. Meanwhile, the fifth transistor T5 is turned on based on the high level signal control of the input signal terminal IN at this time, the low level signal of the first level signal VG1 is transmitted to the second node N2. The low level signal of the second node N2 can control the twelfth transistor T12 to be turned on, and the twelfth transistor T12 transmits the low level signal of the first clock signal terminal CK to the cascade output terminal OUT, and the cascade output terminal OUT outputs the invalid level. Meanwhile, the fourteenth transistor T14 is turned off based on the signal control of the first node N1, the third node N3 has no voltage input and keeps the same voltage as in the pull-down stage S1, the third node N3 controls the fifteenth transistor T15 to be turned on, the low level signal of the first clock signal terminal CK is transmitted to the selection output terminal OUTx, and the selection output terminal OUTx outputs the invalid level.

[0134] In the output stage S3, the first clock signal end CK is high at this time to control the first transistor T1 to be off, and the first node N1 has no voltage input to keep the high level signal in the input stage S2. Meanwhile, the fifth transistor T5 is turned on based on the high level signal of the input signal end IN at this time to transmit the low level signal of the first level signal VG1 to the second node N2. The low level signal of the second node N2 can control the twelfth transistor T12 to be turned on, and the twelfth transistor T12 transmits the high level signal of the first clock signal end CK at this time to the cascade output end OUT, and the cascade output end OUT outputs the effective level. Meanwhile, the fourteenth transistor T14 is off based on the signal control of the first node N1, and the high level signal of the first clock signal end CK is coupled to the third node N3 through the third capacitor C3 to make the third node N3 high, and the third node N3 controls the fifteenth transistor T15 to be off, and the gating output end OUTx has no other voltage input to keep the same voltage as that in the input stage S2, and the gating output end OUTx outputs the ineffective level.

[0135] In the holding stage S4, the first node N1 has no other voltage input to keep the high level signal in the output stage S3. Meanwhile, the fifth transistor T5 is off based on the low level signal of the input signal end IN at this time, and the second node N2 has no voltage input to maintain the low level signal as that in the output stage S3. The low level signal of the second node N2 can control the twelfth transistor T12 to be turned on, and the twelfth transistor T12 transmits the high level signal of the first clock signal end CK at this time to the cascade output end OUT, and the cascade output end OUT maintains the output effective level at this time. Meanwhile, the fourteenth transistor T14 is off based on the signal control of the first node N1, and the high level signal of the first clock signal end CK is coupled to the third node N3 through the third capacitor C3 to make the third node N3 high, and the third node N3 controls the fifteenth transistor T15 to be off, and the gating output end OUTx has no other voltage input to keep the same voltage as that in the output stage S3, and the gating output end OUTx outputs the ineffective level.

[0136] In the transition stage S5, the first clock signal terminal CK is a low level signal at this time, and controls the first transistor T1 to be turned on, so as to transmit the low level signal of the input signal terminal IN at this time to the first node N1. The low level signal of the first node N1 can control the eleventh transistor T11 to be turned on, and the eleventh transistor T11 transmits the low level signal of the first clock signal terminal CK to the second node N2. The twelfth transistor T12 controls to be turned on based on the low level signal of the second node N2, and transmits the low level signal of the first clock signal terminal CK to the cascade output terminal OUT, and the cascade output terminal OUT outputs an invalid level. The fourteenth transistor T14 is turned on based on the signal control of the first node N1, and transmits the low level signal of the first clock signal terminal CK to the third node N3. The fifteenth transistor T15 is turned on based on the signal control of the third node N3, and transmits the low level signal of the first clock signal terminal CK at this time to the gating output terminal OUTx. The sixteenth transistor T16 is turned on based on the signal control of the first node N1, and transmits the low level signal of the first level terminal VGL to the gating output terminal OUTx, and the gating output terminal OUTx outputs an invalid level. In addition, the first capacitor C1 couples the low level signal of the first clock signal terminal CK to the second node N2, so as to adjust the low level voltage of the second node N2 to be less than the level voltage of the first level terminal VGL, thereby enabling the low level signal of the first clock signal terminal CK to be more fully transmitted to the cascade output terminal OUT, so as to avoid the problem of step voltage when the cascade output terminal OUT outputs an invalid level.

[0137] In the end stage S6, the low level signal of the first node N1 controls the second transistor T2 to be turned on, and couples the low level signal of the second clock signal terminal XCK to the first node N1 through the second capacitor C2, so as to adjust the voltage of the first node N1 to be a lower voltage, thereby enabling the low level of the first node N1 to better control the sufficient turn-on of the fourth transistor T4, the eleventh transistor T11 and the sixteenth transistor T16. The fourth transistor T4 transmits the low level signal of the first level terminal VGL to the cascade output terminal OUT, and the cascade output terminal OUT outputs an invalid level. At the same time, the sixteenth transistor T16 transmits the low level signal of the first level terminal VGL to the gating output terminal OUTx, and the gating output terminal OUTx outputs an invalid level.

[0138] Reference Figure 9As shown, the circuit diagram of another driving circuit provided by the embodiment of the present application, the driving circuit 100 provided by the embodiment of the present application further comprises: a first voltage stabilizing transistor M1, a gate of the first voltage stabilizing transistor M1 is electrically connected with a constant-on level terminal VGK (the constant-on level terminal VGK is a level terminal for keeping a transistor electrically connected in a conducting state), a first terminal of the first voltage stabilizing transistor M1 is electrically connected with an output terminal of the first driving input module 111, and a second terminal of the first voltage stabilizing transistor M1 is electrically connected with the first node N1. When the first driving input module 111 comprises a first transistor T1, the first terminal of the first voltage stabilizing transistor M1 is electrically connected with a second terminal of the first transistor T1. The first voltage stabilizing transistor M1 is arranged to isolate the first transistor T1 and the first node N1, so as to avoid the first node N1 from being affected by coupling in the end stage S6, and to avoid the problem that the first transistor T1 in the off state has a large gate-drain bias voltage, thereby ensuring high reliability of the driving circuit 100. In addition, the gating unit 100b provided by the embodiment of the present application further comprises: a fifth voltage stabilizing transistor M5, a gate of the fifth voltage stabilizing transistor M5 is electrically connected with the constant-on level terminal VGK, a first terminal of the fifth voltage stabilizing transistor M5 is electrically connected with an output terminal of the gating control module 150 (and a second terminal of the thirteenth transistor T13), and a second terminal of the fifth voltage stabilizing transistor M5 is electrically connected with the third node N3. The fifth voltage stabilizing transistor M5 can avoid the influence of the potential of the third node N3 caused by coupling on the thirteenth transistor T13, thereby improving the reliability of the driving circuit 100. Optionally, the first voltage stabilizing transistor M1 and the fifth voltage stabilizing transistor M5 provided by the embodiment of the present application are opposite to the conduction type of the fifth transistor T5, and are the same as the conduction type of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the fourteenth transistor T14, the fifteenth transistor T15 and the sixteenth transistor T16. The constant-on level terminal VGK can be reused as the first level terminal VGL. When the first voltage stabilizing transistor M1, the fifth voltage stabilizing transistor M5, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the fourteenth transistor T14, the fifteenth transistor T15 and the sixteenth transistor T16 are all P-type transistors, the first level terminal VGL and the constant-on level terminal VGK are both low level terminals, and the constant-on level terminal VGK can be reused as the first level terminal VGL to reduce the number of level terminals.

[0139] Reference Figure 10As shown, the circuit diagram of another driving circuit provided by the embodiment of the present application, the driving circuit 100 provided by the embodiment of the present application further comprises a third voltage stabilizing transistor M3, a gate of the third voltage stabilizing transistor M3 is electrically connected with a normally open level terminal VGK, a first end of the third voltage stabilizing transistor M3 is electrically connected with a second end of the fifth transistor T5, and a second end of the third voltage stabilizing transistor M3 is electrically connected with the second node N2. The third voltage stabilizing transistor M3 can play a role of isolating the fifth transistor T5 and the second node N2, so as to avoid the problem that the voltage of the second node N2 is adjusted in the transition stage, and the fifth transistor T5 is turned on to affect the voltage of the second node N2. Optionally, the third voltage stabilizing transistor M3 provided by the embodiment of the present application is opposite to the conduction type of the fifth transistor T5, and is the same as the conduction type of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the fourteenth transistor T14, the fifteenth transistor T15 and the sixteenth transistor T16, and the normally open level terminal VGK can reuse the first level terminal VGL. When the third voltage stabilizing transistor M3, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the fourteenth transistor T14, the fifteenth transistor T15 and the sixteenth transistor T16 are all P-type transistors, the first level terminal VGL and the normally open level terminal VGK are both low level terminals, and the normally open level terminal VGK can reuse the first level terminal VGL to reduce the number of level terminals.

[0140] Reference Figure 11As shown in FIG. 6, it is a circuit diagram of another driving circuit provided by the embodiment of the present application, the second driving input module 112 provided by the embodiment of the present application further includes a sixth transistor T6, a gate of the sixth transistor T6 is electrically connected with the normally open level terminal VGK, a first end of the sixth transistor T6 is connected with the first level signal VG1, and a second end of the sixth transistor T6 is electrically connected with a first end of the fifth transistor T5. It can be understood that the embodiment of the present application reduces the low level signal transmitted to the fifth transistor T5 due to threshold loss when the sixth transistor T6 is turned on, so as to ensure the high-off effect of the fifth transistor T5 in the transition stage S5 and the end stage S6, thereby improving the reliability of the driving circuit 100. Optionally, the sixth transistor T6 provided by the embodiment of the present application is opposite to the fifth transistor T5 in the conduction type, and is the same as the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the fourteenth transistor T14, the fifteenth transistor T15 and the sixteenth transistor T16 in the conduction type, and the normally open level terminal VGK can be multiplexed with the first level terminal VGL. When the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the fourteenth transistor T14, the fifteenth transistor T15 and the sixteenth transistor T16 are all P-type transistors, the first level terminal VGL and the normally open level terminal VGK are both low level terminals, and the normally open level terminal VGK can be multiplexed with the first level terminal VGL to reduce the number of level terminals.

[0141] Figure 11The sixth transistor T6 and the third voltage stabilizing transistor M3 are both connected to the common open level terminal VGK. In some embodiments, the gate of the sixth transistor T6 can also be connected to the second clock signal terminal XCK. That is, the gate of the sixth transistor T6 can also be connected to the second clock signal terminal XCK, the first terminal of the sixth transistor T6 is connected to the first level signal VG1, and the second terminal of the sixth transistor T6 is connected to the first terminal of the fifth transistor T5. Thus, when the sixth transistor T6 is turned off, the first level signal VG1 is blocked from being transmitted to the fifth transistor T5, and when the sixth transistor T6 is turned on, the low level signal transmitted to the fifth transistor T5 is reduced due to threshold loss, so as to ensure that the fifth transistor T5 is turned off in the transition stage S5 and the end stage S6, thereby improving the reliability of the driving circuit 100. In some embodiments, the gate of the third voltage stabilizing transistor M3 can also be connected to the second clock signal terminal XCK. That is, the driving circuit 100 can further include the third voltage stabilizing transistor M3, the gate of the third voltage stabilizing transistor M3 is connected to the second clock signal terminal XCK, the first terminal of the third voltage stabilizing transistor M3 is connected to the second terminal of the fifth transistor T5, and the second terminal of the third voltage stabilizing transistor M3 is connected to the second node N2. For details, refer to Figure 12 In the driving circuit 100 shown in FIG. 6, the gate of the sixth transistor T6 is connected to the second clock signal terminal XCK, and the gate of the third voltage stabilizing transistor M3 is connected to the common open level terminal VGK. Alternatively, as shown in FIG. 7, the gate of the sixth transistor T6 is connected to the common open level terminal VGK, and the gate of the third voltage stabilizing transistor M3 is connected to the second clock signal terminal XCK. Alternatively, as shown in FIG. 8, the gate of the sixth transistor T6 and the gate of the third voltage stabilizing transistor M3 are both connected to the second clock signal terminal XCK. Figure 13 In the driving circuit 100 shown in FIG. 6, the gate of the sixth transistor T6 is connected to the second clock signal terminal XCK, and the gate of the third voltage stabilizing transistor M3 is connected to the common open level terminal VGK. Alternatively, as shown in FIG. 7, the gate of the sixth transistor T6 is connected to the common open level terminal VGK, and the gate of the third voltage stabilizing transistor M3 is connected to the second clock signal terminal XCK. Alternatively, as shown in FIG. 8, the gate of the sixth transistor T6 and the gate of the third voltage stabilizing transistor M3 are both connected to the second clock signal terminal XCK. Figure 14 In the driving circuit 100 shown in FIG. 6, the gate of the sixth transistor T6 is connected to the second clock signal terminal XCK, and the gate of the third voltage stabilizing transistor M3 is connected to the common open level terminal VGK. Alternatively, as shown in FIG. 7, the gate of the sixth transistor T6 is connected to the common open level terminal VGK, and the gate of the third voltage stabilizing transistor M3 is connected to the second clock signal terminal XCK. Alternatively, as shown in FIG. 8, the gate of the sixth transistor T6 and the gate of the third voltage stabilizing transistor M3 are both connected to the second clock signal terminal XCK.

[0142] It can be understood that the driving circuit 100 shown in the above Figures 9 to 14 It can be understood that the driving circuit 100 shown in the above Figure 15As shown, the circuit diagram of another driving circuit provided by the embodiment of the present application, the first driving pull-down module 121 provided by the embodiment of the present application includes the second transistor T2, the third transistor T3 and the second capacitor C2, the fifth transistor T5 can be electrically connected with the first node N1 or the input signal end IN, the driving circuit 100 further includes: the first voltage stabilizing transistor M1 and the second voltage stabilizing transistor M2, the gate of the first voltage stabilizing transistor M1 is electrically connected with the always-on level end VGK, the first end of the first voltage stabilizing transistor M1 is electrically connected with the output end of the first driving input module 111, and the second end of the first voltage stabilizing transistor M1 is electrically connected with the first node N1. When the first driving input module 111 includes the first transistor T1, the first end of the first voltage stabilizing transistor M1 is electrically connected with the second end of the first transistor T1. The gate of the second voltage stabilizing transistor M2 is electrically connected with the always-on level end VGK, the first end of the second voltage stabilizing transistor M2 is electrically connected with the output end of the first driving input module 111 (that is, the first end of the second voltage stabilizing transistor M2 is electrically connected with the second end of the first transistor T1), and the second end of the second voltage stabilizing transistor M2 is electrically connected with the first end of the third transistor T3. The second voltage stabilizing transistor M2 can isolate the signal on the second end of the first transistor T1 and the second plate side of the second capacitor C2, avoid the influence of the coupling on the first node N1 in the end stage S6, cause the problem of the larger gate-drain bias voltage of the first transistor T1 in the off state, and ensure the high reliability of the driving circuit 100.

[0143] Reference Figure 16As shown, the circuit diagram of another driving circuit provided by the embodiment of the present application, when the first driving pull-down module 121 provided by the embodiment of the present application includes the second transistor T2, the third transistor T3 and the second capacitor C2, the driving circuit 100 further includes a third voltage stabilizing transistor M3, a gate of the third voltage stabilizing transistor M3 is electrically connected with the always-on voltage level terminal VGK, a first terminal of the third voltage stabilizing transistor M3 is electrically connected with a second terminal of the fifth transistor T5, and a second terminal of the third voltage stabilizing transistor M3 is electrically connected with the second node N2. The third voltage stabilizing transistor M3 can isolate the fifth transistor T5 and the second node N2, so as to avoid the problem that the voltage of the second node N2 is adjusted in the transition stage, and the fifth transistor T5 is turned on to affect the voltage of the second node N2. Optionally, the third voltage stabilizing transistor M3 provided by the embodiment of the present application is opposite to the fifth transistor T5 in the conduction type, and is the same as the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the eleventh transistor T11 to the sixteenth transistor T16 in the conduction type, and the always-on voltage level terminal VGK can reuse the first voltage level terminal VGL. When the third voltage stabilizing transistor M3, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the eleventh transistor T11 to the sixteenth transistor T16 are all P-type transistors, the first voltage level terminal VGL and the always-on voltage level terminal VGK are both low voltage level terminals, and the always-on voltage level terminal VGK can reuse the first voltage level terminal VGL to reduce the number of voltage level terminals.

[0144] Reference Figure 17As shown in the circuit diagram of another driving circuit provided by the embodiment of the present application, when the first driving pull-down module 121 provided by the embodiment of the present application includes the second transistor T2, the third transistor T3 and the second capacitor C2, the second driving input module 112 further includes: a sixth transistor T6, a gate of the sixth transistor T6 is electrically connected with the always-on level terminal VGK, a first end of the sixth transistor T6 is connected to the first level signal VG1, and a second end of the sixth transistor T6 is electrically connected with a first end of the fifth transistor T5. It can be understood that the embodiment of the present application reduces the low-level signal transmitted to the fifth transistor T5 due to threshold loss when the sixth transistor T6 is turned on, so as to ensure the high-off effect of the fifth transistor T5 in the transition stage S5 and the end stage S6, thereby improving the reliability of the driving circuit 100. Optionally, the sixth transistor T6 provided by the embodiment of the present application is opposite in conduction type to the fifth transistor T5, and is the same in conduction type as the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the eleventh transistor T11 to the sixteenth transistor T16, and the always-on level terminal VGK can reuse the first level terminal VGL. When the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11 to the sixteenth transistor T16 are all P-type transistors, the first level terminal VGL and the always-on level terminal VGK are both low-level terminals, and the always-on level terminal VGK can reuse the first level terminal VGL to reduce the number of level terminals.

[0145] Figure 17The sixth transistor T6 and the third voltage stabilizing transistor M3 in the driving circuit 100 are both electrically connected with the always-on level terminal VGK. In some embodiments, the gate of the sixth transistor T6 can also be electrically connected with the second clock signal terminal XCK; that is, the gate of the sixth transistor T6 can also be electrically connected with the second clock signal terminal XCK, the first terminal of the sixth transistor T6 is connected with the first level signal VG1, and the second terminal of the sixth transistor T6 is electrically connected with the first terminal of the fifth transistor T5, so as to cut off the first level signal VG1 from being transmitted to the fifth transistor T5 when the sixth transistor T6 is controlled to be off, and to reduce the low level signal transmitted to the fifth transistor T5 due to threshold loss when the sixth transistor T6 is turned on, thereby ensuring the off effect of the fifth transistor T5 in the transition stage S5 and the end stage S6, and improving the reliability of the driving circuit 100. In some embodiments, the gate of the third voltage stabilizing transistor M3 can also be electrically connected with the second clock signal terminal XCK; that is, the driving circuit 100 provided by the embodiments of the present application further includes: a third voltage stabilizing transistor M3, the gate of the third voltage stabilizing transistor M3 is electrically connected with the second clock signal terminal XCK, the first terminal of the third voltage stabilizing transistor M3 is electrically connected with the second terminal of the fifth transistor T5, and the second terminal of the third voltage stabilizing transistor M3 is electrically connected with the second node N2. As shown in Figure 18 , in the driving circuit 100, the gate of the sixth transistor T6 is electrically connected with the second clock signal terminal XCK, and the gate of the third voltage stabilizing transistor M3 is electrically connected with the always-on level terminal VGK. Or as shown in Figure 19 , in the driving circuit 100, the gate of the sixth transistor T6 is electrically connected with the always-on level terminal VGK, and the gate of the third voltage stabilizing transistor M3 is electrically connected with the second clock signal terminal XCK. Or as shown in Figure 20 , in the driving circuit 100, the gate of the sixth transistor T6 and the gate of the third voltage stabilizing transistor M3 are both electrically connected with the second clock signal terminal XCK.

[0146] It should be noted that the driving circuit 100 shown in Figure 5 , Figures 7 to 20 provided by the embodiments of the present application is only a part of all the circuits to which the present application is applicable, and the present application does not make specific limitations thereon. In addition, the driving circuit 100 provided by the embodiments of the present application is not limited to the above-mentioned circuits. Figure 5 , Figures 7 to 20The working process of the driving circuit 100 can be derived from the timing diagram shown in FIG. 6, which is not repeated here. In some embodiments, the first level signal VG1 output by the first level terminal VGL; or, the first level signal VG1 can also be the first level output by the second clock signal terminal XCK; wherein, when the gate of the sixth transistor T6 is electrically connected with the always-on level terminal VGK, the first level signal VG1 is the level output by the first level terminal VGL, avoiding the second level of the second clock signal terminal XCK being transmitted to the second node N2, and affecting the control state of the second node N2. As the fifth transistor T5 is an N-type transistor, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the fourteenth transistor T14, the fifteenth transistor T15, the sixteenth transistor T16, the first voltage stabilizing transistor M1, the second voltage stabilizing transistor M2, the third voltage stabilizing transistor M3 and the fifth voltage stabilizing transistor M5 are all P-type transistors, the first level output by the second clock signal terminal XCK and the level output by the first level terminal VGL are both low level signals.

[0147] The above description of the driving circuit 100 is taken as an example that the fifth transistor T5 included in the second driving input module 112 is different from the other transistors in the on type. In some embodiments, all the transistors in the second driving input module 112 provided by the embodiments of the present application can also be the same as the on type of the transistors of other modules. For details, refer to Figure 21As shown in FIG. 7, a circuit diagram of another driving circuit provided by the embodiment of the present application is shown, and the second driving input module 112 provided by the embodiment of the present application includes a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10 and a sustain capacitor Cw. The gate of the seventh transistor T7 is electrically connected with the first clock signal terminal CK, the first terminal of the seventh transistor T7 is electrically connected with the first voltage level terminal VGL, the second terminal of the seventh transistor T7 is electrically connected with the second terminal of the eighth transistor T8, and the first voltage level signal VG1 is the voltage level output by the first voltage level terminal VGL. The gate of the eighth transistor T8 is electrically connected with the first node N1, the first terminal of the eighth transistor T8 is electrically connected with the first clock signal terminal CK, and the second terminal of the eighth transistor T8 is electrically connected with the first plate of the sustain capacitor Cw. The gate of the ninth transistor T9 is electrically connected with the first plate of the sustain capacitor Cw, the first terminal of the ninth transistor T9 is electrically connected with the second clock signal terminal XCK, and the second terminal of the ninth transistor T9 is electrically connected with the second terminal of the sustain capacitor Cw. The gate of the tenth transistor T10 is electrically connected with the second clock signal terminal XCK, the first terminal of the tenth transistor T10 is electrically connected with the second plate of the sustain capacitor Cw, and the second terminal of the tenth transistor T10 is electrically connected with the second node N2. Optionally, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the fourteenth transistor T14, the fifteenth transistor T15, the sixteenth transistor T16, the first voltage stabilizing transistor M1, the second voltage stabilizing transistor M2, the third voltage stabilizing transistor M3 and the fifth voltage stabilizing transistor M5 provided by the embodiment of the present application are all of the same conduction type, such as all being P-type transistors, so as to facilitate the preparation of the driving circuit 100.

[0148] In combination Figure 21 the driving circuit 100 and Figure 6a the timing diagram shown in FIG. 7, Figure 21The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the fourteenth transistor T14, the fifteenth transistor T15 and the sixteenth transistor T16 are all P-type transistors. The first level end VGL is a low level end, and the first level signal VG1 is a low level signal. The always-on level end VGK is a low level end, and the always-on level end VGK can be reused as the first level end VGL to reduce the number of level ends. Figure 21 In the driving circuit 100, when the control end Ctrl is a low level signal to control the thirteenth transistor T13 to be turned on, the second node N2 and the third node N3 are connected, and the scanning circuit is in a high-frequency refresh state (at this time, the output waveforms of the cascade output end OUT and the gating output end OUTx are consistent), wherein the working processes of the pull-down stage S1, the input stage S2, the output stage S3, the maintenance stage S4, the transition stage S5 and the end stage S6 are as follows:

[0149] In the pull-down stage S1, the first clock signal end CK controls the first transistor T1 to be turned on, so as to transmit the low level signal of the input signal end IN at this time to the first node N1. The low level signal of the first node N1 can control the eleventh transistor T11 to be turned on, and the eleventh transistor T11 transmits the low level signal of the first clock signal end CK at this time to the second node N2. The low level signal of the second node N2 can control the twelfth transistor T12 to be turned on, and the twelfth transistor T12 transmits the low level signal of the first clock signal end CK at this time to the cascade output end OUT, and the cascade output end OUT outputs an invalid level. At the same time, since the second node N2 and the third node N3 are connected, the fifteenth transistor T15 is turned on based on the signal control of the third node N3, and transmits the low level signal of the first clock signal end CK at this time to the gating output end OUTx, and the gating output end OUTx outputs an invalid level.

[0150] In the input stage S2, the first clock signal end CK controls the first transistor Tl to be turned on, so as to transmit the high level signal of the input signal end IN at this time to the first node Nl. The first clock signal end CK also controls the seventh transistor T7 to be turned on, so as to transmit the low level signal of the first level signal VG1 to the first plate of the sustain capacitor Cw, so as to control the ninth transistor T9 to be turned on. At the same time, the low level signal of the second clock signal end XCK controls the tenth transistor T10 to be turned on, so as to transmit the low level signal of the second clock signal end XCK to the second node N2. The low level signal of the second node N2 controls the twelfth transistor T12 to be turned on, and the twelfth transistor T12 transmits the low level signal of the first clock signal end CK at this time to the cascade output end OUT, and the cascade output end OUT outputs the invalid level. At the same time, since the second node N2 and the third node N3 are connected, the fifteenth transistor T15 is turned on based on the signal control of the third node N3, so as to transmit the low level signal of the first clock signal end CK at this time to the gating output end OUTx, and the gating output end OUTx outputs the invalid level.

[0151] In the output stage S3, the first clock signal end CK at this time is high level, so as to control the first transistor Tl to be turned off, and the first node Nl keeps the high level signal in the input stage S2 without voltage input. At this time, the sustain capacitor Cw keeps the ninth transistor T9 to be turned on, and the low level signal of the second clock signal end XCK controls the tenth transistor T10 to be turned on, so as to continuously transmit the low level signal of the second clock signal end XCK to the second node N2. Until the second clock signal end XCK becomes the high level signal, the second node N2 keeps the low level signal without voltage input. The low level signal of the second node N2 in the output stage S3 controls the twelfth transistor T12 to be turned on, and the twelfth transistor T12 transmits the high level signal of the first clock signal end CK at this time to the cascade output end OUT, and the cascade output end OUT outputs the effective level. At the same time, since the second node N2 and the third node N3 are connected, the fifteenth transistor T15 is turned on based on the signal control of the third node N3, so as to transmit the high level signal of the first clock signal end CK at this time to the gating output end OUTx, and the gating output end OUTx outputs the effective level.

[0152] In the maintaining stage S4, the first node N1 has no other voltage input and maintains the high level signal in the output stage S3. The second clock signal end XCK is a high level signal and controls the tenth transistor T10 to be off, and the second node N2 has no voltage input and maintains the same low level signal as in the output stage S3. The low level signal of the second node N2 in the output stage S3 controls the twelfth transistor T12 to be on, and the twelfth transistor T12 transmits the high level signal of the first clock signal end CK at this time to the cascade output end OUT, and the cascade output end OUT maintains the output active level. At the same time, since the second node N2 and the third node N3 are connected, the fifteenth transistor T15 is on based on the signal control of the third node N3, and transmits the high level signal of the first clock signal end CK at this time to the gating output end OUTx, and the gating output end OUTx outputs the active level.

[0153] In the transition stage S5, the first clock signal end CK is a low level signal at this time and controls the first transistor T1 to be on, so as to transmit the low level signal of the input signal end IN at this time to the first node N1. The low level signal of the first node N1 can control the eleventh transistor T11 to be on, and the eleventh transistor T11 transmits the low level signal of the first clock signal end CK to the second node N2. The twelfth transistor T12 is on based on the low level signal control of the second node N2, and transmits the low level signal of the first clock signal end CK to the cascade output end OUT, and the cascade output end OUT outputs the inactive level. At the same time, since the second node N2 and the third node N3 are connected, the fifteenth transistor T15 is on based on the signal control of the third node N3, and transmits the low level signal of the first clock signal end CK at this time to the gating output end OUTx, and the gating output end OUTx outputs the inactive level. In addition, the first capacitor C1 couples the low level signal of the first clock signal end CK to the second node N2, so as to adjust the low level voltage of the second node N2 to a level voltage less than the first level end VGL, so as to enable the low level signal of the first clock signal end CK to be more fully transmitted to the cascade output end OUT, so as to avoid the problem of step voltage when the cascade output end OUT outputs the inactive level.

[0154] At the end stage S6, the first node N1 low level signal controls the second transistor T2 to turn on, and the low level signal of the second clock signal end XCK is coupled to the first node N1 through the second capacitor C2, so as to adjust the voltage of the first node N1 to a lower voltage, thereby being able to better control the sufficient turn-on of the fourth transistor T4, the eleventh transistor T11 and the sixteenth transistor T16 through the low level of the first node N1, the fourth transistor T4 transmits the low level signal of the first level end VGL to the cascade output end OUT, and the cascade output end OUT outputs an invalid level; meanwhile, the sixteenth transistor T16 transmits the low level signal of the first level end VGL to the gating output end OUTx, and the gating output end OUTx outputs an invalid level.

[0155] With reference to the schematic diagram of the driving circuit 100 shown in Figure 21 With reference to the schematic diagram of the driving circuit 100 shown in Figure 6b The working process of the driving circuit 100 provided by the embodiment of the present application is described in detail with reference to the timing diagram shown in the schematic diagram of the driving circuit 100 and in combination with the working process of the driving circuit 100. Figure 21 In the driving circuit 100 shown in the schematic diagram, when the thirteenth transistor T13 is controlled to be cut off by the high level signal of the gating control end Ctrl, the second node N2 and the third node N3 are disconnected, and the scanning circuit is in a low frequency refresh state (at this time, the gating output end OUTx continuously outputs an invalid level), the working process of the pull-down stage S1, the input stage S2, the output stage S3, the maintaining stage S4, the transition stage S5 and the end stage S6 of the driving circuit 100 is respectively as follows:

[0156] At the pull-down stage S1, the first transistor T1 is controlled to be turned on by the first clock signal end CK, so as to transmit the low level signal of the input signal end IN to the first node N1. The low level signal of the first node N1 can control the eleventh transistor T11 to be turned on, and the eleventh transistor T11 transmits the low level signal of the first clock signal end CK to the second node N2. The low level signal of the second node N2 can control the twelfth transistor T12 to be turned on, and the twelfth transistor T12 transmits the low level signal of the first clock signal end CK to the cascade output end OUT, and the cascade output end OUT outputs an invalid level. Meanwhile, the fourteenth transistor T14 is turned on based on the signal control of the first node N1, transmits the low level signal of the first clock signal end CK to the third node N3, the fifteenth transistor T15 is turned on based on the signal control of the third node N3, transmits the low level signal of the first clock signal end CK to the gating output end OUTx, and the sixteenth transistor T16 is turned on based on the signal control of the first node N1, transmits the low level signal of the first level end VGL to the gating output end OUTx, and the gating output end OUTx outputs an invalid level.

[0157] In the input stage S2, the first clock signal terminal CK controls the first transistor Tl to be turned on, so as to transmit the high level signal of the input signal terminal IN at this time to the first node Nl. The first clock signal terminal CK also controls the seventh transistor T7 to be turned on, so as to transmit the low level signal of the first level signal VGl to the first plate of the sustain capacitor Cw, so as to control the ninth transistor T9 to be turned on. Meanwhile, the low level signal of the second clock signal terminal XCK controls the tenth transistor TlO to be turned on, so as to transmit the low level signal of the second clock signal terminal XCK to the second node N2. The low level signal of the second node N2 controls the twelfth transistor T12 to be turned on, and the twelfth transistor T12 transmits the low level signal of the first clock signal terminal CK at this time to the cascade output terminal OUT, so that the cascade output terminal OUT outputs an invalid level. Meanwhile, the fourteenth transistor T14 is turned off based on the signal control of the first node Nl, the third node N3 keeps the same voltage as that in the pull-down stage S l without voltage input, and the third node N3 controls the fifteenth transistor T15 to be turned on, so as to transmit the low level signal of the first clock signal terminal CK at this time to the gating output terminal OUTx, and the gating output terminal OUTx outputs an invalid level.

[0158] In the output stage S3, the first clock signal terminal CK at this time is high level, so as to control the first transistor Tl to be turned off, and the first node Nl keeps the high level signal in the input stage S2 without voltage input. At this time, the sustain capacitor Cw maintains the control of the ninth transistor T9 to be turned on, and the low level signal of the second clock signal terminal XCK controls the tenth transistor TlO to be turned on, so as to continuously transmit the low level signal of the second clock signal terminal XCK to the second node N2. Until the second clock signal terminal XCK becomes a high level signal, the second node N2 keeps the low level signal without voltage input. The low level signal of the second node N2 in the output stage S3 controls the twelfth transistor T12 to be turned on, and the twelfth transistor T12 transmits the high level signal of the first clock signal terminal CK at this time to the cascade output terminal OUT, so that the cascade output terminal OUT outputs a valid level. Meanwhile, the fourteenth transistor T14 is turned off based on the signal control of the first node Nl, the high level signal of the first clock signal terminal CK is coupled to the third node N3 through the third capacitor C3, so that the third node N3 is high level, the third node N3 controls the fifteenth transistor T15 to be turned off, and the gating output terminal OUTx keeps the same voltage as that in the input stage S2 without other voltage input, so that the gating output terminal OUTx outputs an invalid level.

[0159] In the maintaining stage S4, the first node N1 has no other voltage input and keeps the high level signal in the output stage S3. The second clock signal end XCK is a high level signal and controls the tenth transistor T10 to be off, and the second node N2 has no voltage input and keeps the same low level signal as in the output stage S3. The low level signal of the second node N2 in the output stage S3 controls the twelfth transistor T12 to be on, and the twelfth transistor T12 transmits the high level signal of the first clock signal end CK at this time to the cascade output end OUT, and the cascade output end OUT maintains the output active level. Meanwhile, the fourteenth transistor T14 is controlled to be off based on the signal of the first node N1, and the high level signal of the first clock signal end CK is coupled to the third node N3 through the third capacitor C3, so that the third node N3 is high level, the third node N3 controls the fifteenth transistor T15 to be off, and the gating output end OUTx has no other voltage input and keeps the same voltage as in the output stage S3, and the gating output end OUTx outputs the inactive level.

[0160] In the transition stage S5, the first clock signal end CK is a low level signal at this time and controls the first transistor T1 to be on, so as to transmit the low level signal of the input signal end IN at this time to the first node N1. The low level signal of the first node N1 can control the eleventh transistor T11 to be on, and the eleventh transistor T11 transmits the low level signal of the first clock signal end CK to the second node N2. The twelfth transistor T12 is controlled to be on based on the low level signal of the second node N2, and transmits the low level signal of the first clock signal end CK to the cascade output end OUT, and the cascade output end OUT outputs the inactive level. The fourteenth transistor T14 is controlled to be on based on the signal of the first node N1, and transmits the low level signal of the first clock signal end CK to the third node N3, and the fifteenth transistor T15 is controlled to be on based on the signal of the third node N3, and transmits the low level signal of the first clock signal end CK at this time to the gating output end OUTx; and the sixteenth transistor T16 is controlled to be on based on the signal of the first node N1, and transmits the low level signal of the first level end VGL to the gating output end OUTx, and the gating output end OUTx outputs the inactive level. In addition, the first capacitor C1 couples the low level signal of the first clock signal end CK to the second node N2, so as to adjust the low level voltage of the second node N2 downward to a level voltage less than the first level end VGL, so as to enable the low level signal of the first clock signal end CK to be more fully transmitted to the cascade output end OUT, so as to avoid the problem of step voltage when the cascade output end OUT outputs the inactive level.

[0161] At the end of the stage S6, the first node N1 low level signal control the second transistor T2, the low level signal of the second clock signal end XCK is coupled to the first node N1 through the second capacitor C2, so as to adjust the voltage of the first node N1 to a lower voltage, thereby the low level of the first node N1 can better control the sufficient conduction of the fourth transistor T4, the eleventh transistor T11 and the sixteenth transistor T16, the fourth transistor T4 transmits the low level signal of the first level end VGL to the cascade output end OUT, and the cascade output end OUT outputs an invalid level; at the same time, the sixteenth transistor T16 transmits the low level signal of the first level end VGL to the gating output end OUTx, and the gating output end OUTx outputs an invalid level.

[0162] Reference Figure 22 As shown in FIG. 12, it is a circuit diagram of another driving circuit provided by the embodiment of the present application, the driving circuit 100 provided by the embodiment of the present application further comprises: a fourth voltage stabilizing transistor M4, a gate of the fourth voltage stabilizing transistor M4 is electrically connected with a constant-on level end VGK, a first end of the fourth voltage stabilizing transistor M4 is electrically connected with a second end of the seventh transistor T7 and a second end of the eighth transistor T8, and a second end of the fourth voltage stabilizing transistor M4 is electrically connected with a gate of the ninth transistor T9 and a first plate of the maintaining capacitor Cw. Optionally, the first transistor T1 to the fourth transistor T4, the sixth transistor T6 to the sixteenth transistor T16, and the first voltage stabilizing transistor M1 to the fifth voltage stabilizing transistor M5 provided by the embodiment of the present application are all of the same conduction type, such as P-type transistors, so as to facilitate the preparation of the driving circuit 100; at the same time, the constant-on level end VGK electrically connected with the fourth voltage stabilizing transistor M4 can reuse the first level end VGL to reduce the number of ports.

[0163] Reference Figure 23 As shown in FIG. 12, it is a circuit diagram of another driving circuit provided by the embodiment of the present application, the driving circuit 100 provided by the embodiment of the present application further comprises: a fourth voltage stabilizing transistor M4, a gate of the fourth voltage stabilizing transistor M4 is electrically connected with a constant-on level end VGK, a first end of the fourth voltage stabilizing transistor M4 is electrically connected with a second end of the seventh transistor T7 and a second end of the eighth transistor T8, and a second end of the fourth voltage stabilizing transistor M4 is electrically connected with a gate of the ninth transistor T9 and a first plate of the maintaining capacitor Cw. Optionally, the first transistor T1 to the fourth transistor T4, the sixth transistor T6 to the sixteenth transistor T16, and the first voltage stabilizing transistor M1 to the fifth voltage stabilizing transistor M5 provided by the embodiment of the present application are all of the same conduction type, such as P-type transistors, so as to facilitate the preparation of the driving circuit 100; at the same time, the constant-on level end VGK electrically connected with the fourth voltage stabilizing transistor M4 can reuse the first level end VGL to reduce the number of ports.

[0164] Based on the same inventive concept, the embodiment of the present application further provides a scanning circuit, the scanning circuit comprising the driving circuit 100 provided by any one of the above embodiments.Figure 24 The diagram shown is a circuit diagram of a scanning circuit provided in an embodiment of this application. The scanning circuit 10 provided in this embodiment includes: a first clock signal line VCK1, a second clock signal line VCK2, a third clock signal line VCK3, a fourth clock signal line VCK4, and at least one repeating circuit unit 11; the clock signals output by the first clock signal line VCK1, the second clock signal line VCK2, the third clock signal line VCK3, and the fourth clock signal line VCK4 have the same period and duty cycle, and sequentially have the set phase difference. Figure 25 The timing diagrams of the various clock signal lines shown indicate that there is a set phase difference between the first clock signal line VCK1 and the second clock signal line VCK2, a set phase difference between the second clock signal line VCK2 and the third clock signal line VCK3, and a set phase difference between the third clock signal line VCK3 and the fourth clock signal line VCK4.

[0165] Continue as Figure 24As shown, the repeating circuit unit 11 includes four driving circuits 100 cascaded, and is defined as a first driving circuit 101, a second driving circuit 102, a third driving circuit 103 and a fourth driving circuit 104 cascaded in turn; in the first driving circuit 101, the first clock signal end CK is electrically connected with the first clock signal line VCK1, and the second clock signal end XCK is electrically connected with the second clock signal line VCK2; in the second driving circuit 102, the first clock signal end CK is electrically connected with the second clock signal line VCK2, and the second clock signal end XCK is electrically connected with the third clock signal line VCK3; in the third driving circuit 103, the first clock signal end CK is electrically connected with the third clock signal line VCK3, and the second clock signal end XCK is electrically connected with the fourth clock signal line VCK4; in the fourth driving circuit 104, the first clock signal end CK is electrically connected with the fourth clock signal line VCK4, and the second clock signal end XCK is electrically connected with the first clock signal line VCK1; in all the driving circuits 100 cascaded, the cascade output end OUT of the previous driving circuit 100 is electrically connected with the input signal end IN of the next driving circuit 100. That is, in one repeating circuit unit 11, the cascade output end OUT of the first driving circuit 101 is electrically connected with the input signal end IN of the second driving circuit 102, the cascade output end OUT of the second driving circuit 102 is electrically connected with the input signal end IN of the third driving circuit 103, and the cascade output end OUT of the third driving circuit 103 is electrically connected with the input signal end IN of the fourth driving circuit 104; and then in two adjacent repeating circuit units 11, the cascade output end OUT of the fourth driving circuit 104 of the previous repeating circuit unit 11 is electrically connected with the input signal end IN of the first driving circuit 101 of the next repeating circuit unit 11. In addition, in all the driving circuits 100 cascaded, the input signal end IN of the first driving circuit 100 is externally connected with an opening control signal line.

[0166] Based on the same inventive concept, the embodiment of the present application further provides a display panel, which comprises the scanning circuit 10 provided by any one of the above embodiments. For reference Figure 26As shown in FIG. 1, it is a schematic diagram of a partial structure of a display panel provided in an embodiment of the present application. The display panel 1000 provided in the embodiment of the present application comprises the scan circuit 10 provided in any one of the above embodiments. The scan circuit 10 can be used to provide a driving signal for a pixel circuit. The function is the same as that of the prior art driving circuit 100, and the present application will not make redundant description. In addition, in other embodiments of the present application, the scan circuit 10 can also be used to provide a corresponding driving signal for other applicable circuits, and the present application will not make specific limitation. Optionally, the scan circuit 10 provided in the embodiment of the present application can be arranged on one side of the display panel 1000. Or as shown in FIG. 2, the display panel 1000 is provided with a scan circuit 10 on each of the opposite sides, and the present application will not make specific limitation. Figure 27

[0167] Based on the same inventive concept, the embodiment of the present application also provides an electronic device. Referring to FIG. 3, it is a schematic diagram of a structure of an electronic device provided in an embodiment of the present application. The electronic device 1 comprises the display panel 1000 provided in any one of the above embodiments. In some embodiments, the electronic device 1 provided in the embodiment of the present application can be a mobile terminal, a notebook, a tablet computer, a computer, a wearable device, and the like, and the present application will not make specific limitation. Figure 28

[0168] In summary, the embodiment of the present application provides a driving circuit, a scan circuit, a display panel and an electronic device. The driving circuit comprises a driving unit and a gating unit. The driving unit comprises a first driving input module, a second driving input module, a first driving pull-down module, a second driving pull-down module, a first driving output module and a second driving output module. The gating unit comprises a gating control module, a gating pull-down module, a first gating output module and a second gating output module. Thus, the work of the driving circuit is completed by the cooperation of the driving unit and the gating unit, the circuit structure of the driving circuit is simplified, the occupied area of the scan circuit is reduced, and the narrow frame design of the display panel is facilitated.

[0169] In the description of the embodiments of the present application, it should be understood that the orientation or positional relationship indicated by terms such as "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like is the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, which is only for the convenience of describing the embodiments of the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application.

[0170] ​​Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of embodiments of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0171] In the embodiments of this application, unless otherwise explicitly specified and limited, terms such as "installation," "connection," "linking," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0172] In the embodiments of this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0173] In the embodiments of this application, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0174] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A driving circuit, characterized in that, The driving circuit includes a driving unit and a gating unit; The driving unit includes: A first driving input module is electrically connected to at least an input signal terminal and a first clock signal terminal, and connects the input signal terminal to a first node based at least on the signal control of the first clock signal terminal. The second driving input module is electrically connected to at least the first node or the input signal terminal and is connected to a first level signal. Based at least on the signal control of the first node or the input signal terminal, the second driving input module transmits the first level signal to the second node. The first drive pull-down module is electrically connected to at least the first node and the second clock signal terminal, and couples the signal of the second clock signal terminal to the first node based on the signal control of the first node; the clock signals output by the first clock signal terminal and the second clock signal terminal have the same period and duty cycle, and have a set phase difference. The second drive pull-down module is electrically connected to at least the first node and the first clock signal terminal, and connects the first clock signal terminal and the second node based on the signal control of the first node. A first drive output module is electrically connected to at least the first node and a first level terminal, and connects the first level terminal to the cascaded output terminal of the drive circuit based at least on the signal control of the first node, wherein the first level signal and the level of the first level terminal are the same. The second drive output module is electrically connected to at least the second node and the first clock signal terminal, and connects the first clock signal terminal and the cascaded output terminal based on the signal control of the second node. The gating unit includes: A gating control module, which is electrically connected to at least a gating control terminal and the second node, and connects the second node and the third node based on the signal control of the gating control terminal at least. A gating pull-down module, which is electrically connected to at least the first clock signal terminal, is used to connect the first clock signal terminal and the third node at the end of the effective level output at the cascaded output terminal. The first gating output module is electrically connected to at least the first clock signal terminal and the third node, and connects the first clock signal terminal and the gating output terminal of the gating unit based at least on the signal control of the third node. The second gating output module is electrically connected to at least the first node and the first level terminal, and connects the first level terminal and the gating output terminal based at least on the signal control of the first node.

2. The driving circuit according to claim 1, characterized in that, The drive unit further includes: A coupling module, which is electrically connected to the second node and the first clock signal terminal, is used to couple the voltage level output by the first clock signal terminal to the second node at the end of the effective level output by the cascaded output terminal.

3. The driving circuit according to claim 2, characterized in that, The coupling module includes: The first capacitor has its first plate electrically connected to the first clock signal terminal and its second plate electrically connected to the second node.

4. The driving circuit according to claim 1, characterized in that, The first drive input module includes: The first transistor has its gate electrically connected to the first clock signal terminal, its first terminal electrically connected to the input signal terminal, and its second terminal electrically connected to the first node.

5. The driving circuit according to claim 1, characterized in that, The driving circuit also includes: The first Zener transistor has its gate electrically connected to a normally open terminal, its first terminal electrically connected to the output terminal of the first drive input module, and its second terminal electrically connected to the first node.

6. The driving circuit according to claim 1, characterized in that, The first driver pull-down module includes: The second transistor and the second capacitor are connected in the following ways: the gate of the second transistor is electrically connected to the first node; the first terminal of the second transistor is electrically connected to the second clock signal terminal; the second terminal of the second transistor is electrically connected to the first plate of the second capacitor; and the second plate of the second capacitor is electrically connected to the first node.

7. The driving circuit according to claim 6, characterized in that, The first driver pull-down module also includes: The third transistor is electrically connected between the second plate of the second capacitor and the first node. The second plate of the second capacitor is electrically connected to the gate of the third transistor. The gate of the third transistor and the first terminal of the third transistor are both electrically connected to the output terminal of the first drive input module. The second terminal of the third transistor is electrically connected to the first node.

8. The driving circuit according to claim 7, characterized in that, The driving circuit also includes: The second Zener transistor has its gate electrically connected to a normally open terminal, its first terminal electrically connected to the output terminal of the first drive input module, and its second terminal electrically connected to the first terminal of the third transistor.

9. The driving circuit according to claim 1, characterized in that, The first drive output module includes: The fourth transistor has its gate electrically connected to the first node, its first terminal electrically connected to a first voltage level terminal, and its second terminal electrically connected to the cascaded output terminal.

10. The driving circuit according to claim 1, characterized in that, The second drive input module includes: The fifth transistor has its gate electrically connected to the first node or the input signal terminal, its first terminal connected to the first level signal, and its second terminal electrically connected to the second node.

11. The driving circuit according to claim 10, characterized in that, The second drive input module also includes: The sixth transistor has its gate electrically connected to either a normally open level terminal or a second clock signal terminal, its first terminal connected to the first level signal, and its second terminal electrically connected to the first terminal of the fifth transistor.

12. The driving circuit according to claim 11, characterized in that, The first level signal is either the level output from the first level terminal or the first level output from the second clock signal terminal; When the gate of the sixth transistor is electrically connected to the normally open level terminal, the first level signal is the level output by the first level terminal.

13. The driving circuit according to claim 10, characterized in that, The drive unit further includes: The third Zener transistor has its gate electrically connected to either a normally open level terminal or a second clock signal terminal, its first terminal electrically connected to the second terminal of the fifth transistor, and its second terminal electrically connected to the second node.

14. The driving circuit according to claim 1, characterized in that, The second drive input module includes: The seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, and the sustaining capacitor; The gate of the seventh transistor is electrically connected to the first clock signal terminal, the first terminal of the seventh transistor is electrically connected to the first level terminal, the second terminal of the seventh transistor is electrically connected to the second terminal of the eighth transistor, and the first level signal is the level output by the first level terminal; The gate of the eighth transistor is electrically connected to the first node, the first terminal of the eighth transistor is electrically connected to the first clock signal terminal, and the second terminal of the eighth transistor is electrically connected to the first plate of the sustaining capacitor. The gate of the ninth transistor is electrically connected to the first plate of the sustaining capacitor, the first terminal of the ninth transistor is electrically connected to the second clock signal terminal, and the second terminal of the ninth transistor is electrically connected to the second terminal of the sustaining capacitor. The gate of the tenth transistor is electrically connected to the second clock signal terminal, the first terminal of the tenth transistor is electrically connected to the second plate of the sustaining capacitor, and the second terminal of the tenth transistor is electrically connected to the second node.

15. The driving circuit according to claim 14, characterized in that, The drive unit further includes: The fourth Zener transistor has its gate electrically connected to a normally open terminal, its first terminal electrically connected to the second terminals of the seventh and eighth transistors, and its second terminal electrically connected to the gate of the ninth transistor and the first plate of the sustaining capacitor.

16. The driving circuit according to claim 1, characterized in that, The second drive pull-down module includes: The eleventh transistor has its gate electrically connected to the first node, its first terminal electrically connected to the first clock signal terminal, and its second terminal electrically connected to the second node.

17. The driving circuit according to claim 1, characterized in that, The second drive output module includes: The twelfth transistor has its gate electrically connected to the second node, its first terminal electrically connected to the first clock signal terminal, and its second terminal electrically connected to the cascaded output terminal.

18. The driving circuit according to claim 1, characterized in that, The gating control module includes: The thirteenth transistor has its gate electrically connected to the gating control terminal, its first terminal electrically connected to the second node, and its second terminal electrically connected to the third node.

19. The driving circuit according to claim 1, characterized in that, The gating unit further includes: The fifth Zener transistor has its gate electrically connected to a normally open level terminal, its first terminal electrically connected to the output terminal of the gating control module, and its second terminal electrically connected to the third node.

20. The driving circuit according to claim 1, characterized in that, The gating dropdown module includes: The fourteenth transistor has its gate electrically connected to the first node, its first terminal electrically connected to the first clock signal terminal, and its second terminal electrically connected to the third node.

21. The driving circuit according to claim 7, characterized in that, The gating dropdown module includes: The fourteenth transistor has its gate electrically connected to the second plate of the second capacitor, its first terminal electrically connected to the first clock signal terminal, and its second terminal electrically connected to the third node.

22. The driving circuit according to claim 1, characterized in that, The first strobe output module includes: The fifteenth transistor and the third capacitor are described, wherein the gate of the fifteenth transistor is electrically connected to the third node, the first terminal of the fifteenth transistor is electrically connected to the first clock signal terminal, the second terminal of the fifteenth transistor is electrically connected to the gating output terminal, the first plate of the third capacitor is electrically connected to the first clock signal terminal, and the second plate of the third capacitor is electrically connected to the third node.

23. The driving circuit according to claim 1, characterized in that, The second strobe output module includes: The sixteenth transistor has its gate electrically connected to the first node, one end of the sixteenth transistor electrically connected to the first level terminal, and its second end electrically connected to the gating output terminal.

24. A scanning circuit, characterized in that, The scanning circuit includes the driving circuit according to any one of claims 1-23.

25. The scanning circuit according to claim 24, characterized in that, The scanning circuit includes: A first clock signal line, a second clock signal line, a third clock signal line, a fourth clock signal line, and at least one repeating circuit unit; The clock signals output by the first clock signal line, the second clock signal line, the third clock signal line, and the fourth clock signal line all have the same period and duty cycle, and sequentially have the set phase difference; The repeating circuit unit includes four cascaded driving circuits, and is defined as a first driving circuit, a second driving circuit, a third driving circuit, and a fourth driving circuit cascaded in sequence; in the first driving circuit, the first clock signal terminal is electrically connected to the first clock signal line, and the second clock signal terminal is electrically connected to the second clock signal line. In the second driving circuit, the first clock signal terminal is electrically connected to the second clock signal line, and the second clock signal terminal is electrically connected to the third clock signal line. In the third driving circuit, the first clock signal terminal is electrically connected to the third clock signal line, and the second clock signal terminal is electrically connected to the fourth clock signal line. In the fourth driving circuit, the first clock signal terminal is electrically connected to the fourth clock signal line, and the second clock signal terminal is electrically connected to the first clock signal line. In all the cascaded drive circuits, the cascaded output terminal of the previous stage drive circuit is electrically connected to the input signal terminal of the next stage drive circuit.

26. A display panel, characterized in that, The display panel includes the scanning circuit as described in claim 24 or 25.

27. An electronic device, characterized in that, The electronic device includes the display panel as described in claim 26.

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