Tcspc memory circuit and data read / write method thereof

Abstract

The application provides a TCSPC storage circuit and a data read-write method thereof. The TCSPC storage circuit stores single acquisition data in each time difference interval by using a first memory, and stores data obtained by performing logical operation on multiple acquisition data in each time difference interval by using a second memory. Based on this, by flexibly configuring the number of rows and columns of the first memory and the second memory, the adjustment of the storage space and the storage density is realized, the chip area size occupied by the TCSPC storage circuit is effectively reduced, the read-write period is shortened, and the high device power consumption caused by frequent read-write is avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of memory, in particular to a TCSPC storage circuit and a data reading and writing method thereof. BACKGROUND

[0002] Time-correlated single photon counting (TCSPC) is a high-precision time measurement technology. By recording the arrival time of a single photon, the time distribution characteristics of the photon sequence are analyzed, and repeated measurements can generate a time-photon distribution curve. This technology is widely used in laser ranging, fluorescence lifetime measurement, photon migration measurement and other fields.

[0003] Taking laser ranging as an example, a laser radar usually includes a transmitting unit and a receiving unit for transmitting and detecting laser pulse signals, respectively. By recording the time of flight t (Time of flight, ToF) from laser emission to detection of the echo signal, the distance R of the target object can be calculated, R=C·t / 2, where C represents the speed of light. In order to accurately obtain the time of flight t, TCSPC is usually used as a readout circuit. For details, please refer to Figures 1 to 3 Taking the TCSPC circuit 11 of a single pixel 10 in the receiving unit as an example. The TCSPC circuit 11 includes a histogram accumulator 110 and a memory 111. Among them, in a single measurement process, the transmitting unit will repeatedly light the target object multiple times, and the histogram accumulator 110 is used to accumulate the number of photons detected by the pixel 10 in the multiple lighting processes; and the memory 111 is used to store the detected number of photons. The memory 111 includes a plurality of storage units 1110, each of which corresponds to each time difference interval, for storing the number of photons detected by the pixel 10 in the corresponding time difference interval. For example, Figure 2 The n time difference intervals shown in the figure are respectively corresponding to n storage units 1110, which can be respectively denoted as bin0, bin1, bin2, bin3, bin4, bin5, …, binn-1. Assuming that the time period of each time difference interval is dt, then at each lighting, taking the laser pulse emitted by the transmitting unit as the timing zero point, the pixel 10 performs sampling every time difference interval of time period dt and outputs the detected number of photons to the histogram accumulator 110, and the histogram accumulator 110 reads the data in the corresponding storage unit 1110 in the memory 111 according to the current sampling time difference interval and adds it to the current output value of the pixel 10, and the added result is stored in the corresponding storage unit 1110. The specific accumulation process is as follows Figure 3As shown, assume that the illumination is repeated k times during a single measurement, and there are n time difference intervals and corresponding n storage units 1110. When the illumination is applied for the first time, the number of photons detected in each time difference interval is s. 10 s 11 s 12 s 13 s 14 s 15 ... s 1n-1 During the second illumination, the number of photons detected in each time difference interval was s. 20 s 21 s 22 s 23 s 24 s 25 ... s 2n-1 During the third illumination, the number of photons detected in each time zone was s. 30 s 31 s 32 s 33 s 34 s 35 ... s 3n-1 Until the kth illumination, the number of photons detected in each time difference interval is s. k0 s k1 s k2 s k3 s k4 s k5 ... s kn-1 After k illumination cycles, the cumulative number of photons in the storage unit 1110 corresponding to each time difference interval is as follows: S0 = s 10 +s 20 +……+s k0 S1=s 11 +s 21 +……+s k1 ... Sn-1 = s 1n-1 +s 2n-1 +……+s kn-1 Therefore, based on the above data, we can obtain... Figure 4 The histogram shown. And by Figure 4It is known that the number of photons detected is highest in the time difference interval [Pdt, (P+1)dt], therefore the probability of detecting photons in this interval is higher than in other time difference intervals. Consequently, the probability of flight time t falling within the time difference interval [Pdt, (P+1)dt] is highest. Therefore, the flight time t can be determined using relevant data processing algorithms, and the distance R of the target object can then be calculated. It is worth noting that in the above description, the time difference interval corresponding to each storage unit bin is the same (i.e., all are dt). In reality, the time difference interval corresponding to each storage unit bin can be the same or different, meaning the size of the time difference interval corresponding to each storage unit can be flexibly configured according to the ranging accuracy requirements. For ease of description, the following explanation will also use the example of each storage unit bin having the same time difference interval.

[0004] Based on this Figure 4 A smaller time interval (dt) for each time difference range allows for higher ranging accuracy, but also places higher demands on the clock frequency or bandwidth for memory read / write operations. Currently, the TCSPC circuit 11 primarily uses Static Random Access Memory (SRAM). SRAM is characterized by high read / write speeds but low information storage density. For example... Figure 5 As shown, taking a 6T SRAM (six transistors) as an example, each 6T SRAM in the array acts as a bit cell, capable of storing one bit of binary data (0 or 1). Figure 5 The SRAM array shown includes M×N bit cells, where M and N are both positive integers. Typically, the data of a storage cell 1110 is stored in the same row of SRAM. For example, the cumulative photon count within the first time difference interval [0, dt] is stored in the first storage cell bin0, and the cumulative photon count within the second time difference interval [dt, 2dt] is stored in the second storage cell bin1. Similarly, the cumulative photon count within the nth time difference interval [(n-1)dt, ndt] is stored in the nth storage cell binn-1. Therefore, during read / write operations, data is read and written row by row. The data must first be read from the SRAM corresponding to the row of storage cell 1110, then added to the input data, and finally written back to the SRAM corresponding to the row of storage cell 1110; that is, the data update of storage cell 1110 corresponding to one time difference interval is completed. This requires at least two SRAM clock cycles to complete the read / write operation of one storage cell 1110; furthermore, the storage space required by the existing storage method is also relatively large.

[0005] Assuming that 1024 storage units 1110 are included in one TCSPC circuit 11. The storage space size of each storage unit 1110 is 16 bitcells, so the SRAM storage space size of a single TCSPC circuit 11 needs to be 1024*16=16384 bitcells. If the time difference interval dt corresponding to each storage unit 1110 is 1 ns, the SRAM read-write clock frequency is at most 250 MHz; that is, the clock period is 4 ns, so it takes at least 8 ns to complete the read-write of a row of data, and at least 8 storage units 1110 need to be read / written at a time. Therefore, at least 8*16=128 bitcells are included on one word line (WL), so the SRAM array can be 128 (rows) * 128 (columns) bitcells. However, in actual SRAM applications, the bitcells on one WL are not necessarily equal to the port bit width of the SRAM. In most cases, the port bit width is 2 k times the number of bitcells on one WL, so an additional column decoder is needed to select the required data from these bitcells. Therefore, the existing SRAM array can be configured in the form of 64 (rows) * 256 (columns) bitcells, 32 (rows) * 512 (columns) bitcells, etc. Generally speaking, the more bitcells on the same row, the larger the area occupied by the SRAM read-write circuit, resulting in lower storage density. However, in the existing storage scheme, due to the relatively high requirement of data read-write rate on bandwidth, the port width can only be made relatively large, resulting in low storage density and large physical area occupied by the same storage space.

[0006] Therefore, there is an urgent need for a new TCSPC storage circuit to solve the above technical problems. SUMMARY

[0007] The purpose of the present application is to provide a TCSPC storage circuit and a data read-write method thereof, at least to solve at least one of the problems of how to reduce the occupied area of the memory and how to reduce the power consumption of the memory.

[0008] To solve the above technical problems, the present application provides a TCSPC storage circuit, comprising: a first memory, a second memory, a read-write circuit and a calculator; wherein,

[0009] The first memory comprises a plurality of first bitcells arranged in an array; each column of first bitcells constitutes at least one first storage unit; each first storage unit corresponds to a time difference interval, and is at least used for storing single acquisition data within the corresponding time difference interval;

[0010] The second memory comprises a plurality of second bit cells arranged in an array; each column of the second bit cells constitutes at least one second memory cell; each second memory cell corresponds to one time difference interval and is used to store data obtained by logical operation on a plurality of pieces of the collected data in the corresponding time difference interval;

[0011] The read-write circuit is connected to the first memory and is used to receive single pieces of the collected data in different time difference intervals and write the single pieces of the collected data in different time difference intervals into the corresponding first memory cells column by column; and read out the stored data in each first memory cell column by column.

[0012] The calculator is used to read the stored data in the first memory and the second memory row by row, perform the logical operation on the stored data in the first memory cell and the second memory cell corresponding to the same time difference interval, and update and store the data obtained by the logical operation into the second memory cell corresponding to the time difference interval.

[0013] Optionally, in the TCSPC storage circuit, the number of the first memory cells in the first memory is equal to the number of the second memory cells in the second memory; each first memory cell corresponds to one time difference interval; and each second memory cell corresponds to one time difference interval.

[0014] Optionally, in the TCSPC storage circuit, the number of the second memory cells in the second memory is an integer multiple of the number of the first memory cells in the first memory; and the read-write circuit is further used to perform read-write operation on the first memory in batches, and in each batch of read-write operation, each first memory cell corresponds to each time difference interval belonging to the same batch; and each second memory cell corresponds to each time difference interval of all batches.

[0015] Optionally, in the TCSPC storage circuit, the first bit cell is used to store one bit of binary number, the second bit cell is used to store one bit of binary number, and the collected data in each time difference interval comprises K bits of binary number; wherein,

[0016] The first memory cell comprises K first bit cells, the second memory cell comprises K second bit cells, and K is a positive integer; or,

[0017] The first memory cell comprises i first bit cells, the second memory cell comprises K second bit cells, and 1

[0018] The read-write circuit is further configured to, in a write operation, sequentially write the first-i bit binary numbers in the collected data into the corresponding first storage units; and

[0019] The calculator is further configured to, after reading and accumulating each i-th row in the first storage units and each i-th row in the corresponding second storage units, respectively perform the logical operation between the storage data of i+1-th to K-th rows in the corresponding second storage units and 0, and update the i+1-th to K-th rows in the corresponding second storage units.

[0020] Optionally, in the TCSPC storage circuit, in the first memory, each of the first bit units arranged in rows is sequentially connected, and each row is selected and controlled by a horizontal word line; each of the first bit units arranged in columns is sequentially connected, and each column is selected and controlled by a vertical word line; and the first memory further comprises a first row decoder and a first column decoder, which are respectively connected with each of the horizontal word lines and each of the vertical word lines, for selecting and editing each of the first bit units row by row or column by column.

[0021] In the second memory, each of the second bit units arranged in rows is sequentially connected, and each row is selected and controlled by a word line; each of the second bit units arranged in columns is sequentially connected, and each column is selected and edited by a bit line; and the second memory further comprises a second row decoder and a second column decoder, which are respectively connected with each of the word lines and each of the bit lines, for selecting and editing each of the second bit units row by row.

[0022] Optionally, in the TCSPC storage circuit, the second memory further comprises a multiplexing module for selecting and editing part of the second bit units; wherein,

[0023] The multiplexing module comprises a plurality of selectors; and each of the selectors is connected with a plurality of the bit lines in the second memory, for selecting one of the second bit units to read out or write in each time the read-out or write-in operation is performed; and,

[0024] The number of the bit lines connected with each of the selectors is the same, and the number of the selectors in the multiplexing module is the same as the number of columns of the first bit units in the first memory.

[0025] Optionally, in the TCSPC storage circuit, the first memory is divided into at least two first sub-memories; and each of the first sub-memories comprises part of the first bit units arranged in an array; the second memory is divided into at least two second sub-memories; and each of the second sub-memories comprises part of the second bit units arranged in an array.

[0026] The first sub-memory and the second sub-memory correspond to each other, and one first sub-memory and one corresponding second sub-memory form a storage combination structure; each storage combination structure is used to store or read out the acquisition data corresponding to a plurality of time difference intervals in cooperation with the read-write circuit and the calculator; wherein, a plurality of continuous time difference intervals are a time difference interval segment, and the acquisition data corresponding to two continuous time difference interval segments are stored in different storage combination structures; and

[0027] Each storage combination structure is further used to, after the first sub-memory in the storage combination structure corresponding to a previous time difference interval segment completes writing of the corresponding acquisition data, the first sub-memory in the storage combination structure corresponding to a next time difference interval segment starts to execute writing of the corresponding acquisition data; at the same time, the first sub-memory and the second sub-memory in the storage combination structure corresponding to the previous time difference interval segment start to execute the logical operation and update of the storage data.

[0028] Optionally, in the TCSPC storage circuit, the period of writing the acquisition data in the first sub-memory in one storage combination structure is greater than or equal to the period of the logical operation and update of the storage data in another storage combination structure.

[0029] Optionally, in the TCSPC storage circuit, the first bit unit comprises an 8T SRAM, the second bit unit comprises a 6T SRAM, a DRAM or an MRAM; and the logical operation comprises one or more combination operations of addition operation, AND operation, OR operation, NOT operation, XOR operation and assignment operation.

[0030] Based on the same inventive concept, the present application also provides a data read-write method of a TCSPC storage circuit, wherein,

[0031] The process of executing data writing by using the TCSPC storage circuit comprises:

[0032] The read-write circuit receives single acquisition data in different time difference intervals, and writes the single acquisition data in different time difference intervals into different first storage units in the first memory column by column;

[0033] The calculator reads the storage data in the first memory and the second memory row by row, performs a logical operation on the storage data in the first storage unit corresponding to the same time difference interval and the second storage unit in the second memory, and updates the data after the logical operation and stores the data into the second storage unit corresponding to the time difference interval.

[0034] The process of data reading out is performed by using the TCSPC storage circuit, which includes:

[0035] The stored data in the second memory is read out row by row and written into the first memory row by row.

[0036] The stored data in each first storage unit in the first memory is read out column by column by using the read-write circuit.

[0037] In summary, the TCSPC storage circuit and the data reading and writing method thereof are provided. Compared with the prior art, the TCSPC storage circuit stores single acquisition data in each time difference interval by using the first memory, and stores data obtained by logical operation of multiple acquisition data in each time difference interval by using the second memory. Based on this, by flexibly configuring the number of rows and columns of the first memory and the second memory, the adjustment of the storage space and the storage density is realized, the chip area size occupied by the TCSPC storage circuit is effectively shortened, the read-write period is shortened, and the high device power consumption caused by frequent reading and writing is avoided. BRIEF DESCRIPTION OF DRAWINGS

[0038] Those skilled in the art will understand that the provided drawings are for better understanding of the present application, and do not constitute any limitation on the scope of the present application.

[0039] Figure 1 It is a structural schematic diagram of the TCSPC circuit in the prior art.

[0040] Figure 2 It is a structural schematic diagram of the storage unit in the memory in the prior art.

[0041] Figure 3 It is a storage schematic diagram of each storage unit in the k-time light process in the prior art.

[0042] Figure 4 It is a histogram of the number of photons accumulated in each time difference interval in the prior art.

[0043] Figure 5 It is a structural schematic diagram of the TCSPC circuit in the prior art.

[0044] Figure 6 It is a structural schematic diagram of the TCSPC storage circuit in the first embodiment of the present application.

[0045] Figure 7 It is a storage distribution schematic diagram of the first memory and the second memory in the first example in the first embodiment of the present application.

[0046] Figure 8Storage distribution diagram of the first memory and the second memory for the first example in the embodiment one of the present application.

[0047] Figure 9 Storage distribution diagram of the first memory and the second memory for the third example in the embodiment two of the present application.

[0048] Figure 10 Structure diagram of the TCSPC storage circuit in the embodiment three of the present application.

[0049] Figure 11 Storage distribution diagram of the first memory and the second memory for the sixth example in the embodiment three of the present application.

[0050] Figure 12 Structure diagram of the TCSPC storage circuit in the embodiment four of the present application.

[0051] And, in the drawings:

[0052] 10 - pixel; 11 - TCSPC circuit; 110 - histogram accumulator; 111 - memory; 1110 - storage unit;

[0053] 20 - first memory; 20a - first sub-memory; 200 - first bit cell; 201 - first row decoder; 202 - first column decoder;

[0054] 30 - second memory; 30a - second sub-memory; 300 - second bit cell; 301 - second row decoder; 302 - second column decoder; 303 - multiplexing module; 3030 - selector;

[0055] 40 - read-write circuit; 50 - calculator; bitcell - bit cell. DETAILED DESCRIPTION

[0056] For the purposes of the present invention, its advantages and features, the following will be further described in detail in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are very simplified and not drawn to scale, and are only used to facilitate and clarify the purpose of assisting the description of the embodiments of the present invention. In addition, the structures shown in the drawings are often part of the actual structure. In particular, different scales are sometimes used to emphasize different aspects of the drawings. It should also be understood that, unless specifically described or indicated, the terms "first", "second", "third" and the like in the description are only used to distinguish the components, elements, steps and the like in the description, and are not used to represent the logical relationship or sequence relationship between the components, elements, steps and the like. In addition, the singular form "one", "an" and "the" in the specification includes plural objects, the term "or" is generally used in the sense of including "and / or", the term "several" is generally used in the sense of including "at least one", and the term "at least two" is generally used in the sense of including "two or more".

[0057] <Embodiment I>

[0058] Please refer to Figure 6 The embodiment provides a TCSPC storage circuit, which comprises a first memory 20, a second memory 30, a read-write circuit 40 and a calculator 50; wherein,

[0059] The first memory 20 comprises a plurality of first bit cells 200 arranged in an array; each column of the first bit cells 200 constitutes at least one first storage unit; each first storage unit corresponds to a time difference interval and is used for storing single acquisition data in the corresponding time difference interval;

[0060] The second memory 30 comprises a plurality of second bit cells 300 arranged in an array; each column of the second bit cells 300 constitutes at least one second storage unit; each second storage unit corresponds to a time difference interval and is used for storing data obtained by logical operation of a plurality of acquisition data in the corresponding time difference interval;

[0061] The read-write circuit 40 is connected with the first memory 20 and is used for receiving single acquisition data in different time difference intervals and writing the single acquisition data in different time difference intervals into corresponding first storage units column by column; and reading out the storage data in each first storage unit column by column;

[0062] The calculator 50 is configured to read the stored data in the first memory 20 and the second memory 30 row by row, perform the logical operation on the stored data in the first memory unit and the second memory unit corresponding to the same time difference interval, and update and store the data after the logical operation into the second memory unit corresponding to the time difference interval.

[0063] Based on the same concept, the embodiment further provides a data reading and writing method of the TCSPC storage circuit. The process of data writing performed by the TCSPC storage circuit comprises:

[0064] The reading and writing circuit 40 is configured to receive single acquisition data in different time difference intervals and write the single acquisition data in different time difference intervals into different first memory units in the first memory 20 column by column.

[0065] The calculator 50 is configured to read the stored data in the first memory 20 and the second memory 30 row by row, perform the logical operation on the stored data in the first memory unit and the second memory unit corresponding to the same time difference interval, and update and store the data after the logical operation into the second memory unit corresponding to the time difference interval.

[0066] In addition, the process of data reading performed by the TCSPC storage circuit comprises:

[0067] The stored data in the second memory 30 is read row by row and written into the first memory 20 row by row.

[0068] The reading and writing circuit 40 is configured to read the stored data in each first memory unit in the first memory 20 column by column.

[0069] The TCSPC storage circuit and the data reading and writing method thereof provided by the embodiment will be described in detail below with reference to the accompanying drawings.

[0070] Please continue to refer to Figure 6 The TCSPC storage circuit provided by the embodiment is used to realize the storage and reading of acquisition data in different time difference intervals. For example, the TCSPC storage circuit is applied to a laser radar. After the first laser pulse signal is sent by the emission unit in the laser radar, the number of received photons needs to be recorded every time difference interval, and the number of received photons is taken as acquisition data and stored in the TCSPC storage circuit. Therefore, a plurality of memory units are set in the TCSPC storage circuit according to the different time difference intervals. Each memory unit stores the number of photons in a time difference interval.

[0071] Since the laser radar emits multiple laser pulse signals in the ranging process, the number of photons in different time difference intervals needs to be stored after each laser pulse signal is emitted according to the above method, and the number of photons counted from different laser pulse signals in the same time difference interval needs to be accumulated as the total number of photons corresponding to the time difference interval.

[0072] Therefore, to meet the above storage requirements, the TCSPC storage circuit provided in the embodiment includes a first memory 20, a second memory 30, a read-write circuit 40, and a calculator 50. The first memory 20 is configured to store single acquisition data in different time difference intervals after each laser pulse signal is emitted in a writing process, and store accumulated data in different time difference intervals in a reading process. The second memory 30 is configured to store and accumulate single acquisition data in different time difference intervals after each laser pulse signal is emitted, and finally store accumulated data of the acquisition data in different time difference intervals after multiple laser pulse signals are emitted. In the embodiment, single acquisition data refers to the number of photons acquired in a time difference interval after a laser pulse signal is emitted. In the embodiment, multiple acquisition data refers to the number of photons acquired multiple times in a same time difference interval after multiple laser pulse signals are emitted one by one.

[0073] To meet the storage requirements of the first memory 20 and the second memory 30, the read-write circuit 40 serves as a read-write interface and is configured to receive the acquisition data in different time difference intervals after each laser pulse signal is emitted in a writing process, and write the corresponding acquisition data into different first memory cells column by column; and in a reading process, read out the stored data in each first memory cell column by column. The calculator 50 is mainly configured to implement a logical operation function, that is, read the stored data in the first memory 20 and the second memory 30 row by row and perform a logical operation on the stored data, so that the stored data in the first memory cell and the second memory cell corresponding to a same time difference interval is subjected to a logical operation, and the data after the logical operation is stored in the second memory cell corresponding to the time difference interval. In the embodiment, the logical operation includes but is not limited to one or a combination of addition, AND operation, OR operation, NOT operation, XOR operation, and assignment operation. To fully illustrate the TCSPC storage circuit and the data read-write method provided in the embodiment, the logical operation in the following description is taken as an example of addition, and other operation modes are not exemplified one by one.

[0074] Specifically, the first memory 20 includes a plurality of first bit cells 200 arranged in an array. Preferably, each first bit cell 200 includes 8T SRAM; that is, an SRAM composed of 8 transistors. The 8T SRAM can be read and written row by row or column by column. The row-arranged first bit cells 200 are connected sequentially, and each row is selected and controlled by a horizontal word line (HWL); the column-arranged first bit cells 200 are connected sequentially, and each column is selected and controlled by a vertical word line (VWL) to achieve bidirectional access. Furthermore, the first memory 20 also includes a first row decoder 201 and a first column decoder 202, which are respectively connected to the horizontal word line and the vertical word line to enable row-by-row or column-by-column selection and editing of each first bit cell 200.

[0075] Furthermore, in the first memory 20, each column of the first bit units 200 constitutes at least one first storage unit. Each first storage unit stores a single collection of data within a time difference interval. For example, the collected data within each time difference interval is represented in binary, requiring K binary bits. Each first bit unit 200 can store one binary bit. In this embodiment, the collected data is stored column-wise in the corresponding first storage units, so the number of first bit units 200 in each column needs to be greater than or equal to K, for example, an integer multiple of K.

[0076] Assume that the first memory 20 includes K×N first bit cells 200 to form a first storage array; and K and N are positive integers. Figure 6 As shown, each column of the first memory 20 contains K first bit units 200, and there are a total of N columns. Therefore, the first memory 20 can constitute N first storage units, and can store the acquired data corresponding to N time difference intervals. The N first storage units are respectively denoted as: bin0', bin1', bin2', bin3', bin4', ..., binN-2', binN-1'. Furthermore, the time difference interval corresponding to each first storage unit is each time interval dt after the laser pulse signal is emitted, and each time difference interval is respectively denoted as: [0, dt], [dt, 2dt], [2dt, 3dt], [3dt, 4dt], [4dt, 5dt], ..., [N-2dt, N-1dt], [N-1dt, Ndt]. That is, each first storage unit corresponds to one time difference interval.

[0077] Since the first memory 20 is connected with the read-write circuit 40, and after a laser pulse signal is sent, the number of received photons is counted every time interval dt, as the collection data corresponding to the time difference interval. Therefore, when the read-write circuit 40 writes the collection data into the first memory 20, the collection data of N time difference intervals can be written into N first memory cells in sequence. For example, the collection data of the time difference interval [0, dt] is written into the first memory cell bin0', the collection data of the time difference interval [dt, 2dt] is written into the first memory cell bin1', and so on, until the collection data of the time difference interval [N-1dt, Ndt] is written into the first memory cell binN-1'.

[0078] Please continue to refer to Figure 6 The second memory 30 includes a plurality of second bit cells 300 arranged in an array. Preferably, the second bit cell 300 includes a 6T SRAM, i.e., an SRAM composed of six transistors, and the 6T SRAM can only be read and written in rows. Each of the second bit cells 300 arranged in rows is connected in sequence, and each row is selected and controlled by a word line. Each of the second bit cells 300 arranged in columns is connected in sequence, and each column is selected and edited by a bit line. The second memory 30 further includes a second row decoder 301 and a second column decoder 302, which are connected with each of the word lines and each of the bit lines, respectively, to select and edit each of the second bit cells 300 row by row.

[0079] The second memory 30 is also columnarly constructed. That is, the second memory 30 stores data in columns. However, the second memory 30 is different from the first memory 20 in that the second memory 30 stores the collected data accumulated in each time difference interval. For example, in the process of laser ranging, k laser pulse signals are emitted, and after each laser pulse signal is emitted, the number of photons is counted at every time interval dt. For example, after each laser pulse signal is emitted, the number of photons is counted in the following time difference intervals: [0, dt], [dt, 2dt], [2dt, 3dt], [3dt, 4dt], [4dt, 5dt], …, [N-2dt, N-1dt], [N-1dt, Ndt]. Accordingly, the second memory 30 has N second memory units corresponding to the N time difference intervals, respectively denoted as bin0, bin1, bin2, bin3, bin4, …, binN-2, binN-1. The second memory unit bin0 stores the collected data accumulated in the first time difference interval [0, dt] after each laser pulse signal is emitted, the second memory unit bin1 stores the collected data accumulated in the second time difference interval [dt, 2dt] after each laser pulse signal is emitted, and the other second memory units store the collected data accumulated in the corresponding time difference intervals after each laser pulse signal is emitted. Therefore, the data stored in the second memory 30 is histogram data.

[0080] Based on this, the second memory 30 needs to obtain the collection data of each time difference interval after each laser pulse signal is sent from the first memory 20 in time, and add the accumulated data in the corresponding time difference interval to itself, and then update the added data to the second storage unit corresponding to the time interval. Therefore, the TCSPC storage circuit is also provided with the calculator 50 for reading and accumulating the storage data in the first memory 20 and the second memory 30 by row, so that the storage data in the first storage unit and the second storage unit corresponding to the same time difference interval is accumulated; and the accumulated data is updated and stored in the second storage unit corresponding to the time difference interval. It should be noted that in the accumulation process, although the calculator 50 reads the storage data in each first storage unit and each second storage unit by row, since the collection data and the storage data are stored by column in this embodiment, in the operation process, the sum of one row of the first bit unit 200 performing full addition operation and the corresponding row of the second bit unit 300 is written back to the second bit unit 300 of the corresponding row, and the carry is taken as the input of the next row full addition operation; that is, the carry is still calculated by column, so that the accumulation of the storage data in the first storage unit and the second storage unit corresponding to the same time difference interval can be realized.

[0081] Further, the total number of the first storage units in the first memory 20 and the total number of the second storage units in the second memory 30 can be equal or different.

[0082] Please refer to Figure 7In the first example, the total number of the first memory cells in the first memory 20 is equal to the total number of the second memory cells in the second memory 30. And the number of the first bit cells 200 in the first memory cell is equal to the number of the second bit cells 300 in the second memory cell. For example, the first memory 20 includes 128x128 first bit cells 200. Each first memory cell includes 16 first bit cells 200; that is, the collection data is a 16-bit binary number. Therefore, the first memory 20 can be composed of 8x128 first memory cells, and corresponds to 1024 time difference intervals. And each first memory cell is respectively recorded as: bin0', bin1', bin2', bin3', bin4',..., bin1022', bin1023'. Similarly, the second memory 30 also includes 128x128 second bit cells 300, and each second memory cell also includes 16 second bit cells 300; that is, it can be composed of 8x128 second memory cells, and also corresponds to 1024 time difference intervals. And each second memory cell is respectively recorded as: bin0, bin1, bin2, bin3, bin4,..., bin1022, bin1023.

[0083] Based on this, the data read-write method of the TCSPC storage circuit includes:

[0084] When performing data writing, the read-write circuit 40 writes the collection data corresponding to 1024 time difference intervals of continuous sampling into the first memory 20 column by column. That is, 128 column writing is performed to fill 8x128 first memory cells. Then, the calculator 50 reads out the collection data in the first memory 20 row by row, and reads out the storage data in the second memory 30 row by row, to perform 128-bit full accumulation operation row by row, and update the storage data in the second memory 30 row by row. Wherein, when first accumulating, the storage data in the second memory 30 is all assigned as 0. And in the 16th, 32nd, 48th, 64th, 80th, 96th and 112th rows of the second memory 30, because these rows are the starting bits of another second memory cell, the carry of these rows is 0. And the carry of the 1st-15th, 17th-31st,..., 113th-127th rows is taken as the carry after adding the data of the previous row; that is, the carry is calculated in column, so as to ensure that the storage data in the first memory cell and the second memory cell corresponding to the same time difference interval is accumulated.

[0085] When the data readout is performed, the 128 rows of stored data in the second memory 30 are written into the corresponding 128 rows in the first memory 20 row by row, and then the 128 columns of stored data in the first memory 20 are read out column by column by using the read-write circuit 40, so that the readout of the accumulated data in the 1024 time difference intervals corresponding to the 8*128 first storage units is completed.

[0086] As can be seen from the above, in the first example, the first memory 20 and the second memory 30 each include 128*128 bit cells, so that the data storage of 1024 time difference intervals can be completed through one batch of continuous acquisition and storage. In order to reduce the size of the TCSPC storage circuit, the number of first storage units in the first memory 20 can be reduced to store in batches. In the batch storage mode, the number of second storage units in the second memory 30 is an integer multiple of the number of first storage units in the first memory 20. Each second storage unit corresponds to each time difference interval of all batches, and each first storage unit only needs to correspond to each time difference interval of the same batch.

[0087] Please refer to Figure 8 In the second example, the total number of first storage units in the first memory 20 is less than the total number of second storage units in the second memory 30. For example, the first memory 20 includes 64*128 first bit cells 200. The second memory 30 includes 128*128 second bit cells 300. Since the acquisition data is a 16-bit binary number, and the first storage unit includes 16 first bit cells 200 and the second storage unit includes 16 second bit cells 300, the first memory 20 includes 4*128 first storage units, corresponding to 512 time difference intervals; the second memory 30 includes 8*128 second storage units, corresponding to 1024 time difference intervals. Among them, each first storage unit is respectively recorded as: bin0', bin1', bin2', bin3', bin4',..., bin510', bin511'; each second storage unit is respectively recorded as: bin0, bin1, bin2, bin3, bin4,..., bin1022, bin1023.

[0088] Obviously, unlike the first example, the time difference interval corresponding to the first memory 20 is reduced by half compared to the time difference interval corresponding to the second memory 30. It is understood that the stored data in the second memory 30 corresponds to histogram data, therefore the data in each of the second storage units in the second memory 30 needs to correspond one-to-one with the time difference intervals collected after each laser pulse information emission, in order to store the accumulated data corresponding to all the time difference intervals. The first memory 20 stores the collected data corresponding to the time difference intervals continuously sampled after one laser pulse information emission. Therefore, to reduce the overall area of ​​the storage circuit, the number of the first bit units 200 can be reduced, and by increasing the write batches, the storage of the collected data corresponding to all the time difference intervals of one laser pulse information emission can be completed. As can be seen from the above, according to... Figure 8 The first memory 20 shown needs to perform two batches of data storage. The first batch is to store the corresponding acquired data with time difference intervals of [0, dt], [dt, 2dt], [2dt, 3dt], ..., [511dt, 512dt]. The second batch is to store the corresponding acquired data with time difference intervals of [512dt, 513dt], [513dt, 514dt], [514dt, 515dt], ..., [1023dt, 1024dt].

[0089] Specifically, when performing data writing, the read / write circuit 40 first writes the collected data corresponding to the first 512 consecutively sampled time difference intervals into the first memory 20 column by column. That is, it performs 128 writes to fill 4×128 of the first storage cells; that is, it fills bin0', bin1', bin2', bin3', bin4', ..., bin510', bin511'. Then, the calculator 50 reads all the collected data from the first memory 20 row by row, and reads the stored data of the corresponding row in the second memory 30 row by row; that is, bin0, bin1, bin2, bin3, bin4, ..., bin510, bin511, and then performs a 128-bit full accumulation operation row by row, and updates the stored data of the second storage cells bin0~bin511 in the second memory 30 row by row.

[0090] Then, the read-write circuit 40 continues to write the collected data corresponding to the last 512 time difference intervals into the first memory 20 row by row. The writing is performed 128 times to fill the 4x128 first memory cells; that is, bin0', bin1', bin2', bin3', bin4',..., bin510', bin511' are filled again. Then, the calculator 50 reads out all the collected data in the first memory 20 row by row and reads out the corresponding row of the stored data in the second memory 30 row by row; that is, bin512, bin513, bin514, bin515, bin516,..., bin1022, bin1023. The full accumulation operation of 128 bits is performed row by row, and the stored data of the second memory cells bin512-bin1023 in the second memory 30 is updated row by row.

[0091] Further, when the data readout is performed, the stored data of the corresponding rows of the second memory cells bin0-bin511 in the second memory 30 is written into the corresponding rows of the first memory cells bin0'-bin511' in the first memory 20 row by row. Then, the read-write circuit 40 reads out the stored data of 128 columns in the first memory 20 row by row, and the readout of the accumulated data in the first 512 time difference intervals corresponding to the 4x128 first memory cells is completed. Subsequently, the stored data of the corresponding rows of the second memory cells bin512-bin1023 in the second memory 30 is written into the corresponding rows of the first memory cells bin0'-bin511' in the first memory 20 row by row. Finally, the read-write circuit 40 reads out the stored data of 128 columns in the first memory 20 row by row, and the readout of the accumulated data in the last 512 time difference intervals is completed.

[0092] It is to be noted that in the present embodiment, each time the writing from outside to inside or the reading from inside to outside is performed, one clock cycle T is required. In the design of the calculation in memory, the reading, accumulation and updating of the corresponding rows of the first memory 20 and the second memory 30 by the calculator 50 belong to the read-write operation between the internal, and the time required for this read-write operation is controlled within one clock cycle T. Therefore, in the first example, after the laser pulse signal is emitted, the first memory 20 performs 128 times of column writing from outside to inside, which requires 128 clock cycles T; the second memory 30 performs 128 times of row updating, which also requires 128 clock cycles T. In the process of data reading, based on the design of the calculation in memory, the 128 rows of data in the second memory 30 are read row by row and then written into the first memory 20 row by row, which also requires 128 clock cycles T. However, the reading of the 128 columns of storage data in the first memory 20 by the read-write circuit 40 belongs to the reading from inside to outside, which requires 128 clock cycles T. Therefore, in the first example, for one laser pulse signal, the total time required for data accumulation and updating is 128 x 2 clock cycles T. In addition, the reading of the accumulated histogram data stored in the second memory 30 requires 128 x 2 clock cycles T.

[0093] In the second example, since a single column in the first memory 20 is 64 first bit cells 200, which only corresponds to 512 time interval intervals, after the laser pulse signal is emitted, 128 times of column writing need to be performed twice, which requires 128 x 2 clock cycles T; the second memory 30 still needs to update 128 rows of data, which requires 128 clock cycles T. In the process of data reading, based on the design of the calculation in memory, the 64 rows of data in the second memory 30 are read row by row and then written into the first memory 20 row by row, which requires 64 clock cycles T; and the reading of the 128 columns of storage data in the first memory 20 by the read-write circuit 40 requires 128 clock cycles T. Then, the remaining 64 rows of data in the second memory 30 are read row by row and written into the first memory 20, which requires 64 clock cycles T; and the reading of the 128 columns of storage data in the first memory 20 by the read-write circuit 40 also requires 128 clock cycles T. Therefore, in the second example, for one laser pulse signal, the total time required for data accumulation and updating is 128 x 3 clock cycles T. In addition, the reading of the accumulated histogram data stored in the second memory 30 requires 128 x 3 clock cycles T.

[0094] Therefore, in the first example, the total number of the first storage units in the first memory 20 is equal to the total number of the second storage units in the second memory 30, and all the collected data corresponding to the time difference intervals needs to be stored in the first memory 20 and the second memory 30. Such a TCSPC storage circuit has the characteristics of large storage space, large occupied area, and short read-write period. In the second example, the total number of the first storage units in the first memory 20 is less than the total number of the second storage units in the second memory 30, and the storage space in the first memory 20 can only store part of the collected data corresponding to the time difference intervals. Such a TCSPC storage circuit has the characteristics of small storage space, small occupied area, and long read-write period. Based on this, different types of TCSPC storage circuits can be flexibly selected according to actual application requirements.

[0095] Further, the above is only an exemplary description of data collection and storage after the emission of a laser pulse signal. In actual ranging applications, the laser radar will emit laser pulse signals multiple times according to the set frequency and correspondingly collect. Among them, the data collection and storage after the emission of each laser pulse signal can refer to the above description. And the data stored after the emission of each laser pulse signal is accumulated in the second storage unit corresponding to each time difference interval in the second memory 30. And after completing the data storage after the emission of all the laser pulse signals, the stored data can be read out according to the above data reading process.

[0096] It should be noted that the interval time between two laser pulse signals is much greater than the sum of all the time difference intervals. For example Figure 7 In the first example shown, the time period dt of each time difference interval is 1 ns, and the total time of collecting data corresponding to all the time difference intervals is 1024dt=1024ns. The interval time between two laser pulse signals is much greater than 1024ns, for example, 10μs. Based on this, assuming that each clock cycle T is 4ns, the time spent to complete the data collection and storage after the emission of a laser pulse signal is 128×2T=1024ns. Therefore, from data collection to data storage, a total of 2048ns is spent, which is much less than 10μs. Similarly, for the second example shown in Figure 8 In the second example shown, the time spent to complete the data collection and storage after the emission of a laser pulse signal is 128×3T=1536ns, and the total time from data collection to data storage is 2560ns, which is also much less than 10μs.

[0097] Therefore, according to the interval time of the two laser pulse signals, the arrangement and the number of the bit cells in the first memory 20 and the second memory 30 can be diversified to meet different requirements of the storage space, the storage density and the power consumption of the TCSPC storage circuit in practical applications. In addition, since the interval time of the two laser pulse signals is long, some other types of memories with low read-write frequency but high storage density can be used to replace the 6T SRAM in the second memory 30, such as Dynamic Random Access Memory (DRAM) and Magnetoresistive Random Access Memory (MRAM), so as to further save the area occupied by the memory and reduce the cost.

[0098] In summary, the TCSPC storage circuit and the data read-write method thereof provided in the embodiment store the single acquisition data in each time difference interval in the first memory 20 and store the accumulated data of the multiple acquisition data in each time difference interval in the second memory 30. Based on this, by configuring the number of rows and columns of the first memory 20 and the second memory 30, the purpose of flexibly adjusting the storage space and the storage density is achieved, which not only can control the chip area size occupied by the TCSPC storage circuit, but also can shorten the read-write period and avoid high device power consumption caused by frequent read-write. In addition, the parts not described in detail in the embodiment can be referred to the description in other embodiments.

[0099] <Embodiment Two>

[0100] Please refer to Figure 6 and Figure 9 to further reduce the size of the first memory 20 and meet the development trend of device miniaturization. Based on the TCSPC storage circuit and the data read-write method thereof provided in other embodiments, the embodiment further provides a TCSPC storage circuit and a data read-write method thereof. The TCSPC storage circuit includes a first memory 20, a second memory 30, a read-write circuit 40 and a calculator 50. It should be noted that the basic structure and function of the first memory 20, the second memory 30, the read-write circuit 40 and the calculator 50 are described in other embodiments, and will not be described here.

[0101] Further, in practical applications, the maximum number of photons accumulated in each time difference interval is much smaller than the maximum number of binary numbers that can be stored by the first memory unit. For example, a memory unit includes 16 first bit cells 200, i.e., 16-bit binary. The maximum value of 16-bit binary is 2 6- 1 = 65535. The maximum value of the number of photons accumulated in the time interval depends on the configuration of the pixel, for example, 9, which is much smaller than 65535. Therefore, during storage, the 0-3 bits of the binary number corresponding to the 16 first bit units 200 in each first storage unit store data, and the 4-15 bits are certainly 0, which causes waste of storage space. To this end, the first memory 20 provided in the embodiment reduces the data of the first bit unit 200 in each first storage unit, so as to further reduce the size of the chip occupied by the first memory 20.

[0102] Specifically, the collected data in each time interval includes K binary numbers, and the binary number corresponding to the maximum value of the number of photons actually stored only needs i bits; and 1 < i < K, i and K are integers. Therefore, the first storage unit in the first memory 20 provided in the embodiment includes i first bit units 200; that is, one first storage unit is used to store 0-i-1 binary numbers. The second storage unit includes K second bit units 300; that is, one second storage unit is used to store 0-K-1 binary numbers.

[0103] Based on this, when the read-write circuit 40 is used to perform a write operation on the first memory 20, only the binary data of the 0-i-1 bits in the collected data corresponding to the time interval is written into the first storage unit corresponding to the time interval in the column. In addition, during the reading and logical operation process of the calculator 50, since the number of binary bits stored in the first storage unit and the second storage unit corresponding to the same time interval is different, after reading and logically operating the data of all rows of a first storage unit, the data of the remaining rows in the corresponding second storage unit which have not been logically operated are logically operated with 0 respectively, and the corresponding rows in the second storage unit are updated and stored.

[0104] The TCSPC storage circuit and the data reading and writing method thereof provided in the embodiment will be specifically described below with examples. The logical operation involved takes addition as an example.

[0105] As Figure 9As shown in the third example, the first memory 20 includes 16x128 first bit cells 200, and the second memory 30 includes 128x128 second bit cells 300. Assuming K=16 and i=4, the second memory 30 can form 8x128 second memory cells to correspond to 1024 time interval bins respectively. In the first memory 20, the 0~3 rows in the 0th column can form a first first memory cell bin0', the 4~7 rows can form a second first memory cell bin1', the 8~11 rows can form a third first memory cell bin2', and the 12~15 rows can form a fourth first memory cell bin3'. Similarly, the first memory 20 can form 4x128 first memory cells to correspond to 512 time interval bins respectively, and two batches of data storage are needed to complete the data storage of 1024 time interval bins for one laser pulse information. Therefore, when the read-write circuit 40 performs the write operation on the first memory 20, only the binary data of the 0~3 bits in the collected data corresponding to the time interval bins are written into the first memory cells corresponding to the time interval bins in the column. For example, the first first memory cell bin0' stores the 4-bit binary photon number corresponding to the first time interval bin [0, dt] of the current collection.

[0106] In the first batch of data storage, each of the first storage units bin0'~bin511' in the first memory 20 corresponds to each of the second storage units bin0~bin511 in the second memory 30. In the second batch of data collection and storage, each of the first storage units bin0'~bin511' in the first memory 20 corresponds to each of the second storage units bin512~bin1023 in the second memory 30. Taking the first batch of data collection and storage as an example, the first storage units included in the 0~3 rows of the first memory 20 are bin0', bin4', bin8', …, bin508' respectively; and the first storage units included in the 0~15 rows of the second memory 30 are bin0, bin4, bin8, …, bin508 respectively. Based on this, in the process of reading, accumulating and updating row by row, the 0th row of the first memory 20 and the 0th row of the second memory 30 are read first, and accumulation and data updating are performed; then the 1st row of the first memory 20 and the 1st row of the second memory 30 are read, and accumulation and data updating are performed; then the 2nd row of the first memory 20 and the 2nd row of the second memory 30 are read, and accumulation and data updating are performed; then the 3rd row of the first memory 20 and the 3rd row of the second memory 30 are read, and accumulation and data updating are performed. At this time, the data of the corresponding row in the single first storage unit in the first memory 20 has been read, while the data of the corresponding row in the single second storage unit in the second memory 30 has only been read and updated for 4 rows, and there are still 4~15 rows that have not been read and updated. In this regard, the data of the remaining rows in the corresponding second storage unit that have not been accumulated are added to 0 respectively, and the data is updated and stored in the corresponding row of the second storage unit. That is, the data in the 4th~15th rows in the second memory 30 is still read row by row by the calculator 50, and the other input end of the calculator 50 inputs 0. After the binary number stored in the second bit unit 300 in each of the remaining rows in the corresponding second storage unit is added to 0, the binary number is updated and stored in the second bit unit 300 in the corresponding row. Therefore, in the third example, the data in the 4th~15th rows, the 20th~31st rows, the 36th~47th rows, the 52nd~63rd rows, the 68th~79th rows, the 84th~95th rows, the 100th~111th rows and the 116th~127th rows in the second memory 30 are all added to 0.

[0107] In the process of reading out the stored data in the first memory 20 by the read-write circuit 40, since the first memory 20 includes 16x128 first bit cells 200 and the second memory 30 includes 128x128 second bit cells 300, the data in the 0th~15th rows of the second memory 30 is read out and written into the first memory 20 row by row first, and then read out column by column by the read-write circuit 40; then, the data in the 16th~31st rows of the second memory 30 is read out and written into the first memory 20 row by row, and then read out column by column by the read-write circuit 40; and so on, until the data in the 112th~127th rows of the second memory 30 is read out and written into the first memory 20 row by row, and then read out column by column by the read-write circuit 40, so that the readout of the accumulated histogram data is completed.

[0108] As can be seen from the above, for one laser pulse signal, two 128-column write operations are needed to be performed on the first memory 20, which takes 128x2 clock periods T; and 128 rows of the second memory 30 need to be updated, which takes 128 clock periods T. In the process of reading out the first memory 20 by the read-write circuit 40, eight 16-row read operations on the second memory 30 and eight 128-column read operations on the first memory 20 are needed to be performed, which takes 16x8 clock periods T and 128x8 clock periods T respectively. Therefore, in the third example, for one laser pulse signal, the data accumulation and update takes 128x3 clock periods T in total, and reading out the accumulated histogram data stored in the second memory 30 takes 128x9 clock periods T in total. Obviously, compared with the second example shown in the first embodiment Figure 8 As can be seen from the above, for one laser pulse signal, two 128-column write operations are needed to be performed on the first memory 20, which takes 128x2 clock periods T; and 128 rows of the second memory 30 need to be updated, which takes 128 clock periods T. In the process of reading out the first memory 20 by the read-write circuit 40, eight 16-row read operations on the second memory 30 and eight 128-column read operations on the first memory 20 are needed to be performed, which takes 16x8 clock periods T and 128x8 clock periods T respectively. Therefore, in the third example, for one laser pulse signal, the data accumulation and update takes 128x3 clock periods T in total, and reading out the accumulated histogram data stored in the second memory 30 takes 128x9 clock periods T in total. Obviously, compared with the second example shown in the first embodiment

[0109] Further, since the interval time between two laser pulse signals is much larger than the sum of all the time difference intervals, the TCSPC storage circuit provided in the embodiment can provide more kinds of storage array design schemes to meet different application requirements and realize more flexible configuration of memory rows and columns.

[0110] In the fourth example, the first memory 20 includes 16x256 first bit cells 200, and the second memory 30 includes 64x256 second bit cells 300. Each first memory cell includes 4 first bit cells 200, and each second memory cell includes 16 second bit cells 300. Thus, the first memory 20 can be configured as 4x256 first memory cells, and the second memory 30 can be configured as 4x256 second memory cells, each corresponding to 1024 time difference intervals.

[0111] Based on this, in the fourth example, for a laser pulse signal, the read-write circuit 40 can be used to write the 1024 time difference intervals corresponding to the photon numbers collected in succession into the first memory 20 column by column without performing data storage in two batches. Then, the 1024 second memory cells in the second memory 30 are added row by row and updated. Thus, in the fourth example, the read-write circuit 40 needs to perform 256 column write operations to fill the first memory 20, which takes 256 clock cycles T; 64 rows of the second memory 30 need to be updated, which takes 64 clock cycles T. In the process of data reading, 16 row read-write operations need to be performed four times, which takes 16x4 clock cycles T; and the read-write circuit 40 needs to perform 256 column read operations four times, which takes 256x4 clock cycles T. Thus, in the fourth example, for a laser pulse signal, the total data accumulation and update takes 128x2.5 clock cycles T. Reading the accumulated histogram data stored in the second memory 30 takes 128x8 clock cycles T. Obviously, compared with the first example in the first embodiment Figure 7 The size of the first memory 20 in the fourth example is reduced by three quarters, and the data accumulation and update period for a laser pulse signal is basically the same, but the area of the TCSPC storage circuit on the chip is significantly reduced.

[0112] In the fifth example, the first memory 20 includes 32x128 first bit cells 200, and the second memory 30 includes 128x128 second bit cells 300. Each first memory cell includes 4 first bit cells 200, and each second memory cell includes 16 second bit cells 300. Thus, the first memory 20 can be configured as 8x128 first memory cells, and the second memory 30 can be configured as 8x128 first memory cells, each corresponding to 1024 time difference intervals.

[0113] Based on this, in the fifth example, for a laser pulse signal, without performing data storage in two batches, the read-write circuit 40 can be used to write the 1024 photon numbers corresponding to the time difference intervals collected continuously into the first memory 20 column by column. Then, the 1024 second storage units in the second memory 30 are added row by row and updated. Therefore, in the fifth example, the read-write circuit 40 fills the first memory 20, which needs to perform 128 column write operations and takes 128 clock cycles T; the 128 rows of the second memory 30 are updated, which takes 128 clock cycles T. In the data reading process, four 32-row read-write operations are performed, which takes 32*4 clock cycles T. In addition, the read-write circuit 40 performs four 128-column read operations, which takes 128*4 clock cycles T. Therefore, in the fifth example, for a laser pulse signal, the total data accumulation and update takes 128*2 clock cycles T. In addition, reading the accumulated histogram data stored in the second memory 30 takes 128*5 clock cycles T. Obviously, compared with the first example in embodiment one Figure 7 The size of the first memory 20 in the fifth example is also reduced by three quarters, and the data accumulation and update period for a laser pulse signal is the same. Compared with the fourth example, the size of the first memory 20 in the fifth example is the same, but the data storage period and read operation period for a laser pulse signal are reduced.

[0114] In summary, the TCSPC storage circuit and the data read-write method thereof provided by the embodiment are based on the fact that each collection data requires fewer storage bits. Under the premise of ensuring effective storage, the number of first bit units 200 in each first storage unit in the first memory 20 is reduced, thereby greatly reducing the size of the chip occupied by the first memory 20 while meeting the storage of the same number of time difference interval corresponding data. In addition, the parts not described in detail in the embodiment can refer to the description in other embodiments.

[0115] <Embodiment Three>

[0116] Please refer to Figure 10 and Figure 11To further reduce the size of the first memory 20, meet the device miniaturization trend. This embodiment is based on the TCSPC storage circuit and its data reading and writing method provided in other embodiments, and further provides a TCSPC storage circuit and its data reading and writing method. Wherein, the TCSPC storage circuit comprises a first memory 20, a second memory 30, a read-write circuit 40 and a calculator 50. It should be noted that the basic structure and function of the first memory 20, the second memory 30, the read-write circuit 40 and the calculator 50 are described in other embodiments, and this embodiment will not be repeated here.

[0117] In this embodiment, the second memory 30 further comprises a multiplexing module 303, and the multiplexing module 303 comprises a plurality of selectors 3030. And each selector 3030 is connected with a plurality of bit lines in the second memory 30, for selecting a bit to read out or write in when the calculator 50 performs logical operation or updates the storage data. It can be understood that due to the presence of the multiplexing module 303, the number of second bit cells 300 that can be read and written in each row of the second memory 30 is reduced, and therefore the number of first bit cells 200 in each row of the first memory 20 can be reduced synchronously, thereby further reducing the size of the first memory 20.

[0118] The TCSPC storage circuit and its data reading and writing method provided in this embodiment are described in detail below in conjunction with examples. Among them, the logical operation is taken as an example of addition operation.

[0119] As shown in Figure 10 and Figure 11 In the sixth example, based on the first embodiment, the first memory 20 comprises 64x32 first bit cells 200, and the second memory 30 comprises 128x128 second bit cells 300. Wherein, each first storage unit comprises 16 first bit cells 200, and the first memory 20 can form 4x32 second storage units to correspond to 128 time difference intervals respectively. And each first storage unit is respectively recorded as: bin0', bin1', bin2', bin3', bin4', …, bin126', bin127'. Each second storage unit comprises 16 second bit cells 300, and the second memory 30 can form 8x128 second storage units to correspond to 1024 time difference intervals respectively. And each second storage unit is respectively recorded as: bin0, bin1, bin2, bin3, bin4, …, bin1022, bin1023.

[0120] The multiplexing module 303 in the second memory 30 includes 32 selectors 3030, and each selector 3030 is connected with four bit lines corresponding to the second bit unit 300 to realize the selection of one bit in four bits for participating in the read / write operation. Preferably, 32 selectors 3030 are sequentially connected with the bit lines corresponding to columns 0-127 in the second memory 30, that is, the first selector 3030 is connected with the bit lines in columns 0-3, the second selector 3030 is connected with the bit lines in columns 4-7, and so on, and the 32nd selector 3030 is connected with the bit lines in columns 124-127.

[0121] Further, the data storage and read / write operation of the first memory 20 and the second memory 30 is consistent with the mode in Embodiment One. Specifically, the read / write circuit 40 continues to write the collected data corresponding to 128 time difference intervals in the first memory 20 column by column to fill bins 0'-127'. Since the selector 3030 in the second memory 30 is set to select one bit in four bits, when performing the data readout and update write in the second memory 30, although it is still row by row, each row reads out the data stored in 32 second bit units 300. For example, when reading out the data in the 0th row in the second memory 30, the first selector 3030 reads out the second bit unit 300 corresponding to the 0th column from the 0th-3rd columns in the 0th row, the second selector 3030 reads out the second bit unit 300 corresponding to the 4th column from the 4th-7th columns in the 0th row, and so on, and the 32nd selector 3030 reads out the second bit unit 300 corresponding to the 124th column from the 124th-127th columns in the 0th row. Therefore, when reading out the data in the 0th row, 32 second bit units 300 are selected and read out. And these 32 second bit units 300 selected and read out need to be added with the data in the 32 first bit units 200 in the 0th row in the first memory 20 and then stored in the 32 second bit units 300 selected and read out.

[0122] Based on this, in order to ensure that the first storage unit and the second storage unit corresponding to the same time difference interval can be added during the accumulation operation, the distribution of each second storage unit in the second memory 30 needs to be set in combination with the selection order of each selector 3030 to ensure that the first storage unit and the corresponding second storage unit are added during the data update storage of 128 time difference intervals each time. For example Figure 11As shown, in one batch of data storage, each of the selectors 3030 is selected in sequence from left to right and without repetition. Therefore, the second storage units bin0~bin3 are located in the 0thcolumn for the first selection of the first selector 3030; the second storage units bin4~bin7 are located in the 4thcolumn for the first selection of the second selector 3030; and so on, the second storage units bin123~bin127 are located in the 124thcolumn for the first selection of the 32ndselector 3030. Therefore, in the process of data storage and update of the first batch of 128 time difference intervals, 32 selectors 3030 will select the second storage units bin0~bin127 for one-to-one corresponding accumulation update with the first storage units bin0’~bin127’ in the first memory 20.

[0123] After the data storage and update of the first batch of 128 time difference intervals are completed, the first memory 20 will continue to be filled with the collected data corresponding to the second batch of 128 time difference intervals. Similarly, in order to meet the accumulation update of the first storage units corresponding to the second batch of 128 time difference intervals with the second storage units corresponding to the time difference intervals, in the second memory 30, the second storage units bin128~bin131 are located in the 1stcolumn for the selection of the corresponding second bit unit 300 in the 1stcolumn by the first selector 3030 for the second time. The second storage units bin132~bin135 are located in the 5thcolumn for the selection of the corresponding second bit unit 300 in the 5thcolumn by the second selector 3030 for the second time; and so on, the second storage units bin252~bin255 are located in the 125thcolumn for the selection of the corresponding second bit unit 300 in the 125thcolumn by the 32ndselector 3030 for the second time. Based on this, in the process of data storage and update of the second batch of 128 time difference intervals, 32 selectors 3030 will select the second storage units bin128~bin255 for one-to-one corresponding accumulation update with the first storage units bin0’~bin127’ in the first memory 20. For the data storage and update of other batches of 128 time difference intervals, the above-mentioned method can be referred to, and the present embodiment will not be described here.

[0124] Based on this, for a laser pulse signal, the first memory 20 needs to collect the photon number of 1024 time difference intervals, and then the first memory 20 needs to perform 32x8 column writes, which takes 32x8 cycles T. In addition, each row of data in the second memory 30 is updated 4 times, so a total of 128x4 updates need to be performed, which takes 128x4 cycles T. When reading the accumulated data of 1024 time difference intervals in the second memory 30, 64x8 row writes need to be performed to the first memory 20, which takes 64x8 cycles T. In addition, the read-write circuit 40 reads the first memory 20 column by column, which takes 32x8 cycles T. Therefore, in the sixth example, for a laser pulse signal, the total data accumulation update takes 128x6 clock cycles T. In addition, reading the accumulated histogram data stored in the second memory 30 takes 128x6 clock cycles T.

[0125] Obviously, compared with other examples, the TCSPC storage circuit provided by the embodiment has a longer data accumulation update period for a laser pulse signal, but the area occupied is the smallest. In addition, since the emission interval time of two laser pulse signals is much longer than the data collection and storage time of all the time difference intervals, the TCSPC storage circuit provided by the embodiment is feasible and can further realize flexible configuration of the memory rows and columns.

[0126] Further, when the first memory 20 in the embodiment adopts the manner in the second embodiment to reduce the number of first bit units 200 in each first storage unit, the read-write operation is also performed by the above method.

[0127] In summary, the TCSPC storage circuit and its data read-write method provided by the embodiment add a multiplexing module 303 to the second memory 30, and the multiplexing module 303 includes a plurality of selectors 3030, so that each selector 3030 selects one bit to perform an operation when the second memory 30 performs row reading and row writing. Thus, the number of second bit units 300 that can be read and written by the second memory 30 each time is reduced, thereby the data in the columns of the first memory 20 can be correspondingly reduced, the size of the first memory 20 can be further reduced, which is beneficial to reducing the overall size of the device and meets the requirement of device miniaturization. In addition, the parts not described in detail in the embodiment can be referred to the description in other embodiments.

[0128] <Embodiment Four>

[0129] Please refer to Figure 6 and Figure 12To effectively shorten the data storage period, on the basis of the TCSPC storage circuit and the data read-write method thereof provided in other embodiments, the embodiment further provides a TCSPC storage circuit and a data read-write method thereof. The TCSPC storage circuit comprises a first memory 20, a second memory 30, a read-write circuit 40, and a calculator 50. It should be noted that the basic structure and functions of the first memory 20, the second memory 30, the read-write circuit 40, and the calculator 50 are described in other embodiments, and will not be repeated here.

[0130] It should be noted that in the above embodiment one to embodiment three, if the storage space in the first memory 20 cannot meet the storage of the acquisition data corresponding to all the time difference intervals, the storage and update of the acquisition data need to be performed in batches. For example, for the acquisition after a laser pulse signal, the total number of all the time difference intervals is 1024, and 1024 first storage units are needed for storage. However, if the first memory 20 only includes 512 first storage units, it can only meet the storage of the acquisition data corresponding to 512 time difference intervals. Therefore, according to the description in the above embodiment one to embodiment three, the storage of the acquisition data needs to be performed in two batches. For example, first store the acquisition data corresponding to 512 time difference intervals into the 512 first storage units in the first memory 20, then wait for the 512 first storage units in the first memory 20 and the 512 second storage units corresponding to the second memory 30 to complete the accumulation update, and then store the acquisition data corresponding to the remaining 512 time difference intervals into the 512 first storage units in the first memory 20 again. Finally, perform the accumulation update of the 512 first storage units in the first memory 20 and the 512 second storage units corresponding to the second memory 30 again. Obviously, in this process, due to the limited storage space of the first memory 20, the data storage in the first memory 20 has a waiting process, which increases the period of data storage.

[0131] To this end, the TCSPC storage circuit divides the first memory 20 into at least two first sub-memories 20a, each of which includes a plurality of first bit cells 200 arranged in an array. The second memory 30 is divided into at least two second sub-memories 30a, each of which includes a plurality of second bit cells 300 arranged in an array. The first sub-memory 20a and the second sub-memory 30a correspond to each other, and one first sub-memory 20a and one corresponding second sub-memory 30a form a storage combination structure. Each storage combination structure is used to cooperate with the read-write circuit 40 and the calculator 50 to store or read out the acquisition data corresponding to a plurality of time difference intervals, and each storage combination structure corresponds to a different time difference interval segment. In short, the storage combination structure can independently perform the data storage and data readout functions in Embodiments 1 to 3, with the difference being that the storage space in the storage combination structure corresponds to a smaller number of time difference intervals. Based on this difference, two or more storage combination structures can be alternately matched for storage, without the need to wait for accumulation before storage, thereby shortening the data storage period.

[0132] Specifically, each storage combination structure can store data corresponding to a plurality of time difference interval segments, and the data corresponding to consecutive time difference interval segments are stored in different storage combination structures. Specifically, a plurality of consecutive time difference intervals form a time difference interval segment. Specifically, the time difference interval segment refers to the sum of each time difference interval that can be stored in each batch of storage by each storage combination structure. For example, one storage combination structure is used to store the first 512 time difference intervals, i.e., [0, dt], [dt, 2dt], [2dt, 3dt], …, [511dt, 512dt], and the time difference interval segment corresponds to the interval [0, 512dt]. Another storage combination structure is used to store the 513th to 1024th time difference intervals, i.e., [513dt, 514dt], [514dt, 515dt], [515dt, 516dt], …, [1023dt, 1024dt], and the time difference interval segment corresponds to the interval [512dt, 1024dt]. The time difference interval segments [0, 512dt] and [513dt, 1024dt] are two consecutive time difference interval segments, but are stored in two storage combination structures, respectively.

[0133] Further, in the two continuous time difference interval segments, after the first sub-memory 20a in the storage combination structure corresponding to the previous time difference interval segment completes the writing of the collected data, the first sub-memory 20a in the storage combination structure corresponding to the next time difference interval segment starts to perform the writing of the collected data; at the same time, the first sub-memory 20a and the second sub-memory 30a in the storage combination structure corresponding to the previous time difference interval segment start to perform the logical operation and update of the stored data.

[0134] For example, the first time difference interval segment [0, 512dt] and the second time difference interval segment [513dt, 1024dt] are two continuous time difference interval segments, after the first sub-memory 20a in one of the storage combination structures corresponding to the first time difference interval segment completes the writing of the collected data corresponding to the time difference interval, the calculator 40 starts to perform the logical operation and update on the second sub-memory 30a in the storage combination structure. At the same time, without waiting for the completion of the logical operation and update of the second sub-memory 30a, the first sub-memory 20a in one of the storage combination structures corresponding to the second time difference interval segment [513dt, 1024dt] starts to write the collected data corresponding to the time difference interval synchronously. Therefore, the time difference interval segment [0, 1024dt] can realize continuous writing of the collected data.

[0135] It should be noted that the storage spaces in each of the storage combination structures can be the same or different. Since the read-write circuit 40 and the calculator 50 are shared by each of the storage combination structures, and in order to reduce or avoid the waiting time, the period of writing the collected data in the first sub-memory 20a in one of the storage combination structures is greater than or equal to the period of accumulating and updating the stored data in another of the storage combination structures. Preferably, the storage spaces in each of the storage combination structures are the same; that is, the storage spaces of each of the first sub-memories 20a are the same, the storage spaces of each of the second sub-memories 30a are the same, and in one batch of data storage, the period of writing the collected data in any one of the storage combination structures is equal to the period of accumulating and updating the stored data.

[0136] The TCSPC storage circuit and the data read-write method thereof provided by the embodiment will be described in detail below with examples. The logical operation involved is taken as an example of addition operation.

[0137] As Figure 6 and Figure 12As shown in the seventh example, the first memory 20 in the TCSPC storage circuit includes 16x128 first bit cells 200 and is divided into two first sub-memories 20a. Each first sub-memory 20a includes 16x64 first bit cells 200. The second memory 30 in the TCSPC storage circuit includes 128x128 second bit cells 300 and is divided into two second sub-memories 30a. Each second sub-memory 30a includes 128x64 second bit cells 300. One first sub-memory 20a and one second sub-memory 30a form a first storage combination structure 60, and the other first sub-memory 20a and the other second sub-memory 30a form a second storage combination structure 70. The first storage combination structure 60 and the second storage combination structure 70 share one read-write circuit 40 and one calculator 50.

[0138] When one first storage unit includes 4 first bit cells 200, the first sub-memory 20a includes 4x64 first storage units. When one second storage unit includes 16 second bit cells 300, the second sub-memory 30a includes 8x64 second storage units. Therefore, the first sub-memory 20a can store data corresponding to 256 time difference intervals, and the second sub-memory 30a can store data corresponding to 512 time difference intervals. Based on this, the first storage combination structure 60 is set to correspond to time difference interval segments [0, 256dt], [512dt, 768dt], and the second storage combination structure 70 is set to correspond to time difference interval segments [256dt, 512dt], [768dt, 1024dt].

[0139] When performing the write of the collected data, the read-write circuit 40 performs 64 column writes to the first sub-memory 20a in the first storage combination structure 60 to store the collected data with time difference intervals of [0, dt], [dt, 2dt], [2dt, 3dt], …, [255dt, 256dt] in the first sub-memory 20a. After the 64 column writes are performed, the calculator 50 starts to read the collected data in the first sub-memory 20a in the first storage combination structure 60 row by row, and performs accumulation and update of the stored data in the corresponding time difference intervals in the second sub-memory 30a in the first storage combination structure 60. At the same time, after the 64 column writes are performed, the first sub-memory 20a in the second storage combination structure 70 starts to perform 64 column writes; that is, 256 data writes of the first storage units corresponding to the continuous time difference interval segment [256dt, 512dt] are performed. It can be understood that since the binary number stored in the first storage unit is only the 0th~3rdbit, the 4th~15thbit is omitted, but the binary number stored in the second storage unit is the 0th~15thbit. Therefore, when the calculator 50 performs data update of 256 second storage units in the second sub-memory 30a in the first storage combination structure 60, 4x16=64 clock periods T are still needed to perform data update of 64 rows. At the same time, the first sub-memory 20a in the second storage combination structure 70 also needs 64 clock periods T to perform 64 column writes. Based on this, when the second sub-memory 30a in the first storage combination structure 60 completes the first batch of data update of 256 second storage units corresponding to the time difference interval segment [0, 256dt], the first sub-memory 20a in the second storage combination structure 70 just completes the second batch of collected data write of 256 first storage units corresponding to the time difference interval segment [256, 512dt].

[0140] Similarly, after the first sub-memory 20a in the second storage combination structure 70 completes the writing of the collected data, the first sub-memory 20a in the first storage combination structure 60 starts to perform the writing of the collected data in the time difference interval segment [512dt, 768dt]. Meanwhile, the calculator 50 starts to read, accumulate and update the stored data in the first sub-memory 20a and the second sub-memory 30a in the second storage combination structure 70. Since the period of reading, accumulating and updating the stored data is equal to the period of writing the collected data, both of which are 4x16=64 clock periods T, when the first sub-memory 20a in the first storage combination structure 60 is full of the collected data in 256 first storage units again, the second sub-memory 30a in the second storage combination structure 70 completes the updating of 256 second storage units. Subsequently, the first sub-memory 20a in the second storage combination structure 70 starts to perform the writing of the collected data in the time difference interval segment [768dt, 1024dt], and the calculator 50 starts to read, accumulate and update the stored data in the first sub-memory 20a and the second sub-memory 30a in the first storage combination structure 60. After 4x16=64 clock periods T are performed by the two storage combination structures respectively, the first storage combination structure 60 completes the updating of the second storage units corresponding to the time difference interval segment [512dt, 768dt], and the second storage combination structure 70 completes the writing of the collected data in the first storage units corresponding to the time difference interval segment [768dt, 1024dt].

[0141] Therefore, it can be seen that the first storage combination structure 60 has completed the data acquisition and storage for the time difference interval corresponding to one laser pulse signal, and can continue to wait for the next laser pulse signal to be emitted. For the second storage combination structure 70, it begins to accumulate and update the data corresponding to the time difference interval [768dt, 1024dt] into the corresponding second storage unit. When the data update for the time difference interval [768dt, 1024dt] is completed, the second storage combination structure 70 has completed the data acquisition and storage for the time difference interval corresponding to one laser pulse signal, and can continue to wait for the next laser pulse signal to be emitted. Furthermore, after the next laser pulse signal is emitted, the data update for the time difference interval [0, 1024dt] corresponding to this laser pulse signal continues according to the above process until the data storage for all laser pulse signals is completed. Therefore, in the seventh example, the data storage time for each instance is reduced by 64 clock cycles T; and for the data acquisition and storage of a single laser pulse signal, 3 × 64 = 128 clock cycles T can be reduced, effectively shortening the data storage cycle.

[0142] Furthermore, after the data storage of all sub-laser pulse signals is completed, the read / write circuit 40 can be used to read the stored data of the corresponding time difference interval within each of the storage combination structures. Continuing with... Figure 12For example, the first storage combination structure 60 stores the accumulated storage data corresponding to the time difference interval segments [0, 256dt] and [512dt, 768dt], and the second storage combination structure 70 stores the accumulated storage data corresponding to the time difference interval segments [256dt, 512dt] and [768dt, 1024dt]. Based on this, in the readout process, since each of the second storage units includes 16 second bit cells 300 and the first sub-memory 20a includes 16x64 first bit cells 200, in one example, the data corresponding to the time difference interval segment [0, 64dt] in the second sub-memory 30a in the first storage combination structure 60 is first read out and written into the first sub-memory 20a in the first storage combination structure 60, and this takes 16 clock periods T. At the same time, the data corresponding to the time difference interval segment [256dt, 320dt] in the second sub-memory 30a in the second storage combination structure 70 is written into the first sub-memory 20a in the second storage combination structure 70, and this also takes 16 clock periods T. After 16 clock periods T, the read-write circuit 40 can sequentially read the data of the first sub-memory 20a in the first storage combination structure 60 and the data of the first sub-memory 20a in the second storage combination structure 70 by column, i.e., the data readout of the time difference interval segments [0, 64dt] and [256dt, 320dt] is completed in 128 clock periods T. Subsequently, the data corresponding to the time difference interval segment [64dt, 128dt] in the second sub-memory 30a in the first storage combination structure 60 is read out and written into the first sub-memory 20a in the first storage combination structure 60, and the data corresponding to the time difference interval segment [320dt, 384dt] in the second sub-memory 30a in the second storage combination structure 70 is written into the first sub-memory 20a in the second storage combination structure 70. After 16 clock periods T, the read-write circuit 40 can sequentially read the data of the first sub-memory 20a in the first storage combination structure 60 and the data of the first sub-memory 20a in the second storage combination structure 70 by column, i.e., the data readout of the time difference interval segments [64, 128dt] and [320dt, 384dt] is completed in 128 clock periods T. In this way, the readout of all the storage data is completed. It should be noted that although the read-write circuit 40 does not read out the corresponding storage data in the order of the time difference interval segments, this does not affect the use of the data, and the data can be rearranged in the order of the time difference interval segments after being read out.

[0143] Since the read operation of the stored data is performed after all the secondary laser pulse signals are illuminated, the time for reading out the data does not need to be strictly limited. Therefore, during the read operation, the above-mentioned alternate read mode can be selected, or the data in each of the second sub-memory 30a can be read out one by one. In another example, the accumulated stored data corresponding to the time difference interval segment [0, 256dt] stored in the second sub-memory 30a in the first storage combination structure 60 is first read out, then the accumulated stored data corresponding to the time difference interval segment [256dt, 512dt] stored in the second storage combination structure 70 is read out, then the accumulated stored data corresponding to the time difference interval segment [512dt, 768dt] stored in the second sub-memory 30a in the first storage combination structure 60 is read out, and finally, the accumulated stored data corresponding to the time difference interval segment [768dt, 1024dt] stored in the second storage combination structure 70 is read out. That is, the accumulated stored data corresponding to the time difference interval segment [0, 256dt] is read out four times and written into the first sub-memory 20a in the first storage combination structure 60, and is read out column by column through the read-write circuit 40. Then, the accumulated stored data corresponding to the time difference interval segment [256dt, 512dt] is read out four times and written into the first sub-memory 20a in the second storage combination structure 70, and is read out column by column through the read-write circuit 40. The accumulated stored data corresponding to the time difference interval segments [512dt, 768dt] and [768dt, 1024dt] is read out in the same way as the above-mentioned read-out process, and will not be described again.

[0144] In summary, the TCSPC storage circuit and the data read-write method thereof provided in the embodiment split the first memory 20 and the second memory 30 to form at least two first sub-memories 20a and at least two second sub-memories 30a, and combine each of the first sub-memories 20a and each of the second sub-memories 30a into a storage combination structure, so as to realize the storage and updating of the data corresponding to the time difference interval segments. By setting the alternate operation between each of the storage combination structures, the continuous writing of the collected data corresponding to all the time difference intervals can be realized, the accumulation waiting time is cancelled, and the data collection and storage period time for each laser pulse signal is greatly reduced. In the embodiment, the parts not described in detail can be referred to the description in other embodiments. It should be noted that the embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts in each embodiment can be referred to each other. In addition, the different parts in each embodiment can also be combined and used, which is not limited by the present application.

[0145] Furthermore, it should be appreciated that the above-described embodiments are merely exemplary as to the present application and need not be practiced as described. It should also be understood that where the above-described embodiments are, for clarity, described in terms of steps or means, these steps or means need not be performed in the order given or even one at a time. Rather, certain steps or means can be performed in an order different than other steps or means or one following another, or performed at least at partially in parallel, to express the sequential order of individual steps or features or functions. Also, description of the above-described embodiments is meant to be illustrative only and not limiting as to the scope of the present application, which is set forth in the following claims.

Claims

1. A TCSPC storage circuit, characterized by, The application relates to a memory device, comprising: a first memory, a second memory, a read-write circuit and a calculator; wherein, the first memory comprises a plurality of first bit cells arranged in an array; each column of the first bit cells constitutes at least one first memory cell; each first memory cell corresponds to a time interval and is used for storing single acquisition data in the corresponding time interval; the second memory comprises a plurality of second bit cells arranged in an array; each column of the second bit cells constitutes at least one second memory cell; each second memory cell corresponds to a time interval and is used for storing data obtained by performing a logical operation on multiple acquisition data in the corresponding time interval; the read-write circuit is connected with the first memory and is used for receiving single acquisition data in different time intervals and writing the single acquisition data in different time intervals into corresponding first memory cells in sequence; and reading out the stored data in each first memory cell in sequence; the calculator is used for reading the stored data in the first memory and the second memory in sequence and performing a logical operation on the stored data in the first memory cells and the second memory cells corresponding to the same time interval; and updating and storing the data obtained by performing the logical operation into the second memory cells corresponding to the time interval.

2. The TCSPC memory circuit of claim 1, wherein, the number of the first memory cells in the first memory is equal to the number of the second memory cells in the second memory; each first memory cell corresponds to each time interval; and each second memory cell corresponds to each time interval.

3. The TCSPC memory circuit of claim 1, wherein, the number of the second memory cells in the second memory is an integer multiple of the number of the first memory cells in the first memory; and the read-write circuit is further used for performing read-write operations on the first memory in batches; in each batch of read-write operations, each first memory cell corresponds to each time interval belonging to the same batch; and each second memory cell corresponds to each time interval of all batches.

4. The TCSPC memory circuit according to any one of claims 1 to 3, characterized in that, each first bit cell is used for storing one binary number; each second bit cell is used for storing one binary number; and the acquisition data in each time interval comprises K binary numbers; wherein, the first memory cell comprises K first bit cells and the second memory cell comprises K second bit cells; and K is a positive integer; or the first memory cell comprises i first bit cells and the second memory cell comprises K second bit cells; and 1 the read-write circuit is further used for writing the first i binary numbers in the acquisition data into corresponding first memory cells in sequence in the writing operation; and the read-write circuit is further used for reading out the stored data in each first memory cell in sequence in the reading operation. The calculator is further configured to, after updating the i-th row in each of the first storage units and the i-th row in the corresponding second storage unit, perform the logical operation between the stored data in the (i+1) to (K) rows in the corresponding second storage unit and 0 respectively, and update the data stored in the (i+1) to (K) rows in the corresponding second storage unit.

5. The TCSPC memory circuit of claim 1, wherein, In the first memory, each of the first bit units arranged in rows is connected sequentially, and each row is selected and controlled by a horizontal word line; each of the first bit units arranged in columns is connected sequentially, and each column is selected and controlled by a vertical word line; and the first memory further includes a first row decoder and a first column decoder, which are connected to each of the horizontal word lines and each of the vertical word lines respectively, for selecting and editing each of the first bit units row by row or column by column. In the second memory, the row-arranged second bit units are connected sequentially, and each row is selected and controlled by a word line; the column-arranged second bit units are connected sequentially, and each column is selected and edited by a bit line; and the second memory also includes a second row decoder and a second column decoder, which are connected to each of the word lines and each of the bit lines respectively, for selecting and editing each of the second bit units row by row.

6. The TCSPC memory circuit of claim 5, wherein, The second memory further includes a multiplexing module for selecting and editing portions of the second bit cells; wherein, The multiplexing module includes multiple selectors; and each selector is connected to multiple bit lines in the second memory, for selecting one bit of the second bit cell to read or write each time a read or write operation is performed; and... Each selector is connected to the same number of bit lines, and the number of selectors in the multiplexing module is the same as the number of columns of the first bit cells in the first memory.

7. The TCSPC memory circuit of claim 3, wherein, The first memory is divided into at least two first sub-memories; and each first sub-memory includes a portion of the first bit units arranged in an array; the second memory is divided into at least two second sub-memories; and each second sub-memory includes a portion of the second bit units arranged in an array; The first sub-memory and the second sub-memory are in one-to-one correspondence, and one first sub-memory and one corresponding second sub-memory constitute a storage combination structure; each storage combination structure is used in conjunction with the read / write circuit and the calculator to store or read the acquired data corresponding to multiple time difference intervals; wherein, a consecutive portion of the time difference intervals constitutes a time difference interval segment, and the acquired data corresponding to two consecutive time difference interval segments are stored in different storage combination structures; and, Each of the aforementioned storage combination structures is further configured to, in two consecutive time difference intervals, after the first sub-memory in the storage combination structure corresponding to the preceding time difference interval completes the writing of the corresponding acquired data, the first sub-memory in the storage combination structure corresponding to the following time difference interval begins to execute the writing of the corresponding acquired data; simultaneously, the first sub-memory and the second sub-memory in the storage combination structure corresponding to the preceding time difference interval begin to execute the logical operations and updates of the stored data.

8. The TCSPC memory circuit of claim 7, wherein, The writing cycle time of the acquired data in the first sub-memory within one of the storage combination structures is greater than or equal to the logical operation and update cycle time of the stored data in another storage combination structure.

9. The TCSPC memory circuit of claim 1, wherein, The first bit unit includes 8T SRAM, the second bit unit includes 6T SRAM, DRAM or MRAM; and the logical operation includes a combination of one or more of the following: addition, AND, OR, NOT, XOR, and assignment.

10. A data read / write method of a TCSPC memory circuit, characterized by, The TCSPC memory circuit as described in any one of claims 1 to 9 is adopted, wherein, The process of performing data writing using the TCSPC storage circuit includes: A read / write circuit is used to receive single-time acquisition data within different time difference intervals, and the single-time acquisition data within different time difference intervals are written into different first storage units in the first memory according to columns. The calculator reads the stored data in the first and second memories line by line, and performs logical operations on the stored data in the first memory cell and the second memory cell in the second memory cell corresponding to the same time difference interval; and updates the data after the logical operation and stores it in the second memory cell corresponding to the time difference interval. The process of reading data using the TCSPC storage circuit includes: Read the stored data in the second memory row by row, and write it into the first memory row by row; The read / write circuit is used to read the stored data in each of the first storage cells in the first memory in columns.

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