Fabrication methods and applications of the top metal layer of power semiconductor chips

Abstract

This invention discloses a method for preparing and applying a top metal layer on a power semiconductor chip, relating to the field of power semiconductor interconnect technology. The method includes: coating a metal sintering material onto the top of a power semiconductor chip or wafer, followed by sintering; when the sintering is pressure sintering, baking the metal-coated power semiconductor chip or wafer at a first temperature; after baking, covering the surface of the baked metal sintering material with an insulating material, and then performing pressure sintering at a second temperature; when the sintering is pressureless sintering, performing pressureless sintering of the metal-coated power semiconductor chip or wafer at a third temperature; the first temperature is lower than the second and third temperatures; the thickness of the metal sintering material coating is 1~1000μm; the wafer is an uncut power semiconductor chip precursor. The technical solution provided by this invention is simple and low-cost.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor interconnect technology, and in particular to a method for preparing and applying a top metal layer of a power semiconductor chip. Background Technology

[0002] Power semiconductor chips are semiconductor devices specifically designed for handling and controlling high voltage and high current. By applying external control signals (such as voltage and current), the electric field distribution of the semiconductor material inside the chip is altered, thereby controlling its on / off state and achieving precise regulation of the power flow in the main circuit. Common power semiconductor chips include wide-bandgap semiconductor chips, silicon-based IGBT chips, and silicon-based MOSFET chips. In copper wire bonding and next-generation embedded packaging technologies for power semiconductor chips, it is necessary to thicken the metal layer on the surface electrodes (mostly the gate and source electrodes). Existing metal layer thickening processes suffer from high costs and complexity; therefore, a simple and low-cost method for fabricating a thickened metal layer on the top of power semiconductor chips is urgently needed. Summary of the Invention

[0003] The main objective of this invention is to propose a method for preparing and applying a top metal layer of a power semiconductor chip, aiming to solve the problems of high cost and difficulty in the existing process of thickening the top metal layer of a power semiconductor chip.

[0004] To achieve the above objectives, the present invention provides a method for preparing a top metal layer of a power semiconductor chip, comprising:

[0005] The metal sintering material is coated on the top of the power semiconductor chip or wafer, and then sintering is performed.

[0006] When the sintering process is a pressure sintering process, the power semiconductor chip or wafer coated with metal sintering material is baked at a first temperature. After the baking process is completed, an isolation material is placed on the surface of the baked metal sintering material, and then pressure sintering is performed at a second temperature.

[0007] When the sintering process is a pressureless sintering process, the power semiconductor chip or wafer coated with metal sintering material is subjected to pressureless sintering at a third temperature.

[0008] Wherein, the first temperature is lower than the second temperature and the third temperature;

[0009] The thickness of the metal sintering material coating is 1~1000 μm;

[0010] The wafer is an uncut power semiconductor chip precursor.

[0011] Preferably, the metal sintering material comprises a sintered metal paste;

[0012] The sintered metal paste includes at least one of sintered copper paste, sintered silver paste, sintered gold paste, and alloy sintering paste.

[0013] Preferably, the coating method includes at least one of stencil printing, screen printing, 3D printing, inkjet printing, and dispensing.

[0014] Preferably, the first temperature is 50~200℃, the baking time is 1~20 min, and the baking atmosphere includes at least one of air, nitrogen, argon, and hydrogen, or the baking atmosphere is a vacuum.

[0015] Preferably, the second temperature is 100~400℃, the pressure sintering time is 1~20min, and the atmosphere of the pressure sintering includes at least one of air, nitrogen, argon, and hydrogen, or the atmosphere of the pressure sintering is a vacuum.

[0016] Preferably, the insulating material includes at least one of glass sheet, ceramic sheet, Teflon film, and graphite paper.

[0017] Preferably, the third temperature is 100~400℃, the pressureless sintering time is 10~240 min, and the atmosphere of the pressureless sintering includes at least one of air, nitrogen, argon, and hydrogen, or the atmosphere of the pressureless sintering is a vacuum.

[0018] Preferably, the sintering process further includes the step of cooling the sintered power semiconductor chip or wafer.

[0019] The atmosphere for the cooling process includes at least one of air, nitrogen, argon, and hydrogen, or the atmosphere for the cooling process is a vacuum.

[0020] Preferably, the cooling process includes natural cooling and accelerated cooling;

[0021] The accelerated cooling refers to cooling the sintered power semiconductor chip or wafer to 20-50°C within 5-120 minutes.

[0022] This invention also proposes the application of the method for preparing the top metal layer of a power semiconductor chip proposed in this invention in the preparation of power semiconductor chips.

[0023] The technical solution of this invention involves directly coating a metal sintering material onto the top of a power semiconductor chip or wafer, followed by customized sintering treatment according to different sintering methods. Specifically, when pressure sintering is required, the power semiconductor chip or wafer coated with the metal sintering material is baked at a first temperature. After baking, an insulating material is placed on the surface of the metal sintering material, and then sintering is performed at a second temperature. When pressureless sintering is required, the power semiconductor chip or wafer coated with the metal sintering material is sintered at a third temperature, thereby achieving the direct fabrication of a thickened metal layer on the power semiconductor chip or wafer. Compared with existing copper sheet sintering processes represented by Heraeus top-mount systems, this method eliminates the need for prefabrication and mounting of sintering materials and copper sheets. Compared with existing thick copper electroplating technologies, it avoids problems such as severe warping of the copper metal layer that may result from large-area electroplating. It offers advantages such as simple process, low cost, and compatibility with different sintering processes. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0025] Figure 1 A schematic flowchart illustrating the method for fabricating the top metal layer of a power semiconductor chip provided by the present invention;

[0026] Figure 2 This is a schematic diagram of the power semiconductor chip provided by the present invention.

[0027] Explanation of icon numbers:

[0028] 100. Power semiconductor chip; 1. Drain; 2. Substrate; 3. Drift region; 4. P-type well region; 5. Source; 6. Gate; 7. N-type + 8. Field insulation layer; 9. Metal layer.

[0029] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0030] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0031] It should be noted that if the embodiments of the present invention involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a specific posture. If the specific posture changes, the directional indicators will also change accordingly.

[0032] Furthermore, if the embodiments of this invention involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the use of "and / or" or "and / or" throughout the text implies three parallel solutions. For example, "A and / or B" includes solution A, solution B, or a solution where both A and B are satisfied simultaneously. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0033] In copper wire bonding of power semiconductor chips and next-generation embedded packaging technology for power chips, it is necessary to thicken the metal layer of the surface electrodes (mostly gate and source electrodes) of the chip. Currently, the commonly used copper wire bonding technology for power semiconductor chips is the copper sheet sintering process represented by Heraeus Die Top System (DTS). However, in practical applications, DTS technology requires pre-forming the sintering material and copper sheet, which is complex. After pre-forming, a high-precision alignment DTS mounting process is required, and after mounting, a certain adhesion between the DTS and the chip is required to ensure no misalignment during thermoforming. Overall, the material and process costs are high, and the process is difficult. On the other hand, in next-generation embedded packaging technology for power chips, thick copper electroplating technology is typically used. The challenges of this technology include high stress, a high risk of chip fragmentation, and the possibility of severe warping of the copper metal layer due to large-area electroplating. Furthermore, the electroplating process is time-consuming, and if wet processes are involved, there are environmentally unfriendly post-processing issues.

[0034] Based on this, the present invention proposes a method for preparing the top metal layer of a power semiconductor chip.

[0035] Please see Figure 1 In one embodiment of the present invention, the method for preparing the top metal layer of the power semiconductor chip includes the following steps:

[0036] S1. Coat the top of the power semiconductor chip or wafer with a metal sintering material, and then perform a sintering process.

[0037] S2. When the sintering process is a pressure sintering process, the power semiconductor chip or wafer coated with metal sintering material is baked at a first temperature. After the baking process is completed, an isolation material is placed on the surface of the baked metal sintering material, and then the sintering process is carried out at a second temperature.

[0038] When the sintering process is a pressureless sintering process, the power semiconductor chip or wafer coated with metal sintering material is sintered at a third temperature.

[0039] The first temperature is lower than the second and third temperatures. When using pressure sintering, baking the metal sintering material at a first temperature lower than the second temperature used in the sintering process allows for pre-shaping of the metal sintering material, facilitating the application of an insulating material to its surface. This insulating material effectively reduces or prevents diffusion bonding between the metal sintering material and the sintering pressure head. The coating thickness of the metal sintering material ranges from 1 to 1000 μm, for example, coating thicknesses of 1 μm, 5 μm, 10 μm, 50 μm, 100 μm, 200 μm, 500 μm, or 1000 μm, to meet the requirements of subsequent copper wire bonding and first-generation power chip embedded packaging. The wafer is an uncut precursor to a power semiconductor chip. Understandably, the method for preparing the top metal layer of a power semiconductor chip provided by this invention can either prepare an integral metal layer on the surface of the wafer directly during the wafer stage of chip fabrication, and then cut the wafer into independent power semiconductor chips, or prepare a metal layer on a single power semiconductor chip, thus meeting the fabrication needs of different stages on the power semiconductor chip fabrication production line.

[0040] The technical solution of this invention involves directly coating the top of a power semiconductor chip or wafer with a metal sintering material, and then directly preparing a thickened metal layer through sintering. Compared with the existing DTS, it eliminates the need for pre-fabrication of the metal sintering material and copper sheet, as well as the need for chip mounting, making the process simple. In addition, it avoids the problems that existing large-area electroplating may cause severe warping of the copper metal layer.

[0041] like Figure 2As shown, in some embodiments, a power semiconductor chip with a metal layer generally includes, from bottom to top, a drain 1, a substrate 2, a drift region 3, a P-type well region 4, a source 5, a gate 6, and an N-type well region 7. + Region 7, field insulating layer 8, and metal layer 9. Metal layer 9 is located above and abuts against gate 6. It should be noted that the method for fabricating the top metal layer of the power semiconductor chip provided by this invention is not limited to... Figure 2 The fabrication of the metal layer shown in the diagram can also be used for wide-bandgap semiconductor chips, silicon-based IGBT chips, etc.

[0042] In some embodiments, the metal sintering material includes a sintered metal paste. The metal paste facilitates coating and shaping on top of a power semiconductor chip or wafer. Further, in some embodiments, the metal paste includes at least one of sintered copper paste, sintered silver paste, sintered gold paste, and alloy sintering paste. The alloy sintering paste can be a gold-silver alloy, a gold-copper alloy, etc., and is not limited thereto.

[0043] In some embodiments, the coating method includes at least one of stencil printing, screen printing, 3D printing, inkjet printing, and dispensing. Specific coating steps are known to those skilled in the art and will not be described in detail here.

[0044] In some embodiments, during the baking process, the first temperature is 50~200°C, for example, the first temperature can be 50°C, 60°C, 80°C, 100°C, 110°C, 130°C, 150°C, 170°C, 190°C, or 200°C. The baking time is 1~20 minutes, for example, the baking time can be 1 minute, 5 minutes, 10 minutes, 15 minutes, or 20 minutes. The baking atmosphere includes at least one of air, nitrogen, argon, and hydrogen, or the baking atmosphere is a vacuum. For example, the baking atmosphere is a mixture of formic acid and nitrogen, a mixture of nitrogen and hydrogen, a nitrogen atmosphere, an argon atmosphere, or a vacuum.

[0045] In some embodiments, during the pressure sintering step, after baking, a separating material is placed on the surface of the metal sintering material. This separating material includes at least one of glass sheets, ceramic sheets, Teflon films, and graphite paper. The aforementioned separating material does not readily generate a diffusion effect with the metal. Therefore, by placing this separating material on the surface of the dried metal sintering material, diffusion bonding between the metal sintering material and the sintering pressure head can be effectively prevented during subsequent pressure sintering processes.

[0046] In some embodiments, the second temperature of the pressure sintering process is 100~400℃, for example, the second temperature can be 100℃, 150℃, 200℃, 250℃, 300℃, 350℃, or 400℃. The pressure sintering time is 1~20 min, for example, the pressure sintering time can be 1 min, 5 min, 10 min, 15 min, or 20 min. The pressure sintering pressure is 1~50 MPa, for example, the pressure sintering pressure is 1 MPa, 5 MPa, 10 MPa, 15 MPa, 20 MPa, 25 MPa, 30 MPa, 35 MPa, 40 MPa, 45 MPa, or 50 MPa. The atmosphere for the pressure sintering process includes at least one of air, nitrogen, argon, and hydrogen, or the atmosphere for the pressure sintering process is a vacuum. For example, the atmosphere for pressure sintering is a mixture of formic acid and nitrogen, a mixture of nitrogen and hydrogen, a nitrogen atmosphere, an argon atmosphere, or a vacuum.

[0047] In some embodiments, the third temperature for pressureless sintering is 100~400°C, for example, the third temperature can be 100°C, 150°C, 200°C, 250°C, 300°C, 350°C, or 400°C. The pressureless sintering time is 10~240 min, for example, the pressureless sintering time can be 10 min, 20 min, 50 min, 100 min, 150 min, 200 min, or 240 min. The atmosphere for pressureless sintering includes at least one of air, nitrogen, argon, and hydrogen, or the atmosphere for pressureless sintering is a vacuum. For example, the atmosphere for pressureless sintering is a mixture of formic acid and nitrogen, a mixture of nitrogen and hydrogen, a nitrogen atmosphere, an argon atmosphere, or a vacuum.

[0048] In some embodiments, the sintering process further includes a step of cooling the sintered power semiconductor chip or wafer. This cooling process includes natural cooling and accelerated cooling. Natural cooling involves placing the sintered power semiconductor chip or wafer at room temperature. Accelerated cooling can involve cooling the power semiconductor chip or wafer to 20-50°C within 5-120 minutes. For example, the accelerated cooling time can be 5 minutes, 10 minutes, 50 minutes, 100 minutes, or 120 minutes, etc.; the final cooling temperature can be 20°C, 25°C, 30°C, 35°C, 40°C, 45°C, or 50°C, etc. The cooling atmosphere includes at least one of air, nitrogen, argon, and hydrogen, or a vacuum. For example, the cooling atmosphere can be a mixture of formic acid and nitrogen, a mixture of nitrogen and hydrogen, a nitrogen atmosphere, an argon atmosphere, or a vacuum, etc.

[0049] The present invention also proposes the application of the method for preparing the top metal layer of a power semiconductor chip as described above in the preparation of power semiconductor chips.

[0050] The present invention will be further illustrated by specific embodiments below.

[0051] Example 1

[0052] (1) Prepare copper metal sintering paste, and apply the copper metal sintering paste to the chip (e.g., using stencil printing). Figure 2 (As shown) at the top electrode metal layer. The coating thickness is 500 μm.

[0053] (2) The chip coated with metal sintering paste in (1) was baked at 120°C for 60 min in a mixed atmosphere of formic acid and nitrogen. After baking, a Teflon film was placed on the top of the chip, and then pressure sintering was carried out in a mixed atmosphere of formic acid and nitrogen at 30 MPa and 200°C for 60 min.

[0054] (3) Place the chip after pressure sintering in (2) in a mixed atmosphere of formic acid and nitrogen, and cool it to 30°C within 60 min to complete the preparation of the top metal layer of the power semiconductor chip.

[0055] Example 2

[0056] (1) Prepare copper metal sintering paste, and apply the copper metal sintering paste to the chip (e.g., using screen printing). Figure 2 (As shown) at the top electrode metal layer. The coating thickness is 1000 μm.

[0057] (2) The chip coated with metal sintering paste in (1) was baked in a vacuum atmosphere at 200°C for 1 min. After baking, a ceramic sheet was placed on top of the chip, and then pressure sintering was carried out under vacuum, 50 MPa and 100°C for 120 min.

[0058] (3) Place the chip after pressure sintering in (2) in a vacuum atmosphere and cool it to 50°C within 5 min to complete the preparation of the top metal layer of the power semiconductor chip.

[0059] Example 3

[0060] (1) Prepare copper metal sintering paste, and apply the copper metal sintering paste to the chip (e.g., using inkjet printing) using inkjet printing. Figure 2 (As shown) at the top electrode metal layer. The coating thickness is 1 μm.

[0061] (2) The chip coated with metal sintering paste in (1) was baked in a vacuum atmosphere at 50°C for 120 min. After baking, a layer of graphite paper was placed on top of the chip, and then pressure sintering was carried out in a vacuum atmosphere at 1 MPa and 400°C for 1 min.

[0062] (3) Place the chip after pressure sintering in (2) in a vacuum atmosphere and cool it to 20°C within 120 min to complete the preparation of the top metal layer of the power semiconductor chip.

[0063] Example 4

[0064] (1) Prepare copper metal sintering paste, and apply the copper metal sintering paste to the wafer using a stencil printing method (preparation as follows). Figure 2 The electrode metal layer on top of the wafer of the power semiconductor chip shown. The coating thickness is 500 μm.

[0065] (2) The wafer coated with metal sintering paste in (1) was baked at 120°C for 60 min in a mixed atmosphere of nitrogen and hydrogen. After baking, a Teflon film was placed on top of the wafer, and then pressure sintering was carried out in a mixed atmosphere of nitrogen and hydrogen at 30 MPa and 200°C for 60 min.

[0066] (3) Place the wafer after pressure sintering in (2) in a mixed atmosphere of nitrogen and hydrogen, and cool it to 30°C within 60 min to complete the preparation of the top metal layer of the power semiconductor chip.

[0067] Example 5

[0068] (1) Prepare copper metal sintering paste, and apply the copper metal sintering paste to the wafer using a stencil printing method (preparation as follows). Figure 2 The electrode metal layer on top of the wafer of the power semiconductor chip shown. The coating thickness is 500 μm.

[0069] (2) The wafer coated with metal sintering paste in (1) was subjected to pressure sintering under nitrogen atmosphere, 30 MPa and 200℃ for 60 min.

[0070] (3) Place the wafer after pressure sintering in (2) in a nitrogen atmosphere and cool it to 30°C within 60 min to complete the preparation of the top metal layer of the power semiconductor chip.

[0071] Example 6

[0072] (1) Prepare copper metal sintering paste, and apply the copper metal sintering paste to the chip (e.g., using stencil printing). Figure 2 (As shown) at the top electrode metal layer. The coating thickness is 500 μm.

[0073] (2) The chip coated with metal sintering paste in (1) was subjected to pressure sintering under argon atmosphere, 30 MPa, and 200℃ for 60 min.

[0074] (3) Place the chip after pressure sintering in (2) in an argon atmosphere and cool it to 30°C within 60 min to complete the preparation of the top metal layer of the power semiconductor chip.

[0075] In summary, the method for preparing the top metal layer of a power semiconductor chip provided by this invention directly applies the metal thickening sintering process to the top electrode of a power semiconductor chip or wafer through sintering. This method has not been used in the industry before. By preparing a thickened metal layer on a power semiconductor chip in a simple and low-cost manner, it can meet the needs of copper wire bonding of power semiconductor chips and next-generation embedded packaging, and has broad application prospects.

[0076] The above description is merely an exemplary embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural transformations made using the contents of the present invention specification and drawings under the technical concept of the present invention, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present invention.

Claims

1. A method of fabricating a top metal layer of a power semiconductor chip, characterized in that, The application relates to a preparation method of a metal sintering material coated on the top of a power semiconductor chip or wafer. The metal sintering material is coated on the top of the power semiconductor chip or wafer, and then a sintering treatment is carried out; When the sintering treatment is a pressure sintering treatment, the power semiconductor chip or wafer coated with the metal sintering material is baked at a first temperature, and after the baking treatment is completed, a separation material is padded on the surface of the baked metal sintering material, and then a pressure sintering treatment is carried out at a second temperature; When the sintering treatment is a pressureless sintering treatment, the power semiconductor chip or wafer coated with the metal sintering material is subjected to a pressureless sintering treatment at a third temperature; The first temperature is less than the second temperature and the third temperature, the first temperature is 50-200 DEG C, the second temperature is 100-400 DEG C, and the third temperature is 100-400 DEG C; The thickness of the metal sintering material coating is 1-1000 microns; The wafer is an uncut power semiconductor chip precursor.

2. The method of claim 1, wherein the method further comprises: The metal sintering material comprises a sintering metal paste; The sintering metal paste comprises at least one of sintering copper paste, sintering silver paste, sintering gold paste and alloy sintering paste.

3. The method of claim 1, wherein the method further comprises: The coating method comprises at least one of steel screen printing, silk screen printing, 3D printing, inkjet printing and dispensing.

4. The method of claim 1, wherein the method further comprises: The baking treatment time is 1-20 min, the baking treatment atmosphere comprises at least one of air, nitrogen, argon, formic acid and hydrogen, or the baking treatment atmosphere is vacuum.

5. The method of claim 1, wherein the power semiconductor chip top metal layer is prepared by a process comprising: forming a first metal layer on the power semiconductor chip; forming a second metal layer on the first metal layer; and forming a third metal layer on the second metal layer. The pressure sintering treatment time is 1-20 min, the pressure sintering treatment atmosphere comprises at least one of air, nitrogen, argon, formic acid and hydrogen, or the pressure sintering treatment atmosphere is vacuum.

6. The method of claim 1, wherein the power semiconductor chip top metal layer is prepared by a process comprising: The separation material comprises at least one of glass sheet, ceramic sheet, Teflon film and graphite paper.

7. The method of claim 1, wherein the power semiconductor chip top metal layer is prepared by a process comprising: forming a first metal layer on the power semiconductor chip; forming a second metal layer on the first metal layer; and forming a third metal layer on the second metal layer. The pressureless sintering treatment time is 10-240 min, the pressureless sintering treatment atmosphere comprises at least one of air, nitrogen, argon and hydrogen, or the pressureless sintering treatment atmosphere is vacuum.

8. The method of claim 1, wherein the power semiconductor chip top metal layer is prepared by a process comprising: forming a first metal layer on the power semiconductor chip; forming a second metal layer on the first metal layer; and forming a third metal layer on the second metal layer. The sintering treatment further comprises the step of cooling the sintered power semiconductor chip or wafer; The cooling treatment atmosphere comprises at least one of air, nitrogen, argon and hydrogen, or the cooling treatment atmosphere is vacuum.

9. The method of claim 8, wherein the method further comprises: The cooling treatment comprises natural cooling and accelerated cooling; The accelerated cooling is to cool the sintered power semiconductor chip or wafer to 20-50 DEG C within 5-120 min.

10. The application relates to the application of the preparation method of the metal layer on the top of the power semiconductor chip in the preparation of the power semiconductor chip.

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