Transverse etching depth measuring method, process evaluation method and device

Abstract

The invention discloses a transverse etching depth measuring method, a process evaluation method and a device thereof, and relates to the technical field of semiconductors. The measurement method comprises the steps that a geometric model of an alignment mark is established, the alignment mark comprises a longitudinal etching mark and a transverse etching mark, the longitudinal etching mark extends in the direction perpendicular to the substrate, and the transverse etching mark extends from the longitudinal etching mark in the direction away from the longitudinal etching mark and parallel to the substrate; acquiring an actual alignment signal of a to-be-detected alignment mark in the to-be-detected wafer; and determining the transverse etching depth of the wafer to be measured according to the actual alignment signal and the geometric model. The efficiency of measuring the transverse etching depth of the wafer to be measured is improved, and the cost of measuring the transverse etching depth is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, in particular to a lateral etching depth measurement method and a measurement device thereof, and a process evaluation method of a lateral etching process and a measurement device thereof. BACKGROUND

[0002] With the development of semiconductor technology, semiconductor devices are transformed from 2D structure to 3D structure, and the lateral etching process is a key process for high-aspect-ratio stacked semiconductor devices in 3D structure. The depth of lateral etching is one of the important indicators in the preparation process of semiconductor devices, and the measurement of lateral etching depth and the evaluation of lateral etching process are indispensable processes. Typically, the method for measuring the lateral etching depth is to slice the wafer after lateral etching, so as to measure the lateral etching depth of the lateral etching process. This method is time-consuming and labor-intensive, and the measurement cost is high. SUMMARY

[0003] The present disclosure provides a lateral etching depth measurement method and a measurement device thereof, and a process evaluation method of a lateral etching process and a measurement device thereof, which can improve the efficiency of measuring the lateral etching depth and reduce the cost of measuring the lateral etching depth.

[0004] The present disclosure provides a lateral etching depth measurement method, comprising:

[0005] establishing a geometric model of an alignment mark, the alignment mark comprising a longitudinal etching mark and a lateral etching mark, the longitudinal etching mark extending in a direction perpendicular to the substrate, and the lateral etching mark extending from the longitudinal etching mark in a direction away from the longitudinal etching mark and parallel to the substrate;

[0006] obtaining an actual alignment signal of a to-be-measured alignment mark in a to-be-measured wafer;

[0007] determining the lateral etching depth of the to-be-measured wafer according to the actual alignment signal and the geometric model.

[0008] In one embodiment, determining the lateral etching depth of the to-be-measured wafer according to the actual alignment signal and the geometric model comprises:

[0009] forming a plurality of alignment marks with different lateral etching depths in an experimental wafer, and measuring the experimental lateral etching depth and the experimental alignment signal of each alignment mark;

[0010] establishing a lateral etching depth database according to the experimental lateral etching depth and the experimental alignment signal of each alignment mark; wherein the lateral etching depth database is used to represent the correlation between the lateral etching depth and the alignment signal;

[0011] The actual alignment signal of the to-be-tested alignment mark in the to-be-tested wafer is taken as an input variable of the lateral etching depth database, and an output variable of the lateral etching depth database corresponds to the lateral etching depth of the to-be-tested wafer.

[0012] In one of the embodiments, before the lateral etching depth database is established according to the experimental lateral etching depth and the experimental alignment signal, the following steps are included:

[0013] A plurality of virtual alignment marks with different virtual lateral etching depths are established.

[0014] A virtual alignment signal of each of the virtual alignment marks is determined according to the corresponding virtual lateral etching depth and the geometric model.

[0015] The lateral etching depth database is established according to the experimental lateral etching depth and the experimental alignment signal of each of the alignment marks.

[0016] The lateral etching depth database is established according to the experimental lateral etching depth and the experimental alignment signal of each of the alignment marks and the virtual lateral etching depth and the virtual alignment signal of each of the virtual alignment marks.

[0017] In one of the embodiments, the lateral etching depth of the to-be-tested wafer is determined according to the actual alignment signal and the geometric model, which includes:

[0018] A theoretical alignment signal of the alignment mark is determined based on a theoretical lateral etching depth and a geometric model of the alignment mark.

[0019] A lateral etching depth evaluation function is established according to the theoretical alignment signal of the alignment mark and the actual alignment signal of the to-be-tested alignment mark, wherein the lateral etching depth evaluation function is used to represent the correlation between the theoretical lateral etching depth and the lateral etching depth of the to-be-tested wafer.

[0020] A permitted depth range of the lateral etching depth of the to-be-tested wafer is determined.

[0021] The lateral etching depth of the to-be-tested wafer is determined according to the lateral etching depth evaluation function within the permitted depth range of the lateral etching depth based on an intelligent algorithm.

[0022] In one of the embodiments, the number of the to-be-tested alignment marks in the to-be-tested wafer is multiple, and the to-be-tested alignment marks are distributed in a plurality of target positions of the to-be-tested wafer, and the lateral etching depth of the to-be-tested wafer is determined according to the actual alignment signal and the geometric model, which further includes:

[0023] According to the actual alignment signal of the to-be-tested alignment mark of the target position and the geometric model, a lateral etching depth of the target position in the to-be-tested wafer is determined.

[0024] The present disclosure also provides a process evaluation method of a lateral etching process, comprising:

[0025] According to the actual alignment signal of the to-be-tested alignment mark of the target position and the geometric model, a lateral etching depth of the target position in the to-be-tested wafer is determined.

[0026] According to the lateral etching depth of each target position, a process evaluation of the lateral etching process of the to-be-tested wafer is performed.

[0027] The present disclosure also provides a lateral etching depth measurement device, comprising:

[0028] A modeling unit is configured to establish a geometric model of an alignment mark, the alignment mark comprising a longitudinal etching mark and a lateral etching mark, the longitudinal etching mark extending along a direction perpendicular to a substrate, and the lateral etching mark extending from the longitudinal etching mark along a direction away from the longitudinal etching mark and parallel to the substrate;

[0029] A measurement unit is configured to measure an actual alignment signal of a to-be-tested alignment mark in a to-be-tested wafer;

[0030] A processing unit is configured to determine a lateral etching depth of the to-be-tested wafer according to the actual alignment signal and the geometric model.

[0031] In one embodiment, the lateral etching depth measurement device further comprises:

[0032] An input unit is configured to input an experimental lateral etching depth and an experimental alignment signal of each of the alignment marks after forming a plurality of alignment marks with different lateral etching depths in a measurement experimental wafer;

[0033] The modeling unit is further configured to establish a lateral etching depth database according to the experimental lateral etching depth and the experimental alignment signal of each of the alignment marks; wherein the lateral etching depth database is configured to represent a correlation between a lateral etching depth and an alignment signal;

[0034] The processing unit is further configured to take the actual alignment signal of the to-be-tested alignment mark in the to-be-tested wafer as an input variable of the lateral etching depth database, and take an output variable of the lateral etching depth database as the lateral etching depth of the to-be-tested wafer.

[0035] In one of the embodiments, the input unit is further configured to input a plurality of different virtual lateral etching depths, and the processing unit is further configured to obtain a virtual alignment signal corresponding to each of the virtual lateral etching depths according to the geometric model and each of the virtual lateral etching depths.

[0036] The modeling unit is further configured to establish the lateral etching depth database according to the experimental lateral etching depths and the experimental alignment signals of each of the alignment marks, and the virtual lateral etching depths and the virtual alignment signals corresponding to each of the virtual lateral etching depths.

[0037] In one of the embodiments, the processing unit comprises:

[0038] The operation module is configured to determine a theoretical alignment signal of the alignment mark according to the theoretical lateral etching depth and the geometric model of the alignment mark, and the operation module is further configured to determine a permissible depth range of the lateral etching depth of the wafer under test.

[0039] The function creation module is configured to establish a lateral etching depth evaluation function according to the theoretical alignment signal and the actual alignment signal of the alignment mark, and the lateral etching depth evaluation function is configured to represent the correlation between the theoretical lateral etching depth and the lateral etching depth of the wafer under test.

[0040] The operation module is further configured to determine the lateral etching depth of the wafer under test according to the lateral etching depth evaluation function within the permissible depth range of the lateral etching depth based on an intelligent algorithm.

[0041] In one of the embodiments, the number of the alignment marks under test is a plurality, and the alignment marks under test are distributed in a plurality of target positions of the wafer under test, and the processing unit is further configured to determine the lateral etching depth of the target position in the wafer under test according to the actual alignment signal of the alignment mark under test of the target position and the geometric model.

[0042] The present disclosure further provides an evaluation device for a lateral etching process, comprising:

[0043] The lateral etching depth measurement device as described above, the measurement unit is configured to measure the actual alignment signals of the alignment marks under test formed in different target positions of the wafer under test by the same lateral etching process, and the processing unit is further configured to determine the lateral etching depths of the different target positions according to the actual alignment signals of the alignment marks under test formed in the different target positions of the wafer under test and the geometric model of the alignment mark.

[0044] The evaluation unit is configured to perform process evaluation on the lateral etching process of the wafer under test according to the lateral etching depths of each of the target positions.

[0045] The present disclosure also provides a computer device comprising a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the method for measuring lateral etching depth or the steps of the method for process evaluation of the lateral etching process.

[0046] The present disclosure also provides a computer readable storage medium storing a computer program, wherein the computer program is executed by a processor to implement the steps of the method for measuring lateral etching depth or the steps of the method for process evaluation of the lateral etching process.

[0047] In the method for measuring lateral etching depth, after obtaining the actual alignment signal of the target alignment mark in the wafer to be measured, the lateral etching depth of the wafer to be measured is determined by the actual alignment signal and the geometric model of the alignment mark, which improves the efficiency of measuring the lateral etching depth of the wafer to be measured, and does not need to be sliced, thereby reducing the cost of measuring the lateral etching depth.

[0048] In the method for process evaluation of the lateral etching process, the lateral etching depths of different target positions in the wafer to be measured are determined according to the actual alignment signals of the target alignment marks formed by the same lateral etching process at different target positions in the wafer to be measured and the geometric model of the alignment mark, and the lateral etching process is evaluated according to the lateral etching depths of different target positions, which improves the efficiency of evaluating the lateral etching process, and does not need to be sliced, thereby reducing the cost of evaluating the lateral etching process.

[0049] In the device for measuring lateral etching depth, the measurement unit measures the actual alignment signal of the target alignment mark in the wafer to be measured, and the processing unit determines the lateral etching depth of the wafer to be measured according to the actual alignment signal of the target alignment mark and the geometric model of the alignment mark, which improves the efficiency of measuring the lateral etching depth of the wafer to be measured, and does not need to be sliced, thereby reducing the cost of measuring the lateral etching depth.

[0050] In the device for evaluating the lateral etching process, the measurement unit measures the actual alignment signals of the target alignment marks formed by the same lateral etching process at different target positions in the wafer to be measured, the processing unit determines the lateral etching depths of different target positions in the wafer to be measured according to the actual alignment signals of the target alignment marks formed by the same lateral etching process at different target positions in the wafer to be measured and the geometric model of the alignment mark, and the evaluation unit evaluates the lateral etching process according to the lateral etching depths of different target positions, which improves the efficiency of evaluating the lateral etching process, and does not need to be sliced, thereby reducing the cost of evaluating the lateral etching process. BRIEF DESCRIPTION OF DRAWINGS

[0051] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0052] Figure 1 This is a flowchart illustrating the method for measuring the lateral etching depth in some embodiments;

[0053] Figure 2 This is a top view of the alignment marks in some embodiments;

[0054] Figure 3 For some embodiments Figure 2 The alignment marks shown are a cross-sectional view along the AA direction perpendicular to the substrate.

[0055] Figure 4 For some embodiments Figure 2 The alignment marks shown are a cross-sectional schematic diagram along the BB direction in a direction perpendicular to the substrate;

[0056] Figure 5 This is a flowchart illustrating the process of determining the lateral etching depth of the wafer under test based on the actual alignment signal and the geometric model in some embodiments.

[0057] Figure 6 This is a flowchart illustrating the process of determining the lateral etching depth of the wafer under test based on the actual alignment signal and the geometric model in some other embodiments.

[0058] Figure 7 This is a flowchart illustrating the process of determining the lateral etching depth of the wafer under test based on the actual alignment signal and the geometric model in some embodiments.

[0059] Figure 8 This is a schematic diagram of the alignment signals of alignment marks for different transverse etchings corresponding to the same geometric model in some embodiments;

[0060] Figure 9 This is a bar chart of alignment signals for alignment marks of different transverse etchings corresponding to the same geometric model in other embodiments;

[0061] Figure 10 This is a bar chart of alignment signals for alignment marks of different transverse etchings corresponding to the same geometric model in some embodiments;

[0062] Figure 11 This is a schematic diagram of the alignment signals of alignment marks for different transverse etchings corresponding to the same geometric model in some other embodiments;

[0063] Figure 12 A flow chart of a process evaluation method for a lateral etching process in an embodiment;

[0064] Figure 13 A structure diagram of a lateral etching depth measurement device in some embodiments;

[0065] Figure 14 A structure diagram of a lateral etching depth measurement device in some other embodiments;

[0066] Figure 15 A structure diagram of a lateral etching process evaluation device in some embodiments.

[0067] Explanation of reference signs:

[0068] Substrate 102, stack structure 104, longitudinal etching mark 202, lateral etching mark 204, first material layer 206, second material layer 208, modeling unit 302, measurement unit 304, processing unit 306, input unit 308, evaluation unit 310, operation module 402, function creation module 404. DETAILED DESCRIPTION

[0069] In order to facilitate the understanding of the present application, the present application will be described in more detail below with reference to the relevant drawings. The preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms, and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0070] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. The terms used in the specification of the present application are only for the purpose of describing specific embodiments of the present application, and are not intended to limit the present application.

[0071] It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present. It will also be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section; for example, a first doped type could be termed a second doped type; and, similarly, a second doped type could be termed a first doped type; a first doped type and a second doped type are different doped types, e.g., a first doped type can be p-type and a second doped type can be n-type, or the first doped type can be n-type and the second doped type can be p-type.

[0072] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can also be oriented in the other direction (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0073] The singular forms "a", "an", and "the" include plural referents unless the context clearly dictates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. In addition, use of the term "and / or" includes any and all combinations of associated items.

[0074] Figure 1 A flowchart of a method for measuring a lateral etching depth in some embodiments, Figure 2 A top view of an alignment mark in some embodiments, Figure 3 A cross-sectional view of an alignment mark in some embodiments, Figure 2 A cross-sectional view of an alignment mark shown in a direction AA perpendicular to the substrate, Figure 4 A cross-sectional view of an alignment mark in some embodiments, Figure 2 A cross-sectional view of an alignment mark shown in a direction BB perpendicular to the substrate, Figure 2 A first direction parallel to the plane of the substrate 102 is shown, Figure 2 A second direction parallel to the plane of the substrate 102 is shown, Figure 2 A third direction from the top surface of the substrate 102 to the bottom surface of the substrate 102 in some embodiments,

[0075] As shown in the figure, Figures 1-4 In the present embodiment, a method for measuring a lateral etching depth is provided, comprising:

[0076] S102, a geometric model of the alignment mark is established.

[0077] Specifically, the alignment mark includes a longitudinal etching mark 202 extending in a third direction Z perpendicular to the substrate 102 and a lateral etching mark 204 extending from the longitudinal etching mark 202 in a direction away from the longitudinal etching mark 202 and parallel to the substrate 102 (a direction in the plane of the first direction X and the second direction Y); a geometric model of the alignment mark is established according to the structural parameter information of the alignment mark, the structural parameter information including the arrangement information of each film layer in the stacked structure constituting the alignment mark, the thickness information of each film layer, the refractive index information of each film layer, the extinction coefficient information of each film layer, the longitudinal depth information of the longitudinal etching mark 202 in the third direction Z, the groove size information of the longitudinal etching mark 202 in the direction parallel to the substrate 102, the line width information of the stacked structure on one side of the longitudinal etching mark 202 in the direction parallel to the substrate 102, the position information of the lateral etching mark 204, the lateral depth information of the lateral etching mark 204, the refractive index information of the substrate 102 where the alignment mark is located, and the extinction coefficient information of the substrate 102 where the alignment mark is located, wherein the lateral depth information of the lateral etching mark 204 is a variable value, and the remaining information is a quantitative value, and the geometric model represents a set of alignment marks that differ only in lateral depth.

[0078] In some embodiments, Figures 2-4The alignment mark shown is used to exemplarily illustrate the structural parameter information. The alignment mark is located on the surface of the substrate 102 and in the stack structure 104. The structural parameter information includes the following information: the arrangement information of the film layers refers to the stack structure 104 including the first material layers 206 and the second material layers 208 which are alternately stacked from the substrate 102 to the direction away from the substrate 102; the thickness information of the film layers refers to the thickness T1 of each first material layer 206 (the thickness T1 of each first material layer 206 can be the same or at least one first material layer 206 has a different thickness T1 from other first material layers 206) and the thickness T2 of each second material layer 208 (the thickness T2 of each second material layer 208 can be the same or at least one second material layer 208 has a different thickness T2 from other second material layers 206); the refractive index information of the film layers refers to the first refractive index of each first material layer 206 under different wavelengths of light and the second refractive index of each second material layer 208 under different wavelengths of light; the extinction coefficient information of the film layers refers to the first extinction coefficient of each first material layer 206 under different wavelengths of light and the second extinction coefficient of each second material layer 208 under different wavelengths of light; the longitudinal depth information refers to the longitudinal depth D1 of the longitudinal etching mark 202 in the third direction Z; the cross section of the longitudinal etching mark 202 in the plane parallel to the substrate 102 is a rectangle, the trench size information refers to the first length L1 of the longitudinal etching mark 202 in the first direction X and the first width W1 of the longitudinal etching mark 202 in the second direction Y; the line width information refers to the second length L2 of the stack structure on one side of the longitudinal etching mark 202 in the first direction X and the second width W2 of the stack structure on one side of the longitudinal etching mark 202 in the second direction Y; the position information of the transverse etching mark 204 refers to the transverse etching mark 204 being located in the second material layer 208; the transverse depth information refers to the depth D2 of the transverse etching mark 204 in the plane parallel to the substrate 102 away from the longitudinal etching mark 202, and the depth D2 is the only variable in the structural parameter information; the refractive index information of the substrate 102 where the alignment mark is located refers to the refractive index of the substrate 102; and the extinction coefficient information of the substrate 102 where the alignment mark is located refers to the extinction coefficient of the substrate 102. Exemplarily, the material of the substrate 102 is single crystal silicon, the material of the first material layer 206 is an oxide layer, and the material of the second material layer 208 is silicon nitride.

[0079] S104, acquiring an actual alignment signal of the alignment mark to be measured in the wafer to be measured.

[0080] The to-be-measured wafer includes a substrate 102 and a stack structure 104 on the surface of the substrate 102. In a process of forming a longitudinal etching groove extending in a third direction Z in the stack structure in the to-be-measured wafer, a longitudinal etching mark in a to-be-measured alignment mark is formed. In a process of laterally etching a second material layer in the stack structure to form a lateral etching groove based on the longitudinal etching groove, a lateral etching mark in the to-be-measured alignment mark is formed. The depth of the lateral etching groove in the to-be-measured wafer away from the longitudinal etching groove is equal to the depth of the lateral etching mark in the to-be-measured alignment mark away from the longitudinal etching mark. The to-be-measured alignment mark is an alignment mark with a lateral etching depth being a constant value. The actual alignment signal of the to-be-measured alignment mark formed in the to-be-measured wafer is measured to obtain an actual alignment signal of the to-be-measured alignment mark.

[0081] It can be understood that when the alignment mark includes a plurality of longitudinal etching marks 202 arranged at intervals and extending in a third direction Z perpendicular to the substrate 102, and a lateral etching mark 204 corresponding to the longitudinal etching mark 202 and extending away from the longitudinal etching mark 202 in a direction parallel to the substrate 102 (a direction in a plane of the first direction X and the second direction Y), each longitudinal etching mark 202 and the corresponding lateral etching mark 204 are taken as an integral structure. In step S104, one integral structure in the to-be-measured alignment mark is selected to represent the to-be-measured alignment mark, and the actual alignment signal of the integral structure is taken as the actual alignment signal of the to-be-measured alignment mark. In subsequent steps related to the alignment mark (for example, an experimental alignment mark, a virtual alignment mark, etc.), the integral structure is selected to represent the alignment mark. In step S104, the actual alignment signals of the integral structures in the to-be-measured alignment mark are obtained, and then a plurality of intermediate lateral etching depths of the to-be-measured wafer are obtained according to the integral structures. The intermediate lateral etching depths correspond to the integral structures one by one. Finally, the plurality of intermediate lateral etching depths are processed (for example, averaged) to obtain the lateral etching depth of the to-be-measured wafer. The following description is based on the alignment mark including only one integral structure.

[0082] In S106, the lateral etching depth of the to-be-measured wafer is determined according to the actual alignment signal and the geometric model of the alignment mark.

[0083] Based on the vector diffraction theory, the lateral etching depth of the to-be-measured wafer is determined according to the actual alignment signal of the to-be-measured alignment mark and the geometric model of the alignment mark. The lateral etching depth is the distance of the lateral etching groove away from the longitudinal etching groove in a plane parallel to the substrate 102.

[0084] In the above-mentioned method for measuring the lateral etching depth, after obtaining the actual alignment signal of the to-be-measured alignment mark in the to-be-measured wafer, the lateral etching depth of the to-be-measured wafer is determined through the actual alignment signal and the geometric model of the alignment mark. The efficiency of measuring the lateral etching depth of the to-be-measured wafer is improved, and slicing is not required, thereby reducing the cost of measuring the lateral etching depth.

[0085] Figure 5 A flowchart for determining the lateral etching depth of a wafer to be measured according to an actual alignment signal and a geometric model in some embodiments is shown in FIG. 2, in which one embodiment, determining the lateral etching depth of the wafer to be measured according to the actual alignment signal and the geometric model comprises: Figure 5

[0086] S202, forming a plurality of alignment marks with different lateral etching depths in an experimental wafer, and measuring the experimental lateral etching depth and the experimental alignment signal of each alignment mark.

[0087] Specifically, the experimental wafer includes a substrate 102 and a stack structure 104 on the surface of the substrate 102, a plurality of alignment marks with different lateral etching depths are formed in the experimental wafer, and the experimental lateral etching depth and the experimental alignment signal of each alignment mark in the experimental wafer are measured. For example, a photolithography machine can be used to align each alignment mark in the experimental wafer to obtain the experimental alignment signal of each alignment mark in the experimental wafer, and a slicing method can be used to obtain the experimental lateral etching depth of each alignment mark in the experimental wafer.

[0088] S204, establishing a lateral etching depth database according to the experimental lateral etching depth and the experimental alignment signal of each alignment mark.

[0089] According to the experimental lateral etching depth and the experimental alignment signal of each alignment mark in the experimental wafer, a lateral etching depth database is established, wherein the lateral etching depth database is used to represent the correlation between the lateral etching depth D2 and the alignment signal WQ (wafer quality) of the alignment mark, and the lateral etching depth database is applicable to the alignment mark to be measured belonging to the same geometric model. Different geometric models of alignment marks correspond to different lateral etching depth databases.

[0090] It can be understood that the more alignment marks with different lateral etching depths formed in the experimental wafer, the more complete the lateral etching depth database, and the higher the data accuracy of the lateral etching depth of the wafer to be measured obtained according to the lateral etching depth database. Further, the lateral etching depth of the alignment mark formed in the experimental wafer fluctuates on both sides of the actual product lateral etching depth, which facilitates the subsequent determination of the lateral etching depth of the wafer to be measured according to the lateral etching depth database.

[0091] S206, obtaining the lateral etching depth of the wafer to be measured according to the actual alignment signal and the lateral etching depth database.

[0092] ​Specifically, the actual alignment signal of the to-be-tested alignment mark in the to-be-tested wafer is taken as an input variable of the lateral etching depth database, and an output variable of the lateral etching depth database corresponds to the lateral etching depth of the to-be-tested wafer. The lateral etching depth database is established according to the experimental lateral etching depths and the experimental alignment signals of the plurality of alignment marks with different lateral etching depths formed in the measurement experimental wafer. The deviation between the data in the lateral etching depth database and the real data of the alignment mark is small, the speed of obtaining the lateral etching depth of the to-be-tested wafer through the actual alignment signal of the to-be-tested alignment mark in the to-be-tested wafer and the lateral etching depth database is fast, and the data precision is high.

[0093] Figure 6 For another embodiment, the flowchart for determining the lateral etching depth of the to-be-tested wafer according to the actual alignment signal and the geometric model is shown in FIG. 2B. In one embodiment, before the lateral etching depth database is established according to the experimental lateral etching depths and the experimental alignment signals, that is, after step S202 and before step S206, the following steps are included: Figure 6

[0094] S302, a plurality of virtual alignment marks with different virtual lateral etching depths are established.

[0095] S304, the virtual alignment signals of the virtual alignment marks are determined according to the virtual lateral etching depths and the geometric model.

[0096] S306, the lateral etching depth database is established according to the experimental lateral etching depths and the experimental alignment signals of the alignment marks and the virtual lateral etching depths and the virtual alignment signals of the virtual alignment marks.

[0097] Steps S302-S306 are specifically, a plurality of virtual alignment marks with different virtual lateral etching depths are set, the virtual alignment marks are not actually formed in the wafer, and are included in the geometric model of the alignment mark. According to the virtual lateral etching depths and the geometric model of the alignment mark, a theoretical model corresponding to each virtual alignment mark can be obtained. For example, a plurality of virtual lateral etching depths are selected between adjacent experimental lateral etching depths, so as to avoid the process deviation from leading to the fact that the lateral etching depth of the to-be-tested wafer cannot be obtained according to the lateral etching depth database and the actual alignment signal. Based on the vector diffraction theory and the theoretical model of each virtual alignment mark, the virtual alignment signals of the virtual alignment marks are determined, and the virtual alignment signals are simulation data of the alignment signals of the virtual alignment marks. Then, the lateral etching depth database is established according to the experimental lateral etching depths and the experimental alignment signals of the alignment marks and the virtual lateral etching depths and the virtual alignment signals of the virtual alignment marks. The virtual alignment marks can be used to perfect the lateral etching depth database and increase the application range of the lateral etching depth database. ​

[0098] Figure 7 For further embodiments, a flowchart for determining the lateral etching depth of the wafer under test according to the actual alignment signals and the geometric model is shown in FIG. 4, in which one embodiment, the lateral etching depth of the wafer under test is determined according to the actual alignment signals and the geometric model, comprising: Figure 7

[0099] S402, determining the theoretical alignment signal of the alignment mark based on the theoretical lateral etching depth and the geometric model of the alignment mark.

[0100] Specifically, the theoretical lateral etching depth D2nis set, and based on the vector diffraction theory, the theoretical alignment signal WQnof the alignment mark corresponding to the theoretical lateral etching depth D2nis determined according to the theoretical lateral etching depth D2nand the geometric model of the alignment mark.

[0101] S404, establishing a lateral etching depth evaluation function according to the theoretical alignment signal of the alignment mark and the actual alignment signal of the alignment mark under test.

[0102] According to the theoretical alignment signal WQnof the alignment mark corresponding to the theoretical lateral etching depth D2nand the actual alignment signal WQ1of the alignment mark under test, a lateral etching depth evaluation function F is established, which is used to represent the correlation between the theoretical lateral etching depth D2nand the lateral etching depth D20of the wafer under test. For example, the lateral etching depth evaluation function F = WQn-WQ1.

[0103] S406, determining the permissible depth range of the lateral etching depth of the wafer under test.

[0104] Specifically, according to the design value of the lateral etching depth of the alignment mark under test or according to the process experience, the permissible depth range of the lateral etching depth D20of the wafer under test is determined, which represents the approximate range of the lateral etching depth D20of the wafer under test.

[0105] S408, based on the intelligent algorithm, the lateral etching depth of the wafer under test is determined according to the lateral etching depth evaluation function within the permissible depth range of the lateral etching depth.

[0106] ​Specifically, based on the intelligent algorithm, a theoretical lateral etching depth D2n is selected within the permitted depth range of the lateral etching depth D20, and a theoretical alignment signal WQn corresponding to the theoretical lateral etching depth D2n is calculated, so that the theoretical lateral etching depth D2n satisfying the preset condition of the lateral etching depth evaluation function F is the lateral etching depth D20 of the wafer under test. For example, the preset condition is that the absolute value of the lateral etching depth evaluation function F is less than or equal to a preset value, for example, the preset value is 0. In the process of confirming the lateral etching depth of the wafer under test, the lateral etching depth and the alignment signal do not need to be collected in advance, which improves the speed of measuring the lateral etching depth and saves the cost.

[0107] In one of the embodiments, the number of the alignment marks under test in the wafer under test is multiple, and the alignment marks under test are distributed in multiple target positions of the wafer under test. The method of determining the lateral etching depth of the wafer under test according to the actual alignment signal and the geometric model further comprises: determining the lateral etching depth of the target position of the wafer under test according to the actual alignment signal of the alignment mark under test of the target position and the geometric model. By forming the alignment marks under test in different target positions of the wafer under test, the lateral etching depths of different target positions of the wafer under test can be confirmed, and the accuracy of measuring the lateral etching depth is improved.

[0108] In one of the embodiments, the alignment mark comprises a horizontal subdivision mark, a vertical subdivision mark or a square subdivision mark.

[0109] In one of the embodiments, the same wavelength of alignment light is used to measure the lateral etching depth of the wafer under test. Specifically, the same wavelength of alignment light is used to measure the actual alignment signal of the alignment mark under test. This measurement method is simple to operate and fast. For example, the wavelength of the alignment light comprises 532 nm, 633 nm, 780 nm or 852 nm.

[0110] In one of the embodiments, different wavelengths of alignment light are used to measure the lateral etching depth of the wafer under test, and the lateral etching depth of the wafer under test is determined according to the actual alignment signal and the geometric model, which comprises: determining the wavelength lateral etching depth of the wafer under test corresponding to different wavelengths according to the actual alignment signal and the geometric model corresponding to different wavelengths; and confirming the lateral etching depth of the wafer under test according to the wavelength lateral etching depth of the wafer under test corresponding to different wavelengths. At this time, different wavelengths of alignment light are used to measure the actual alignment signal of the alignment mark under test, and this measurement method has high accuracy. For example, the wavelength of the alignment light comprises multiple of 532 nm, 633 nm, 780 nm and 852 nm.

[0111] It can be understood that the step of measuring the experimental lateral etching depth of each alignment mark and the experimental alignment signal includes: measuring the experimental lateral etching depth of each alignment mark and the experimental alignment signal corresponding to different wavelengths. According to the actual alignment signal and the lateral etching depth database, the step of obtaining the lateral etching depth of the wafer under test includes: taking the actual alignment signal of the alignment mark under test in the wafer under test and the wavelength corresponding to the actual alignment signal as the input variable of the lateral etching depth database, and the output variable of the lateral etching depth database corresponds to the wavelength lateral etching depth of the wafer under test corresponding to the wavelength.

[0112] In one embodiment, according to the wavelength lateral etching depth of the wafer under test corresponding to different wavelengths, the lateral etching depth of the wafer under test is confirmed, including: averaging each wavelength lateral etching depth, and taking the average value as the lateral etching depth of the wafer under test. This method is simple to operate and removes the influence of wavelength on lateral etching depth.

[0113] In one embodiment, according to the wavelength lateral etching depth of the wafer under test corresponding to different wavelengths, the lateral etching depth of the wafer under test is confirmed, including: according to the size of the alignment signal corresponding to each wavelength, obtaining the weight of the wavelength lateral etching depth corresponding to each wavelength in the lateral etching depth of the wafer under test; according to each wavelength lateral etching depth and the weight of each wavelength lateral etching depth, confirming the lateral etching depth of the wafer under test; wherein the sum of the weights corresponding to each wavelength lateral etching depth is equal to 1. Specifically, the size of the alignment signal corresponding to each wavelength is proportional to the weight, the weight of the wavelength lateral etching depth corresponding to the wavelength with a large alignment signal is large, and the weight of the wavelength lateral etching depth corresponding to the wavelength with a small alignment signal is small. Through this method, the accuracy of measuring the lateral etching depth can be improved.

[0114] Figure 8 A columnar diagram of alignment signals of alignment marks corresponding to different lateral etchings of the same geometric model in some embodiments, Figure 9 A columnar diagram of alignment signals of alignment marks corresponding to different lateral etchings of the same geometric model in some other embodiments, Figure 10 A columnar diagram of alignment signals of alignment marks corresponding to different lateral etchings of the same geometric model in some other embodiments, Figure 11 A columnar diagram of alignment signals of alignment marks corresponding to different lateral etchings of the same geometric model in some other embodiments, Figure 8As shown in the figure, the alignment marks are the subdivided alignment marks along the first direction X, the subdivided line width (line width information) and the groove width (groove size information) are both 100 nm, the figure shows the measurement values of the alignment signals of each alignment mark when the corresponding lateral etching depths of the alignment marks of the same geometric model are D21=0 nm, D22=10 nm, D23=20 nm and D24=30 nm under the alignment light with a wavelength of 532 nm, the alignment light with a wavelength of 633 nm, the alignment light with a wavelength of 780 nm and the alignment light with a wavelength of 852 nm; as shown in the figure, Figure 9 As shown in the figure, the alignment marks are the subdivided alignment marks along the second direction Y, the subdivided line width (line width information) and the groove width (groove size information) are both 100 nm, the figure shows the measurement values of the alignment signals of each alignment mark when the corresponding lateral etching depths of the alignment marks of the same geometric model are D21=0 nm, D22=10 nm, D23=20 nm and D24=30 nm under the alignment light with a wavelength of 532 nm, the alignment light with a wavelength of 633 nm, the alignment light with a wavelength of 780 nm and the alignment light with a wavelength of 852 nm; as shown in the figure, Figure 10 As shown in the figure, the alignment marks are the subdivided alignment marks along the first direction X, the subdivided line width (line width information) and the groove width (groove size information) are both 200 nm, the figure shows the measurement values of the alignment signals of each alignment mark when the corresponding lateral etching depths of the alignment marks of the same geometric model are D21=0 nm, D22=20 nm, D23=40 nm and D24=60 nm under the alignment light with a wavelength of 532 nm, the alignment light with a wavelength of 633 nm, the alignment light with a wavelength of 780 nm and the alignment light with a wavelength of 852 nm; as shown in the figure, Figure 11 As shown in the figure, the alignment marks are the subdivided alignment marks along the second direction Y, the subdivided line width (line width information) and the groove width (groove size information) are both 200 nm, the figure shows the measurement values of the alignment signals of each alignment mark when the corresponding lateral etching depths of the alignment marks of the same geometric model are D21=0 nm, D22=20 nm, D23=40 nm and D24=60 nm under the alignment light with a wavelength of 532 nm, the alignment light with a wavelength of 633 nm, the alignment light with a wavelength of 780 nm and the alignment light with a wavelength of 852 nm; as shown in the figure, Figure 8 — Figure 11It can be seen that, for the same wavelength of alignment light, the alignment signals of the alignment marks corresponding to the same geometric model and different lateral etching depths are different, the alignment signals change with the change of the lateral etching depth, and the wafer quality (WQ) alignment signal is more sensitive to the change of the lateral etching depth; for different wavelengths of alignment light, the alignment signals of the alignment marks corresponding to the same geometric model and the same lateral etching depth are different, and the alignment signals change with the change of the wavelength of the alignment light.

[0115] Figure 12 For an embodiment of the process evaluation method of the lateral etching process, as shown in FIG. 6, in the embodiment, a process evaluation method of a lateral etching process is provided, and the same or corresponding parts of the above-mentioned measurement method of the lateral etching depth will not be described hereinafter. The process evaluation method of the lateral etching process comprises the following steps: Figure 12 S502, establishing a geometric model of the alignment mark.

[0116] Specifically, the alignment mark comprises a longitudinal etching mark 202 extending along a third direction Z perpendicular to the substrate 102 and a lateral etching mark 204 extending from the longitudinal etching mark 202 in a direction away from the longitudinal etching mark 202 and parallel to the substrate 102 (a direction in the plane of the first direction X and the second direction Y); a geometric model of the alignment mark is established according to the structure parameter information of the alignment mark, the structure parameter information comprising arrangement information of each film layer in the stacked structure constituting the alignment mark, thickness information of each film layer, refractive index information of each film layer, extinction coefficient information of each film layer, longitudinal depth information of the longitudinal etching mark 202 in the third direction Z, groove size information of the longitudinal etching mark 202 in the direction parallel to the substrate 102, line width information of the stacked structure on one side of the longitudinal etching mark 202 in the direction parallel to the substrate 102, position information of the lateral etching mark 204, lateral depth information of the lateral etching mark 204, refractive index information of the substrate 102 where the alignment mark is located, and extinction coefficient information of the substrate 102 where the alignment mark is located, wherein the lateral depth information of the lateral etching mark 204 is a variable value, and the remaining information is a quantitative value, and the geometric model represents a set of alignment marks that differ only in lateral depth.

[0117] S504, obtaining actual alignment signals of each test alignment mark formed by the same lateral etching process at different target positions in the test wafer.

[0118]

[0119] ​Specifically, the same lateral etching process is used to form the to-be-measured alignment marks at different target positions in the to-be-measured wafer, and then actual alignment signals of the to-be-measured alignment marks are measured and obtained. For example, the target positions are uniformly distributed in the to-be-measured wafer, so that the process evaluation of the lateral etching process is more accurate.

[0120] S506, according to the actual alignment signals of the to-be-measured alignment marks and the geometric model of the alignment marks, the lateral etching depths of the different target positions are confirmed.

[0121] According to the actual alignment signals of the to-be-measured alignment marks and the geometric model of the alignment marks, the lateral etching depths of the different target positions in the to-be-measured wafer are confirmed based on the vector diffraction theory.

[0122] S508, according to the lateral etching depths of the target positions, the process evaluation of the lateral etching process of the to-be-measured wafer is performed.

[0123] Specifically, according to the deviation of the lateral etching depths of the target positions, the process evaluation of the lateral etching process of the to-be-measured wafer is performed. For example, when the deviation of the lateral etching depths of the target positions is less than or equal to a preset deviation, it is determined that the lateral etching process of the to-be-measured wafer meets the process requirement; when the deviation of the lateral etching depths of the target positions is greater than the preset deviation, it is determined that the lateral etching process of the to-be-measured wafer does not meet the process requirement.

[0124] In the process evaluation method of the lateral etching process, according to the actual alignment signals of the to-be-measured alignment marks formed at different target positions in the to-be-measured wafer by the same lateral etching process and the geometric model of the alignment marks, the lateral etching depths of the different target positions in the to-be-measured wafer are confirmed, and the lateral etching process is evaluated according to the lateral etching depths of the different target positions, which improves the efficiency of evaluating the lateral etching process and reduces the cost of evaluating the lateral etching process without slicing.

[0125] It should be understood that, although Figure 1 , Figure 5 , Figure 6 , Figure 7 and Figure 12 the steps in the flowcharts are displayed in sequence according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, the execution of these steps is not strictly limited in sequence, and these steps can be executed in other orders. Moreover, Figure 1 , Figure 5 , Figure 6 , Figure 7 and Figure 12At least one of the steps in the above method can include multiple steps or multiple stages, which are not necessarily performed at the same time, but can be performed at different times, and the order of the steps or stages is not necessarily sequential, but can be performed alternately or alternately with at least one of the other steps or steps in the step or stage.

[0126] Figure 13 For the structure of the lateral etching depth measurement device in some embodiments, as shown in Figure 2 、 Figure 3 、 Figure 4 and Figure 13 , in this embodiment, a lateral etching depth measurement device is provided, and the same or corresponding parts of the above-mentioned lateral etching depth measurement method are not described in detail, a lateral etching depth measurement device includes: a modeling unit 302, a measurement unit 304 and a processing unit 306; the modeling unit 302 is used to establish a geometric model of the alignment mark, the alignment mark includes a longitudinal etching mark 202 and a lateral etching mark 204, the longitudinal etching mark 202 extends along a third direction Z perpendicular to the substrate 102, and the lateral etching mark 204 extends from the longitudinal etching mark 202 in a direction away from the longitudinal etching mark 202 and parallel to the substrate 102 (a direction in the plane of the first direction X and the second direction Y); the measurement unit 304 is used to measure the actual alignment signal of the alignment mark to be measured in the wafer to be measured; the processing unit 306 is used to determine the lateral etching depth of the wafer to be measured according to the actual alignment signal and the geometric model.

[0127] Specifically, the modeling unit 302 establishes a geometric model of the alignment mark according to the structure parameter information of the alignment mark, and the structure parameter information includes the arrangement information of each film layer in the stacked structure constituting the alignment mark, the thickness information of each film layer, the refractive index information of each film layer, the extinction coefficient information of each film layer, the longitudinal depth information of the longitudinal etching mark 202 in the third direction Z, the groove size information of the longitudinal etching mark 202 in the direction parallel to the substrate 102, the line width information of the one side stacked structure of the longitudinal etching mark 202 in the direction parallel to the substrate 102, the position information of the lateral etching mark 204, the lateral depth information of the lateral etching mark 204, the refractive index information of the substrate 102 where the alignment mark is located, and the extinction coefficient information of the substrate 102 where the alignment mark is located. The lateral depth information of the lateral etching mark 204 is a variable value, and the rest is a quantitative value, and the geometric model represents a set of alignment marks with different lateral depths.

[0128] The to-be-measured wafer includes a substrate 102 and a stack structure 104 on the surface of the substrate 102. In the process of forming a longitudinal etching groove extending in a third direction Z in the stack structure in the to-be-measured wafer, a longitudinal etching mark in a to-be-measured alignment mark is formed. In the process of forming a transverse etching groove by transversely etching a second material layer in the stack structure based on the longitudinal etching groove, a transverse etching mark in the to-be-measured alignment mark is formed. The depth of the transverse etching groove in the to-be-measured wafer away from the longitudinal etching groove is equal to the depth of the transverse etching mark in the to-be-measured alignment mark away from the longitudinal etching mark. The to-be-measured alignment mark is an alignment mark with a fixed transverse etching depth. The measurement unit 304 measures the to-be-measured alignment mark formed in the to-be-measured wafer to obtain an actual alignment signal of the to-be-measured alignment mark.

[0129] The processing unit 306 determines the transverse etching depth of the to-be-measured wafer based on the actual alignment signal of the to-be-measured alignment mark and the geometric model of the alignment mark according to the vector diffraction theory. The transverse etching depth is the distance of the transverse etching groove away from the longitudinal etching groove in a plane parallel to the substrate 102.

[0130] It can be understood that when the alignment mark includes a plurality of longitudinal etching marks 202 arranged at intervals and extending in a third direction Z perpendicular to the substrate 102, and a transverse etching mark 204 corresponding to each longitudinal etching mark 202 and extending away from the longitudinal etching mark 202 in a direction parallel to the substrate 102 (a direction in a plane of the first direction X and the second direction Y), each longitudinal etching mark 202 and the corresponding transverse etching mark 204 are taken as an integral structure. The measurement unit 304 can select one integral structure in the to-be-measured alignment mark to represent the to-be-measured alignment mark. The actual alignment signal of the integral structure is measured as the actual alignment signal of the to-be-measured alignment mark. In subsequent processes related to the alignment mark (such as the experimental alignment mark, the virtual alignment mark, etc.), the integral structure is selected to represent the alignment mark. The measurement unit 304 can also measure the actual alignment signals of the integral structures in the to-be-measured alignment mark. The processing unit 306 obtains a plurality of intermediate transverse etching depths of the to-be-measured wafer according to the integral structures. The intermediate transverse etching depths correspond to the integral structures one by one. The plurality of intermediate transverse etching depths are processed (such as averaging) to obtain the transverse etching depth of the to-be-measured wafer. The following description is based on the alignment mark including only one integral structure.

[0131] In the above-described measurement device of the transverse etching depth, the measurement unit 304 measures the actual alignment signal of the to-be-measured alignment mark in the to-be-measured wafer. The processing unit 306 determines the transverse etching depth of the to-be-measured wafer according to the actual alignment signal of the to-be-measured alignment mark and the geometric model of the alignment mark. The efficiency of measuring the transverse etching depth of the to-be-measured wafer is improved. Moreover, slicing is not required, and the cost of measuring the transverse etching depth is reduced.

[0132] Figure 14 Fig. 1 is a schematic diagram of a structure of a lateral etching depth measurement device according to some embodiments; Figure 14 In one of the embodiments, the lateral etching depth measurement device further comprises an input unit 308 configured to input the experimental lateral etching depth and the experimental alignment signal of each of the alignment marks with different lateral etching depths formed in the experimental wafer after alignment of the experimental wafer; the modeling unit 302 is further configured to establish a lateral etching depth database according to the experimental lateral etching depth and the experimental alignment signal of each of the alignment marks; wherein the lateral etching depth database is configured to represent the correlation between the lateral etching depth and the alignment signal; and the processing unit 306 is further configured to take the actual alignment signal of the to-be-measured alignment mark in the to-be-measured wafer as an input variable of the lateral etching depth database, and take the output variable of the lateral etching depth database as the lateral etching depth of the to-be-measured wafer. The lateral etching depth database is established according to the experimental lateral etching depth and the experimental alignment signal of the alignment marks with different lateral etching depths formed in the experimental wafer, the deviation between the data in the lateral etching depth database and the real data of the alignment marks is small, and the speed of obtaining the lateral etching depth of the to-be-measured wafer through the actual alignment signal of the to-be-measured alignment mark in the to-be-measured wafer and the lateral etching depth database is fast, and the data accuracy is high.

[0133] Specifically, the experimental wafer comprises a substrate 102 and a stack structure 104 on the surface of the substrate 102, a plurality of alignment marks with different lateral etching depths of lateral etching marks 204 are formed in the experimental wafer, and the experimental lateral etching depth and the experimental alignment signal of each of the alignment marks in the experimental wafer are measured, and then the experimental lateral etching depth and the experimental alignment signal of each of the alignment marks are input to the input unit 308. For example, the lithography machine can be used to align each of the alignment marks in the experimental wafer to obtain the experimental alignment signal of each of the alignment marks in the experimental wafer, and the experimental lateral etching depth of each of the alignment marks in the experimental wafer can be obtained by slicing. The lateral etching depth database is suitable for to-be-measured alignment marks belonging to the same geometric model, and alignment marks of different geometric models correspond to different lateral etching depth databases. It can be understood that the more alignment marks with different lateral etching depths formed in the experimental wafer, the more perfect the lateral etching depth database, and the higher the data accuracy of the lateral etching depth of the to-be-measured wafer obtained according to the lateral etching depth database subsequently. Further, the lateral etching depth of the alignment marks formed in the experimental wafer fluctuates on both sides of the lateral etching depth of the actual product, which facilitates obtaining the lateral etching depth of the to-be-measured wafer according to the lateral etching depth database subsequently.

[0134] In one of the embodiments, the input unit 308 is further configured to input a plurality of different virtual lateral etching depths, and the processing unit 306 is further configured to obtain a virtual alignment signal corresponding to each of the virtual lateral etching depths according to the geometric model of the alignment mark and each of the virtual lateral etching depths, and the modeling unit 302 is further configured to establish the lateral etching depth database according to the experimental lateral etching depth of each of the alignment marks, the experimental alignment signal, and each of the virtual lateral etching depth and the virtual alignment signal corresponding to each of the virtual lateral etching depths.

[0135] Specifically, the input unit 308 is configured to input a plurality of different virtual lateral etching depths, and in an example, a plurality of virtual lateral etching depths are selected between adjacent experimental lateral etching depths, so as to avoid that the process deviation causes the lateral etching depth of the wafer under test to be unable to be obtained according to the lateral etching depth database and the actual alignment signal. The processing unit 306 is configured to obtain a theoretical model of a virtual alignment mark corresponding to each of the virtual lateral etching depths according to each of the virtual lateral etching depths and the geometric model of the alignment mark, and confirm a virtual alignment signal of each of the virtual alignment marks based on the vector diffraction theory and the theoretical model of each of the virtual alignment marks, where the virtual alignment signal is simulation data of the alignment signal of the virtual alignment mark. The modeling unit 302 is configured to establish the lateral etching depth database according to the experimental lateral etching depth of each of the alignment marks, the experimental alignment signal, and each of the virtual lateral etching depth and the virtual alignment signal of each of the virtual alignment marks. The lateral etching depth database can be perfected by setting the virtual alignment mark, and the application range of the lateral etching depth database can be increased.

[0136] In one of the embodiments, the processing unit 306 includes an operation module 402 and a function creating module 404. The operation module 402 is configured to determine a theoretical alignment signal of the alignment mark according to the theoretical lateral etching depth and the geometric model of the alignment mark, and determine a permissible depth range of the lateral etching depth of the wafer under test. The function creating module 404 is configured to establish a lateral etching depth evaluation function according to the theoretical alignment signal of the alignment mark and the actual alignment signal, where the lateral etching depth evaluation function is used to represent the correlation between the theoretical lateral etching depth and the lateral etching depth of the wafer under test. The operation module 402 is further configured to determine the lateral etching depth of the wafer under test according to the lateral etching depth evaluation function within the permissible depth range of the lateral etching depth based on an intelligent algorithm. In the process of confirming the lateral etching depth of the wafer under test, the lateral etching depth and the alignment signal do not need to be collected in advance, and the cost of measuring the lateral etching depth is reduced.

[0137] Specifically, the operation module 402 determines the theoretical alignment signal WQn of the alignment mark corresponding to the theoretical lateral etching depth D2n based on the vector diffraction theory and according to the set theoretical lateral etching depth D2n and the geometric model of the alignment mark. The operation module 402 is also configured to determine the permissible depth range of the lateral etching depth D20 of the wafer under test according to the design value or process experience of the lateral etching depth of the alignment mark under test, and the permissible depth range represents the approximate range of the lateral etching depth D20 of the wafer under test. The function creation module 404 establishes a lateral etching depth evaluation function F according to the theoretical alignment signal WQn of the alignment mark corresponding to the theoretical lateral etching depth D2n and the actual alignment signal WQ1 of the alignment mark under test, and the lateral etching depth evaluation function F is used to represent the correlation between the theoretical lateral etching depth D2n and the lateral etching depth D20 of the wafer under test. For example, the lateral etching depth evaluation function F = WQn-WQ1. The operation module 402 selects the theoretical lateral etching depth D2n within the permissible depth range of the lateral etching depth D20 based on an intelligent algorithm, and calculates the theoretical alignment signal WQn corresponding to the theoretical lateral etching depth D2n, so that the theoretical lateral etching depth D2n satisfying the preset condition of the lateral etching depth evaluation function F is the lateral etching depth D20 of the wafer under test. For example, the preset condition is that the absolute value of the lateral etching depth evaluation function F is less than or equal to a preset value, for example, the preset value is 0.

[0138] In one embodiment, the number of the alignment marks under test is multiple, and the alignment marks under test are distributed in multiple target positions of the wafer under test. The processing unit 306 is also configured to determine the lateral etching depth of the target position in the wafer under test according to the actual alignment signal of the alignment mark under test in the target position and the geometric model. By forming the alignment marks under test in different target positions of the wafer under test, the lateral etching depths of different target positions in the wafer under test can be determined, and the accuracy of measuring the lateral etching depth is improved.

[0139] Figure 15 For the structure of the evaluation device of the lateral etching process in some embodiments, as shown in Figure 15As shown, in the embodiment, a lateral etching depth measurement device is provided, and the same or corresponding parts of the above-mentioned embodiment of the lateral etching depth measurement method will not be described here. The lateral etching depth measurement device comprises a modeling unit 302, a measurement unit 304, a processing unit 306, and an evaluation unit 310. The modeling unit 302 is configured to establish a geometric model of the alignment mark, the alignment mark comprising a longitudinal etching mark 202 and a lateral etching mark 204, the longitudinal etching mark 202 extending along a third direction Z perpendicular to the substrate 102, and the lateral etching mark 204 extending from the longitudinal etching mark 202 in a direction away from the longitudinal etching mark 202 and parallel to the substrate 102 (a direction in the plane of the first direction X and the second direction Y). The measurement unit 304 is configured to measure actual alignment signals of the to-be-measured alignment marks at different target positions of the to-be-measured wafer subjected to the same lateral etching process. The processing unit 306 is configured to determine the lateral etching depths of the different target positions according to the actual alignment signals of the to-be-measured alignment marks formed at the different target positions of the to-be-measured wafer and the geometric model of the alignment mark. The evaluation unit 310 is configured to perform process evaluation on the lateral etching process of the to-be-measured wafer according to the lateral etching depths of the different target positions.

[0140] Specifically, the evaluation unit 310 performs process evaluation on the lateral etching process of the to-be-measured wafer according to the deviation of the lateral etching depths of the different target positions. For example, when the deviation of the lateral etching depths of the different target positions is less than or equal to a preset deviation, the evaluation unit 310 determines that the lateral etching process of the to-be-measured wafer meets the process requirement. When the deviation of the lateral etching depths of the different target positions is greater than the preset deviation, the evaluation unit 310 determines that the lateral etching process of the to-be-measured wafer does not meet the process requirement.

[0141] In the above-mentioned evaluation device of the lateral etching process, the measurement unit 304 measures the actual alignment signals of the to-be-measured alignment marks at different target positions of the to-be-measured wafer subjected to the same lateral etching process, the processing unit 306 determines the lateral etching depths of the different target positions according to the actual alignment signals of the to-be-measured alignment marks formed at the different target positions of the to-be-measured wafer and the geometric model of the alignment mark, and the evaluation unit 310 performs process evaluation on the lateral etching process according to the lateral etching depths of the different target positions. Therefore, the efficiency of evaluating the lateral etching process is improved, and slicing is not required, thereby reducing the cost of evaluating the lateral etching process.

[0142] The present disclosure further provides a computer device comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the above-mentioned lateral etching depth measurement method or the steps of the above-mentioned process evaluation method of the lateral etching process when executing the computer program.

[0143] The present disclosure also provides a computer readable storage medium having stored thereon a computer program, which, when executed by a processor, implements the steps of the lateral etching depth measurement method or the process evaluation method of the lateral etching process according to any one of the above.

[0144] The specific limitations of the lateral etching depth measurement device can refer to the limitations of the lateral etching depth measurement method described above, which will not be repeated here. Each unit in the above lateral etching depth measurement device can be implemented by software, hardware, and a combination thereof. The above units can be embedded in or independent of the processor in the computer device in hardware form, or stored in the memory of the computer device in software form, so that the processor invokes and executes the corresponding operations of each module. It should be noted that the division of units in the embodiments of the present application is illustrative, and is only a logical functional division. In actual implementation, there can be another division method.

[0145] The present disclosure also provides a computer device comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the lateral etching depth measurement method or the process evaluation method of the lateral etching process according to any one of the above when executing the computer program.

[0146] The present disclosure also provides a computer readable storage medium having stored thereon a computer program, which, when executed by a processor, implements the steps of the lateral etching depth measurement method or the process evaluation method of the lateral etching process according to any one of the above.

[0147] A person of ordinary skill in the art can understand that all or part of the above-mentioned embodiment methods can be completed by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer readable storage medium. When the computer program is executed, it can include the processes of the above-mentioned embodiments. Any reference to memory, storage, database or other medium used in the embodiments provided by the present application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory or optical memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration but not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM).

[0148] The technical features of the above-described embodiments can be combined in any manner. For the sake of brevity, not all possible combinations are described, however, any combination of the technical features is considered to be within the scope of the present specification.

[0149] The above-described embodiments are merely illustrative of several embodiments of the present application, and the description is relatively specific and detailed, but should not be construed as limiting the scope of the patent application. It should be noted that for those skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are all within the scope of the present application. Therefore, the scope of the patent of the present application should be subject to the appended claims.

Claims

1. A method for measuring lateral etching depth, characterized in that, include: A geometric model of alignment marks is established, the alignment marks including longitudinal etching marks and lateral etching marks, the longitudinal etching marks extending in a direction perpendicular to the substrate, and the lateral etching marks extending from the longitudinal etching marks in a direction away from the longitudinal etching marks and parallel to the substrate; Acquire the actual alignment signal of the alignment mark to be tested in the wafer under test; The lateral etching depth of the wafer under test is determined based on the actual alignment signal and the geometric model.

2. The method for measuring lateral etching depth according to claim 1, characterized in that, Determining the lateral etching depth of the wafer under test based on the actual alignment signal and the geometric model includes: Multiple alignment marks with different lateral etching depths are formed in the experimental wafer, and the experimental lateral etching depth and experimental alignment signal of each alignment mark are measured. A lateral etching depth database is established based on the experimental lateral etching depth of each alignment mark and the experimental alignment signal; wherein, the lateral etching depth database is used to characterize the correlation between the lateral etching depth and the alignment signal; The actual alignment signal of the alignment mark to be tested in the wafer under test is used as the input variable of the lateral etching depth database, and the output variable of the lateral etching depth database corresponds to the lateral etching depth of the wafer under test.

3. The method for measuring lateral etching depth according to claim 2, characterized in that, Before establishing the lateral etching depth database based on the experimental lateral etching depth and the experimental alignment signal, the following steps are included: Establish several virtual alignment marks with different virtual lateral etching depths; Based on the virtual lateral etching depth and the geometric model, determine the virtual alignment signal for each virtual alignment mark; The step of establishing a lateral etching depth database based on the experimental lateral etching depth of each alignment mark and the experimental alignment signal includes: A lateral etching depth database is established based on the experimental lateral etching depth and experimental alignment signal of each alignment mark, and the virtual lateral etching depth and virtual alignment signal of each virtual alignment mark.

4. The method for measuring lateral etching depth according to claim 1, characterized in that, Determining the lateral etching depth of the wafer under test based on the actual alignment signal and the geometric model includes: Based on the theoretical lateral etching depth and the geometric model of the alignment mark, the theoretical alignment signal of the alignment mark is determined; A lateral etching depth evaluation function is established based on the theoretical alignment signal of the alignment mark and the actual alignment signal of the alignment mark under test; wherein, the lateral etching depth evaluation function is used to characterize the correlation between the theoretical lateral etching depth and the lateral etching depth of the wafer under test. Determine the permissible depth range of the lateral etching depth of the wafer under test; Based on an intelligent algorithm, the lateral etching depth of the wafer under test is determined according to the lateral etching depth evaluation function within the permissible depth range of the lateral etching depth.

5. The method for measuring the lateral etching depth according to any one of claims 1-4, characterized in that, The number of alignment marks to be tested in the wafer under test is multiple, and they are distributed at multiple target locations on the wafer under test. Determining the lateral etching depth of the wafer under test based on the actual alignment signal and the geometric model further includes: Based on the actual alignment signal of the alignment mark to be tested at the target location and the geometric model, the lateral etching depth at the target location in the wafer to be tested is determined.

6. A process evaluation method for lateral etching, characterized in that, include: Using the lateral etching depth measurement method as described in any one of claims 1-5, the lateral etching depth at different target positions is confirmed based on the actual alignment signal and geometric model of the alignment mark formed at different target positions in the wafer under test by the same lateral etching process. Based on the lateral etching depth at each target location, the lateral etching process of the wafer under test is evaluated.

7. A device for measuring lateral etching depth, characterized in that, include: A modeling unit is used to establish a geometric model of alignment marks, which include longitudinal etching marks and transverse etching marks. The longitudinal etching marks extend in a direction perpendicular to the substrate, and the transverse etching marks extend from the longitudinal etching marks in a direction away from the longitudinal etching marks and parallel to the substrate. The measurement unit is used to measure the actual alignment signal of the alignment mark to be measured in the wafer under test; The processing unit is used to determine the lateral etching depth of the wafer under test based on the actual alignment signal and the geometric model.

8. The measuring device for lateral etching depth according to claim 7, characterized in that, Also includes: The input unit is used to input the experimental lateral etching depth and experimental alignment signal of each alignment mark obtained after measuring multiple alignment marks with different lateral etching depths formed in the experimental wafer. The modeling unit is also used to establish a lateral etching depth database based on the experimental lateral etching depth and experimental alignment signal of each alignment mark; wherein, the lateral etching depth database is used to characterize the correlation between the lateral etching depth and the alignment signal; The processing unit is further configured to use the actual alignment signal of the alignment mark to be tested in the wafer under test as the input variable of the lateral etching depth database, and use the output variable of the lateral etching depth database as the lateral etching depth of the wafer under test.

9. The measuring device for lateral etching depth according to claim 7, characterized in that, The input unit is further configured to input multiple different virtual lateral etching depths, and the processing unit is further configured to obtain a virtual alignment signal corresponding to each virtual lateral etching depth based on the geometric model and each virtual lateral etching depth. The modeling unit is further configured to establish the lateral etching depth database based on the experimental lateral etching depth and experimental alignment signal of each alignment mark, as well as each virtual lateral etching depth and the virtual alignment signal corresponding to each virtual lateral etching depth.

10. The measuring device for lateral etching depth according to claim 6, characterized in that, The processing unit includes: The calculation module is used to determine the theoretical alignment signal of the alignment mark based on the theoretical lateral etching depth and the geometric model of the alignment mark. The calculation module is also used to determine the permissible depth range of the lateral etching depth of the wafer under test. The function creation module is used to establish a lateral etching depth evaluation function based on the theoretical alignment signal and the actual alignment signal of the alignment mark; wherein, the lateral etching depth evaluation function is used to characterize the correlation between the theoretical lateral etching depth and the lateral etching depth of the wafer under test; The computing module is also used to determine the lateral etching depth of the wafer under test based on an intelligent algorithm, within the permissible depth range of the lateral etching depth, according to the lateral etching depth evaluation function.

11. The measuring device for lateral etching depth according to any one of claims 6-10, characterized in that, The number of alignment marks to be tested is multiple and they are distributed at multiple target positions on the wafer to be tested. The processing unit is also used to determine the lateral etching depth of the target position in the wafer to be tested based on the actual alignment signal of the alignment mark to be tested at the target position and the geometric model.

12. An evaluation apparatus for a lateral etching process, characterized in that, include: The transverse etching depth measuring device as described in any one of claims 6-11, wherein the measuring unit is used to measure the actual alignment signal of the alignment mark to be measured at different target positions in the wafer under test for the same transverse etching process, and the processing unit is further used to confirm the transverse etching depth at different target positions based on the actual alignment signal of the alignment mark to be measured formed at different target positions in the wafer under test and the geometric model of the alignment mark. The evaluation unit is used to evaluate the lateral etching process of the wafer under test based on the lateral etching depth at each target location.

13. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method for measuring the lateral etching depth as described in any one of claims 1 to 5, or the steps of the method for evaluating the lateral etching process as described in claim 6.

14. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the method for measuring the lateral etching depth as described in any one of claims 1 to 5, or the steps of the method for evaluating the lateral etching process as described in claim 6.

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