Electrostatic chuck with sealing surface

Abstract

Apparatuses and systems for a pedestal are provided. An exemplary base may have a body having an upper annular sealing surface, the sealing surface being flat, perpendicular to a vertical central axis of the body, and having a radial thickness; a lower recess surface offset from the upper annular sealing surface; and a plurality of microcontact regions (MCAs) protruding from the recess surface, each MCA having a top surface offset from the recess surface by a second distance; and one or more electrodes within the body. The upper annular sealing surface may be configured to support an outer edge of a semiconductor substrate when the semiconductor substrate is supported by the susceptor, and the upper annular sealing surface and the top of the MCA may be configured to support the semiconductor substrate when the susceptor supports the semiconductor substrate.

Description

This application is a continuation-in-part of the patent application with application number 201980024665.7, filing date 4 April 2019, applicant Lam Research Corporation, and invention entitled “Electrostatic Chuck with Sealing Surface”. INCORPORATED BY REFERENCE

[0001] The PCT application table is filed with the present specification as part of the application. Each of the applications from which this application claims benefit or priority, as identified in the concurrently filed PCT application table, is incorporated by reference in its entirety and for all purposes. BACKGROUND

[0002] During semiconductor processing operations, substrates are typically supported on a susceptor within a processing chamber. SUMMARY

[0003] The systems, methods, and devices of the disclosure each have several innovative aspects, no single one of which is solely responsible for the desirable attributes disclosed herein. At least the following implementations make possible the realization of the benefits and / or results described herein, though further implementations can be evident from the discussion herein or can be learned by practice thereof.

[0004] In some embodiments, a susceptor is provided. The susceptor can include a body comprising: an upper annular sealing surface that is planar, perpendicular to a vertical central axis of the body and having a radial thickness; a lower recessed surface offset from the upper annular sealing surface by a first distance; a plurality of micro-contact areas (MCAs) protruding from the lower recessed surface, each MCA having a top surface that is offset from the lower recessed surface by a second distance that is less than or equal to the first distance; and one or more electrodes within the body. The upper annular sealing surface can be configured to support an outer edge of a semiconductor substrate when the semiconductor substrate is supported by the susceptor, the upper annular sealing surface and the top surfaces of the MCAs can be configured to support the semiconductor substrate when the susceptor supports the semiconductor substrate, and the one or more electrodes are configured to be electrically connected to a radio frequency (RF) power source, an electrical ground, or a direct current (DC) power source.

[0005] In some embodiments, the one or more electrodes can be electrostatic chucking electrodes, and the one or more electrostatic chucking electrodes can be configured to provide an electrostatic chucking force on the semiconductor substrate when the semiconductor substrate is supported by the susceptor and when the one or more electrostatic chucking electrodes are powered by the DC power source.

[0006] In some embodiments, a seal can be formed between the upper annular sealing surface and the semiconductor substrate when the semiconductor substrate is supported by the susceptor and when the one or more electrostatic clamping electrodes provide an electrostatic clamping force on the semiconductor substrate.

[0007] In some embodiments, the one or more electrodes can be configured to be electrically connected with, or receive RF power from, the RF power source.

[0008] In some embodiments, the upper annular sealing surface can have an inner radius that is less than the radius of the semiconductor substrate and an outer radius that is greater than the radius of the semiconductor substrate.

[0009] In some such embodiments, the inner radius can be about 142 millimeters.

[0010] In some other such embodiments, the outer radius can be about 150 millimeters.

[0011] In some embodiments, the radial thickness can be less than or equal to about 25 millimeters.

[0012] In some such embodiments, the radial thickness can be less than or equal to about 15 millimeters.

[0013] In some embodiments, the upper annular sealing surface and the top surface of the MCA can be coplanar, and the first distance is equal to the second distance.

[0014] In some such embodiments, the first distance and the second distance can be equal to or between 0.0127 millimeters and 0.0381 millimeters.

[0015] In some other such embodiments, the first distance and the second distance can be 0.0254 millimeters.

[0016] In some embodiments, the first distance can be greater than the second distance.

[0017] In some such embodiments, the first distance and the second distance can be equal to or between 0.0127 millimeters and 0.0381 millimeters.

[0018] In some embodiments, the plurality of MCAs can include more than 2,000 MCAs.

[0019] In some such embodiments, the plurality of MCAs can include more than 4,000 MCAs.

[0020] In some such embodiments, substantially all of the MCAs can be equally spaced from one another.

[0021] In some other such embodiments, substantially all of the MCAs can be spaced apart from each other by 3.9 millimeters.

[0022] In some such embodiments, the plurality of MCAs can be divided into a plurality of sub-arrangements, and the MCAs in each sub-arrangement can be positioned on the lower recess surface in a triangular pattern, a square pattern, a symmetrical pattern, a radial arrangement, or a hexagonal pattern.

[0023] In some embodiments, the lower recessed surface can have a recessed surface area, each MCA top surface can have a top surface area, and the sum of all top surface areas of the MCAs in the plurality of MCAs can be less than or equal to 3% of the recess surface area.

[0024] In some embodiments, each MCA can be a cylinder having a flat top surface area.

[0025] In some such embodiments, the radius of each MCA can be about 0.35 millimeters.

[0026] In some embodiments, the upper annular sealing surface can have a roughness of between about 0.8128 micrometers and about 0.2032 micrometers.

[0027] In some embodiments, each MCA top surface can have a roughness of between about 0.8128 micrometers and about 0.2032 micrometers.

[0028] In some embodiments, the upper annular sealing surface can have a flatness with a maximum range of 0.0254 millimeters.

[0029] In some embodiments, each MCA top surface can have a flatness with a maximum range of 0.0254 millimeters.

[0030] In some embodiments, the body can comprise a ceramic.

[0031] In some embodiments, the body can comprise a metal or metal alloy, and the body can be coated with a ceramic.

[0032] In some embodiments, a semiconductor processing system can be included. The system can include: a processing chamber; one or more processing stations in the processing chamber; an electrostatic chuck in each of the one or more processing stations. Each electrostatic chuck can have a body including: an upper annular sealing surface that is planar, perpendicular to a vertical center axis of the body, and has a radial thickness; a lower recessed surface offset from the upper annular sealing surface by a first distance; a plurality of micro contact areas (MCAs) protruding from the lower recessed surface, each MCA having a top surface that is offset from the lower recessed surface by a second distance that is less than or equal to the first distance; and one or more electrostatic clamping electrodes within the body. The upper annular sealing surface can be configured to support an outer edge of a semiconductor substrate when the semiconductor substrate is supported by the electrostatic chuck, the upper annular sealing surface and the top surfaces of the MCAs can be configured to support the semiconductor substrate when the electrostatic chuck supports the semiconductor substrate, and the one or more electrostatic clamping electrodes can be configured to provide an electrostatic clamping force on the semiconductor substrate when the semiconductor substrate is supported by the electrostatic chuck and when the one or more electrostatic clamping electrodes are powered by a DC power source. The system can further include: the DC power source electrically connected to the electrostatic clamping electrodes; and a controller having a memory and a processor, the memory storing instructions configured to cause the DC power source to power the electrostatic clamping electrodes to provide the electrostatic clamping force on the semiconductor substrate when the semiconductor substrate is supported by the electrostatic chuck.

[0033] In some embodiments, the system can further include an end effector configured to position a semiconductor substrate on each of the electrostatic chucks. The memory can further store instructions configured to cause the end effector to position the semiconductor substrate on each of the electrostatic chucks, and after positioning the semiconductor substrate on one of the electrostatic chucks, cause the DC power source to provide power to the electrostatic clamping electrodes in the one electrostatic chuck to provide the electrostatic clamping force on the semiconductor substrate.

[0034] In some embodiments, the memory can further store instructions configured to cause the DC power source to provide power to the electrostatic clamping electrodes of one of the electrostatic chucks to provide a lower electrostatic clamping force on the semiconductor substrate when the end effector positions the semiconductor substrate on the one of the electrostatic chucks.

[0035] In some embodiments, a semiconductor processing system can be included. The system can include: a processing chamber; one or more processing stations in the processing chamber; a pedestal in each of the one or more processing stations. Each pedestal can have a body including: an upper annular sealing surface that is planar, perpendicular to a vertical center axis of the body, and has a radial thickness; a lower recessed surface that is offset from the upper annular sealing surface by a first distance; a plurality of micro contact areas (MCAs) protruding from the lower recessed surface, each MCA having a top surface that is offset from the lower recessed surface by a second distance that is less than or equal to the first distance; and one or more electrodes within the body. The upper annular sealing surface can be configured to support an outer edge of a semiconductor substrate when the semiconductor substrate is supported by the pedestal, the upper annular sealing surface and the top surfaces of the MCAs can be configured to support the semiconductor substrate when the pedestal supports the semiconductor substrate, and the one or more electrodes are configured to be electrically connected to a radio frequency (RF) power source. The system can further include: a showerhead above the pedestal that is electrically connected to electrical ground; the RF power source that is electrically connected to the one or more electrodes; and a controller having a memory and a processor, the memory storing instructions configured to cause the RF power source to provide an RF voltage to the one or more electrodes so as to generate a plasma between the pedestal and the showerhead.

[0036] In some embodiments, an electrostatic clamping force can not be applied to the substrate when the plasma is generated between the pedestal and the showerhead.

[0037] In some embodiments, the system can further include a direct current (DC) power source. The DC power source can be electrically connected to the one or more electrodes, the one or more electrodes can be configured to provide an electrostatic clamping force on the semiconductor substrate when the semiconductor substrate is supported by the pedestal and when the one or more electrodes are powered by the DC power source, and the memory can further store instructions configured to cause the DC power source to power the one or more electrodes so as to provide the electrostatic clamping force on the semiconductor substrate when the semiconductor substrate is supported by the pedestal. BRIEF DESCRIPTION OF DRAWINGS

[0038] Figure 1 A substrate processing apparatus for depositing films on semiconductor substrates using any number of processes is depicted.

[0039] Figure 2 Implementations of a multi-station processing tool are described.

[0040] Figure 3 A top view of an exemplary electrostatic chuck (ESC) is depicted.

[0041] Figure 4A And 4BIllustrative cross-sectional slices of the ESC body of Figure 3 are depicted; these figures have an exaggerated scale along the vertical axis.

[0042] Figure 5A and 5B depicts a cross-sectional view of an exemplary substrate supported by an annular ring, Figure 5C depicts a cross-sectional view of an exemplary substrate supported by three contact areas, Figure 5A are depicted; these figures have an exaggerated scale along the vertical axis.

[0043] Figure 6A depicts an illustrative cross-sectional slice of the ESC body of Figure 4A as well as the MCA feature.

[0044] Figure 6B depicts a substrate on a representative ESC of Figure 6A .

[0045] Figure 7 depicts an oblique-angle detail view of a portion of the ESC in Figure 3 .

[0046] Figure 8 depicts a detailed view of the ESC body of Figure 3 as indicated by the circular boundary in Figure 3 .

[0047] Figure 9 depicts results of a first deposition experiment.

[0048] Figure 10 depicts the results of measurements of backside deposition thickness on a number of unchucked substrates on the susceptor of a processing chamber as a function of chamber cumulative amount.

[0049] Figure 11 depicts the results of measurements of backside deposition thickness on a number of chucked substrates on the ESC in a processing chamber as a function of chamber cumulative amount.

[0050] Figure 12 depicts a region of mathematical modeling of deposition on the backside of a substrate. DETAILED DESCRIPTION

[0051] In the following description, numerous specific details are set forth to provide a thorough understanding of the presented concepts. The presented concepts can be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail so as not to unnecessarily obscure the presented concepts. While some concepts will be described in conjunction with specific embodiments thereof, it will be understood that these embodiments are not intended to be limiting. In some types of semiconductor processing, a wafer or substrate is processed within a processing chamber, which can have a pedestal or support structure on which the wafer can be placed during processing. In this application, the terms "semiconductor wafer," "wafer," "substrate," "wafer substrate," and "partially processed integrated circuit" are used interchangeably. Those skilled in the art will understand that the term "partially processed integrated circuit" can refer to a silicon wafer during any of the many stages of processing an integrated circuit thereon. Wafers or substrates used in the semiconductor equipment industry typically have a diameter of 200 mm, or 300 mm, or 450 mm. The following detailed description assumes that the present application is implemented for use with such wafers. However, the present application is not so limited. The workpiece can have various shapes, sizes, and materials. In addition to semiconductor wafers, other workpieces that can utilize the present application include various articles of manufacture such as printed circuit boards, magnetic recording media, magnetic recording sensors, mirrors, optical elements, micro-mechanical devices, etc.

[0052] Semiconductor processing can include depositing one or more layers of film on a substrate, such as chemical vapor deposition ("CVD"), plasma enhanced CVD ("PECVD"), atomic layer deposition ("ALD"), low pressure CVD, ultra-high CVD, physical vapor deposition ("PVD"), and conformal film deposition ("CFD"). For example, some CVD processes can deposit a film on a wafer surface by flowing one or more gaseous reactants into a reactor that forms a film precursor and byproducts. The precursors are transported to the wafer surface, where they are absorbed by the wafer, diffuse into the wafer, and deposit on the wafer by a chemical reaction that also produces byproducts that are removed from the surface and the reactor. For another example, certain deposition processes involve multiple film deposition cycles, each of which produces a "discrete" film thickness. ALD is one such film deposition method, but any technique that forms thin film layers and is used in a repetitive sequence can be considered to involve multiple deposition cycles.

[0053] As device and feature sizes continue to shrink in the semiconductor industry, and as 3D device structures become more prevalent in integrated circuit (IC) designs, the ability to deposit thin conformal films (films of material having uniform thickness with respect to the shape of the underlying structure, even if non-planar) continues to become important. ALD is a film deposition technique that is well suited for the deposition of conformal films due to the fact that a single cycle of ALD deposits only a single thin layer of material, the thickness of which is limited by the amount of one or more film precursor reactants that can be adsorbed onto the substrate surface prior to the film formation chemistry itself (i.e., forming an adsorption-limited layer). Multiple "ALD cycles" can then be used to accumulate a film of the desired thickness, and because each layer is thin and conformal, the resulting film substantially conforms to the shape of the underlying device structure. In certain embodiments, each ALD cycle includes the following steps: 1. Exposing a substrate surface to a first precursor. 2. Purging the reaction chamber in which the substrate is positioned. 3. Activating the reaction of the substrate surface, typically using plasma and / or a second precursor. 4. Purging the reaction chamber in which the substrate is positioned.

[0054] Figure 1 A substrate processing apparatus for depositing films on a semiconductor substrate using any number of processes is shown. Figure 1 The apparatus 100 of FIG. 1 has a single processing chamber 110 having a single substrate holder 118 (e.g., a susceptor or ESC) in an interior volume space that can be maintained under vacuum by a vacuum pump 130. A gas delivery system 102 and a showerhead 104 are coupled to the chamber for delivery of, for example, film precursors, carrier and / or purge gases and / or process gases, secondary reactants, etc. Figure 1 Also shown are facilities for generating plasma within the processing chamber. Figure 1 The apparatus shown schematically in FIG. 1 is generally used to perform ALD, but it can be adapted to perform other film deposition operations, such as conventional CVD, particularly plasma-enhanced CVD.

[0055] For simplicity, the processing apparatus 100 is described as a standalone processing station having a processing chamber body 110 for maintaining a low pressure environment. However, it should be understood that multiple processing stations as described herein can be included in a common processing tool environment, e.g., within a common reaction chamber. For example, Figure 2 Implementations of multi-station processing tools are depicted and discussed in further detail below. Moreover, it should be understood that in some embodiments, one or more hardware parameters of the processing apparatus 100, including those discussed in detail herein, can be adjusted programmatically by one or more system controllers.

[0056] The processing station 100 is in fluid communication with a gas delivery system 102 to deliver process gases, which can include liquids and / or gases, to the distribution showerhead 104. The gas delivery system 102 includes a mixing vessel 106 for mixing and / or conditioning process gases for delivery to the showerhead 104. One or more mixing vessel inlet valves 108 and 108A can control the introduction of process gases to the mixing vessel 106.

[0057] Some reactants can be stored in liquid form prior to vaporization and then delivered to the processing chamber 110. Figure 1 Implementations include a vaporization point 112 for vaporizing liquid reactants that will be supplied to the mixing vessel 106. In some implementations, the vaporization point 112 can be a heated liquid injection module. In some other implementations, the vaporization point 112 can be a heated vaporizer. In other implementations, the vaporization point 112 can be removed from the processing station. In some implementations, a liquid flow controller (LFC) can be provided upstream of the vaporization point 112 to control the mass flow of liquid for vaporization and delivery to the processing chamber 110.

[0058] The showerhead 104 distributes process gases and / or reactants (e.g., film precursors) to the substrate 114 at the processing station, the flow of which is controlled by one or more valves upstream of the showerhead (e.g., valves 108, 108A, and 116). In some implementations, the process gases and / or reactants can be delivered to the processing chamber 110 in a pulsed manner. Figure 1 In the illustrated implementation, the substrate 114 is positioned below the showerhead 104 and is shown as being placed on an ESC 118. The showerhead 104 can have any suitable shape and can have any suitable number and arrangement of ports for distributing process gases to the substrate 114. In some implementations with two or more stations, the gas delivery system 102 includes valves or other flow control structures upstream of the showerhead that can independently control the flow of process gases and / or reactants to each station, such that gas can be flowed to one station but not another. Further, the gas delivery system 102 can be configured to independently control the process gases and / or reactants delivered to each station in a multi-station apparatus such that the gas composition provided to different stations is different; for example, the partial pressure of a gas component can be varied between stations at the same time.

[0059] A volume space 120 is positioned below the showerhead 104. In some implementations, the ESC 118 can be raised or lowered to expose the substrate 114 to the volume space 120 and / or to change the volume of the volume space 120. Optionally, the ESC 118 can be lowered and / or raised to adjust the process pressure, reactant concentration, etc. within the volume space 120 during portions of a deposition process.

[0060] In some implementations, the processing station 100 can include a gas analyzer 122 to analyze the composition of the process gases and / or reactants delivered to the processing chamber 110. The gas analyzer 122 can be positioned upstream of the processing station 100 to analyze the composition of the process gases and / or reactants prior to delivery to the processing chamber 110. In some implementations, the gas analyzer 122 can be positioned downstream of the processing station 100 to analyze the composition of the process gases and / or reactants after delivery to the processing chamber 110. Figure 1In some implementations, the plasma energy is controlled by controlling one or more of the process station pressure, gas concentrations, RF source power, RF source frequency, and plasma power pulse timing, e.g., via a system controller having appropriate machine readable instructions and / or control logic. For example, the RF power source 122 and matching network 124 can be operated at any suitable power to form a plasma having a desired composition of radical species. Likewise, the RF power source 122 can provide RF power having any suitable frequency and power. The apparatus 100 also includes a DC power source 126 configured to provide direct current to the ESC 118 in order to generate and provide an electrostatic clamping force to the ESC 118 and substrate 114. The ESC 118 can also have one or more temperature control elements 128 configured to heat and / or cool the substrate 114.

[0061] In some implementations, the apparatus is controlled with appropriate hardware and / or appropriate machine readable instructions in a system controller, which can provide control instructions via a sequence of input / output control (IOC) instructions. In an example, instructions for setting plasma conditions for plasma ignition or maintenance are provided in the form of a plasma activation recipe of a process recipe. In some cases, process recipes can be sequenced so that all instructions for a process are executed concurrently with the process. In some implementations, instructions for setting one or more plasma parameters can be included in a recipe prior to a plasma process. For example, a first recipe can include instructions for setting flow rates of an inert gas (e.g., helium) and / or a reactive gas, instructions for setting a plasma generator to a power setpoint, and a time delay instruction for the first recipe. A second, subsequent recipe can include instructions for enabling the plasma generator and a time delay instruction for the second recipe. A third recipe can include instructions for disabling the plasma generator and a time delay instruction for the third recipe. It will be appreciated that these recipes can be further subdivided and / or iterated in any suitable manner within the scope of the present disclosure.

[0062] As noted above, one or more process stations can be included in a multi-station substrate processing tool. Figure 2 An exemplary multi-station substrate processing apparatus is shown. With respect to facility costs, operating expenses, and increased production volume, it can be beneficial to use a multi-station substrate processing apparatus such as Figure 2The multi-station processing equipment shown achieves various efficiencies. For example, a single vacuum pump can be used to create a single high-vacuum environment for all four processing stations by venting waste process gases, etc., from all four processing stations. Depending on the implementation, each processing station may have its own dedicated nozzle for gas delivery, but may share the same gas delivery system. Similarly, some components of the plasma generator equipment may be shared between processing stations (e.g., power supply), but depending on the implementation, some aspects may be specific to the processing station (e.g., if nozzles are used to apply the potential for plasma generation). Again, it should be understood that this efficiency can be achieved more or less by using more or fewer processing stations in each processing chamber (e.g., 2, 3, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, or 16 or more processing stations per reaction chamber).

[0063] Figure 2 The substrate processing apparatus 200 employs a single substrate processing chamber 210 accommodating multiple substrate processing stations, each of which can be used to perform processing operations on a substrate held in a wafer holder (e.g., a pedestal or ESC) at that processing station. In this particular implementation, the multi-station substrate processing apparatus 200 is shown with four processing stations 231, 232, 233, and 234. Other similar multi-station processing apparatuses may have more or fewer processing stations, depending on the implementation and, for example, the desired level of parallel wafer processing, size / space constraints, cost constraints, etc. Figure 2 The substrate processor robot 236 and controller 238 are also shown.

[0064] like Figure 2 As shown, the multi-station processing tool 200 has a substrate loading port 240 and a robot 236 configured to move a substrate from a cassette loaded via a boat 242 through the atmospheric port 240 into a processing chamber 210 and onto one of four stations 231, 232, 233 or 234.

[0065] Figure 2 The depicted processing chamber 210 provides four processing stations 231, 232, 233, and 234. The RF power is generated at an RF power system 222 and distributed to each of stations 231, 232, 233, and 234; similarly, a DC power supply 226 is distributed to each station. The RF power system may include one or more RF power sources, such as high-frequency (HFRF) and low-frequency (LFRF) sources, impedance matching modules, and filters. In some embodiments, the power supply may be limited to only the high-frequency or low-frequency source. The distribution system of the RF power system may be symmetrical about the reactor and may have high impedance. This symmetry and impedance result in approximately equal amounts of power being delivered to each station.

[0066] Figure 2 Implementations of a system controller 238 for controlling process conditions and hardware states of the processing tool 200 and its processing stations are also depicted. The system controller 238 can include one or more memory devices 244, one or more mass storage devices 246, and one or more processors 248. The processors 248 can include one or more CPUs, ASICs, general purpose computers and / or special purpose computers, one or more analog and / or digital input / output connections, one or more stepper motor controller boards, etc.

[0067] The system controller 238 can execute machine-readable system control instructions 250 on the processors 248, which in some implementations are loaded into the memory devices 244 from the mass storage devices 246. The system control instructions 250 can include instructions for controlling timing, mixtures of gaseous and liquid reactants, chamber and / or station pressure, chamber and / or station temperature, wafer temperature, target power levels, RF power levels, RF exposure time, duration of DC power and clamped substrate, substrate pedestal, chuck and / or pedestal position, plasma formation in each station (which as noted above can include independent plasma formation in one or more stations), flow of gaseous and liquid reactants (which as noted above can include independent flow for one or more stations), and other parameters of the particular processes performed by the processing tool 200. These processes can include various types of processes including, but not limited to, processes involving deposition of films on substrates. The system control instructions 258 can be configured in any suitable manner.

[0068] In various aspects of processing, it can be desirable to hold the wafer in a fixed position, as substrate movement during processing can have adverse effects on the processing of the substrate, such as deposition layers, and can have adverse effects on the performance of semiconductor processing tools that index and move substrates.

[0069] Wafers can be held in place within a semiconductor processing chamber by an electrostatic chuck (ESC). Some ESCs hold wafers (which can be charged with static electricity as a result of processing operations) in place by applying a single direct current (“DC”) voltage to one or more clamping electrodes in the ESC, causing the clamping electrodes and wafer to act as a capacitive circuit; the capacitive circuit can be completed by the presence of a plasma within the chamber. The clamping electrodes are typically thin, planar structures that are parallel to the entire plane of the wafer, and typically extend across an area corresponding to the size of the wafer. The electrostatic forces resulting from the capacitive effect provide the clamping force. Such a configuration can be referred to as “uni-polar.”

[0070] An ESC can also be used in a chamber that does not produce a plasma environment during processing. In such implementations, the capacitive circuit cannot be completed by the plasma, and the ESC electrodes can instead include one or more cathodes and one or more anodes. The anodes and cathodes can occupy different areas of the wafer-facing side of the ESC, for example, the anodes and cathodes occupy opposite semi-circular areas below the wafer, or the anodes or cathodes are arranged as a central circular electrode, while a concentric outer electrode arranged below the wafer acts as the anode. The anodes and cathodes in such an ESC are electrically isolated from one another in the ESC, but when a wafer is placed on the ESC, the wafer will complete two capacitive circuits - one capacitive circuit is: the anode on the wafer is the cathode of the ESC, and the other capacitive circuit is: the wafer is the cathode of the ESC anode.

[0071] An ESC can have a dielectric layer or other insulator interposed between the clamping electrode and the wafer; the dielectric layer or insulator serves to prevent a short circuit between the clamping electrode and the other half of the capacitive circuit (i.e., the wafer), and defines the gap that controls the capacitive properties of the capacitive circuit formed by the ESC and the wafer. The electrode is often embedded in a dielectric or insulating material to protect the electrode from exposure to the processing environment.

[0072] Certain ESCs can also include lift pin holes that allow lift pins to extend through the ESC and lift the wafer off the ESC. The ESC lift pins can be configured to retract completely into the ESC lift pin holes, such that in one position the ESC lift pins do not extend beyond the ESC. These lift pins and their corresponding holes, among other things, enable an end effector of a robot or other mechanical device to place a wafer onto the ESC and / or remove a wafer from the ESC without contacting and / or disturbing the ESC.

[0073] Many current ESCs and wafer support pedestals (e.g., pedestals without clamping force) allow for unintentional deposition on the backside of the wafer, which is undesirable for a variety of reasons. For example, during deposition in a processing chamber, a film can be deposited not only on the frontside of the wafer, but also on the backside of the wafer. In conformal deposition techniques, such as in atomic layer deposition (ALD), a film can be deposited layer-by-layer through successive dosing and activation steps. In many ALD processing chambers, a precursor gas can be directed to the wafer, and the precursor gas can chemisorb onto the surface of the wafer to form a monolayer. Another precursor gas that reacts with the monolayer can be introduced, and a purge gas can be introduced to remove excess precursor and gaseous reaction byproducts. The precursor gases can be pulsed alternately without overlap, and can be repeated as many cycles as necessary to form a film of suitable thickness.

[0074] However, during the deposition process, process gases such as precursor gases in ALD can deposit on wafer surfaces that are not intended for deposition, such as the backside of the wafer. Since ALD is a surface-based deposition process, films will be deposited on any accessible surface in the process chamber. Thus, any gap into the backside of the wafer can allow process gases to flow to the backside. Films on the backside can be created by delivering precursor gases during the dosing step, and reactions of the precursor gases can occur during the activation step. In some implementations, an unwanted film ring as thick as the frontside film at the outer edge of the wafer can form on the backside of the wafer and extend more than 5 mm inward from the outer edge of the wafer.

[0075] One of the disadvantages of this unwanted backside deposition is that it can cause alignment / focus issues in the photolithography process. In order to apply a desired pattern on a target portion of the wafer, various tools in photolithography can be used to properly align and focus on the desired pattern. After the deposition step, if films are deposited on the backside of the wafer, various photolithography tools can need to be readjusted for focus and alignment. This can cause unnecessary photolithography marks in the patterning process, resulting in wafer defects, and increasing the time spent to recalibrate the various photolithography tools.

[0076] The ESC described herein is configured to apply an electrostatic clamping force on the substrate to force the backside of the substrate to press down against the upper annular sealing surface of the ESC in order to prevent or reduce the flow of gases to the underside of the substrate, thereby reducing or practically eliminating deposition on the backside of the substrate. As described above, the nature of conformal deposition causes deposition to occur wherever process gases can flow, including any surface of the substrate that is exposed to these gases. To prevent process gases and other materials from flowing to the bottom surface of the substrate, a seal can be formed between the bottom surface of the substrate and the flat, smooth upper annular sealing surface in an area that begins at the edge of the bottom surface of the substrate and extends radially inward to the vertical center axis of the main body of the ESC. Since the seal occurs at the edge of the substrate, gases and other materials cannot flow underneath the substrate. The application of the downward electrostatic clamping force can help to bring the edge of the bottom surface of the substrate, as well as a portion of the bottom surface of the substrate, into contact with the upper annular sealing surface and form the seal.

[0077] Using an upper annular sealing surface has many advantages over having a continuous planar circular sealing surface equal to or larger than the diameter of the substrate. For example, when placing a substrate on the planar circular surface of an ESC, air (or other gas) can become trapped between the circular surface and the substrate when placing the substrate on the ESC, which can cause the substrate to translate and / or rotate relative to the ESC, i.e., "float" on an air cushion of trapped gas, before the trapped gas can escape, which can result in misregistration errors and wafer defects caused by wafer misalignment. In addition, unexpected deposition of material can occur on the inner portion of the circular surface, which can prevent the substrate from lying in a horizontal plane, which can result in defects on the substrate during deposition. Such deposition on the circular surface can also form or increase the gap between the substrate and the circular surface, which can allow process gas to flow to the bottom surface of the substrate and cause backside deposition, which, as noted above, adversely affects later processing steps and can ultimately result in defects on the substrate, or cause further deposition on the circular surface, which can result in further such problems. Thus, the ESC can use an upper annular ring to avoid problems associated with a circular surface, and in turn utilize a plurality of microcontact area features (hereinafter referred to as "MCAs") disposed within a recess of the ESC body to support the substrate, distribute the downward clamping force pressure sufficiently, and prevent the substrate from being subjected to undesirable deformation and damage.

[0078] The ESCs described herein are configured to apply a downward electrostatic clamping force to the substrate in order to create and maintain a seal between the upper annular sealing surface and the bottom surface of the substrate. Without the application of this downward force, there can still be a small gap between the wafer edge and the annular sealing surface, and process gas can still flow to the bottom surface of the substrate and cause undesirable backside deposition. For example, in some cases, gravity alone can not create a seal sufficient to prevent gas from flowing under the substrate. In some such cases, the substrate edge can bow or the substrate itself can deform, which can allow gas to flow to the backside of the substrate. Furthermore, some processing conditions can be more aggressive than others, e.g., greater aggressiveness occurs at higher temperatures and longer durations, which can create conditions, e.g., that cause the edge of the substrate to bow, allowing gas to flow to the backside of the substrate and cause backside deposition. In particular, in some cases, the wafer can have material deposited on the top surface of the wafer that has a different coefficient of thermal expansion than the wafer itself, and during a temperature change, can cause a tensile stress gradient to form across the thickness of the wafer, causing the wafer to "dish" (show a slight concavity in the top surface), and cause the wafer edge to lift slightly off the pedestal.

[0079] In many existing ESC designs, clamping electrodes are embedded in a dielectric plate, which is then bonded to a metal baseplate of the ESC (sometimes with other layers in between, such as a resistive heater layer); the baseplate often serves as both the overall structural frame of the ESC and as a radio frequency (RF) electrode for generating a plasma environment within the process chamber. The ESC can also include thermal management components for heating and / or cooling the wafer in many semiconductor processing operations. In certain semiconductor processes, the wafer can be heated to a temperature range from about 30°C to 150°C while on the ESC, which can be considered a low temperature range, or to a higher temperature above 150°C, such as 400°C, for certain processing requirements, for which heating elements embedded within the ESC are used.

[0080] Figure 3 A top view of an exemplary ESC 318 is depicted, having a body 360 that includes an upper annular sealing surface 362, a recess 364 represented in semi-transparent cross-hatching, and a plurality of micro-contact areas ("MCAs") 366 disposed within the recess 364. Figure 3 The view is along (i.e., parallel to) the vertical central axis of the ESC, which is also perpendicular to the upper annular sealing surface 362. As in the Figure 3As can be seen, the upper annular sealing surface 362 is a circumferential ring, depicted in shaded detail in the figure to highlight it, which extends completely around the recess 364. The upper annular sealing surface 362 is defined by an inner radius 368 and an outer radius 370, such that the upper annular sealing surface 362 has a radial thickness 372. The upper annular sealing surface 362 is configured to support the bottom side or back edge and portion of the substrate. Therefore, the inner radius 368 can be smaller than the radius of the substrate, while the outer radius 370 can be larger than the radius of the substrate. For example, in some embodiments, the inner radius 370 can be between about 142.9 mm (about 5.625 inches) or about 131.6 mm (about 5.18 inches), while the outer radius can be about 150.6 mm (or about 5.9275 inches). In some such embodiments, the radial thickness of the upper annular sealing surface can be less than or equal to about 25 mm, including about 15.4 mm (about 0.605 inches). In some embodiments, the radial thickness may be configured to support the annular sealing surface and enable it to seal against substrates with diameters of 300 mm, 450 mm, and 200 mm. The upper annular sealing surface 362 is a flat, flat, and smooth surface that at least partially enables a seal to be formed between the back side of the substrate and the upper annular sealing surface. In some embodiments, the smoothness may be equal to or less than 0.8128 micrometers (32 Ra), including approximately 0.2032 micrometers (8 Ra) or less. The maximum range of flatness is 0.0254 mm (0.001 inch), which is the maximum variation of the upper annular sealing surface from its highest to its lowest point, with a local range of 0.00254 mm per 25.4 mm × 25.4 mm square annular sealing surface (0.0001 inch per 1 inch × 1 inch square annular sealing surface).

[0081] like Figure 3 As shown, when viewed along the central vertical axis, the recess 364 of the body 360 is positioned closer to the central vertical axis of the body 360 than the upper annular sealing surface 362. The upper annular sealing surface 362 can be considered to extend around the recess 364 and at least partially constrain the recess 364. The recess 364 may include a lower recess surface 374 and recess side surfaces 376 starting from the boundary of the recess 364. Figure 4A and 4B It shows Figure 3 Illustrative cross-sectional slices of the ESC body. These figures are not drawn to scale and are enlarged on the vertical axis to illustrate the aspects described herein. Figure 4Athe line of sight of the viewer is perpendicular to the vertical center axis 378 and parallel to the upper annular sealing surface 362. Here, a slice of the side of the body 360 is shown, which includes the lower recess surface 374, the recess side surface 376, the upper annular sealing surface 362; the MCA is not depicted for illustrative purposes, and is described below in Figures 6A-7 .

[0082] The lower recess surface 374 can be a flat circular surface, as shown in Figure 4A , which is offset from or below the upper annular sealing surface 362 by a first distance 380 along the vertical center axis 378. In some embodiments, the lower recess surface 374 and the upper annular sealing surface 362 can also be considered parallel to one another. The recess side surface 376 can be a circular ring extending around the lower recess surface 374, and in some embodiments, can be substantially perpendicular to the lower recess surface 374 and / or perpendicular to the upper annular sealing surface 362 (e.g., within + / - 5% of orthogonal). In some embodiments, the lower recess surface 374 can have a radius 386, which can be substantially equal to the inner radius 368 of the upper annular sealing surface 362 (e.g., about 10% or about 1% less than the inner radius 368), as shown in Figure 4A . In Figure 4B , the same body 360 is seen, but a volume representative slice of the recess 364 is shown in light shading. Figure 4A

[0083] In some embodiments, the body 360 can be a monolithic, one-piece structure, while in other embodiments, it can be composed of multiple parts. For example, Figure 4B , the body can include a first portion 382 including the lower recess surface 374 and a second portion 384 including the upper annular sealing surface 362 and the side surface 376, and the second portion 384 can be an annular ring having a height of the first distance 380 and a thickness of the radial thickness 372. When the first portion 382 and the second portion 384 are connected together in a gas-tight manner (e.g., brazed, diffusion bonded), the recess 364 is formed. The body can be made of a dielectric material such as ceramic, or can be a metal or metal alloy coated with a dielectric material.

[0084] The vertical offset 380 between the lower recess surface 374 and the upper annular sealing surface can be configured to enable a clamping force to be applied to a substrate located on the ESC. Again referring to Figure 4A ​The body 360 includes one or more electrostatic clamping electrodes 394 configured to induce a downward clamping force to the substrate when the substrate is supported by the ESC and when power is supplied to the one or more electrostatic clamping electrodes 394. This clamping force between the substrate and the one or more electrostatic clamping electrodes 394 depends on, among other factors, the distance between the substrate and the one or more electrostatic clamping electrodes 394, such that the force decreases as the distance increases. Accordingly, the vertical offset 380 between the lower recessed surface 374 and the upper annular sealing surface 362 can be sized such that a clamping force can be applied between the substrate and the ESC during a processing operation to hold the substrate in place on the ESC. In some embodiments, this vertical offset 380 can be non-zero and less than or equal to 0.0381 millimeters (0.0015 inches), 0.0254 millimeters (0.001 inches), or 0.0127 millimeters (0.0005 inches). In some embodiments, the one or more electrostatic clamping electrodes can be configured to apply an electrostatic clamping force or pressure, for example, between 1 Torr and 40 Torr (0.02 psi to 0.8 psi). In some embodiments, the body can include two or more electrostatic clamping electrodes 394 located below the lower recessed surface and configured to be connected to a DC voltage of 300 volts or higher, for example, a DC voltage of 600 volts, 700 volts, 800 volts, 900 volts, and 1000 volts. In some embodiments, the RF electrodes of the ESC are also used as electrostatic clamping electrodes such that a DC voltage is applied to the RF electrodes to generate the electrostatic clamping force described herein.

[0085] The plurality of MCAs, together with the upper annular sealing surface 332, are configured to support a substrate positioned on the ESC and to prevent unwanted deformation and stress of the substrate when the substrate is subjected to a downward electrostatic clamping force. Generally, when a substrate is placed on and supported only by an annular surface, the gravitational force on the substrate causes little or no vertical deformation. In contrast, when the same substrate is subjected to a downward clamping force, the substrate can be caused to deform, which can result in defects and damage on the substrate. Similarly, if a substrate is supported by an annular ring and a small number of MCAs (e.g., 5 or 10), the gravitational force typically does not cause unwanted stress on the substrate. However, if there are not a sufficient number of properly arranged MCAs to distribute the stress of the downward clamping force equally and sufficiently to the substrate, the downward force applied to the substrate can cause undesirable deformation or point stress where the MCAs contact the substrate, which can cause damage to or result in defects in the substrate.

[0086] Figure 5A and 5B depicts a cross-sectional view of an exemplary substrate supported by an annular ring, while Figure 5C depicts a cross-sectional view of an exemplary substrate supported by three contact areas, while Figure 5Aa cross-sectional view of an exemplary substrate. Again, the figures are not drawn to scale and are exaggerated in the vertical axis in order to illustrate aspects described herein. In Figure 4A and Figure 4B like, the figures are not drawn to scale and are exaggerated in the vertical axis in order to illustrate aspects described herein. In Figure 5A , the substrate 514 is supported only by the annular ring 588; there is no recessed portion 564 (indicated by light shading) vertically supporting the substrate 514; the recessed portion 564 is positioned radially within the annular ring 588 and below most of the substrate 514. Here, no downward electrostatic clamping force is applied to the substrate 514, thus no deformation of the substrate 514 is induced. In Figure 5B , a downward electrostatic clamping force is applied to the substrate 514 of Figure 5A , as indicated by the downward arrow, causing the substrate 514 to deform into the recessed portion 564 by a first deformation distance 590. As described above, this deformation can cause damage to or defects on the substrate 514. In Figure 5C , three MCAs 566 are positioned in the recessed portion 564 and below the substrate 514, but the positions of these MCAs 566 are such that the pressure of the downward clamping force, as indicated by the downward arrows, is not sufficiently distributed along the substrate, causing unnecessary deformation of the substrate and point pressures at the substrate’s contact with the MCAs, circled by identifier 592.

[0087] Referring again to Figure 3 , the body including the annular ring 332, the recessed portion 334, and the MCAs 336 is arranged and configured to reduce or eliminate adverse effects on the substrate caused by the downward clamping force. For example, the radial thickness 372 of the upper annular sealing surface and the surface area of the recessed portion 364 (as depicted in Figure 3 ) can be arranged based on a variety of factors. In some embodiments, it can be desirable to have a large recessed portion below the substrate in order to provide uniform conditions for a large portion of the substrate’s back surface. For example, it can be advantageous to have the surface area of the recessed portion 364 be 80%, 85%, 95%, 98%, or more of the surface area of the substrate’s back surface. It can also be advantageous to have the radial thickness 372 sized large enough, e.g., the first radius 368 small enough, such that when viewed along the vertical central axis of the body, the circumference of the substrate’s edge circumscribes or extends around the inner circumference of the upper annular sealing surface, such that there is sufficient contact between the substrate’s back surface and the upper annular sealing surface in order to form a seal between the two surfaces. This annular thickness 372 must also be thick enough to seal the entire edge of the substrate, including sealing the index or alignment cut, while also accounting for inaccuracies and tolerances of wafer handlers positioning the substrate on the ESC.

[0088] In some embodiments, the plurality of MCAs 366 protrude from the lower recessed surface 374 and have a top surface offset from the lower recessed surface. Figure 6A depicts Figure 4Aof the ESC 360 along with an illustrative cross-sectional slice of the MCA. One sees multiple MCAs 366 protruding from the lower recess surface 374, and each MCA 366 includes a top surface 396 and a body 398. In some embodiments, the top surface 396 of each MCA can be coplanar with the upper annular seal surface 362, such that the upper annular seal surface 362 and the top surface 396 of each MCA are offset from the lower recess surface 374 by the same distance, i.e., the same vertical offset 380. In Figure 6A In some embodiments, the top surface 396 of the MCA is offset from the lower recess surface 374 by a second distance 3100, which can be substantially equal to the first distance 380. In some other embodiments, the top surface 396 of the MCA 366 can be lower than the upper annular seal surface 362, or offset from the lower recess surface 374 by a lesser amount than the upper annular seal surface 362. This can be advantageous because some substrates can have been deformed in a recessed or convex manner prior to being placed on the ESC, and thus will not incur additional deformation due to the clamping force applied to the substrate. This can also help avoid leaks even if the substrate is flat. For example, if there is only one "high" MCA near the edge of the recess, it can be lifted from the upper annular seal surface at that location, and the clamping force can not be able to overcome that lift.

[0089] Similar to the upper annular seal surface 362, it can be advantageous in some embodiments to make the top surface 396 of the MCA a flat surface in order to provide consistent, uniformly distributed contact between each MCA and the substrate. The flatness and planarity can be the same as described above with respect to the upper annular seal surface. The body of each MCA can be inserted between the lower recess surface 374 and the top surface 396, and it can be, for example, a cylindrical body, a conical body, or a square body.

[0090] Figure 7 depicts an oblique detail view of a portion of the ESC in Figure 3 . This view is larger than the Figure 8 below. Here, four MCAs 366 are depicted, each MCA 366 being a cylinder with a circular flat top surface 396 and extending upward from the lower recess surface 374 by a second height 3100. A portion of the upper annular seal surface 362 is also depicted, and the first distance 380 and the recess side surface 376 are determined.

[0091] As noted above, the size and arrangement of the MCAs can be set so as to distribute the pressure of the downward electrostatic clamping force evenly across the substrate. In some embodiments, it has been found advantageous to use hundreds or thousands of MCAs so as to evenly distribute the pressure, for example, using 2,000 MCAs, 4,000 MCAs, or more. In conjunction with this, it has been found advantageous for the total surface area of all of the MCA top surfaces 396 to be 3% or less of the total surface area of the recess 364, including the surface area occupied by the MCAs; it has been found that this can reduce and spread the pressure on the substrate. For example, the main body can have a recess with a radius of about 142 millimeters (which can be the same as the first radius 368 of the upper annular sealing surface 362), and can include 4,000 MCAs, each with a top surface radius of about 0.35 millimeters, which results in a total surface area of the MCA top surfaces of 1,539.4 millimeters 2 , which is about 2.4% of the total surface area of the recess, which is 63,347.1 millimeters 2 .

[0092] The arrangement and distribution of the MCAs within the recess can also be configured to distribute the electrostatic pressure evenly across the substrate. For example, the MCAs can be evenly, symmetrically, and equally spaced apart from one another when viewed along the vertical axis of the main body, such that pressure can be evenly distributed onto the wafer. Figure 8 A detailed view of the ESC main body of Figure 3 is depicted, as indicated by the circular border on Figure 3 . Here, a portion of the upper annular sealing surface 362 can be seen, and the plurality of MCAs 366 are depicted as circular surfaces and equally spaced apart. In some embodiments, the plurality of MCAs can be arranged into a plurality of sub-arrangement patterns, such as triangular patterns, square patterns, symmetric patterns, radial arrangements, and hexagonal patterns. In Figure 8 , the MCAs are arranged into a plurality of symmetric sub-arrangements, which are triangular, with three MCAs in each sub-arrangement triangle. One sub-arrangement 8104 is identified inside the dashed triangle, and as can be seen from the three spacing measurements 8106A, 8106B, and 8106C, the three MCAs are equally spaced apart. In some embodiments, the equal spacing can be about 3.9 millimeters (0.1535 inches).

[0093] The arrangement and location of the outermost MCAs can be based on several factors. These outermost MCAs are considered to be the MCAs that are closest to the upper annular sealing surface, for example Figure 8the MCA 366A. Some of these factors can be the local flatness or tolerance of the MCAs and the shape of the substrate as it is clamped, which can be governed by Kirchoff-Love plate theory. This theory is a mathematical model for determining the deformation and stress of thin plates under load. In one example, it was found that the height of the outermost MCAs, which are located within a recess having a radius of about 131.6 millimeters (about 5.18 inches), caused a displacement of about 0.00254 millimeters (0.0001 inches) at the wafer edge, which is within an acceptable flatness threshold.

[0094] As described above, when a substrate is placed on an ESC described herein and an electrostatic clamping force is applied to the substrate, a seal can be formed between the substrate and the upper annular seal surface, which reduces backside deposition on the substrate. For example, Figure 6B A substrate is depicted on a representative ESC of Figure 6A The substrate 614 is centered over the recess 364 and is supported by the MCAs 366 and the upper annular seal surface 362. When the electrostatic clamping electrode 394 is energized and thus causes a downward electrostatic clamping force to be applied on the substrate 614, a seal is formed between the portion of the upper annular seal surface 362 that is in contact with the substrate 614 and the upper annular seal surface 362, as identified within the ellipse 6108. This seal can be considered a circumferential region that extends around the circumference of the substrate 614.

[0095] The ESC and electrostatic clamping can create a seal between flat substrates as well as some non-flat substrates that can have a curved face or convex shape, for example, that can be caused by previous processing steps. As described above, when these non-flat substrates are placed on the upper annular seal surface, there can not be enough contact between the backside of the substrate and the annular seal to create a seal, which can result in unwanted backside deposition. However, when these substrates on the ESC are subjected to a downward electrostatic clamping force, the substrate can be caused to flatten, which causes the backside of the substrate to come into contact with and seal to the upper annular seal surface, thus reducing backside deposition.

[0096] In some embodiments, the ESCs described herein can be used to improve the centering of a substrate when the substrate is placed on the ESC. For example, a chucking voltage that is less than the voltage applied during deposition can be applied during this positioning, which can prevent the substrate from moving when it is placed on the ESC. This centering of the substrate makes the backside deposition performance more stable by placing the substrate in the same location each time, so that the substrate does not rest on accumulated deposits on the ESC.

[0097] The ESCs described herein can be used in a semiconductor processing system, such as the one described above with respect to Figure 1 and Figure 2The system 200 can include, for example: a controller 238; a DC power supply 226; a chamber 210 having four processing stations 231-234, each having an ESC as described above, for example, with an upper annular sealing surface, a recess, and an MCA disposed within the recess. The memory 244 of the controller 238 can store instructions for controlling various aspects of the system 200, including causing the substrate handler robot 236 to position a substrate on the ESC of each processing station and to power the electrostatic clamping electrodes of each ESC to induce an electrostatic clamping force to be applied to the substrate when on the ESC and when placing the substrate onto the ESC. As described above, the memory 244 can also include instructions for performing a deposition process such as ALD or CVD.

[0098] In some embodiments, the structure of the electrostatic chucks described herein can be used to provide an electrode for generating plasma, rather than providing an electrode for providing an electrostatic clamping force. In these embodiments, the "clamping electrodes" of the ESC can instead be used as powered RF electrodes or grounds for generating plasma, and no electrostatic clamping force is applied to the ESC and substrate on the ESC during processing operations. Thus, a substrate can be placed on the ESC as described above and at least partially sealed to the ESC under the force of gravity. While electrostatic clamping forces provide advantages for certain substrates under certain processing conditions, the ESC structure described herein can still reduce unwanted backside deposition during processing operations compared to conventional pedestals, such as those having a flat substrate surface, without any electrostatic clamping force. In some cases, this benefit can be provided by the radial thickness of the upper annular sealing surface as described above, which can prevent some backside deposition compared to conventional pedestals.

[0099] In these embodiments where the ESC does not apply any electrostatic clamping force and the ESC is used as an electrode for generating plasma, the ESC can be referred to as a "powered pedestal" when it is used as a powered RF electrode and a "grounded pedestal" when it is used as a ground for generating plasma. For example, referring again to Figure 1 and the related description above, the ESC 118 can be a powered pedestal when it is electrically connected to the RF power supply 122 and matching network 124, which in some cases can be a shared power supply between multiple stations, as shown in Figure 2 In these cases, the showerhead 104 or other components within the chamber can be used as a ground. For a grounded pedestal, the ESC 118 can be electrically connected to the ground, and the showerhead 104 can be used, for example, as the applied RF power source. The electrodes of the ESC described above, for example Figure 4A 、 6AAnd as with the electrodes 394 shown in FIGS. 6A and 6B and described above, the electrodes 394 can be used as RF ground or applied RF power for generating plasma.

[0100] The construction features and configurations of these powered and grounded pedestals can be the same or nearly the same as the ESCs described above. In some such embodiments, the powered and grounded pedestals have any or all of the features of the ESCs described herein, including any of the combinations and constructions described above, including Figure 3 and 6A -8 of the example ESC 318. This includes the body 360 having the upper annular sealing surface 362, the recess 364, the plurality of MCAs 366 disposed within the recess 364, and any of the constructions and arrangements of these features described herein.

[0101] For example, this includes the upper annular sealing surface 362 being a circumferential ring extending completely around the recess 364, the upper annular sealing surface 362 being bounded by an inner radius 368 and an outer radius 370, such that the upper annular sealing surface 362 has a radial thickness 372, and the upper annular sealing surface 362 being configured to support an edge and a portion of a bottom or back surface of a substrate. This also includes any of the measurements of these features, such as the inner radius 370 being between about 142.9 millimeters (about 5.625 inches) or about 131.6 millimeters (about 5.18 inches), the outer radius being about 150.6 millimeters (or about 5.9275 inches), the radial thickness of the upper annular sealing surface being less than or equal to about 25 millimeters, including about 15.4 millimeters (about 0.605 inches), the radial thickness being sized to support and enable the annular sealing surface to seal with substrates having diameters of 300 millimeters, 450 millimeters, and 200 millimeters, the upper annular sealing surface 362 being a planar, flat, and smooth surface as described above.

[0102] In some embodiments, this further includes a lower recess surface 374 that is a flat, circular surface, as described above and seen in FIGS. 6A and 6B, that is offset from the upper annular sealing surface 362 by a first distance 380 or below the lower annular sealing surface 362 by the first distance 380 along a vertical center axis 378. This also includes the construction and arrangement of the MCAs, as described above in Figure 4A Figures 6A-8 For example, the plurality of MCAs 366 can protrude from the lower recess surface 374 and have a top surface that is offset from the lower recess surface; there can also be hundreds or thousands of MCAs, such as more than 2,000 MCAs or more than 4,000 MCAs.

[0103] ​In some embodiments, the powered and grounded susceptor and ESC described above can differ in the electrical connections of the electrodes, the application of electrostatic clamping force, and / or the configuration of the electrodes. In some cases, the electrodes can only be connected to an RF power source or an electrical ground, but not to a DC power source. These electrodes can be configured to receive a voltage from the RF power source. In other cases, the electrodes can be connected to an RF power source or an electrical ground as well as a DC power source, but the DC power source is not applied to the electrodes during processing. In some embodiments, the electrodes of the powered and grounded susceptor can not be configured to apply an electrostatic clamping force.

[0104] In some embodiments, the powered and grounded susceptors and ESC described above can be configured the same as the ESCs described herein, such that they are configured to apply an electrostatic clamping force on the substrate as well as generate a plasma within the processing chamber. However, in these embodiments, the electrostatic clamping force can not be applied during some or all of the processing operation. Experimental Results

[0105] Various embodiments of the ESCs described herein have achieved a reduction in backside deposition on a substrate. In one experiment, the use of a clamping voltage of 300 volts or more was shown to improve backside deposition compared to not using a clamping force. Figure 9 Results of a first deposition experiment are depicted. Here, a material layer of material was deposited on a plurality of substrates at one station using a variety of electrostatic clamping voltages. For each processed substrate, measurements (e.g., azimuthal measurements) at 72 points around the circumferential edge of the substrate plus a kerf were obtained and formed the horizontal axis; the vertical axis was thickness, dimensionless. From Figure 9 It can be seen that the substrate with no clamping force applied (i.e., zero voltage) had a backside deposit of about 70 to 700 between edge points 40 and 60. In contrast, the remaining substrates all had a clamping force applied during the deposition process in a range from about 300 V to about 1000 V, and for these substrates, the backside deposit was about 30 or less. The high measurements near zero are the location of the substrate kerf, which, regardless of clamping, caused increased backside deposition in the area around the kerf.

[0106] In another experiment, the backside deposition thickness of clamped and unclamped substrates was measured as a function of chamber accumulation. Figure 10 Measurements of backside deposition thickness on a number of unclamped substrates on a susceptor of a processing chamber are shown as a function of chamber accumulation; these substrates were placed on a conventional susceptor that did not have the upper annular sealing surface, MCA, and recess described above, and were not subjected to an electrostatic clamping force during deposition. Each deposition process produced a layer of material on the front side of the substrate. The backside deposition thickness was measured at 72 points around the circumference of the substrate plus a kerf. The measurements are shown in FIG. 8. The horizontal axis is the azimuthal measurement, and the vertical axis is the backside deposition thickness, in Angstroms. The measurements are shown as a function of chamber accumulation in FIG. 9. The horizontal axis is the chamber accumulation, and the vertical axis is the backside deposition thickness, in Angstroms. The measurements are shown as a function of chamber accumulation in FIG. 9. The horizontal axis is the chamber accumulation, and the vertical axis is the backside deposition thickness, in Angstroms. Figure 9Similarly, the data shown at each chamber accumulation thickness represents backside deposition thickness measurements (vertical axis in dimensionless units) taken at about 72 points around the substrate's circumferential edge (horizontal axis). It can be seen that the backside deposition thickness, outside the cutout region, ranges between about 200 units and 30 units throughout the deposition process, up to a chamber accumulation of 19,234 units. For example, at a chamber accumulation of 2,190 units, the backside deposition thickness ranges between about 30 units and 100 units, while at a chamber accumulation of 14,221 units, the backside deposition thickness ranges between about 200 units and 20 units.

[0107] Figure 11 Measurements of backside deposition thickness on a number of clamped substrates on an ESC are depicted. These substrates were placed on an ESC that did indeed have an upper annular sealing surface, MCA, and recess as described above, and during deposition, the substrates were subjected to electrostatic clamping forces; other deposition conditions were the same as in Figure 10 and each deposition condition resulted in a layer of material on the substrate's front side. The data shown at each chamber accumulation thickness again represents backside deposition thickness measurements taken at about 72 points around the substrate's circumferential edge. In Figure 11 the backside deposition thickness throughout the deposition process remained relatively flat, up to about a chamber accumulation of 19,234 units, and did not exceed about 30 units. In some embodiments, the backside deposition criterion is to have less than or equal to 5% of the frontside deposition at 1 mm from the substrate edge. Here, the substrate passed this criterion.

[0108] Using a mathematical model, it has been found that the ESC described herein can minimize backside deposition in a radial region up to 1 mm radially inward from the edge of the substrate to the center of the substrate. Figure 12 A mathematically modeled region of deposition on a substrate's backside is depicted. The vertical axis represents normalized surface concentration, which is equal to the surface sites of the substrate's backside with precursor divided by the total surface sites density of the substrate; the horizontal axis is the distance from the edge of the substrate (zero point) to the center of the substrate. Each line represents the height (inches) of the MCA and upper annular sealing surface, which are coplanar with each other, and the normalized surface concentration was measured for a deposition process with a dose time of 0.8 seconds. It can be seen that the depth of penetration of the presence of backside deposition inward from the edge of the substrate does not exceed about 0.4 mm, which complies with the criterion described above.

[0109] Unless the context clearly requires otherwise, throughout the description and the claims, the words "comprise," "comprising," and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is to say, in the sense of "including, but not limited to." Words using the singular or plural number also include the plural or singular number respectively. Additionally, the words "herein," "hereunder," "above"- "below," and words of similar import refer to this application as a whole and not to any particular portion of this application. When the word "or" is used in reference to a list of two or more items, that word covers all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list. The term "implementation" means an implementation of the technology and methods described herein, as well as an entity object embodying these structures and / or incorporating the technology and / or methods described herein. "Substantially" herein means within 5% of the referenced value, unless otherwise stated. For example, substantially vertical means within + / - 5% of vertical.

[0110] It is to be understood that the above-referenced arrangements are merely examples of one or more particular implementations and are not intended to limit the discussion to those described. Many variations and modifications of the implementations described herein can be made which fall within the scope of the disclosure. In particular, the following numbered list of implementations is considered to be part of the disclosure. List of numbered implementations

[0111] Implementation 1 : One implementation includes a susceptor, the susceptor comprising a body including: an upper annular sealing surface that is planar, perpendicular to a vertical center axis of the body, and has a radial thickness; a lower recessed surface offset from the upper annular sealing surface by a first distance; a plurality of micro-contact areas (MCAs) protruding from the lower recessed surface, each MCA having a top surface that is offset from the lower recessed surface by a second distance that is less than or equal to the first distance; and one or more electrodes within the body, wherein the upper annular sealing surface is configured to support an outer edge of a semiconductor substrate when the semiconductor substrate is supported by the susceptor, the upper annular sealing surface and the top surfaces of the MCAs are configured to support the semiconductor substrate when the susceptor supports the semiconductor substrate, and the one or more electrodes are configured to electrically connect with one or more selected from a group consisting of: a radio frequency (RF) power source, an electrical ground, and a direct current (DC) power source.

[0112] Implementation 2: The susceptor of implementation 1, wherein the one or more electrodes are electrostatic chucking electrodes, and the one or more electrostatic chucking electrodes are configured to provide an electrostatic chucking force on the semiconductor substrate when the semiconductor substrate is supported by the susceptor and when the one or more electrostatic chucking electrodes are powered by the DC power source.

[0113] Implementation 3: The susceptor of implementation 2, wherein a seal is formed between the upper annular sealing surface and the semiconductor substrate when the semiconductor substrate is supported by the susceptor and when the one or more electrostatic chucking electrodes provide an electrostatic chucking force on the semiconductor substrate.

[0114] Implementation 4: The susceptor of implementation 1, wherein the one or more electrodes are configured to be electrically connected to the RF power source and to receive RF power from the RF power source.

[0115] Implementation 5: The susceptor of implementation 1, wherein the upper annular sealing surface has an inner radius that is less than the radius of the semiconductor substrate and an outer radius that is greater than the radius of the semiconductor substrate.

[0116] Implementation 6: The susceptor of implementation 5, wherein the inner radius is about 142 millimeters.

[0117] Implementation 7: The susceptor of implementation 6, wherein the outer radius is about 150 millimeters.

[0118] Implementation 8: The susceptor of implementation 1, wherein the radial thickness is less than or equal to about 25 millimeters.

[0119] Implementation 9: The susceptor of implementation 8, wherein the radial thickness is less than or equal to about 15 millimeters.

[0120] Implementation 10: The susceptor of implementation 1, wherein the upper annular sealing surface and the top surface of the MCA are coplanar, and the first distance is equal to the second distance.

[0121] Implementation 11: The susceptor of implementation 10, wherein the first distance and the second distance are equal to or between 0.0127 millimeters and 0.0381 millimeters.

[0122] Implementation 12: The susceptor of implementation 11, wherein the first distance and the second distance are 0.0254 millimeters.

[0123] Implementation 13: The susceptor of implementation 1, wherein the first distance is greater than the second distance.

[0124] Implementation 14: The susceptor of implementation 13, wherein the first distance and the second distance are equal to or between 0.0127 millimeters and 0.0381 millimeters.

[0125] Implementation 15: The susceptor of implementation 1, wherein the plurality of MCAs comprises more than 2,000 MCAs.

[0126] Implementation 16: The susceptor of implementation 15, wherein the plurality of MCAs comprises more than 4,000 MCAs.

[0127] Implementation 17: The susceptor of implementation 15, wherein substantially all of the MCAs are equally spaced from one another.

[0128] Implementation 18: The susceptor of implementation 17, wherein substantially all of the MCAs are spaced 3.9 millimeters from one another.

[0129] Implementation 19: The susceptor of implementation 15, wherein the plurality of MCAs is divided into a plurality of sub-arrangements, and the MCAs in each sub-arrangement are positioned on the lower recess surface in one or more of a triangular pattern, a square pattern, a symmetrical pattern, a radial arrangement, and a hexagonal pattern.

[0130] Implementation 20: The susceptor of implementation 1, wherein the lower recess surface has a recess surface area, each MCA top surface has a top surface area, and the sum of all top surface areas of the MCAs in the plurality of MCAs is less than or equal to 3% of the recess surface area.

[0131] Implementation 21: The susceptor of implementation 1, wherein each MCA is a cylinder having a flat top surface area.

[0132] Implementation 22: The susceptor of implementation 21, wherein each MCA has a radius of about 0.35 millimeters.

[0133] Implementation 23: The susceptor of implementation 1, wherein the upper annular sealing surface has a roughness of between about 0.8128 micrometers and about 0.2032 micrometers.

[0134] Implementation 24: The susceptor of implementation 1, wherein each MCA top surface has a roughness of between about 0.8128 micrometers and about 0.2032 micrometers.

[0135] Implementation 25: The susceptor of implementation 1, wherein the upper annular sealing surface has a flatness of a maximum range of 0.0254 millimeters.

[0136] Implementation 26: The susceptor of implementation 1, wherein each MCA top surface has a flatness of a maximum range of 0.0254 millimeters.

[0137] Implementation 27: The susceptor of implementation 1, wherein the body comprises a ceramic.

[0138] Implementation 28: The susceptor of implementation 1, wherein the body comprises a metal or metal alloy, and the body is coated with a ceramic.

[0139] Implementation 29: An implementation includes a semiconductor processing system. The system includes: a processing chamber; one or more processing stations in the processing chamber; an electrostatic chuck in each of the one or more processing stations, each electrostatic chuck having a body comprising an upper annular sealing surface that is flat, perpendicular to a vertical central axis of the body and has a radial thickness, a lower recessed surface that is offset from the upper annular sealing surface by a first distance, a plurality of micro contact areas (MCAs) protruding from the lower recessed surface, each MCA having a top surface that is offset from the lower recessed surface by a second distance that is less than or equal to the first distance, and one or more electrostatic clamping electrodes within the body, wherein the upper annular sealing surface is configured to support an outer edge of a semiconductor substrate when the semiconductor substrate is supported by the electrostatic chuck, the upper annular sealing surface and the top surfaces of the MCAs are configured to support the semiconductor substrate when the electrostatic chuck supports the semiconductor substrate, and the one or more electrostatic clamping electrodes are configured to provide an electrostatic clamping force on the semiconductor substrate when the semiconductor substrate is supported by the electrostatic chuck and when the one or more electrostatic clamping electrodes are powered by a DC power source; the DC power source electrically connected to the electrostatic clamping electrodes; and a controller having a memory and a processor, the memory storing instructions configured to cause the DC power source to power the electrostatic clamping electrodes to provide an electrostatic clamping force on the semiconductor substrate when the semiconductor substrate is supported by the electrostatic chuck.

[0140] Implementation 30: The semiconductor processing system of implementation 29, further comprising an end effector configured to position a semiconductor substrate on each of the electrostatic chucks, wherein the memory further stores instructions configured to cause the end effector to position a semiconductor substrate on each of the electrostatic chucks and, after positioning the semiconductor substrate on one of the electrostatic chucks, cause the DC power supply to provide power to the electrostatic clamping electrodes in the one electrostatic chuck to provide an electrostatic clamping force on the semiconductor substrate.

[0141] Implementation 31 : The semiconductor processing system of implementation 30, wherein the memory further stores instructions configured to cause the DC power supply to provide power to the electrostatic clamping electrodes of one of the electrostatic chucks to provide a lower electrostatic clamping force on the semiconductor substrate when the end effector positions the semiconductor substrate on the one of the electrostatic chucks.

[0142] Implementation 32: An implementation includes a semiconductor processing implementation including: a process chamber; one or more process stations in the process chamber; a pedestal in each of the one or more process stations, each pedestal having a body including an upper annular sealing surface that is planar, perpendicular to a vertical central axis of the body and has a radial thickness, a lower recessed surface that is offset from the upper annular sealing surface by a first distance, a plurality of micro contact areas (MCAs) protruding from the lower recessed surface, each MCA having a top surface that is offset from the lower recessed surface by a second distance that is less than or equal to the first distance, and one or more electrodes within the body, wherein the upper annular sealing surface is configured to support an outer edge of a semiconductor substrate when the semiconductor substrate is supported by the pedestal, the upper annular sealing surface and the top surfaces of the MCAs are configured to support the semiconductor substrate when the pedestal supports the semiconductor substrate, and the one or more electrodes are configured to be electrically connected to a radio frequency (RF) power source; a showerhead above the pedestal electrically connected to electrical ground; the RF power source electrically connected to the one or more electrodes; and a controller having a memory and a processor, the memory storing instructions configured to cause the RF power source to provide an RF voltage to the one or more electrodes to generate a plasma between the pedestal and the showerhead.

[0143] Implementation 33: The semiconductor processing system of implementation 32, wherein no electrostatic clamping force is applied to the substrate when the plasma is generated between the pedestal and the showerhead.

[0144] Implementation 34: The semiconductor processing system of implementation 32, further comprising a direct current (DC) power source, wherein the DC power source is electrically connected to the one or more electrodes configured to provide an electrostatic clamping force on the semiconductor substrate when the semiconductor substrate is supported by the pedestal and when the one or more electrodes are powered by the DC power source, and the memory further stores instructions configured to cause the DC power source to power the one or more electrodes to provide the electrostatic clamping force on the semiconductor substrate while the semiconductor substrate is supported by the pedestal.

Claims

1. A base comprising: The main body includes: The upper annular sealing surface is flat, perpendicular to the vertical central axis of the body, and has a radial thickness. The recessed surface is offset from the upper annular sealing surface by a first distance. Multiple micro-contact areas (MCAs) protruding from the surface of the recess, each MCA having a top surface offset from the surface of the recess by a second distance less than or equal to a first distance; and One or more electrodes within the body, wherein: The upper annular sealing surface is configured to support the outer edge of the semiconductor substrate when the semiconductor substrate is supported by the base. The upper annular sealing surface and the top surface of the MCA are configured to support the semiconductor substrate when the base supports the semiconductor substrate, and The one or more electrodes are configured to be electrically connected to both an RF power supply and a DC power supply simultaneously, and The one or more electrodes are configured to provide electrostatic clamping force on a semiconductor substrate when the one or more electrostatic clamping electrodes are powered by a DC power supply, and are configured to provide plasma generation when the one or more electrostatic clamping electrodes are powered by a radio frequency power supply.

2. The base according to claim 1, wherein, When the semiconductor substrate is supported by the base and when the one or more electrostatic clamping electrodes provide electrostatic clamping force on the semiconductor substrate, a seal is formed between the upper annular sealing surface and the semiconductor substrate.

3. The base according to claim 1, wherein, The upper annular sealing surface has an inner radius smaller than the radius of the semiconductor substrate and an outer radius larger than the radius of the semiconductor substrate.

4. The base according to claim 3, wherein, The inner radius is 142 mm.

5. The base according to claim 4, wherein, The outer radius is 150 mm.

6. The base according to claim 1, wherein, The radial thickness is less than or equal to 25 mm.

7. The base according to claim 6, wherein, The radial thickness is less than or equal to 15 mm.

8. The base according to claim 1, wherein: The upper annular sealing surface and the top surface of the MCA are coplanar, and The first distance is equal to the second distance.

9. The base according to claim 8, wherein, The first distance and the second distance are between 0.0127 mm and 0.0381 mm.

10. The base according to claim 9, wherein, The first distance and the second distance are 0.0254 mm.

11. The base according to claim 1, wherein, The first distance is greater than the second distance.

12. The base according to claim 11, wherein, The first distance and the second distance are between 0.0127 mm and 0.0381 mm.

13. The base according to claim 1, wherein, The plurality of MCAs includes more than 2,000 MCAs.

14. The base according to claim 13, wherein, The plurality of MCAs includes more than 4,000 MCAs.

15. The base according to claim 13, wherein, All MCAs are spaced equally apart from each other.

16. The base according to claim 15, wherein, All MCAs are spaced 3.9 mm apart.

17. The base according to claim 13, wherein: The plurality of MCAs are divided into a plurality of sub-arrangements, and the MCAs in each sub-arrangement are positioned on the recessed surface in one or more of the following patterns: triangular, square, and hexagonal.

18. The base according to claim 1, wherein: The surface of the recessed portion has a concave surface area. Each MCA top surface has a top surface area, and The sum of the top surface areas of all the MCAs in the plurality of MCAs is less than or equal to 3% of the surface area of ​​the recess.

19. The base according to claim 1, wherein, Each MCA is a cylinder with a flat top surface area.

20. The base according to claim 19, wherein, Each MCA has a radius of 0.35 mm.

21. The base according to claim 1, wherein, The upper annular sealing surface has a roughness between 0.8128 micrometers and 0.2032 micrometers.

22. The base according to claim 1, wherein, Each MCA top surface has a roughness between 0.8128 micrometers and 0.2032 micrometers.

23. The base according to claim 1, wherein, The upper annular sealing surface has a flatness of up to 0.0254 mm.

24. The base according to claim 1, wherein, Each MCA top surface has a flatness of up to 0.0254 mm.

25. The base according to claim 1, wherein, The main body comprises ceramic.

26. The base according to claim 1, wherein: The main body comprises metal or metal alloy, and The main body is coated with ceramic.

27. The base according to claim 13, wherein: The plurality of MCAs are divided into a plurality of sub-arrangements, and the MCAs in each sub-arrangement are positioned on the recessed surface in a symmetrical pattern.

28. The base according to claim 13, wherein: The plurality of MCAs are divided into a plurality of sub-arrangements, and the MCAs in each sub-arrangement are positioned radially on the surface of the recess.

29. A semiconductor processing system comprising: Processing room; One or more processing stations in the processing room; In each of the one or more processing stations, an electrostatic chuck is provided, each electrostatic chuck having a body comprising: The upper annular sealing surface is flat, perpendicular to the vertical central axis of the body, and has a radial thickness. The recessed surface is offset from the upper annular sealing surface by a first distance. Multiple micro-contact areas (MCAs) protruding from the surface of the recess, each MCA having a top surface offset from the surface of the recess by a second distance less than or equal to a first distance; and One or more electrodes within the body, wherein: The upper annular sealing surface is configured to support the outer edge of the semiconductor substrate when the semiconductor substrate is supported by the electrostatic chuck. The upper annular sealing surface and the top surface of the MCA are configured to support the semiconductor substrate when the electrostatic chuck supports the semiconductor substrate, and The one or more electrodes are configured to provide an electrostatic clamping force on the semiconductor substrate when the semiconductor substrate is supported by the electrostatic chuck and when the one or more electrodes are powered by a DC power supply. The DC power supply is electrically connected to the one or more electrodes; A radio frequency power supply electrically connected to the one or more electrodes; and A controller having a memory and a processor, the memory storing instructions configured to: The DC power supply provides direct current to the one or more electrodes to provide an electrostatic clamping force on the semiconductor substrate when the semiconductor substrate is supported by the electrostatic chuck. The radio frequency power supply provides radio frequency voltage to the one or more electrodes, while simultaneously providing DC power to the one or more electrodes, to generate plasma between the electrostatic chuck and the nozzle.

30. The semiconductor processing system of claim 29, further comprising an end effector configured to position the semiconductor substrate on the electrostatic chuck, wherein the memory further stores instructions configured to: The end effector positions the semiconductor substrate on the electrostatic chuck, and Before positioning the semiconductor substrate on the electrostatic chuck, the DC power supply provides direct current to the one or more electrodes to provide the electrostatic clamping force on the semiconductor substrate.

31. The semiconductor processing system according to claim 30, wherein, The memory further stores instructions configured as follows: This allows the DC power supply to provide direct current to the one or more electrodes when the end effector positions the semiconductor substrate on the electrostatic chuck, thereby reducing the electrostatic clamping force applied to the semiconductor substrate.

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