Reverse conducting insulated gate bipolar transistor with asymmetric deep trench structure and design method thereof

Abstract

The invention provides a reverse conducting insulated gate bipolar transistor with an asymmetric deep groove structure and a design method of the reverse conducting insulated gate bipolar transistor. The method comprises the following steps: providing a photomask layer layout for limiting the positions of a plurality of deep trenches; the layout is modified, the position of at least one deep groove is shifted, and asymmetric deep groove arrangement is formed; based on the asymmetric arrangement, a first injection region is formed at the bottom of the deep trench, and a second injection region is formed between the first injection region and the second injection region. Wherein the offset enables a part of adjacent first injection regions to form a continuous guide region due to the reduction of the distance, and enables the width of the second injection region to be increased to form a short circuit region. According to the invention, only the photomask layout is modified, and the similar guide type structure is indirectly formed on the back surface of the device under the condition of not increasing additional process cost, so that the inflection effect is effectively inhibited, the working stability and reliability of the device are improved, the design is flexible, and the performance is adjustable.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to an asymmetric deep trench structure reverse conducting insulated gate bipolar transistor (RC-IGBT) and a design method thereof. BACKGROUND

[0002] Insulated gate bipolar transistor (IGBT) combines the advantages of power MOSFET and bipolar transistor, has the characteristics of high input impedance, low on-state voltage drop and high switching speed, and is widely used in the field of power electronics. In order to further improve the integration of power devices and reduce the cost of system, the freewheeling diode is usually integrated with the IGBT on the same chip to form a reverse conducting IGBT (RC-IGBT). RC-IGBT is suitable for air conditioners, frequency converters and other household appliances, and large power supplies and other industrial fields.

[0003] At present, the mainstream implementation scheme of RC-IGBT includes a guide type structure and a deep trench structure. Among them, the RC-IGBT of the guide type structure realizes functional integration by setting alternating P-type collector region (IGBT region) and N+ short circuit region (diode region) on the back of the device, and its manufacturing process is relatively simple, which is the main structure for current production.

[0004] Another RC-IGBT of deep trench structure can share the same mask plate for patterning injection (such as P-type injection) on the back and deep trench structure on the front, and only needs to increase ion injection at the bottom of the trench once after deep trench etching, without back alignment, so the process flow is simpler and the cost control is better. However, the traditional deep trench RC-IGBT adopts uniform and periodic arrangement of deep trenches, which leads to obvious folding effect of the device during work, also known as negative resistance effect, which seriously affects the stability and reliability of the device, limiting its use in some application scenarios.

[0005] Therefore, how to effectively suppress the folding effect of deep trench RC-IGBT while maintaining the advantages of simple process and controllable cost is a technical problem to be solved by those skilled in the art. SUMMARY

[0006] The purpose of the present application is to provide an asymmetric deep trench structure reverse conducting insulated gate bipolar transistor (RC-IGBT) and a design method thereof, to solve the technical problem that the existing deep trench RC-IGBT has obvious folding effect due to uniform arrangement of trenches, which affects the stability and reliability of the device during work.

[0007] To achieve the above object and other related objects, the present application provides a design method of an asymmetric deep trench structure reverse conducting insulated gate bipolar transistor, comprising:

[0008] Step one, providing a mask layout, the mask layout is used to define the position of a plurality of deep trenches, wherein the plurality of deep trenches are periodically arranged with a preset cell pitch;

[0009] Step two, modifying the mask layout, selecting at least one deep trench from the plurality of deep trenches, and offsetting the position of the at least one deep trench relative to the position of the periodic arrangement, thereby forming an asymmetric deep trench arrangement on the mask layout;

[0010] Step three, based on the asymmetric deep trench arrangement, forming a first implantation region at the bottom of the deep trench, and forming a second implantation region in the area between the first implantation regions, wherein the offset causes the spacing between part of the adjacent first implantation regions to decrease to form at least one continuous guide region, and causes the width of the second implantation region to increase to form a short circuit region.

[0011] Preferably, in step two, the offset includes moving the at least one deep trench towards its adjacent deep trench, so that the mesa width between the two deep trenches decreases, while the mesa width between the deep trench and its other adjacent deep trench increases.

[0012] Preferably, in step two, the magnitude of the offset is 10% to 20% of the mesa width.

[0013] Preferably, the etching window width of the deep trench is 4 microns, the mesa width is 5 microns, and the magnitude of the offset is within 1 micron; or, the etching window width of the deep trench is 2 microns, the mesa width is 3 microns, and the magnitude of the offset is within 0.4 microns; or, the etching window width of the deep trench is 5 microns, the mesa width is 6 microns, and the magnitude of the offset is within 1.5 microns.

[0014] Preferably, the method further comprises: determining the magnitude of the offset according to a preset area ratio of the guide region to the short circuit region.

[0015] Preferably, in step two, the asymmetric deep trench arrangement on the mask layout is a global arrangement or a local arrangement.

[0016] Preferably, in step three, the first implantation region is a P-type implantation region, and the second implantation region is an N-type implantation region.

[0017] Preferably, the P-type implantation region is formed by a process such that its width after heat treatment is greater than the etching window width of the deep trench and less than the preset cell pitch.

[0018] Preferably, the asymmetric deep trench arrangement includes at least one of the following: an arrangement formed by offsetting a single deep trench, wherein the cell corresponds to two deep trenches; an arrangement formed by offsetting two deep trenches, wherein the cell corresponds to three deep trenches; or an arrangement formed by offsetting multiple deep trenches, wherein the cell has multiple offset pitches.

[0019] Preferably, the design method is applied to silicon-based or silicon carbide-based reverse-conducting insulated-gate bipolar transistors.

[0020] This invention provides a reverse-conducting insulated-gate bipolar transistor with an asymmetric deep trench structure, comprising:

[0021] Multiple deep trenches arranged asymmetrically;

[0022] Multiple first injection zones formed at the bottom of the deep trench; and

[0023] The second injection region formed between the first injection regions serves as a short-circuit region;

[0024] The asymmetrical arrangement of the multiple deep trenches causes the spacing between some adjacent first injection areas to be reduced to form at least one continuous guide area, and causes the second injection area to form short-circuit areas of unequal width.

[0025] Preferably, the first injection region is a P-type injection region and the second injection region is an N-type injection region.

[0026] Preferably, the width of the P-type injection region is greater than the etching window width of the deep trench and less than the cell pitch of the plurality of deep trenches.

[0027] Preferably, the magnitude of the positional offset of the deep trench determines the area ratio of the guide area to the short-circuit area.

[0028] Preferably, the multiple deep trenches arranged in an asymmetric manner are arranged globally or locally on the transistor.

[0029] Preferably, the asymmetrical arrangement of deep trenches is formed by offsetting at least one deep trench in a periodically arranged array of deep trenches, such offset causing the width of the platform on one side to decrease and the width of the platform on the other side to increase.

[0030] Preferably, the position offset is 10% to 20% of the table width.

[0031] Preferably, the etching window width of the deep trench is 4 micrometers and the mesa width is 5 micrometers; or, the etching window width of the deep trench is 2 micrometers and the mesa width is 3 micrometers; or, the etching window width of the deep trench is 5 micrometers and the mesa width is 6 micrometers.

[0032] Preferably, the asymmetric arrangement includes at least one of the following: an arrangement formed by offsetting a single deep trench, wherein the cell corresponds to two deep trenches; an arrangement formed by offsetting two deep trenches, wherein the cell corresponds to three deep trenches; or an arrangement formed by offsetting multiple deep trenches, wherein the cell has multiple offset pitches.

[0033] Preferably, the semiconductor material of the reverse-conducting insulated-gate bipolar transistor includes silicon or silicon carbide.

[0034] As described above, the reverse-conducting insulated-gate bipolar transistor with an asymmetric deep trench structure and its design method of the present invention have the following beneficial effects:

[0035] This application breaks the traditional periodic structure by offsetting the position of some deep trenches on the photomask layout, allowing some adjacent P-type injection regions (first injection region) to be connected and merged in subsequent processes, thereby indirectly forming a continuous IGBT guide region on the back side of the device. The introduction of this guide-like structure ensures that holes are preferentially injected into the guide region when the device is turned on, effectively suppressing the backflip effect and significantly enhancing the device's operational stability and reliability.

[0036] The core of this invention lies in modifying the layout design of only the same photomask used to form the deep trench, without adding any additional photomask, injection, or alignment processes. Therefore, this method solves the key technical problem of the foldback effect while fully retaining the advantages of the deep trench RC-IGBT process: simple process flow, no need for back-side alignment, and excellent cost control. Attached Figure Description

[0037] Figure 1 The diagram shows a cross-sectional view of a symmetrically arranged deep trench structure and the injection area.

[0038] Figure 2 The diagram shows a cross-sectional view of an asymmetric structure with a single deep groove offset according to an embodiment of the present invention.

[0039] Figure 3 The diagram shows a cross-sectional view of an asymmetric structure with two deep groove offsets according to another embodiment of the present invention.

[0040] Figure 4 The diagram shows a cross-sectional view of an asymmetric deep trench reverse-conducting IGBT according to an embodiment of the present invention.

[0041] Figure 5 The diagram shown illustrates the design method of the reverse-conducting insulated gate bipolar transistor with an asymmetric deep trench structure according to the present invention. Detailed Implementation

[0042] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0043] In some embodiments, please refer to Figure 5 This application provides a design method for an asymmetric deep trench reverse-conducting insulated-gate bipolar transistor, comprising the following steps:

[0044] Step 1: Provide a photomask layout, which is used to define the positions of multiple deep trenches, wherein the multiple deep trenches are arranged periodically with a preset cell pitch.

[0045] Step 2: Modify the photomask layout by selecting at least one deep trench from multiple deep trenches and shifting its position relative to its periodic arrangement, thereby forming an asymmetric deep trench arrangement on the photomask layout.

[0046] In some embodiments, step two, the offsetting includes moving at least one deep trench toward an adjacent deep trench, such that the mesa width between the two deep trenches decreases, while the mesa width between the deep trench and its adjacent deep trench on the other side increases. This asymmetric design breaks the uniformity of traditional device structures and is key to achieving subsequent functional partitioning and performance optimization.

[0047] In some embodiments, the method further includes determining the amount of offset based on a preset area ratio between the guide region and the short-circuit region. This indicates that the offset is no longer a fixed value, but a design parameter that can be used to actively adjust and optimize device performance.

[0048] In some embodiments, in step two, the offset is 10% to 20% of the mesa width. Controlling the offset within this range can effectively form the guide region and short-circuit region while avoiding excessive negative impact on core performance indicators such as the breakdown voltage of the device, thus achieving a balance and optimization of device performance.

[0049] In some embodiments, in step two, the etching window width of the deep trench is 4 micrometers, the mesa width is 5 micrometers, and the offset is within 1 micrometer; or, the etching window width of the deep trench is 2 micrometers, the mesa width is 3 micrometers, and the offset is within 0.4 micrometers; or, the etching window width of the deep trench is 5 micrometers, the mesa width is 6 micrometers, and the offset is within 1.5 micrometers. It should be noted that these specific combinations of dimensions and offsets can also employ other designs to accommodate device designs with different voltage ratings and current density requirements.

[0050] In some embodiments, in step two, the asymmetric deep trench arrangement can be globally or locally arranged on the photomask layer layout. This means that designers can choose to use an asymmetric design throughout the entire effective area of ​​the chip, or introduce an asymmetric structure only in specific functional areas (such as the edge or center), depending on the overall needs of the chip, thus providing great design flexibility.

[0051] Step 3: Based on the asymmetric deep trench arrangement, a first injection area is formed at the bottom of the deep trench, and a second injection area is formed in the area between the first injection areas. The offset reduces the spacing between some adjacent first injection areas to form at least one continuous guide area, and increases the width of the second injection area to form a short-circuit area.

[0052] In some embodiments, in step three, the first implantation region is a P-type implantation region, and the second implantation region is an N-type implantation region. By implanting P-type ions (e.g., boron ions) at the bottom of the deep trench, the collector region of the IGBT can be formed. The offset operation allows some adjacent P-type implantation regions to connect after subsequent thermal diffusion, forming a continuous P-type region, i.e., the IGBT guide region. Simultaneously, implanting N-type ions between the P-type implantation regions forms a highly doped N+ short-circuit region. The offset operation increases the mesa width of some regions, thereby correspondingly increasing the N+ short-circuit region window formed there, which provides a low-resistance freewheeling path and good ohmic contact for the freewheeling diode.

[0053] In some embodiments, in step three, the formation process of the P-type implantation region ensures that its width after the thermal process is greater than the etching window width of the deep trench and less than a preset cell pitch. For example, in a preferred embodiment, by controlling the implantation dose of P-type ions (e.g., 5e15) and the subsequent annealing and diffusion process, the size of the formed P-type ring can be stabilized within a specific range. This size range must satisfy the following conditions: the width must be greater than the trench window to ensure that the implantation region effectively covers the bottom of the trench; the width must be less than the cell pitch to avoid accidental connections in wide mesa regions designed as short-circuit areas. This ensures that in areas where the mesa width decreases, adjacent P-type rings can reliably connect and merge to form an effective guiding region, while in areas where the mesa width increases, they can remain separated to form a clear short-circuit region.

[0054] By utilizing the aforementioned design method and taking advantage of the fact that reverse-guided structures and deep trench structures can share the same photomask, the IGBT guiding region and N+ short-circuit region can be simultaneously constructed on the back side of the device simply by modifying the layout of the deep trenches on the photomask layer. This quasi-guiding structure effectively suppresses the severe foldback / negative resistance effect in conventional deep trench RC-IGBTs, thereby significantly improving the device's operational stability and reliability, widening the safe operating area, and reducing the oscillation risk during switching. Simultaneously, this method eliminates the need for additional photomasks or complex alignment processes, maintaining the core advantages of low cost and simple process of deep trench technology.

[0055] For a more detailed explanation, please refer to the appendix. Figures 1 to 4 .

[0056] Figure 1 This illustrates a conventional, symmetrically arranged deep trench structure upon which this design method is based. In this example, the deep trenches have a periodic structure with a pitch of |4:5|, meaning the etching window width of the deep trench is 4 micrometers, and the mesa width between adjacent trenches is 5 micrometers, forming a cell with a pitch of 9 micrometers. P-type implantation regions are formed at the bottom of each deep trench, and these P-type implantation regions, after thermal diffusion, form P-type rings with a width of approximately 8 micrometers, which are separated from each other.

[0057] Figure 2 An asymmetric arrangement of a single deep trench offset is illustrated. The original |4:5|:|4:5|... arrangement is adjusted to |4:4.5:4:5.5|.... It can be seen that by offsetting a deep trench by 0.5 micrometers, the mesa width between it and the left deep trench is reduced to 4.5 micrometers, while the mesa width between it and the right deep trench is increased to 5.5 micrometers. The reduced mesa width allows two adjacent P-rings to connect after thermal diffusion, forming a continuous guiding region composed of two P-rings. In a preferred embodiment, by implanting P-rings with boron ions at a dose of 5e15 and subsequent thermal diffusion, the final width of the P-rings can be stabilized at approximately 9 micrometers. This width is greater than the trench window width (4 micrometers) and less than the trench pitch (4+5=9 micrometers), ensuring reliable connection in the region where the mesa width is narrowed. The increased mesa forms a wider N-window, i.e., a short-circuit region. This creates a new cell containing two deep grooves with a pitch of 18 micrometers.

[0058] Figure 3An asymmetric arrangement with two deep trench offsets is illustrated. The original arrangement is adjusted to |4:4.5:4:4.5:4:6|... Through two consecutive offsets, two mesa with a width of 4.5 micrometers and one mesa with a width of 6 micrometers are formed. This allows three adjacent P-rings to connect, forming a wider continuous guide region, thereby enhancing the IGBT's conduction capability and hole injection efficiency. Simultaneously, the large mesa with a width of 6 micrometers also creates a larger short-circuit region. This arrangement forms a new cell containing three deep trenches with a pitch of 27 micrometers.

[0059] In some embodiments, the asymmetric deep trench arrangement includes at least one of the following: an arrangement formed by offsetting a single deep trench, where each cell corresponds to two deep trenches; an arrangement formed by offsetting two deep trenches, where each cell corresponds to three deep trenches; or an arrangement formed by offsetting multiple deep trenches, where each cell has multiple offset pitches. For example... Figure 4 The multiple deep trench offsets shown can form continuous guide regions of |4:4.5:...|, and short-circuit regions with different widths such as |4:5.5:...| and |4:6:...|. By adjusting the number and amount of the offset deep trenches, the area ratio of the IGBT guide region to the short-circuit region in the device can be flexibly adjusted, thereby precisely fine-tuning key electrical parameters such as on-state voltage drop, switching losses, and freewheeling characteristics to meet the specific needs of different application scenarios. The offset can be set locally in the layout, introducing asymmetric structures only in specific areas, or it can be set globally, making the entire chip adopt an asymmetric design.

[0060] In some embodiments, the design method is applied to silicon (Si)-based or silicon carbide (SiC)-based reverse-conducting insulated-gate bipolar transistors. Besides traditional silicon-based devices, this method is also applicable to wide-bandgap semiconductor devices such as silicon carbide and gallium nitride (GaN), facilitating the development of high-voltage, high-temperature, and high-frequency power devices with superior performance.

[0061] In some embodiments, this application also provides an asymmetric deep trench structure reverse-conducting insulated-gate bipolar transistor, the structure of which can be seen in... Figure 4 . Figure 4This is a schematic diagram of the final structure of the asymmetric deep trench reverse-conducting IGBT formed using the above design method. The complete structure of the device is clearly visible in the diagram, including the gate (G) and emitter on the front side, and the collector on the back side. The device includes: multiple deep trenches arranged asymmetrically; multiple first injection regions formed at the bottom of the deep trenches; and second injection regions formed between the first injection regions as short-circuit regions. The asymmetric arrangement of the multiple deep trenches reduces the spacing between some adjacent first injection regions to form at least one continuous guiding region, and causes the second injection regions to form short-circuit regions of varying widths. This device structure integrates the functions of an IGBT and a freewheeling diode, and through its built-in quasi-guiding structure, fundamentally overcomes the foldback effect problem of traditional deep trench RC-IGBTs, improving the overall performance of the device.

[0062] In some embodiments, the first injection region is a P-type injection region, and the second injection region is an N-type injection region. The key point is that, due to the asymmetrical arrangement of deep trenches, the back side of the device naturally forms a "continuous guiding region" (formed by connecting P-type injection regions) and a "short-circuit region" (formed by N-type injection regions). The continuous guiding region corresponds to... Figure 2 and Figure 3 The area where the P-rings are interconnected is responsible for hole injection in IGBT mode. Short-circuit region (e.g.) Figure 4 The short-circuit regions 1 and 2 marked in the middle are N-type injection regions located in the region where the mesa width increases. They are responsible for serving as the cathode path of the diode in reverse freewheeling mode. As the cathode of the reverse parallel diode, they form a good ohmic contact with the collector metal of the device, providing a low-impedance path for the freewheeling current.

[0063] In some embodiments, the width of the P-type injection region is greater than the etching window width of the deep trench and less than the cell pitch of the multiple deep trenches.

[0064] In some embodiments, the magnitude of the positional offset of the deep trench determines the area ratio of the guide region to the short-circuit region.

[0065] In some embodiments, multiple deep trenches arranged in an asymmetric manner are arranged globally or locally on the transistor.

[0066] In some embodiments, the asymmetrical arrangement of deep trenches is formed by offsetting the position of at least one deep trench in a periodically arranged array of deep trenches, such offset causing the width of the platform on one side to decrease and the width of the platform on the other side to increase.

[0067] In some embodiments, the position offset is 10% to 20% of the table width.

[0068] In some embodiments, the etching window width of the deep trench is 4 micrometers and the mesa width is 5 micrometers; or, the etching window width of the deep trench is 2 micrometers and the mesa width is 3 micrometers; or, the etching window width of the deep trench is 5 micrometers and the mesa width is 6 micrometers.

[0069] In some embodiments, the asymmetric arrangement includes at least one of the following: an arrangement formed by offsetting a single deep trench, wherein the cell corresponds to two deep trenches; an arrangement formed by offsetting two deep trenches, wherein the cell corresponds to three deep trenches; or an arrangement formed by offsetting multiple deep trenches, wherein the cell has multiple offset pitches.

[0070] In some embodiments, the semiconductor material of the reverse-conducting insulated-gate bipolar transistor includes silicon or silicon carbide.

[0071] In summary, the design method and device structure provided in this application achieve a quasi-guided RC-IGBT structure at extremely low cost by making simple asymmetric modifications to the deep trench photomask layout. This effectively suppresses the back-flip effect, improves the stability and reliability of the device, and provides an innovative technical approach for the mass production of high-performance, low-cost RC-IGBTs.

[0072] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0073] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A design method for a reverse-conducting insulated-gate bipolar transistor with an asymmetric deep trench structure, characterized in that, At least including: Step 1: Provide a photomask layer layout, which is used to define the positions of multiple deep trenches, wherein the multiple deep trenches are arranged periodically with a preset cell pitch; Step 2: Modify the photomask layout by selecting at least one deep trench from the plurality of deep trenches and shifting its position relative to its periodic arrangement, thereby forming an asymmetrical deep trench arrangement on the photomask layout. Step 3: Based on the asymmetric deep trench arrangement, a first injection area is formed at the bottom of the deep trench, and a second injection area is formed in the area between the first injection areas. The offset reduces the spacing between some adjacent first injection areas to form at least one continuous guide area, and increases the width of the second injection area to form a short-circuit area.

2. The design method of the reverse-conducting insulated-gate bipolar transistor with an asymmetric deep trench structure according to claim 1, characterized in that: In step two, the offset includes moving the at least one deep trench toward an adjacent deep trench, such that the platform width between the two deep trenches decreases, while the platform width between the deep trench and the deep trench adjacent to its other side increases.

3. The design method of the reverse-conducting insulated-gate bipolar transistor with an asymmetric deep trench structure according to claim 2, characterized in that: In step two, the amount of offset is 10% to 20% of the table width.

4. The design method of the reverse-conducting insulated-gate bipolar transistor with an asymmetric deep trench structure according to claim 3, characterized in that: The etching window width of the deep trench is 4 micrometers, the mesa width is 5 micrometers, and the offset is within 1 micrometer; or, the etching window width of the deep trench is 2 micrometers, the mesa width is 3 micrometers, and the offset is within 0.4 micrometers; or, the etching window width of the deep trench is 5 micrometers, the mesa width is 6 micrometers, and the offset is within 1.5 micrometers.

5. The design method of the reverse-conducting insulated-gate bipolar transistor with an asymmetric deep trench structure according to claim 1, characterized in that: The method further includes determining the amount of offset based on a preset area ratio between the guide area and the short-circuit area.

6. The design method of the reverse-conducting insulated-gate bipolar transistor with an asymmetric deep trench structure according to claim 1, characterized in that: In step two, the asymmetric deep trenches are arranged globally or locally on the photomask layer layout.

7. The design method of the reverse-conducting insulated-gate bipolar transistor with an asymmetric deep trench structure according to claim 1, characterized in that: In step three, the first injection region is a P-type injection region, and the second injection region is an N-type injection region.

8. The design method of the reverse-conducting insulated-gate bipolar transistor with an asymmetric deep trench structure according to claim 7, characterized in that: The formation process of the P-type injection region results in a width after thermal processing that is greater than the etching window width of the deep trench and less than the preset cell pitch.

9. The design method of the reverse-conducting insulated-gate bipolar transistor with an asymmetric deep trench structure according to claim 1, characterized in that: The asymmetric deep trench arrangement includes at least one of the following: an arrangement formed by the offset of a single deep trench, wherein the cell corresponds to two deep trenches; The arrangement formed by the offset of two deep trenches has a cell corresponding to three deep trenches; The arrangement formed by multiple deep groove offsets has cells with various offset pitches.

10. The design method of the reverse-conducting insulated-gate bipolar transistor with an asymmetric deep trench structure according to claim 1, characterized in that: The design method is applied to silicon-based or silicon carbide-based reverse-conducting insulated-gate bipolar transistors.

11. A reverse-conducting insulated-gate bipolar transistor with an asymmetric deep trench structure, characterized in that, include: Multiple deep trenches arranged asymmetrically; Multiple first injection zones are formed at the bottom of the deep trench; as well as The second injection region formed between the first injection regions serves as a short-circuit region; The asymmetrical arrangement of the multiple deep trenches causes the spacing between some adjacent first injection areas to be reduced to form at least one continuous guide area, and causes the second injection area to form short-circuit areas of unequal width.

12. The reverse-conducting insulated-gate bipolar transistor with an asymmetric deep trench structure according to claim 11, characterized in that: The first injection region is a P-type injection region, and the second injection region is an N-type injection region.

13. The reverse-conducting insulated-gate bipolar transistor with an asymmetric deep trench structure according to claim 11, characterized in that: The width of the P-type injection region is greater than the etching window width of the deep trench, but less than the cell pitch of the plurality of deep trenches.

14. The reverse-conducting insulated-gate bipolar transistor with an asymmetric deep trench structure according to claim 11, characterized in that: The magnitude of the positional offset of the deep trench determines the area ratio of the guide area to the short-circuit area.

15. The reverse-conducting insulated-gate bipolar transistor with an asymmetric deep trench structure according to claim 11, characterized in that: The multiple deep trenches arranged in an asymmetric manner are arranged globally or locally on the transistor.

16. The reverse-conducting insulated-gate bipolar transistor with an asymmetric deep trench structure according to claim 11, characterized in that: The asymmetrical arrangement of deep trenches is formed by offsetting at least one deep trench in a periodically arranged array of deep trenches, such offset causing the width of the platform on one side to decrease and the width of the platform on the other side to increase.

17. The reverse-conducting insulated-gate bipolar transistor with an asymmetric deep trench structure according to claim 16, characterized in that: The amount of the positional offset is 10% to 20% of the table width.

18. The reverse-conducting insulated-gate bipolar transistor with an asymmetric deep trench structure according to claim 11, characterized in that: The etching window width of the deep trench is 4 micrometers, and the mesa width is 5 micrometers; or, the etching window width of the deep trench is 2 micrometers, and the mesa width is 3 micrometers; or, the etching window width of the deep trench is 5 micrometers, and the mesa width is 6 micrometers.

19. The reverse-conducting insulated-gate bipolar transistor with an asymmetric deep trench structure according to claim 11, characterized in that: The asymmetric arrangement includes at least one of the following: an arrangement formed by the offset of a single deep trench, wherein the cell corresponds to two deep trenches; The arrangement formed by the offset of two deep trenches has a cell corresponding to three deep trenches; The arrangement formed by multiple deep groove offsets has cells with various offset pitches.

20. The reverse-conducting insulated-gate bipolar transistor with an asymmetric deep trench structure according to claim 11, characterized in that: The semiconductor material of the reverse-conducting insulated gate bipolar transistor includes silicon or silicon carbide.

Images