Epitaxial structure, preparation method thereof and semiconductor device

Abstract

The invention provides an epitaxial structure, a preparation method thereof and a semiconductor device, and the epitaxial structure comprises a substrate layer, a nucleating layer, a buffer layer, a high-resistance layer, a channel layer, an insertion layer and a barrier layer which are sequentially stacked from bottom to top. Wherein the buffer layer comprises a first superlattice structure layer, a second superlattice structure layer and a third superlattice structure layer which are sequentially stacked together from bottom to top, the buffer layer can better control the curvature of the epitaxial structure in the epitaxial growth process, and edge crack initiation and expansion caused by overlarge warping of the epitaxial structure are avoided; meanwhile, in the cooling springback stage after epitaxial growth is finished, the buffer layer structure with the three superlattice structure layers has better stress adjusting capacity, and therefore cracks are effectively improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, in particular to an epitaxial structure, a preparation method thereof and a semiconductor device. BACKGROUND

[0002] The third generation of semiconductor materials mainly including gallium nitride (GaN) and silicon carbide (SiC) has significant advantages such as wide band gap, high breakdown electric field, high thermal conductivity, high electron saturation velocity and high radiation resistance compared with the first generation of semiconductor silicon (Si) and germanium (Ge), which makes it an ideal choice for manufacturing high-temperature, high-frequency and high-power devices.

[0003] Among them, gallium nitride devices have been widely concerned in the fields of lighting, lasers, electronic power devices and microwave power devices due to their high voltage resistance, high current density, high conversion efficiency and high response frequency. At present, silicon-based gallium nitride (GaN-on-Si) power devices are the mainstream in the market, especially 6-inch high electron mobility transistor (HEMT) devices, which are mainly used in low-voltage consumer, medium-voltage vehicle and high-voltage industrial scenes according to the voltage requirement. In order to further reduce the cost and improve the scale benefit, the industry is actively transitioning to 8-inch silicon-based gallium nitride epitaxial technology.

[0004] However, the core challenge of epitaxial growth of gallium nitride material on an 8-inch large-size silicon substrate is the serious warping and stress problem of the epitaxial wafer during the growth process. The thermal mismatch and lattice mismatch effects are significantly amplified by the larger diameter and the use area, which leads to more cracks in the 8-inch epitaxial wafer compared with the 6-inch product, which poses a major threat to the product yield and reliability. SUMMARY

[0005] The present application provides an epitaxial structure, a preparation method thereof and a semiconductor device. The epitaxial structure has a first superlattice structure layer, a second superlattice structure layer and a third superlattice structure layer arranged in the buffer layer, which can better control the curvature of the epitaxial structure during epitaxial growth, avoid the edge crack initiation and expansion caused by excessive warping of the epitaxial structure, and solve the problems of easy crack generation and decline of vertical breakdown voltage performance of the epitaxial structure.

[0006] According to a first aspect of the present application, an epitaxial structure is provided, comprising: a substrate layer, a nucleation layer, a buffer layer, a high resistance layer, a channel layer, an insertion layer, a barrier layer stacked together from bottom to top. Among them, the buffer layer comprises a first superlattice structure layer, a second superlattice structure layer and a third superlattice structure layer stacked together from bottom to top.

[0007] Optionally, the buffer layer satisfies at least one of the following conditions: (1) the molar content of aluminum element in the buffer layer satisfies: first superlattice structure layer > second superlattice structure layer > third superlattice structure layer; (2) the thickness of the first superlattice structure layer, the second superlattice structure layer and the third superlattice structure layer is respectively 1000nm-1500nm, 1500nm-2000nm and 2000nm-2500nm, (3) the molar content of aluminum element in the first superlattice structure layer, the second superlattice structure layer and the third superlattice structure layer is respectively 40%-55%, 25%-35% and 8%-15%.

[0008] Optionally, the material of the first superlattice structure layer, the second superlattice structure layer and the third superlattice structure layer is at least one of AlN / AlGaN, AlGaN / AlGaN and AlGaN / GaN.

[0009] Optionally, the nucleation layer comprises a first nucleation layer, a second nucleation layer and a third nucleation layer stacked together from bottom to top.

[0010] Optionally, the nucleation layer satisfies at least one of the following conditions: (1) the thickness of the first nucleation layer, the second nucleation layer and the third nucleation layer is respectively 15nm-30nm, 30nm-90nm and 55nm-230nm; (2) the third nucleation layer comprises at least two sub-layers stacked together.

[0011] Optionally, the epitaxial structure satisfies at least one of the following conditions: (1) the substrate layer is an 8-inch single crystal silicon polishing wafer; (2) the material of the nucleation layer is aluminum nitride, (3) the material of the high resistance layer is carbon-doped gallium nitride, and the doping source in the carbon-doped gallium nitride is at least one of ethylene, acetylene, propane and butane; (4) the material of the channel layer is intrinsic gallium nitride; (5) the material of the insertion layer is aluminum nitride; (6) the material of the barrier layer is aluminum gallium nitride; (7) the thickness of the high resistance layer is 1000nm-3500nm; (8) the thickness of the channel layer is 150nm-350nm; (9) the thickness of the insertion layer is 0.5nm-1.5nm; (10) the thickness of the barrier layer is 10nm-25nm.

[0012] According to a second aspect of the present application, a method for preparing the epitaxial structure of the first aspect is provided, comprising the following steps: Step one, providing a substrate layer; Step two, forming the nucleation layer on the substrate layer; Step three, forming the buffer layer on the nucleation layer, Step four, forming the high-resistance layer on the buffer layer; Step five, forming the channel layer on the high-resistance layer; Step six, forming the insertion layer on the channel layer; Step seven, forming the barrier layer on the insertion layer.

[0013] Optionally, in step two, the nucleation layer comprises a first nucleation layer, a second nucleation layer, and a third nucleation layer stacked together from bottom to top; The growth conditions of the first nucleation layer are as follows: the reaction temperature is 830-900℃, the reaction pressure is 50-100 mbar, the trimethylaluminum flow rate is 100-200 sccm, the ammonia flow rate is 1-5 slm, the hydrogen flow rate is 150-190 slm, and the growth time is 50 s-250 s; The third nucleation layer comprises a first sublayer and a second sublayer stacked together from bottom to top, and the growth conditions of the third nucleation layer are as follows: the reaction temperature is 1000-1100℃, the reaction pressure is 50-100 mbar, the trimethylaluminum flow rate is 100-300 sccm, and the hydrogen flow rate is 130-170 slm; The ammonia flow rates corresponding to the first sublayer and the second sublayer are 0.5-5 slm and 10-30 slm, respectively, the growth times are 1-2 min and 3-5 min, respectively, and the cycle number is 6-20. The growth conditions of the second nucleation layer are linearly transitioned from the growth conditions of the first nucleation layer to the growth conditions of the first sublayer, and the growth time is 2-10 min.

[0014] Optionally, in step three, the buffer layer comprises a first superlattice structure layer, a second superlattice structure layer, and a third superlattice structure layer stacked together from bottom to top; The growth conditions of the buffer layer are as follows: the reaction temperature is 980-1040℃, the reaction pressure is 50-100 mbar, the trimethylaluminum flow rate is 300-700 sccm, the trimethylgallium flow rate is 80-300 sccm, the ammonia flow rate is 1.5-10 slm, and the hydrogen flow rate is 120-150 slm; The inner structure growth time of the first superlattice structure layer, the second superlattice structure layer and the third superlattice structure layer is respectively 20-60s, 30-100s, and the corresponding cycle number of the first superlattice structure layer, the second superlattice structure layer and the third superlattice structure layer is respectively 20-60, 60-100 and 100-140.

[0015] In a third aspect, the application provides a semiconductor device comprising the epitaxial structure of the first aspect or the epitaxial structure prepared by the preparation method of the second aspect.

[0016] The application has the following beneficial effects: Based on the above technical solution, the epitaxial structure has the following beneficial effects: the buffer layer is provided with the first superlattice structure layer, the second superlattice structure layer and the third superlattice structure layer, so that the buffer layer has a stress adjustment function, can effectively relieve thermal stress generated due to the difference in thermal expansion coefficient in the epitaxial growth process, can better control the curvature of the epitaxial structure in the epitaxial growth process, and avoids the edge crack initiation and expansion caused by excessive warping of the epitaxial structure; meanwhile, the buffer layer structure with the three superlattice structure layers has better stress adjustment capability in the cooling and rebound stage after the epitaxial growth is completed, thereby effectively improving the crack, and compared with the traditional low-temperature insertion layer (such as AlN or SiN), the superlattice structure layer does not need to introduce a heterogeneous interface defect or an impurity diffusion source, avoids damaging the electrical properties of the high-resistance layer, thereby guaranteeing the vertical breakdown voltage performance of the epitaxial structure.

[0017] Other features and advantages of the application will be described in detail in the following specific embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can also be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0019] Figure 1 The structure schematic diagram of the epitaxial structure provided in the specific embodiments of the application; Figure 2 The structure schematic diagram of the buffer layer provided in the specific embodiments of the application; Figure 3 The structure schematic diagram of the nucleation layer provided in the specific embodiments of the application; Figure 4 The process flow chart of the preparation method of the epitaxial structure provided in the specific embodiments of the application.

[0020] 10, substrate layer; 20, nucleation layer; 21, first nucleation layer; 22, second nucleation layer; 23, third nucleation layer; 231, sublayer; 30, buffer layer; 31, first superlattice structure layer; 32, second superlattice structure layer; 33, third superlattice structure layer; 40, high resistance layer; 50, channel layer; 60, insertion layer; 70, barrier layer. DETAILED DESCRIPTION

[0021] In order to make the purposes, technical solutions and advantages of the present application clearer, the present application is further described in detail below in combination with the drawings and examples. It should be understood that the specific examples described herein are only used to explain the present application and do not limit the present application.

[0022] The inventors have found that, in order to solve the crack problem of 8-inch super-high voltage gallium nitride (GaN) epitaxial wafer, a method of introducing a low-temperature aluminum nitride (AlN) insertion layer or a low-temperature silicon nitride (SiN) insertion layer in the high resistance layer is generally used to control stress and improve warping. Although these insertion layer methods can alleviate the crack problem to some extent, the core defect is that the structural integrity and electrical properties of the high resistance layer are destroyed: the low-temperature aluminum nitride (AlN) insertion layer interface easily induces defect formation of a leakage channel; the low-temperature silicon nitride (SiN) insertion layer has a silicon (Si) diffusion problem, which significantly increases the background electron concentration of the high resistance gallium nitride (GaN) layer. These negative effects seriously weaken the voltage resistance and breakdown resistance of the epitaxial wafer, which directly conflicts with the key requirements of high voltage devices for high quality, low leakage, and high insulation of the high resistance layer, and becomes a key technical bottleneck restricting the development and application of 8-inch large-size, super-high voltage gallium nitride (GaN) power devices.

[0023] Therefore, the first aspect of the present application provides an epitaxial structure as shown in Figure 1 The epitaxial structure comprises, from bottom to top, a substrate layer 10, a nucleation layer 20, a buffer layer 30, a high resistance layer 40, a channel layer 50, an insertion layer 60, and a barrier layer 70 stacked together in sequence. As shown in Figure 2 The buffer layer 30 comprises, from bottom to top, a first superlattice structure layer 31, a second superlattice structure layer 32, and a third superlattice structure layer 33 stacked together in sequence.

[0024] By the technical solution, the buffer layer 30 of the epitaxial structure is provided with the first superlattice structure layer 31, the second superlattice structure layer 32 and the third superlattice structure layer 33, so that the buffer layer 30 has a stress adjustment function, can effectively relieve thermal stress generated due to the difference in the thermal expansion coefficient in the epitaxial growth process, can better control the curvature of the epitaxial structure in the epitaxial growth process, and avoids the edge crack initiation and expansion caused by the excessive warping of the epitaxial structure; meanwhile, in the cooling and rebounding stage after the epitaxial growth is completed, the buffer layer structure with the three-layer superlattice structure layers has a better stress adjustment capability, thereby effectively improving the crack, and compared with the traditional low-temperature insertion layer (such as AlN or SiN), the superlattice structure layer does not need to introduce a heterogeneous interface defect or an impurity diffusion source, avoids damaging the electrical performance of the high-resistance layer, and thus guarantees the vertical breakdown voltage performance of the epitaxial structure.

[0025] It can be understood that the superlattice structure layer is a multilayer composite structure formed by periodically and alternately stacking extremely thin film materials of two or more different components or lattice parameters; the superlattice structure layer can balance the lattice mismatch and thermal stress by alternately stacking materials with different thermal expansion coefficients or lattice constants, and can inhibit crack initiation.

[0026] In some embodiments, the molar content of aluminum elements in the buffer layer satisfies the first superlattice structure layer > the second superlattice structure layer > the third superlattice structure layer, so that the molar content of aluminum elements in the above buffer layer decreases from bottom to top, a gradient stress regulation mechanism is constructed, dynamic dispersion and stress release of thermal stress are realized, and the crack problem of the 8-inch large-size super-high-voltage GaN epitaxial wafer is significantly improved.

[0027] In the above technical solution, the layer-by-layer decrease of the aluminum molar content causes the three-layer superlattice structure layers to form a gradually changing lattice constant and thermal expansion coefficient difference in the vertical direction, thereby gradually releasing the strain energy generated due to the lattice mismatch in the growth process, and avoiding stress concentration to cause crack initiation. Moreover, the first superlattice structure layer with a high aluminum molar content can effectively buffer the thermal expansion mismatch between the substrate and the subsequent layer (for example, the mismatch between the silicon substrate and GaN), and the third superlattice structure layer with a low aluminum molar content gradually transitions to the thermal expansion coefficient matched with the high-resistance layer (such as carbon-doped gallium nitride), thereby reducing the stress accumulation at the interface.

[0028] In addition, in the cooling process, the first superlattice structure layer with high aluminum molar content has high rigidity, which can inhibit the rapid change of the overall wafer warping, and the third superlattice structure layer with low aluminum molar content has high flexibility, allowing local stress to be released through lattice adjustment or dislocation absorption, thereby reducing the risk of crack propagation. Compared with the interface defects or impurity diffusion problems that may be introduced by the traditional low-temperature insertion layer (such as AlN or SiN), the present application realizes stress regulation through the aluminum content gradient superlattice structure, without introducing heterogeneous materials, thereby maintaining the electrical properties (such as low leakage and high insulation) of the high resistance layer and improving the structural integrity.

[0029] In some embodiments, the material of the first superlattice structure layer, the second superlattice structure layer, and the third superlattice structure layer is at least one of AlN / AlGaN, AlGaN / AlGaN, and AlGaN / GaN. By combining the materials, the crack problem of the 8-inch super-high voltage GaN epitaxial wafer is significantly improved, and the strict requirements of high-performance power devices on the high resistance layer are also met.

[0030] In the above technical solution, the combination of AlN / AlGaN alternately stacks AlN (high aluminum content) and AlGaN (gradient aluminum content), which can balance the lattice mismatch between the substrate (such as silicon) and GaN. The high lattice rigidity of AlN and the adjustable lattice constant of AlGaN form a synergistic effect, reducing the dislocation defect density caused by lattice mismatch; the combination of AlGaN / AlGaN adjusts the aluminum components of adjacent layers (for example, high-aluminum AlGaN and low-aluminum AlGaN are alternated), which can build a gradual lattice strain gradient, further inhibiting crack initiation.

[0031] In addition, the AlN / AlGaN layer with high aluminum content (the first superlattice structure layer) has a lower thermal expansion coefficient (close to 3.5x10 -6 / ℃ of AlN), which can effectively buffer the thermal expansion mismatch between the silicon substrate (4.2x10 -6 / ℃) and the subsequent GaN layer (about 5.6x10 -6 / ℃).

[0032] If the third superlattice structure layer adopts the AlGaN / GaN combination, then by introducing low-aluminum AlGaN and GaN, the thermal expansion properties gradually transition to the high resistance layer (carbon-doped GaN), avoiding stress concentration caused by thermal mismatch during the cooling and rebounding stage.

[0033] Compared with the traditional low-temperature insertion layer (such as AlN or SiN), the present application realizes stress regulation through the periodicity and component gradient of the superlattice structure, without introducing heterogeneous interface defects or impurity diffusion sources, thereby avoiding the destruction of the electrical properties (such as low leakage and high insulation) of the high resistance layer and maintaining the structural integrity.

[0034] In some examples, the first superlattice structure layer in the buffer layer has a material of AlN / AlGaN, and a mole content of Al is 40-55%, for example, the mole content of Al can be 40%, 42%, 45%, 47%, 48%, 50%, 55%, or a value within a range formed by any two of these values; the second superlattice structure layer in the buffer layer has a material of AlN / AlGaN, and a mole content of Al is 25-35%, for example, the mole content of Al can be 25%, 27%, 28%, 30%, 35%, or a value within a range formed by any two of these values; the third superlattice structure layer in the buffer layer has a material of AlN / AlGaN, and a mole content of Al is 8-15%, for example, the mole content of Al can be 8%, 10%, 11%, 12%, 15%, or a value within a range formed by any two of these values.

[0035] In some examples, the first superlattice structure layer in the buffer layer has a material of AlGaN / AlGaN, and a mole content of Al is 40-55%, for example, the mole content of Al can be 40%, 42%, 45%, 47%, 48%, 50%, 55%, or a value within a range formed by any two of these values; the second superlattice structure layer in the buffer layer has a material of AlGaN / AlGaN, and a mole content of Al is 25-35%, for example, the mole content of Al can be 25%, 27%, 28%, 30%, 35%, or a value within a range formed by any two of these values; the third superlattice structure layer in the buffer layer has a material of AlGaN / AlGaN, and a mole content of Al is 8-15%, for example, the mole content of Al can be 8%, 10%, 11%, 12%, 15%, or a value within a range formed by any two of these values.

[0036] In some examples, the first superlattice structure layer in the buffer layer has a material of AlGaN / GaN, and a mole content of Al is 40-55%, for example, the mole content of Al can be 40%, 42%, 45%, 47%, 48%, 50%, 55%, or a value within a range formed by any two of these values; the second superlattice structure layer in the buffer layer has a material of AlGaN / GaN, and a mole content of Al is 25-35%, for example, the mole content of Al can be 25%, 27%, 28%, 30%, 35%, or a value within a range formed by any two of these values; the third superlattice structure layer in the buffer layer has a material of AlGaN / GaN, and a mole content of Al is 8-15%, for example, the mole content of Al can be 8%, 10%, 11%, 12%, 15%, or a value within a range formed by any two of these values.

[0037] In some embodiments, the nucleation layer adopts a pulsed aluminum nitride structure layer, which forms a periodic structure by alternately growing aluminum nitride sublayers with different physical or chemical properties (such as thickness, doping, composition, etc.), thereby achieving multi-dimensional optimization of lattice stress, defect distribution and interface quality.

[0038] Compared to conventional homogeneous aluminum nitride nucleation layers, the nucleation layer in this application introduces controllable lattice mismatch and thermal expansion gradients through a pulsed structure design, thereby significantly improving the crack resistance of the epitaxial layer. For example, by periodically adjusting the growth parameters of the sublayer (such as thickness), a local stress buffer is formed, inducing dislocations to bend and annihilate at the interface, reducing the density of penetrating dislocations, effectively preventing vertical dislocation propagation, reducing deep-level defects in the epitaxial layer, and improving crystal uniformity. Furthermore, during the cooling phase, the pulsed structure gradually releases the stress concentration caused by the difference in thermal contraction through a progressive transition of the thermal expansion coefficient, avoiding crack propagation caused by rapid warping of the epitaxial layer, thereby significantly slowing down the stress accumulation rate and improving the mechanical stability of the epitaxial layer.

[0039] In some embodiments, such as Figure 3 As shown, the nucleation layer 20 includes a first nucleus layer 21, a second nucleus layer 22, and a third nucleus layer 23 stacked together from bottom to top. The first nucleus layer 21 is formed by growth under constant conditions, the second nucleus layer 22 is formed by growth under linearly varying conditions, and the third nucleus layer 23 is formed by pulsed cyclic growth. The first nucleus layer, formed by growth under constant conditions, provides a stable initial nucleation interface with low defect density, laying the foundation for lattice compatibility in subsequent layers. The second nucleus layer, formed by growth under linear gradient conditions, can form a local stress buffer, gradually releasing lattice mismatch stress. The third nucleus layer, formed by pulsed cyclic growth, can periodically store and release stress, suppressing vertical dislocation propagation and optimizing thermal expansion.

[0040] The above-mentioned technical solution, which has a pulsed aluminum nitride structure layer with a first core layer, a second core layer, and a third core layer, can significantly reduce the risk of crack propagation during the cooling stage.

[0041] In some embodiments, the nucleation layer thickness is 100~350nm. Within this thickness range, the pulsed aluminum nitride structure layer can effectively function: it can form a stable initial nucleation interface, and through a multi-level stress management mechanism of the first, second, and third nucleation layers, it can fully buffer the lattice mismatch and thermal stress between the substrate and subsequent layers, reduce the penetration dislocation density, provide a good lattice fit foundation for the buffer layer and other subsequent layers, help suppress epitaxial wafer cracks, and ensure crystal quality. If the thickness is less than 100nm, the nucleation layer cannot fully achieve stress buffering and lattice fit, resulting in incomplete initial nucleation, which will lead to increased defect density in subsequent layer growth, stress concentration, and easy induction of cracks. If the thickness is greater than 350nm, the excessively thick nucleation layer itself will accumulate stress, and the stress release will be uneven during cooling, which will increase the risk of cracks and may also affect the interface quality with the buffer layer, weaken the overall stress control effect, and be detrimental to the integrity and electrical performance of the epitaxial structure.

[0042] In some examples, the thicknesses of the first, second, and third core layers are 15-30 nm, 30-90 nm, and 55-230 nm, respectively. For example, the thickness of the first core layer can be 15 nm, 18 nm, 25 nm, 30 nm, or any value within the range of any two of these values; the thickness of the second core layer can be 30 nm, 45 nm, 58 nm, 75 nm, 80 nm, 90 nm, or any value within the range of any two of these values; and the thickness of the third core layer can be 55 nm, 75 nm, 89 nm, 130 nm, 180 nm, 200 nm, 230 nm, or any value within the range of any two of these values.

[0043] For example, from bottom to top, a first core layer is stacked on a substrate layer, a buffer layer (a first superlattice structure layer) is stacked on a third core layer, and a second core layer is stacked between the first and third core layers.

[0044] In some embodiments, such as Figure 3 As shown, the third core layer 23 includes at least two sub-layers 231 stacked together, such as two sub-layers 231, three sub-layers 231, four sub-layers 231, or five sub-layers 231.

[0045] In some examples, the aforementioned epitaxial structure employs a pulsed aluminum nitride structure for the nucleation layer and a three-layer superlattice structure for the buffer layer. This significantly reduces curvature changes during epitaxial growth and effectively controls the rate and amount of curvature change during the cooling phase. It can greatly improve the cracking of the epitaxial wafer, ensuring that edge cracks are less than 5 mm even when the total epitaxial thickness of the structure reaches greater than 7.5 micrometers. Furthermore, the high-resistivity layer structure in the epitaxial structure remains intact, thus preventing a decrease in the vertical breakdown voltage performance of the epitaxial structure.

[0046] In some embodiments, the substrate layer material is an 8-inch single crystal silicon wafer, and the thermal expansion coefficient (4.2x10 -6 / ℃) of the single crystal silicon substrate is adapted to the high-aluminum-content superlattice structure (such as AlN / AlGaN, with a thermal expansion coefficient close to 3.5x10 -6 / ℃) in the buffer layer. In combination with the gradient stress regulation mechanism of the buffer layer, the thermal expansion mismatch between the buffer layer and the subsequent GaN layer (about 5.6x10 -6 / ℃) can be effectively buffered. The surface quality of the single crystal silicon wafer is excellent, which ensures the uniformity of the growth of the nucleation layer and also cooperates with the buffer layer to relieve thermal stress and reduce cracks.

[0047] In some embodiments, the high-resistance layer material is carbon-doped gallium nitride, and the doping source in the carbon-doped gallium nitride is at least one of ethylene, acetylene, propane, and butane. Carbon as an acceptor impurity can compensate for the n-type carriers in gallium nitride, reducing the background electron concentration. The above carbon-containing doping source can stably decompose and release carbon elements during the growth process, achieving effective doping. Through carbon doping, the high-resistance layer has high resistivity, meeting the high insulation requirement of high-voltage devices. These doping sources do not introduce silicon and other impurities, avoiding the problem of silicon diffusion similar to the low-temperature SiN insertion layer, and at the same time, the structural integrity of the high-resistance layer is not damaged, unlike the low-temperature AlN insertion layer, which induces defect formation to form a leakage channel, thereby maintaining the low leakage characteristics of the high-resistance layer and ensuring the withstand voltage capability and anti-breakdown performance of the epitaxial structure.

[0048] In some embodiments, the channel layer material is intrinsic gallium nitride, which has the intrinsic characteristics of low impurity concentration and high crystal integrity. As the core layer of the device conductive channel, the intrinsic GaN forms a heterojunction with the aluminum nitride insertion layer and the aluminum gallium nitride barrier layer above it. Through the difference in bandgap width and polarization effect (spontaneous polarization and piezoelectric polarization) between the materials, a high-concentration and high-mobility two-dimensional electron gas (2DEG) is induced at the interface between the channel layer and the barrier layer, serving as the conductive channel of the device. The intrinsic GaN has fewer impurities, which can reduce electron scattering centers and ensure high mobility of the two-dimensional electron gas, improving the conductivity efficiency.

[0049] In some embodiments, the insertion layer material is aluminum nitride. The high bandgap and strong polarization characteristics of aluminum nitride can enhance the polarization electric field between the channel layer and the barrier layer, effectively improving the concentration and mobility of the two-dimensional electron gas (2DEG) and optimizing the conductivity performance of the device. Moreover, by utilizing the differences in lattice and polarization characteristics between AlN and the adjacent GaN channel layer and AlGaN barrier layer, a heterojunction regulation mechanism is constructed, which does not introduce impurity diffusion sources (such as Si) and does not damage the high-resistance layer structure, avoiding the problems of leakage or increased background electron concentration, and achieving good compatibility with the high insulation requirement of the high-resistance layer.

[0050] In some embodiments, the barrier layer material is aluminum gallium nitride, and a high-concentration and high-mobility two-dimensional electron gas (2DEG) is formed at the interface as a conductive channel by taking advantage of the band gap difference between AlGaN (aluminum gallium nitride) and GaN and the polarization effect. The barrier layer of AlGaN material cooperates with the structural design of the buffer layer and the insertion layer to ensure the quality of crystal growth (reduce defects) while not affecting the excellent electrical properties (low leakage and high insulation) of the high-resistance layer, thereby further ensuring the overall withstand voltage capability and anti-breakdown performance of the epitaxial structure on the basis of effectively inhibiting cracks.

[0051] In some embodiments, the buffer layer has a thickness of 4500-6000 nm, and the three-layer superlattice structure can fully play a stress regulation role: the gradually changing lattice constant and thermal expansion coefficient constructed by the aluminum content gradient can effectively balance the lattice mismatch and thermal stress between the substrate and the subsequent layers, dynamically disperse strain energy, and avoid stress concentration; at the same time, this thickness adapts to the transition requirements of the nucleation layer and the high-resistance layer, ensures the stability of the curvature during epitaxial growth, inhibits the initiation and expansion of edge cracks, and does not affect the structural integrity and electrical properties of the high-resistance layer. If the thickness is less than 4500 nm, the buffer layer is too thin, and the stress regulation capability is insufficient, it is difficult to fully release the stress generated by the lattice mismatch and thermal expansion difference, and it is easy to cause stress concentration and trigger cracks. If the thickness is greater than 6000 nm, the over-thick buffer layer will accumulate too much internal stress, and the stress will not be released uniformly during the cooling and rebounding stage, which will increase the risk of crack expansion and may also reduce the uniformity of the epitaxial layer, affecting the stability of the electrical properties of the overall structure.

[0052] In some embodiments, the thicknesses of the first superlattice structure layer, the second superlattice structure layer, and the third superlattice structure layer are 1000-1500 nm, 1500-2000 nm, and 2000-2500 nm, respectively, and gradually increase in thickness, which cooperates with the decreasing aluminum element molar content (first superlattice structure layer > second superlattice structure layer > third superlattice structure layer) to construct a vertically changing lattice constant and thermal expansion coefficient distribution, forming a dynamic stress dispersion mechanism that can accurately balance the thermal expansion and lattice mismatch stress between the substrate (such as an 8-inch single crystal silicon) and the subsequent layers (such as the high-resistance layer and the channel layer), gradually releasing strain energy during the growth process to avoid stress concentration; at the same time, the thickness-increasing superlattice structure enhances the stress regulation capability during the cooling and rebounding stage, effectively controls the curvature change of the epitaxial structure, and reduces the initiation and expansion of edge cracks. In addition, this thickness range adapts to the transition requirements of the nucleation layer and the high-resistance layer, ensuring the uniformity of crystal growth and not damaging the structural integrity of the high-resistance layer, thus ensuring its low leakage and high insulation characteristics, thereby ensuring the vertical breakdown voltage performance.

[0053] If the thickness of the first superlattice structure layer, the second superlattice structure layer and the third superlattice structure layer is less than the corresponding range, the total thickness of the buffer layer is insufficient, the stress regulation ability is weakened, the strain energy cannot be fully dispersed, stress concentration is caused, and cracks are easily induced; and it is difficult to form an effective lattice transition, the crystal defect density of the subsequent layer growth is increased, and the stability of the epitaxial structure is affected. If the thickness of the first superlattice structure layer, the second superlattice structure layer and the third superlattice structure layer exceeds the corresponding range, the over-thick buffer layer will accumulate too much internal stress, the stress is not uniformly released during cooling, and the crack propagation risk is even aggravated; at the same time, the over-thickness will reduce the uniformity of the epitaxial layer, damage the interface quality with the high resistance layer, weaken the overall electrical performance stability, and even cause the mechanical strength of the epitaxial wafer to decrease due to stress accumulation.

[0054] In some embodiments, the thickness of the high resistance layer is 1000-3500 nm, which can fully exert the high resistance characteristics of the carbon-doped gallium nitride: it can provide an insulating barrier with sufficient thickness to meet the requirements of high-voltage devices for high insulation and low leakage, and ensure the withstand voltage capability and anti-breakdown performance of the epitaxial wafer; it can also cooperate with the stress regulation mechanism of the buffer layer to avoid stress accumulation caused by its own over-thickness, maintain the structural integrity, reduce the risk of cracks, and adapt to the interface transition with the channel layer without affecting the stability of the overall epitaxial growth. If the thickness is less than 1000 nm, the insulating layer is too thin to effectively block the leakage, which will reduce the withstand voltage capability of the epitaxial wafer and cannot meet the needs of super-high voltage devices. If the thickness is greater than 3500 nm, the over-thick high resistance layer will accumulate too much internal stress, superimpose the thermal stress of epitaxial growth, easily cause crack initiation and propagation, and possibly damage the interface quality with the buffer layer and the channel layer, affecting the overall structural integrity and electrical performance stability.

[0055] In some embodiments, the thickness of the channel layer is 150-350 nm, and the material of the channel layer is intrinsic gallium nitride. The intrinsic gallium nitride can form a stable heterojunction with the insertion layer (aluminum nitride) and the barrier layer (aluminum gallium nitride), and the channel layer within the thickness range adapts to the demand of polarization effect, can provide sufficient space for two-dimensional electron gas (2DEG), reduce electron scattering, ensure high mobility of 2DEG, and ensure efficient and stable conduction channel; at the same time, the thickness matches the structure of the upper and lower layers, can balance the lattice stress, avoid stress concentration caused by improper thickness, cooperate with the stress regulation of the buffer layer, reduce the risk of cracks, and do not affect the electrical performance of the high resistance layer. If the thickness is less than 150 nm, the channel layer is too thin to stably accommodate 2DEG, the electron mobility decreases, and the electrical conductivity decreases; and it may aggravate the lattice mismatch with the upper and lower layers, and increase the interface defects. If the thickness is greater than 350 nm, the over-thick intrinsic gallium nitride will cause the background carrier concentration in the channel layer to be too high, affecting the withstand voltage performance of the device.

[0056] In some embodiments, the thickness of the insertion layer is 0.5-1.5 nm. The thinness of the insertion layer can effectively reduce the lattice mismatch between the AlGaN barrier layer and the GaN channel layer, and reduce the interface defect density. Meanwhile, the thickness range of the insertion layer can meet the requirement of the polarization effect, enhance the concentration and stability of the interface two-dimensional electron gas (2DEG), and ensure the performance of the conductive channel without causing additional stress due to the over-thickness, and maintain the structural integrity in cooperation with other layers, without affecting the low leakage and high insulation characteristics of the high-resistance layer. If the thickness is less than 0.5 nm, it is difficult to fully buffer the lattice mismatch, the interface defects increase, the polarization effect is weakened, and the stability of 2DEG is reduced, which affects the conductive performance. If the thickness is greater than 1.5 nm, the over-thickness will cause an increase in interface defects and a decrease in barrier polarization effect, resulting in a decrease in device performance.

[0057] In some embodiments, the thickness of the barrier layer is 10-25 nm. The AlGaN can fully exert the heterojunction characteristics with the channel layer. The barrier layer with the thickness range can meet the requirement of the polarization effect, generate a sufficient concentration of two-dimensional electron gas (2DEG) through spontaneous polarization and piezoelectric polarization, and ensure the efficient and stable conductive channel. Meanwhile, the thickness can balance the lattice mismatch with the channel layer, reduce the interface defects, provide a high breakdown field strength, and meet the voltage withstand requirement of high-voltage devices.

[0058] If the thickness is less than 10 nm, the over-thin barrier layer will weaken the polarization effect, cause insufficient 2DEG concentration, reduce the conductive performance, and cause insufficient barrier height and reduced breakdown voltage, which cannot meet the requirement of super-high voltage devices. If the thickness is greater than 25 nm, the barrier relaxation will be enhanced, the polarization effect will be weakened, and the conductive ability will be reduced.

[0059] According to a second aspect of the present application, as shown in Figure 4 the preparation method of the above-mentioned first aspect epitaxial structure comprises the following steps: Step one, providing a substrate layer; Step two, forming a nucleation layer on the substrate layer; Step three, forming a buffer layer on the nucleation layer, Step four, forming a high-resistance layer on the buffer layer; Step five, forming a channel layer on the high-resistance layer; Step six, forming an insertion layer on the channel layer; Step seven, forming a barrier layer on the insertion layer.

[0060] In some embodiments, the formation of the nucleation layer, the buffer layer, the high-resistance layer, the channel layer, the insertion layer, and the barrier layer adopts at least one of the MOCVD method and the MBE method.

[0061] It can be understood that the MOCVD method is that metal organic compounds (as metal source precursors) and other reaction gases (such as group V hydride in group III-V compound) are carried into a reaction chamber by a carrier gas (usually hydrogen, nitrogen, etc.), and under certain process conditions such as temperature and pressure, thermal decomposition or chemical reaction occurs on the substrate surface, the solid product generated is deposited on the substrate surface, and gradually forms a thin film or epitaxial layer with specific structure and performance, and the gaseous by-product generated by the reaction is discharged from the reaction chamber.

[0062] Therefore, the MOCVD method realizes the controllable growth of materials on the substrate surface by using gas phase chemical reaction, and can realize the accurate control of the composition, thickness, and crystalline quality of the deposited layer by adjusting the reaction temperature, pressure, gas flow, precursor concentration, etc., and is suitable for preparing various semiconductor thin film materials (such as gallium nitride, gallium arsenide, etc.) and related device structures.

[0063] It can be understood that the MBE method (Molecular Beam Epitaxy) is an advanced crystal growth technology for preparing high-quality thin films and epitaxial layers in an ultra-high vacuum environment, and its core principle is to accurately control the molecular beam or atomic beam generated by the material source, so that it is deposited, adsorbed, migrated and epitaxially grown on the heated substrate surface, realizing atomic-level thin film preparation.

[0064] The MBE method is carried out in an ultra-high vacuum environment (usually with a vacuum degree better than 10 -8 Pa), which can minimize impurity pollution and ensure high purity of the epitaxial layer; by adjusting the heating temperature of the material source (such as metal source, gas source) to control the molecular beam intensity, combined with precise adjustment of the substrate temperature, growth time and other parameters, nanoscale or even atomic scale thickness control and component uniformity can be achieved; the growth process can be monitored in real time (such as by a reflection high-energy electron diffraction instrument RHEED), which facilitates dynamic adjustment of the growth conditions and ensures the integrity of the crystal structure.

[0065] The growth temperature of the MBE method is relatively low, which can reduce heat-induced defects, and is especially suitable for preparing complex structures (such as superlattices, quantum wells) sensitive to heat; by alternately controlling the molecular beams of different material sources, the periodic stacking of multilayer heterostructures can be accurately realized, and the interface between layers is steep, which is beneficial to the regulation of the electrical and optical properties of the material. In the preparation of gallium nitride epitaxial structure, the MBE method can accurately control the pulse structure of the nucleation layer, the superlattice gradient component of the buffer layer, and the thickness and doping of each functional layer, which provides key technical support for suppressing cracks and ensuring the performance of high-resistance layers.

[0066] In some embodiments, in step two, the nucleation layer comprises a first nucleation layer, a second nucleation layer, and a third nucleation layer stacked together from bottom to top; The growth conditions of the first nucleation layer are that the reaction temperature is 830-900 DEG C, the reaction pressure is 50-100 mbar, the trimethylaluminum flow rate is 100-200 sccm, the ammonia flow rate is 1-5 slm, the hydrogen flow rate is 150-190 slm, and the growth time is 50 s-250 s. The relatively low temperature environment (830-900 DEG C) is used to promote the uniform distribution of initial nucleation points and avoid defects caused by the aggregation of nucleation points at high temperature. By adjusting the flow rates of aluminum source and nitrogen source and the pressure, the crystallization of aluminum nitride is ensured to be stable, a thin and dense first nucleation layer is formed, a low defect density lattice adaptation basis is provided for the subsequent layer, the generation of threading dislocations is reduced, the stability of linear transition of the second nucleation layer and pulse growth of the third nucleation layer is improved, and finally the stress between the substrate and the epitaxial layer is relieved, the cracks are reduced, and the overall crystal quality of the epitaxial structure is ensured.

[0067] The third nucleation layer at least includes a first sublayer and a second sublayer stacked together from bottom to top. The growth conditions are that the reaction temperature is 1000-1100 DEG C, the reaction pressure is 50-100 mbar, the trimethylaluminum flow rate is 100-300 sccm, the hydrogen flow rate is 130-170 slm, the ammonia flow rates of the first sublayer and the second sublayer are 0.5-5 slm and 10-30 slm respectively, the growth times are 1-2 min and 3-5 min respectively, and the cycle number is 6-20. The relatively high temperature (1000-1100 DEG C) is used to promote atomic migration to improve the crystallization quality. By changing the ammonia flow rate, the nitrogen-aluminum ratio is adjusted to form an aluminum nitride-based structure with alternating components: the low-ammonia-flow sublayer can introduce moderate defects to release stress, and the high-ammonia-flow sublayer can ensure the stability of the stoichiometric ratio. The stress is gradually dispersed through cyclic growth, avoiding concentration. The lattice continuity of the nucleation layer is enhanced, the generation of threading dislocations is reduced, a low-defect growth substrate is provided for the subsequent buffer layer, the mismatch stress between the substrate and the epitaxial layer is relieved, the risk of cracks is reduced, and the crystal quality and stability of the overall epitaxial structure are ensured.

[0068] The second nucleation layer is a linear transition from the first nucleation layer to the first sublayer, and the growth time is 2-10 min.

[0069] For example, the reaction temperature linearly changes from the first nucleation layer growth temperature (830-900 DEG C) to the third nucleation layer growth temperature (1000-1100 DEG C) according to the second nucleation layer growth time (2-10 min), and other conditions such as pressure and flow rate are the same. The growth conditions are started from the growth conditions of the first nucleation layer, uniformly changed to the growth conditions of the first sublayer of the third nucleation layer according to the growth time of the second nucleation layer, the lattice stress is gradually released, and the interface quality is optimized.

[0070] For example, the linear transition of the reaction temperature is: The first nucleation layer growth temperature is 850°C, the third nucleation layer first sublayer growth temperature is 1050°C, and the second nucleation layer growth time is set to 5 min. The temperature starts from 850°C and linearly increases at a rate of 40°C per minute, and reaches 1050°C after 5 min, realizing smooth transition from the low temperature of the first nucleation layer to the high temperature of the first sublayer of the third nucleation layer, avoiding lattice defects caused by sudden temperature change.

[0071] Exemplarily, the linear transition of trimethylaluminum flow is: The trimethylaluminum flow of the first nucleation layer is set to 150 sccm, the trimethylaluminum flow of the first sublayer of the third nucleation layer is set to 250 sccm, and the second nucleation layer growth time is set to 4 min. The flow starts from 150 sccm and increases by 25 sccm per minute, and reaches 250 sccm after 4 min. By gradually adjusting the aluminum source supply, the aluminum element doping concentration of the nucleation layer is balanced, and the interface stress is reduced.

[0072] The linear transition of hydrogen flow is: Exemplarily, the hydrogen flow of the first nucleation layer is set to 180 slm, the hydrogen flow of the first sublayer of the third nucleation layer is set to 140 slm, and the second nucleation layer growth time is set to 8 min. The hydrogen flow starts from 180 slm and decreases by 5 slm per minute, and decreases to 140 slm after 8 min. By gradually changing the carrier gas flow rate, the reaction chamber atmosphere is stabilized, and the influence of gas flow disturbance on nucleation quality is avoided.

[0073] Exemplarily, the linear transition of ammonia flow is: The ammonia flow of the first nucleation layer is set to 3 slm, the ammonia flow of the first sublayer of the third nucleation layer is set to 2 slm, and the second nucleation layer growth time is set to 2 min. The ammonia flow starts from 3 slm and decreases by 0.5 slm per minute, and reaches 2 slm after 2 min. By slowly adjusting the nitrogen source supply, the aluminum source change rhythm is matched, and the stoichiometric ratio of aluminum nitride nucleation is stabilized.

[0074] Exemplarily, the linear transition of reaction pressure is The reaction pressure of the first nucleation layer is set to 80 mbar, the reaction pressure of the first sublayer of the third nucleation layer is set to 60 mbar, and the second nucleation layer growth time is set to 10 min. The pressure starts from 80 mbar and decreases by 2 mbar per minute, and decreases to 60 mbar after 10 min. By gradually changing the pressure, the gas diffusion rate in the reaction chamber is balanced, and the nucleation layer density fluctuation caused by sudden pressure change is reduced.

[0075] In some embodiments, in step three, a buffer layer is formed on the nucleation layer, and the buffer layer comprises a first superlattice structure layer, a second superlattice structure layer, and a third superlattice structure layer stacked together from bottom to top; The growth conditions of the buffer layer are as follows: the reaction temperature is 980-1040℃, the reaction pressure is 50-100 mbar, the trimethylaluminum flow rate is 300-700 sccm, the trimethylgallium flow rate is 80-300 sccm, the ammonia flow rate is 1.5-10 slm, the hydrogen flow rate is 120-150 slm, the growth time of the inner structure (such as AlN / AlGaN or AlGaN / AlGaN or AlGaN / GaN) of the first superlattice structure layer, the second superlattice structure layer and the third superlattice structure layer is 20-60 s, 30-100 s and 100-140 s respectively, the cycle number is 20-60, 60-100 and 100-140 respectively, and the thickness is 1000-1500 nm, 1500-2000 nm and 2000-2500 nm respectively, and the effective aluminum content is 40-55%, 25-35% and 8-15% respectively.

[0076] By periodically alternating stacking of the inner structure of AlN / AlGaN, AlGaN / AlGaN or AlGaN / GaN, combined with a gradient decrease of the aluminum content from 40-55% to 25-35% to 8-15% and an increase of the thickness from 1000-1500 nm to 1500-2000 nm to 2000-2500 nm, together with the reaction temperature of 980-1040℃, the pressure of 50-100 mbar and the specific growth parameters of trimethylaluminum / gallium, ammonia and hydrogen flow rate, a gradually changing lattice constant and thermal expansion coefficient distribution is constructed, which can dynamically disperse the lattice mismatch and thermal stress between the substrate and the subsequent layer, gradually release the strain energy in the growth process, control the curvature of the epitaxial structure to avoid edge cracks, enhance the stress adjustment ability during cooling and reduce crack propagation. At the same time, the superlattice structure does not need to introduce hetero-defects or impurity diffusion sources, which guarantees the integrity of the high-resistance layer and maintains the low leakage and high insulation characteristics, thereby guaranteeing the vertical breakdown voltage performance.

[0077] In some embodiments, in step four, a high-resistance layer is formed on the buffer layer by the MOCVD method; The growth conditions of the high-resistance layer are as follows: the reaction temperature is 970-1020℃, the reaction pressure is 100-200 mbar, the hydrogen flow rate is 80-130 slm, the ammonia flow rate is 10-30 slm, the trimethylgallium flow rate is 250-400 sccm, the ethylene flow rate is 150-400 sccm, and the growth time is 20-50 min.

[0078] In some embodiments, in step five, a channel layer is formed on the high-resistance layer by the MOCVD method; The growth conditions for the channel layer are as follows: reaction temperature of 1030~1060℃, reaction pressure of 200~400mbar, hydrogen flow rate of 90~110slm, ammonia flow rate of 30~45slm, trimethylgallium flow rate of 100~300sccm, and growth time of 15~40min.

[0079] In some embodiments, in step six, an insertion layer is formed on the channel layer by MOCVD. The growth conditions for the insertion layer were as follows: reaction temperature of 1030~1060℃, reaction pressure of 50~150mbar, hydrogen flow rate of 80~110slm, ammonia flow rate of 10~35slm, trimethylaluminum flow rate of 40~120sccm, and growth time of 26s~2min.

[0080] In some embodiments, in step seven, a barrier layer is formed on the insertion layer by MOCVD.

[0081] The growth conditions for the barrier layer are as follows: reaction temperature of 1030~1060℃, reaction pressure of 50~150mbar, hydrogen flow rate of 80~110slm, ammonia flow rate of 10~35slm, trimethylgallium flow rate of 30~60sccm, trimethylaluminum flow rate of 40~120sccm, and growth time of 1.5~5min.

[0082] According to a third aspect of this application, a semiconductor device is provided, comprising the epitaxial structure described in the first aspect, or the epitaxial structure fabricated by the method described in the second aspect. The semiconductor device may include, but is not limited to, power devices, radio frequency devices, etc. Power devices may be, for example, high electron mobility transistors (HEMTs); radio frequency devices may be, for example, radio frequency switches, radio frequency power amplifiers, low noise amplifiers, etc. Because this semiconductor device includes the aforementioned epitaxial structure, it also possesses the various beneficial effects brought about by the aforementioned epitaxial structure, such as high yield and good vertical breakdown voltage performance.

[0083] Example The following examples, using epitaxial wafers as a case study, illustrate the implementation of the epitaxial structure of this application in more detail through embodiments and comparative examples.

[0084] Test methods and equipment Thickness test: The total thickness and distribution of the epitaxial wafer were determined using an Etamax PLATO photoluminescence spectrometer.

[0085] Surface defect distribution test: The surface defects of the epitaxial wafer were detected using a Candela 8720 surface defect detector, with a focus on edge cracks and their length.

[0086] Vertical breakdown voltage test: The vertical breakdown voltage of the epitaxial wafer was measured using a power device analyzer B1505A.

[0087] Example 1-1 The fabrication method of an eight-inch gallium nitride epitaxial wafer is achieved through the following specific process steps; Step 1: Use an 8-inch single-crystal silicon polished wafer as the substrate layer; Step 2: On the substrate, a nucleation layer is formed by MOCVD. The material of the nucleation layer is aluminum nitride. The nucleation layer includes a first nucleation layer, a second nucleation layer, and a third nucleation layer stacked together from bottom to top. The thicknesses of the first nucleation layer, the second nucleation layer, and the third nucleation layer are 15nm, 30nm, and 100nm, respectively.

[0088] The growth conditions for the first core layer are: reaction temperature of 830℃, reaction pressure of 50mbar, trimethylaluminum flow rate of 120sccm, ammonia flow rate of 3slm, hydrogen flow rate of 110slm, and growth time of 120s. The third core layer consists of a first sublayer and a second sublayer stacked from bottom to top. The reaction temperature is 1050℃, the reaction pressure is 70mbar, the trimethylaluminum flow rate is 150sccm, the hydrogen flow rate is 170slm, and the corresponding ammonia flow rates for the first and second sublayers are 0.6slm and 12slm, respectively. The growth times are 1.1min and 3.1min, respectively, and the number of cycles is 6. The second nucleus layer is a linear transition from the growth conditions of the first nucleus layer to the growth conditions of the first daughter layer, with a growth time of 3 minutes.

[0089] Step 3: A buffer layer is formed on the nucleation layer using the MOCVD method. The buffer layer comprises a first superlattice structure layer, a second superlattice structure layer, and a third superlattice structure layer stacked together from bottom to top. The thicknesses of the first superlattice structure layer, the second superlattice structure layer, and the third superlattice structure layer are 1000 nm, 1500 nm, and 2000 nm, respectively, and the aluminum molar contents are 40%, 25%, and 8%, respectively.

[0090] The growth conditions were as follows: reaction temperature 1010℃, reaction pressure 70 mbar, trimethylaluminum flow rate 500 sccm, trimethylgallium flow rate 200 sccm, ammonia flow rate 5 slm, and hydrogen flow rate 135 slm. The growth times for the inner structures of the first, second, and third superlattice layers are 22 s and 35 s, respectively, and the corresponding cycle numbers are 25, 60, and 110, respectively. Step 4: A high-resistivity layer with a thickness of 2500 nm is formed on the third superlattice structure layer by MOCVD. The growth conditions were as follows: reaction temperature 990℃, reaction pressure 150mbar, hydrogen flow rate 100slm, ammonia flow rate 20slm, trimethylgallium flow rate 320sccm, ethylene flow rate 250sccm, and growth time 35min.

[0091] Step 5: Form a channel layer on the high-resistivity layer using MOCVD. The channel layer thickness is 250 nm. The growth conditions were as follows: reaction temperature 1045℃, reaction pressure 200mbar, hydrogen flow rate 100slm, ammonia flow rate 38slm, trimethylgallium flow rate 100sccm, and growth time 18min.

[0092] Step 6: An insertion layer with a thickness of 1 nm is formed on the channel layer using MOCVD. The growth conditions were as follows: reaction temperature 1045℃, reaction pressure 100mbar, hydrogen flow rate 95slm, ammonia flow rate 25slm, trimethylaluminum flow rate 80sccm, and growth time 50s.

[0093] Step 7: On the insertion layer, a barrier layer is formed by MOCVD, with a thickness of 18 nm. The growth conditions were as follows: reaction temperature 1045℃, reaction pressure 100mbar, hydrogen flow rate 95slm, ammonia flow rate 25slm, trimethylgallium flow rate 45sccm, trimethylaluminum flow rate 80sccm, and growth time 3min.

[0094] Examples 1-2 to 1-18 and Comparative Examples 1-1 to 1-6 Except for adjusting the core layer and buffer layer according to Tables 1 and 2, the rest is the same as in Example 1-1.

[0095] The epitaxial wafers prepared in Examples 1-1 to 1-18 and Comparative Examples 1-1 to 1-6 were tested according to the test methods and equipment described above, and the results are summarized in Tables 1 and 2.

[0096] Table 1

[0097] Table 2

[0098] From Table 1, and in conjunction with Examples 1-1 to 1-10, it can be seen that: When the buffer layer parameters are within a reasonable range (aluminum content 40%~55%, 25%~35%, 8%~15%; thickness 1000~1500nm, 1500~2000nm, 2000~2500nm) (as in Examples 1-1 to 1-8), the total epitaxial thickness is >7.5μm, the edge cracks are <5mm (1.9~4.6mm), and the vertical breakdown voltage increases with increasing thickness (942~1002V). Among them, different materials (AlN / AlGaN, AlGaN / AlGaN, AlGaN / GaN) can effectively suppress cracks (2.1~2.3mm), and the vertical breakdown voltage is close (965~981V), indicating that all three materials are suitable for stress control. When the aluminum content is in the middle gradient (45%, 30%, 12%), the cracks are shorter (2.1mm) and the vertical breakdown voltage is higher (986V), reflecting the optimization effect of the aluminum content gradient.

[0099] When the buffer layer parameters exceed the reasonable range, the performance degrades: The buffer layer thickness in Examples 1-9 is too thick (1600nm for the first superlattice structure layer, 2200nm for the second superlattice structure layer, and 2700nm for the third superlattice structure layer), resulting in cracks up to 5.6mm (exceeding 5mm). Although the increased thickness raises the breakdown voltage to 1024V, the cracks exceed the limit. The buffer layer thickness in Examples 1-10 is insufficient (800nm ​​for the first superlattice structure layer, 1300nm for the second superlattice structure layer, and 1800nm ​​for the third superlattice structure layer), with an epitaxial thickness of 7.21μm (<7.5μm). The vertical breakdown voltage drops to 907V, and the vertical breakdown voltage performance is affected by insufficient stress control.

[0100] As can be seen from Examples 1-1 to 1-10, the three-layer superlattice structure (with decreasing aluminum content and increasing thickness, and materials of AlN / AlGaN, AlGaN / AlGaN, or AlGaN / GaN) can effectively control stress, so that the crack is less than 5mm when the epitaxial thickness is >7.5μm, without affecting the integrity of the high-resistivity layer, and ensuring that the breakdown voltage increases with the increase of thickness; if the parameters of the superlattice structure layer are out of range, the crack will increase or the electrical performance will decrease.

[0101] From Table 2, and in conjunction with Examples 1-11 to 1-18, it can be seen that: When the nucleation layer parameters are within a reasonable range (Examples 1-1, 1-11 to 1-14), the epitaxial thickness is >7.5μm, the edge cracks are <5mm (2.3-4.8mm), and the vertical breakdown voltage is stable at 953-982V. Among them, Example 1-1 (first nucleation layer 15nm, second nucleation layer 30nm, third nucleation layer 100nm) has the shortest crack (2.3mm); Example 1-14 (first nucleation layer 30nm, second nucleation layer 90nm, third nucleation layer 230nm, 5 sublayers) has a crack increase to 4.8mm, but still meets the requirements. This shows that increasing the nucleation layer thickness or the number of sublayers within a reasonable range, although slightly increasing the crack size, can maintain structural integrity through cooperation with the buffer layer.

[0102] When the nucleation layer parameters exceed the reasonable range (Examples 1-15 to 1-18), the performance deteriorates significantly: In Example 1-15 (first nucleation layer 10nm < 15nm, second nucleation layer 25nm < 30nm), the crack is 4.2mm, close to the critical value; In Example 1-16 (first nucleation layer 40nm > 30nm, second nucleation layer 100nm > 90nm, third nucleation layer 260nm > 230nm), the crack increases to 15.8mm (far exceeding 5mm); In Example 1-17 (no second nucleation layer, no triple nucleation layer) and Example 1-18 (no first nucleation layer, no second nucleation layer), due to the lack of nucleation layer structure, the cracks reach 21.7mm and 15.5mm respectively, destroying the structural integrity. Although the vertical breakdown voltage of these epitaxial wafers is still relatively high (976-991V), the cracks are seriously unacceptable.

[0103] It is evident that the nucleation layer needs to maintain a structure with the first nucleus layer at 15~30nm, the second nucleus layer at 30~90nm, and the third nucleus layer at 55~230nm, with a sublayer number ≥2. This structure, along with the three superlattice buffer layers, works in synergy to regulate stress, ensuring that the crack size is <5mm when the epitaxial thickness is >7.5μm, thus guaranteeing the performance of the vertical breakdown voltage. Parameters exceeding the range will lead to a surge in cracks and loss of structural integrity.

[0104] From Table 2, and in conjunction with Examples 1-1, Comparative Examples 1-1 to 1-6, it can be seen that: Example 1-1 has an epitaxial thickness of 7.73 μm (>7.5 μm), an edge crack of only 2.3 mm (<5 mm), and a vertical breakdown voltage of 965 V, fully meeting the performance requirements. In contrast, the comparative examples all performed poorly due to structural defects: Comparative Examples 1-1 to 1-3 had cracks of 7.5-11.6 mm (all >5 mm) and vertical breakdown voltages of 851-922 V (lower than the example), indicating stress concentration because the single-layer superlattice could not form a gradient stress; Comparative Example 1-4, lacking a third superlattice, had a crack of 5.6 mm (slightly over 5 mm) and a breakdown voltage of 919 V, indicating incomplete stress control; Comparative Examples 1-5 and 1-6, with incomplete nucleation and buffer layers, had cracks of 24.6-26.1 mm and vertical breakdown voltages of 864-879 V, completely losing their stress control capability.

[0105] In summary, the combination of a three-layer superlattice buffer layer (aluminum content and thickness gradient) with a complete three-layer nucleation layer is the key to achieving a crack thickness of less than 5 mm and ensuring vertical breakdown voltage when the epitaxial thickness is greater than 7.5 μm. Simplifying the structure will lead to a significant reduction in performance.

[0106] It should be noted that, in this document, the terms “comprising,” “including,” or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, or article that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, or article.

[0107] The various embodiments in this specification are described in a related manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0108] The above are merely embodiments of this application and are not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. An epitaxial structure, characterized in that, include: The substrate layer, nucleation layer, buffer layer, high resistivity layer, channel layer, insertion layer, and barrier layer are stacked together from bottom to top. The buffer layer comprises a first superlattice structure layer, a second superlattice structure layer, and a third superlattice structure layer stacked together from bottom to top.

2. The epitaxial structure according to claim 1, characterized in that, The buffer layer satisfies at least one of the following conditions: (1) The molar content of aluminum in the buffer layer satisfies the condition that the first superlattice structure layer > the second superlattice structure layer > the third superlattice structure layer; (2) The thicknesses of the first superlattice structure layer, the second superlattice structure layer, and the third superlattice structure layer are 1000nm~1500nm, 1500nm~2000nm, and 2000nm~2500nm, respectively. (3) The molar contents of aluminum in the first superlattice structure layer, the second superlattice structure layer and the third superlattice structure layer are 40%~55%, 25%~35% and 8%~15%, respectively.

3. The epitaxial structure according to claim 2, characterized in that, The first superlattice structure layer, the second superlattice structure layer, and the third superlattice structure layer are made of at least one of AlN / AlGaN, AlGaN / AlGaN, and AlGaN / GaN.

4. The epitaxial structure according to any one of claims 1 to 3, characterized in that, The nucleation layer comprises a first nucleus layer, a second nucleus layer, and a third nucleus layer stacked together from bottom to top.

5. The epitaxial structure according to claim 4, characterized in that, The nucleation layer satisfies at least one of the following conditions: (1) The thicknesses of the first core layer, the second core layer, and the third core layer are 15nm~30nm, 30nm~90nm, and 55nm~230nm, respectively; (2) The third core layer comprises at least two sub-layers stacked together in sequence.

6. The epitaxial structure according to claim 1, characterized in that, The epitaxial structure satisfies at least one of the following conditions: (1) The substrate is an 8-inch single-crystal silicon polished wafer; (2) The nucleation layer material is aluminum nitride. (3) The high-resistivity layer material is gallium carbon nitride, and the doping source in the gallium carbon nitride is at least one of ethylene, acetylene, propane, and butane; (4) The channel layer material is intrinsic gallium nitride; (5) The insert layer material is aluminum nitride; (6) The barrier layer material is aluminum gallium nitride; (7) The thickness of the high-resistivity layer is 1000nm~3500nm; (8) The thickness of the channel layer is 150nm~350nm; (9) The thickness of the insertion layer is 0.5 nm to 1.5 nm; (10) The thickness of the barrier layer is 10nm~25nm.

7. The method for preparing the epitaxial structure according to any one of claims 1 to 6, characterized in that, Includes the following steps: Step 1: Provide a substrate layer; Step 2: Form the nucleation layer on the substrate layer; Step 3: Form the buffer layer on the nucleation layer. Step four, forming the high-resistivity layer on the buffer layer; Step 5: Form the channel layer on the high-resistivity layer; Step six, forming the insertion layer on the channel layer; Step 7: Form the barrier layer on the insertion layer.

8. The preparation method according to claim 7, characterized in that, In step two, the nucleation layer includes a first nucleus layer, a second nucleus layer, and a third nucleus layer stacked together from bottom to top; The growth conditions for the first core layer are: reaction temperature of 830~900℃, reaction pressure of 50~100mbar, trimethylaluminum flow rate of 100~200sccm, ammonia flow rate of 1~5slm, hydrogen flow rate of 150~190slm, and growth time of 50s~250s. The third core layer includes at least a first sublayer and a second sublayer stacked together from bottom to top. The growth conditions of the third core layer are: reaction temperature of 1000~1100℃, reaction pressure of 50~100mbar, trimethylaluminum flow rate of 100~300sccm, and hydrogen flow rate of 130~170slm. The ammonia flow rates for the first sublayer and the second sublayer are 0.5~5slm and 10~30slm, respectively; the growth times are 1~2min and 3~5min, respectively; and the number of cycles is 6~20. The growth conditions for the second core layer are: a linear transition between the growth conditions of the first core layer and the growth conditions of the first sublayer, with a growth time of 2 to 10 minutes.

9. The preparation method according to claim 7, characterized in that, In step three, the buffer layer includes a first superlattice structure layer, a second superlattice structure layer, and a third superlattice structure layer stacked together from bottom to top; The growth conditions for the buffer layer are as follows: reaction temperature is 980~1040℃, reaction pressure is 50~100mbar, trimethylaluminum flow rate is 300~700sccm, trimethylgallium flow rate is 80~300sccm, ammonia flow rate is 1.5~10slm, and hydrogen flow rate is 120~150slm. Wherein: the growth time of the inner structure of the first superlattice structure layer, the second superlattice structure layer, and the third superlattice structure layer is 20~60s, 30~100s, respectively, and the cycle number of the first superlattice structure layer, the second superlattice structure layer, and the third superlattice structure layer is 20~60, 60~100, and 100~140, respectively.

10. A semiconductor device, characterized in that, It includes the epitaxial structure described in any one of claims 1 to 6, or the epitaxial structure prepared by the preparation method described in any one of claims 7 to 9.

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