A high-quality silicon carbide homoepitaxial wafer and its preparation method

Abstract

This invention discloses a high-quality silicon carbide homoepitaxial wafer and its preparation method. The epitaxial wafer includes an epitaxial layer, a SiC substrate, and a control layer. The control layer is located outside or inside the back side of the substrate, and the epitaxial layer is located on the front side of the substrate. The lattice mismatch between the control layer and the substrate has the same sign as the lattice mismatch between the epitaxial layer and the substrate, but a larger absolute value. The preparation method is as follows: a control layer is prepared on the back side of the SiC substrate; chemical mechanical polishing (CMP) is used to remove the deposition and surface scratches on the front side of the substrate caused in the previous step; an epitaxial layer is grown on the front side of the substrate; finally, CMP is used to remove micro-pits and step-gathering morphology on the surface of the epitaxial layer to obtain the epitaxial wafer. This invention introduces a control layer on the back side of the substrate, which weakens the lattice mismatch between the epitaxial layer and the substrate, reduces dislocation multiplication and slip, and prepares a high-quality silicon carbide homoepitaxial wafer with low defect density and small deformation.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor single crystal thin film technology, and specifically relates to a high-quality silicon carbide homoepitaxial wafer and its preparation method. Background Technology

[0002] Silicon carbide (SiC) is a wide bandgap semiconductor material with properties such as high critical breakdown electric field strength, high electron saturation velocity and high thermal conductivity, making it an ideal material for fabricating high-voltage, high-power power electronic devices.

[0003] The breakdown voltage of SiC power electronic devices is directly proportional to the thickness of the drift layer. Although SiC epitaxy is homogeneous, differences in lattice size and thermal expansion coefficients introduced by variations in doping concentration or type between the substrate and epitaxial layer still result in lattice mismatch. Simultaneously, differences in lattice constants among polymorphs at the locations of defects in the epitaxial layer also introduce localized lattice mismatch. With increasing epitaxial thickness, the strain energy introduced by mismatch stress gradually increases. When the thickness reaches a certain value, the energy for introducing mismatch dislocations becomes more favorable, leading to a sharp increase in the number of defects in thick epitaxial layers. Therefore, for high-resistivity thick-layer SiC epitaxy used in high-power devices, it is necessary to reduce the stress introduced by lattice mismatch between the substrate and epitaxial layer, as well as the resulting dislocation multiplication and slip.

[0004] For n-type doped SiC crystals with nitrogen as the dopant, the incorporation of nitrogen atoms occurs at carbon atom sites. Since the covalent radius of nitrogen atoms is smaller than that of carbon atoms, this leads to a decrease in the lattice constant. Similarly, for p-type doped SiC crystals with aluminum as the dopant, the incorporation of aluminum atoms occurs at silicon atom sites. The covalent radius of aluminum atoms is larger than that of silicon atoms, leading to an increase in the lattice constant. Therefore, the doping state (i.e., whether the dopant element is nitrogen (N) or aluminum (Al) and the doping concentration) has an important influence on the lattice constant of SiC, which is an important material property. In general, the lattice constant α of SiC with different doping types has the following relationship: α Al高浓度掺杂 > a Al低浓度掺杂 > a 非掺 > a N低浓度掺杂 >a N高浓度掺杂 .

[0005] The development of power electronic devices mainly utilizes n-type substrates doped with a high concentration of nitrogen (doping concentration of approximately 1 × 10⁻⁶). 19 cm -3 Some bipolar devices also use p-type substrates with high-concentration Al doping (doping concentration of approximately 2 × 10⁻⁶). 20 cm -3 The core thick epitaxial layer is typically a low-concentration n-type or p-type epitaxial layer (doping concentration 2×10⁻⁶). 14 ~5×10 15 cm -3Due to the lattice mismatch between the substrate and the epitaxial layer, the epitaxial wafer deforms severely when the epitaxial thickness exceeds 100 micrometers, and the number of mismatched dislocations in the epitaxial layer increases rapidly, leading to a decrease in the quality of the epitaxial wafer and subsequent device performance degradation. Summary of the Invention

[0006] Objectives of the invention: The first objective of this invention is to provide a high-quality silicon carbide homoepitaxial wafer with low deformation and low defect density; the second objective of this invention is to provide a method for preparing the high-quality silicon carbide homoepitaxial wafer.

[0007] Technical solution: The high-quality silicon carbide homoepitaxial wafer of the present invention includes an epitaxial layer, a SiC substrate, and a control layer. The control layer is located outside or inside the back side of the substrate, and the epitaxial layer is located on the front side of the substrate. The lattice mismatch between the control layer and the substrate has the same sign as the lattice mismatch between the epitaxial layer and the substrate, but the absolute value is larger.

[0008] This invention utilizes a lattice mismatch control layer fabricated on the back side of a SiC substrate to regulate substrate stress. The doping type, concentration, and thickness of the control layer on the back side are designed based on the doping parameters of the epitaxial layer in the SiC epitaxial structure and the substrate type. The concentration of elemental doping introduces lattice mismatch between the substrate and the control layer; a higher elemental concentration results in a greater absolute value of the introduced lattice mismatch. A greater absolute value of the lattice mismatch leads to greater deformation per unit thickness of the control layer. By changing the thickness of the control layer, the overall deformation of the composite structure of the substrate and control layer can be controlled. A thicker control layer results in greater deformation of the composite structure. By growing the control layer on the back side of the substrate, the deformation of the composite structure is made similar to that of a conventional epitaxial layer grown on the front side of the substrate. The preferred absolute value of the bow (boob) for the composite structure is 20-50 micrometers.

[0009] Preferably, the lattice constant of the epitaxial layer is greater than the lattice constant of the substrate, and the control layer is an aluminum-doped p-type layer.

[0010] Preferably, the lattice constant of the epitaxial layer is smaller than that of the substrate, and the control layer is a nitrogen-doped n-type layer.

[0011] The doping concentration of the control layer is more than two orders of magnitude higher than that of the epitaxial layer. Preferably, the elemental doping concentration of the control layer is 1 × 10⁻⁶. 18 ~ 2×10 20 cm -3 .

[0012] The thickness of the control layer is less than or equal to one-third of the thickness of the epitaxial layer. Preferably, the thickness of the control layer is 0.5 to 100 micrometers.

[0013] The method for preparing high-quality silicon carbide homoepitaxial wafers according to the present invention includes the following steps:

[0014] Step 1: Prepare a control layer on the back side of a SiC substrate by epitaxial deposition or ion implantation.

[0015] Step 2: Chemical mechanical polishing to remove substrate front-side deposits and surface scratches caused in Step 1;

[0016] Step 3: Epitaxial layer is grown on the front side of the substrate treated in Step 2;

[0017] Step 4: Finally, chemical mechanical polishing is performed to remove micro-pits and step-like aggregates on the surface of the epitaxial layer, resulting in the epitaxial wafer.

[0018] Preferably, the control layer is an aluminum-doped p-type layer or a nitrogen-doped n-type layer, prepared by homoepitaxial deposition; the p-type control layer with a thickness of 0.5 to 1 micrometer is prepared by homoepitaxial deposition or ion implantation, wherein the implanted ions are aluminum or other elements with an atomic radius greater than silicon.

[0019] The specific method for preparing the control layer by homogeneous epitaxial deposition growth is as follows: a double-sided polished SiC substrate is placed with the back side facing up in the reaction chamber, the temperature of the reaction chamber is raised to the epitaxial growth temperature under a hydrogen atmosphere, and growth source and doping source are introduced to grow the control layer on the back side of the SiC substrate.

[0020] The specific method for epitaxially depositing and growing an epitaxial layer on the front Si side of the substrate is as follows: the substrate containing the back control layer is placed face up again in the reaction chamber, the temperature of the reaction chamber is raised to the epitaxial growth temperature under a hydrogen atmosphere, and the growth source and doping source are introduced to complete the growth of the required epitaxial layer.

[0021] Preferably, the epitaxial deposition growth temperature is 1550~1650℃.

[0022] Preferably, the growth source for the epitaxial deposition growth consists of a silicon source and a carbon source, wherein the silicon source is silane and / or trichlorosilane, and the carbon source is ethylene and / or propane.

[0023] Preferably, the doping element in the epitaxial deposition growth is aluminum, and the aluminum source is trimethylaluminum.

[0024] Preferably, the doping element in the epitaxial deposition growth is nitrogen, and the nitrogen source is nitrogen gas and / or ammonia gas.

[0025] Invention Mechanism:

[0026] This invention modulates the stress and deformation of a substrate by depositing a lattice mismatch control layer on the back side of the substrate. The lattice mismatch between the control layer and the substrate has the same sign as that between the epitaxial layer and the substrate, but a larger absolute value, effectively weakening the lattice mismatch between the epitaxial layer and the substrate. During the growth of the epitaxial layer on this composite substrate, lattice relaxation preferentially occurs between the substrate and the control layer, with some mismatched dislocations extending into the back side of the substrate, thus releasing stress. Chemical mechanical polishing of the epitaxial layer surface eliminates surface step aggregation morphology and surface micropits, resulting in a high-quality silicon carbide homoepitaxial wafer with low defect density. In subsequent chip fabrication, the mismatch control layer and part of the substrate will be removed through a back-side thinning process.

[0027] (1) Taking the growth of an n-type epitaxial layer with low doping concentration (n-) on a highly doped n-type (n+) SiC substrate as an example, the mechanism is as follows:

[0028] Conventional process: Epitaxial wafers grown on the front side (Si side) deform as follows Figure 1 As shown, the substrate lattice constant is smaller than the epitaxial layer lattice constant, resulting in an epitaxial wafer that bulges upwards (positive bow value), and a certain number of mismatch dislocations exist at the epitaxial layer interface.

[0029] Preparation method of the present invention:

[0030] like Figure 2 As shown in Figure a, an Al-doped p-type high-concentration doped (p+) control layer with a larger lattice constant than that of the epitaxial layer is first grown on the back side (C-plane) of the substrate. The disc of this composite structure has an upward convex (positive bow) shape, and the thicker the p+ layer, the more pronounced the upward convexity.

[0031] like Figure 2 As shown in b, the composite structure wafer is then inverted, resulting in a downward-convex shape (negative bow value). After CMP processing of the Si surface, an n-layer is deposited on the Si surface. The initial deformation of the composite structure offsets the upward-convex deformation introduced during the n-layer growth process, thus reducing the epitaxial wafer deformation value. Simultaneously, due to the greater lattice mismatch between the p+ layer and the substrate, mismatched dislocations accumulate on the back side of the substrate, reducing the probability of formation of the epitaxial layer on the front side.

[0032] (2) Taking the growth of an n-type epitaxial layer with low doping concentration (n-) on a highly doped p-type (p+) SiC substrate as an example, the mechanism is as follows:

[0033] Conventional process: Epitaxial wafers grown on the front side (Si side) deform as follows Figure 3 As shown, the substrate lattice constant is greater than the epitaxial layer lattice constant, resulting in an epitaxial wafer that bulges downward (negative bow value), and there are a certain number of mismatch dislocations at the epitaxial layer interface.

[0034] Preparation method of the present invention:

[0035] like Figure 4 As shown in Figure a, a nitrogen-doped n-type high-concentration doped (n+) control layer with a smaller lattice constant than that of the epitaxial layer is first grown on the back side (C-plane) of the substrate. The disc of this composite structure has a downward convex (negative bow) shape, and the thicker the n+ layer, the more severe the downward convexity.

[0036] like Figure 4 As shown in b, the composite structure wafer is then inverted, resulting in an upwardly convex shape (positive bow value). After CMP processing of the Si surface, an n-layer is deposited on the Si surface. The initial deformation of the composite structure offsets the downward convex deformation introduced during the growth of the n-layer, thus reducing the epitaxial wafer deformation. Simultaneously, due to the greater lattice mismatch between the n+ layer and the substrate, mismatched dislocations accumulate on the back side of the substrate, reducing the probability of formation of the epitaxial layer on the front side.

[0037] Beneficial effects: Compared with the prior art, the present invention has the following significant advantages: (1) The silicon carbide homoepitaxial wafer of the present invention weakens the lattice mismatch between the epitaxial layer and the substrate by introducing a control layer, reduces the deformation of the epitaxial wafer, and suppresses the proliferation and slip of dislocations, thereby reducing the defect density of the silicon carbide homoepitaxial wafer, especially the dislocation density of the basal plane; (2) The method of the present invention is applicable to existing commercial SiC epitaxial furnaces, and the process is compatible with existing conventional epitaxial processes. Attached Figure Description

[0038] Figure 1 A schematic diagram of conventional fabrication processes where the substrate lattice constant is smaller than the epitaxial layer lattice constant.

[0039] Figure 2 The diagram shows the process of this invention where the lattice constant of the substrate is smaller than that of the epitaxial layer. In the diagram, a is a schematic diagram of the growth of the control layer on the back side of the substrate, and b is a schematic diagram of the growth of the epitaxial layer on the front side of the substrate.

[0040] Figure 3 A schematic diagram of conventional fabrication processes where the substrate lattice constant is greater than the epitaxial layer lattice constant.

[0041] Figure 4 The diagram illustrates the process of this invention where the substrate lattice constant is greater than the epitaxial layer lattice constant, where a is a schematic diagram of the growth of the control layer on the back side of the substrate, and b is a schematic diagram of the growth of the epitaxial layer on the front side of the substrate.

[0042] Figure 5 This is a schematic diagram of the epitaxial wafer structure of the present invention;

[0043] Figure 6 This is a sample image from Embodiment 1 of the present invention;

[0044] Figure 7 This is a sample image from Embodiment 2 of the present invention;

[0045] Figure 8 The distribution diagrams of dislocation defects in the epitaxial substrate plane of Embodiment 1 and Comparative Example 1 of the present invention, wherein a corresponds to Comparative Example 1 and b corresponds to Embodiment 1;

[0046] Figure 9 Bow and Warp value diagrams of epitaxial wafers in Embodiment 1 and Comparative Example 1 of the present invention, wherein a corresponds to Comparative Example 1 and b corresponds to Embodiment 1;

[0047] Figure 10 The distribution diagrams of planar dislocation defects on epitaxial substrates in Embodiment 2 and Comparative Example 2 of the present invention, wherein a corresponds to Comparative Example 2 and b corresponds to Embodiment 2;

[0048] Figure 11 The Bow and Warp values ​​of epitaxial wafers in Embodiment 2 and Comparative Example 2 of this invention are shown in the diagram, where a corresponds to Comparative Example 2 and b corresponds to Embodiment 2. Detailed Implementation

[0049] The technical solution of the present invention will be further described below with reference to the embodiments.

[0050] Example 1

[0051] like Figure 5 As shown, the high-quality silicon carbide homoepitaxial wafer of the present invention includes an epitaxial layer 3, a 4H-SiC substrate 1, and a control layer 2. The control layer 2 is located on the outer side of the back surface of the substrate 1, and the epitaxial layer 3 is located on the front surface of the substrate 1. The preparation method includes the following steps:

[0052] Step 1: Determine the parameters of control layer 2. Epitaxial layer 3 has a thickness of 150 micrometers and 2×10⁻⁶ ppm. 14 cm -3 Low concentration n-type doping, substrate 1 is 362 micrometers thick, 1×10 19 cm -3 The substrate is a highly doped n-type 4H-SiC substrate (resistivity 0.018 ohm-cm). The lattice constant of substrate 1 is smaller than that of epitaxial layer 3. The control layer 2 is a highly concentrated Al-doped p-type layer with a doping concentration of 1×10⁻⁶. 19 cm -3 Thickness 50 micrometers;

[0053] Step 2: Place the double-sided polished SiC substrate 1, back side up, in the reaction chamber. Raise the temperature of the reaction chamber to 1630℃ under a hydrogen atmosphere, set the reaction chamber pressure to 100 mbar, and introduce saturated vapors of trichlorosilane, ethylene, and trimethylaluminum at flow rates of 160 sccm, 40 sccm, and 600 sccm, respectively. Control the growth time to 1.5 hours. This will grow a control layer 2 (a high-concentration Al-doped p-type layer with a doping concentration of 1×10⁻⁶) on the back side of the SiC substrate, satisfying the design parameters of Step 1. 19 cm -3 (50 micrometers thick), after growth, it is taken out from the reaction chamber;

[0054] Step 3: Perform front-side chemical mechanical polishing and RCA cleaning on the substrate 1 containing the back-side control layer 2 to eliminate the front-side deposition and surface scratches on the substrate 1 caused in Step 2.

[0055] Step 4: Place the substrate 1, including the backside control layer 2, face up back into the reaction chamber. Raise the temperature of the reaction chamber to 1600℃ under a hydrogen atmosphere, set the reaction chamber pressure to 100 mbar, and introduce trichlorosilane, ethylene, and diluted nitrogen (hydrogen diluted, concentration 1.5%) at flow rates of 350 sccm, 140 sccm, and 30 sccm, respectively. Control the growth time to 2.5 hours to complete the required epitaxial layer 3 (low-concentration n-type layer, doping concentration 2×10⁻⁶). 14 cm -3 The growth process (with a thickness of 150 micrometers) is completed, followed by natural cooling and purging of the reaction chamber with argon gas before removal from the reaction chamber.

[0056] Step 5: Perform positive surface chemical mechanical polishing on epitaxial layer 3 to eliminate surface micropits and step agglomeration morphology, obtaining the final 4H-SiC epitaxial wafer (e.g., Figure 6 (As shown).

[0057] Example 2

[0058] The high-quality silicon carbide homoepitaxial wafer of the present invention includes an epitaxial layer 3, a 4H-SiC substrate 1, and a control layer 2. The control layer 2 is located on the outer side of the back surface of the substrate 1, and the epitaxial layer 3 is located on the front surface of the substrate 1. The preparation method includes the following steps:

[0059] Step 1: Determine the parameters of control layer 2. Epitaxial layer 3 has a thickness of 100 micrometers and a diameter of 5×10⁻⁶ micrometers. 14 cm -3 Low concentration of n-type doping, substrate thickness 367 micrometers, 2×10 20 cm -3 A high-concentration p-type 4H-SiC substrate (resistivity 0.2 ohm-cm) is used, with a substrate lattice constant greater than that of the epitaxial layer. The control layer 2 is a high-concentration nitrogen-doped n-type layer with a doping concentration of 1×10⁻⁶.19 cm -3 Thickness 30 micrometers;

[0060] Step 2: Place the double-sided polished SiC substrate 1, back side up, in the reaction chamber. In a hydrogen atmosphere, raise the temperature of the reaction chamber to 1600℃ and set the pressure to 100 mbar. Introduce trichlorosilane, ethylene, and nitrogen at flow rates of 190 sccm, 50 sccm, and 800 sccm, respectively. Control the growth time to 1 hour. This will grow a control layer 2 (a high-concentration nitrogen-doped n-type layer, 30 micrometers thick, with a doping concentration of 1×10⁻⁶) on the back side of the SiC substrate 1, satisfying the design parameters of Step 1. 19 cm -3 After growth is complete, it is removed from the reaction chamber;

[0061] Step 3: Perform front-side chemical mechanical polishing and RCA cleaning on the substrate 1 containing the back-side control layer 2 to eliminate the front-side deposition and surface scratches on the substrate 1 caused in Step 2.

[0062] Step 4: Place the substrate 1, including the backside control layer 2, face up back into the reaction chamber. Raise the temperature of the reaction chamber to 1600°C under a hydrogen atmosphere. Set the reaction chamber pressure to 100 mbar. Introduce trichlorosilane, ethylene, and diluted nitrogen (hydrogen diluted, concentration 1.5%) at flow rates of 350 sccm, 140 sccm, and 75 sccm, respectively. Control the growth time to 1 hour and 40 minutes to complete the growth of the required epitaxial layer 3 (low-concentration n-type layer, doping concentration 5 × 10⁻⁶). 14 cm -3 (100 micrometers thick), after growth, it is removed from the reaction chamber;

[0063] Step 5: Perform positive surface chemical mechanical polishing on epitaxial layer 3 to eliminate surface micropits and step agglomeration morphology, obtaining the final 4H-SiC epitaxial wafer (e.g., Figure 7 (As shown).

[0064] Comparative Example 1

[0065] Based on Example 1, without introducing a control layer, an epitaxial layer is grown directly on the substrate, while keeping all other conditions unchanged.

[0066] Comparative Example 2

[0067] Based on Example 2, without introducing a control layer, an epitaxial layer is grown directly on the substrate, while keeping all other conditions unchanged.

[0068] The dislocation defects and deformations of the epitaxial wafers prepared in Examples 1-2 and Comparative Examples 1-2 were tested, and the results are as follows: Figures 8-11 As shown.

[0069] Depend on Figure 8From 'a', we can see that the epitaxial wafer prepared by the conventional epitaxial method in Comparative Example 1 has 6801 base plane dislocation defects. Figure 8 As can be seen from b, the epitaxial wafer prepared by the method in Example 1 of this invention has 459 base plane dislocation defects.

[0070] Depend on Figure 9 From 'a', we can obtain that the Bow and Warp of the epitaxial wafer prepared by the conventional epitaxial method in Comparative Example 1 are 61.2 μm and 64.7 μm, respectively. (From...) Figure 9 From b, we can see that the Bow and Warp of the epitaxial wafer prepared by the method in Example 1 of this invention are 17.7 μm and 25.5 μm, respectively.

[0071] Depend on Figure 10 From 'a', we can see that, in Comparative Example 2, the epitaxial substrate prepared by the conventional epitaxial method contained 3100 planar dislocation defects. (From...) Figure 10 As can be seen from b, the epitaxial wafer prepared by the method in Example 2 of this invention has 276 base plane dislocation defects.

[0072] Depend on Figure 11 From 'a', we can obtain that the Bow and Warp of the epitaxial wafer prepared by the conventional epitaxial method in Comparative Example 2 are -63 μm and 146 μm, respectively. Figure 11 From b, we can see that the Bow and Warp of the epitaxial wafer prepared by the method in Example 2 of this invention are -2.2 μm and 26.1 μm, respectively.

Claims

1. A high quality silicon carbide homoepitaxial wafer, characterized by, The epitaxial wafer comprises an epitaxial layer (3), a SiC substrate (1) and a regulation layer (2), the regulation layer (2) is located on the back surface of the substrate (1) or inside the back surface of the substrate (1), and the epitaxial layer (3) is located on the front surface of the substrate (1); wherein the lattice mismatch degree between the regulation layer (2) and the substrate (1) is the same in sign as the lattice mismatch degree between the epitaxial layer (3) and the substrate (1), but the absolute value is larger; the element doping concentration of the regulation layer (2) is higher than the element doping concentration of the epitaxial layer (3) by more than 2 orders of magnitude; the thickness of the regulation layer (2) is less than or equal to one third of the thickness of the epitaxial layer; the lattice constant of the epitaxial layer (3) is smaller than the lattice constant of the substrate (1), and the regulation layer is a nitrogen-doped n-type layer.

2. The high-quality silicon carbide homoepitaxial wafer of claim 1, wherein, The thickness of the regulation layer (2) is 0.5-100 microns.

3. A method of producing a high-quality silicon carbide homoepitaxial wafer according to claim 1, characterized by, The method comprises the following steps: Step one, preparing the regulation layer (2) on the back surface of the SiC substrate (1) by epitaxial deposition growth or ion implantation method; Step two, chemical mechanical polishing to eliminate the deposition on the front surface of the substrate (1) and surface scratches caused in step one; Step three, epitaxial deposition growth of the epitaxial layer (3) on the front surface of the substrate (1) treated in step two; Step four, finally, chemical mechanical polishing to eliminate the surface pits and step coalescence morphology of the epitaxial layer (3), to obtain the epitaxial wafer.

4. The method of claim 3, wherein the high-quality silicon carbide homoepitaxial wafer is prepared by the steps of: The regulation layer (2) is a nitrogen-doped n-type layer prepared by homoepitaxial deposition growth. ​ 5. The method of claim 3, wherein the high-quality silicon carbide homoepitaxial wafer is prepared by the steps of: The epitaxial growth temperature of the epitaxial deposition growth is 1550-1650℃. ​ 6. The method of claim 3, wherein the high-quality silicon carbide homoepitaxial wafer is prepared by the steps of: The growth source of the epitaxial deposition growth is composed of a silicon source and a carbon source, the silicon source is silane and / or trichlorosilane, and the carbon source is ethylene and / or propane. ​ 7. The method of claim 3, wherein the high-quality silicon carbide homoepitaxial wafer is prepared by the steps of: When the doping element of the epitaxial deposition growth is nitrogen element, the nitrogen source is nitrogen and / or ammonia. ​

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