A method and apparatus for predicting the packaging performance of COOLMOS devices

Abstract

This invention relates to the field of semiconductor packaging technology, specifically including a method and apparatus for predicting the packaging performance of COOLMOS devices. The method includes: determining a set of key packaging characteristic parameters; determining a preset performance threshold conforming to industry specifications for power COOLMOS devices; configuring a correction coefficient for the preset performance threshold; setting a dynamic constraint mechanism for packaging stress; combining this with a bonding reliability intervention mechanism; synchronously verifying the predicted packaging performance parameters; and outputting a performance evaluation report for the target COOLMOS device. This invention solves the technical problems of low matching degree between performance thresholds and actual performance degradation patterns, insufficient correlation between prediction verification and risk, and delayed risk warning when COOLMOS device operating conditions fluctuate. It achieves the technical effect of dynamically correcting preset performance thresholds, setting a dynamic constraint mechanism for packaging stress, and controlling the risk of packaging stress evolution through dynamic constraints, thereby improving the accuracy of COOLMOS device packaging performance prediction.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor packaging, in particular to a COOLMOS device packaging performance prediction method and device. BACKGROUND

[0002] As a power semiconductor COOLMOS device with high voltage, high frequency and low loss characteristics, COOLMOS devices are widely used in new energy vehicle inverters, photovoltaic inverters, industrial power supplies and other key power electronic fields. The performance and reliability of COOLMOS devices depend largely on their packaging performance. However, current COOLMOS device packaging performance prediction cannot meet the prediction needs under complex working conditions. A fixed preset performance threshold that meets industry standards is used. When the COOLMOS device operating conditions fluctuate, the threshold does not match the actual performance degradation law, potential performance degradation paths cannot be identified in advance, and passive disposal can only be done after packaging failure, resulting in low accuracy of COOLMOS device packaging performance prediction and delayed risk warning.

[0003] In summary, the prior art has the technical problems of low matching degree of performance threshold and actual performance degradation law when COOLMOS device operating conditions fluctuate, insufficient prediction verification and risk correlation, and delayed risk warning. SUMMARY

[0004] The present application provides a COOLMOS device packaging performance prediction method and device to solve the technical problems of low matching degree of performance threshold and actual performance degradation law when COOLMOS device operating conditions fluctuate, insufficient prediction verification and risk correlation, and delayed risk warning in the prior art.

[0005] In view of the above problems, the technical solution of the present application is as follows:

[0006] In a first aspect, the present application provides a COOLMOS device packaging performance prediction method, wherein the method comprises: using a data bus to connect a performance prediction host, associating model process factors, power level factors, and application condition factors of a target COOLMOS device to determine a set of key packaging characteristic parameters; determining a preset performance threshold that meets the power COOLMOS device industry specification based on the rated operating parameters and packaging reliability standards of the target COOLMOS device; configuring a correction coefficient for the preset performance threshold through chip junction temperature state, packaging stress state, and bonding wire aging state, and setting a packaging stress dynamic constraint mechanism in combination with the set of key packaging characteristic parameters; based on the packaging stress dynamic constraint mechanism and the bonding reliability intervention mechanism, synchronously verifying the packaging performance prediction parameters corresponding to the performance prediction host, and outputting a performance evaluation report of the target COOLMOS device.

[0007] Preferably, the current erosion state, interface delamination state, and bonding wire material fatigue state are used as dynamic correction factors for the preset performance threshold; based on the dynamic correction factors and combined with the key packaging feature parameter set, the bonding reliability intervention mechanism is set.

[0008] Preferably, the bonding degradation features are extracted, and the potential bonding failure acceleration factor is determined by combining the resistance increment value of the bonding degradation features with the thermal stress level at the current junction temperature; the potential bonding failure propagation path is determined by the similarity between the triggering conditions of the historical fracture modes in the bonding degradation features and the current packaging process parameters; and the bonding reliability intervention mechanism is set according to the potential bonding failure acceleration factor and the potential bonding failure propagation path.

[0009] Preferably, the model process factors include doping concentration gradient, wafer defect density, and gate oxide layer thickness data collected based on chip-level monitoring nodes, which are deployed on the active region surface of the target COOLMOS device.

[0010] Preferably, the power rating factor includes bonding wire current density, substrate thermal resistance, and lead frame inductance data collected based on package structure-level monitoring nodes, which are deployed at the connection points between the lead bonds and the substrate.

[0011] Preferably, the application operating conditions include bus voltage fluctuation, load current transient rate, and ambient temperature cycle data collected by the system application-level monitoring node, which is deployed at the interface between the target COOLMOS device and the external circuit.

[0012] Preferably, the bias voltage excitation signal is sent to the chip-level monitoring node, package-level monitoring node, and system application-level monitoring node via the data bus; when the target COOLMOS device is forward-biased, the chip-level monitoring node, package-level monitoring node, and system application-level monitoring node receive the bias voltage excitation signal and use a hierarchical collaborative mechanism based on power loss distribution to perform the allocation and management of performance monitoring tasks.

[0013] Preferably, the system connects to a historical encapsulation failure event database and extracts matching historical events by combining the encapsulation performance feature matrix; it determines the potential performance degradation duration based on the cumulative periodic distribution of encapsulation stress and the current encapsulation stress growth rate of the matching historical events; it determines the potential performance risk impact range based on the matching historical events; and it sets the dynamic constraint mechanism for encapsulation stress based on the potential performance degradation duration and the potential performance risk impact range.

[0014] Preferably, the periodicity and doping concentration of the columnar structure in the N-type drift region, the complementary filling ratio and charge balance of the P-type doped region are determined by the key packaging feature parameter set; feature correlation analysis is performed based on the periodicity and doping concentration of the columnar structure in the N-type drift region, the complementary filling ratio and charge balance of the P-type doped region, to construct the packaging performance feature matrix.

[0015] In a second aspect, this application provides a packaging performance prediction device for COOLMOS devices, comprising: a data bus connection module: using a data bus to connect to a performance prediction host, associating the target COOLMOS device with model process factors, power level factors, and application operating condition factors to determine a set of key packaging characteristic parameters; a preset performance threshold determination module: determining a preset performance threshold conforming to industry specifications for power COOLMOS devices based on the rated operating parameters and packaging reliability standards of the target COOLMOS device; a correction coefficient configuration module: configuring correction coefficients for the preset performance threshold based on chip junction temperature state, packaging stress state, and bond wire aging state, and setting a dynamic packaging stress constraint mechanism in conjunction with the set of key packaging characteristic parameters; and a synchronous verification module: synchronously verifying the packaging performance prediction parameters corresponding to the performance prediction host based on the dynamic packaging stress constraint mechanism and the bond reliability intervention mechanism, and outputting a performance evaluation report for the target COOLMOS device.

[0016] In summary, one or more technical solutions provided in this application achieve the technical effect of dynamically correcting preset performance thresholds, setting dynamic constraint mechanisms for packaging stress, and controlling the risk of packaging stress evolution through dynamic constraints, thereby improving the accuracy of packaging performance prediction for COOLMOS devices. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are merely exemplary. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0018] Figure 1 This application provides a flowchart illustrating a method for predicting the packaging performance of COOLMOS devices.

[0019] Figure 2 This application provides a schematic diagram of the structure of a COOLMOS device packaging performance prediction device.

[0020] Explanation of reference numerals in the attached diagram: Data bus connection module M100, preset performance threshold determination module M200, correction coefficient configuration module M300, and synchronization verification module M400. Detailed Implementation

[0021] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. It should be understood that this application is not limited to the exemplary embodiments described herein. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application. It should also be noted that, for ease of description, only the parts related to this application are shown in the accompanying drawings, not all of them.

[0022] Example 1: The present application will be described in detail below with reference to the accompanying drawings, as follows... Figure 1 As shown, this application provides a method for predicting the packaging performance of a COOLMOS device, wherein the method includes:

[0023] S1: Use the data bus to connect to the performance prediction host, associate the model process factors, power level factors, and application condition factors of the target COOLMOS device, and determine the set of key packaging characteristic parameters; S2: Based on the rated operating parameters and packaging reliability standards of the target COOLMOS device, determine the preset performance threshold that conforms to the industry specifications for power COOLMOS devices.

[0024] It is important to know that the performance and reliability of COOLMOS devices largely depend on their packaging performance. The packaging not only protects the chip from the influence of the external environment, but also undertakes important functions such as heat dissipation and electrical connection. Good packaging performance can effectively improve the heat dissipation efficiency of the device and reduce electrical parasitic parameters, thereby improving the overall performance and reliability of the device. Conversely, poor packaging performance may lead to overheating of the device, deterioration of electrical performance, or even failure, seriously affecting the normal operation of the system.

[0025] Specifically, the data bus connects the performance prediction host and various monitoring nodes of the COOLMOS device to enable real-time data transmission and interaction. The performance prediction host is a central processing unit that receives and processes various data from the COOLMOS device. Model process factors include parameters related to the manufacturing process of the COOLMOS device, such as doping concentration gradient, wafer defect density, and gate oxide layer thickness, which affect the performance and reliability of the COOLMOS device. Power level factors include parameters related to the power handling capability of the COOLMOS device, such as bonding wire current density, substrate thermal resistance, and lead frame inductance, which determine the performance of the COOLMOS device under high power conditions.

[0026] Application operating conditions factors include parameters related to the actual operating environment of COOLMOS devices, such as bus voltage fluctuations, load current transients, and ambient temperature cycling, reflecting the operating conditions of COOLMOS devices in actual applications; the key package characteristic parameter set is a set of parameters that have the greatest impact on package performance by comprehensively considering model process factors, power rating factors, and application operating conditions factors; the preset performance threshold is a performance index set according to the rated operating parameters of COOLMOS devices and package reliability standards, used to evaluate whether the package performance of COOLMOS devices meets industry specifications.

[0027] Execution steps: Connect the performance prediction host to each monitoring node of the COOLMOS device via the data bus to ensure real-time data transmission; collect data on the model process factors, power level factors, and application condition factors of the target COOLMOS device. Specifically, the doping concentration gradient in the model process factors can be collected through chip-level monitoring nodes, the bonding wire current density in the power level factors can be collected through package structure-level monitoring nodes, and the bus voltage fluctuation in the application condition factors can be collected through system application-level monitoring nodes. Based on the collected data, screen out the parameters that have the greatest impact on package performance and determine the set of key package characteristic parameters.

[0028] Based on the rated operating parameters and package reliability standards of the target COOLMOS device, preset performance thresholds conforming to industry specifications for power COOLMOS devices are set to ensure that the COOLMOS device will not be damaged due to excessive current under normal operating conditions. In the above steps, connecting and associating multi-dimensional factors through a data bus comprehensively covers various factors affecting package performance, providing accurate data support for subsequent dynamic correction and verification. Determining the key package characteristic parameter set ensures the representativeness of the input data for the prediction model, while the preset performance thresholds provide a benchmark for subsequent dynamic correction and verification, enabling timely detection of potential performance degradation risks and improving the accuracy of predictions and the timeliness of risk warnings.

[0029] S3: Configure the correction coefficient of the preset performance threshold by considering the chip junction temperature, packaging stress, and bonding wire aging status, and set a dynamic packaging stress constraint mechanism in conjunction with the key packaging feature parameter set; S4: Based on the dynamic packaging stress constraint mechanism and the bonding reliability intervention mechanism, synchronously verify the packaging performance prediction parameters corresponding to the performance prediction host, and output the performance evaluation report of the target COOLMOS device.

[0030] Specifically, the chip junction temperature refers to the temperature of the active region of the chip. The chip junction temperature is one of the factors affecting the performance and reliability of COOLMOS devices. Excessively high junction temperatures may lead to a decrease in the performance of COOLMOS devices or even damage. Packaging stress refers to the stress distribution caused by factors such as differences in thermal expansion coefficients and mechanical stress during the packaging and use process. The packaging stress state reflects the stress level of COOLMOS devices in actual use. Excessively high stress may lead to fatigue and failure of the packaging material. Bond wire aging refers to the performance degradation of bond wires due to factors such as heat and mechanical stress during long-term use. The bond wire aging state reflects the health status of the bond wires. Severely aged bond wires may lead to increased contact resistance or breakage. The correction factor is a coefficient that adjusts the preset performance threshold according to the actual operating conditions. By introducing the correction factor, the performance threshold can be more adapted to changes in actual operating conditions, improving the accuracy of prediction.

[0031] The dynamic packaging stress constraint mechanism refers to the mechanism that dynamically adjusts the packaging stress constraint conditions based on real-time monitoring of the packaging stress state to prevent the stress from exceeding the safe range, effectively managing the evolution risk of packaging stress. The bonding reliability intervention mechanism refers to the mechanism that takes early intervention measures for bonding wire aging and potential failure risks, timely discovering and handling potential problems with the bonding wire, and improving the reliability of the bonding wire. Synchronous verification refers to verifying multiple parameters simultaneously during the prediction process to ensure the accuracy and reliability of the prediction results. Synchronous verification can promptly discover inconsistencies and potential problems between prediction parameters. The performance evaluation report is a report generated based on the prediction results, which includes the packaging performance evaluation results of COOLMOS devices, potential risk warnings, etc. The performance evaluation report can provide important reference for the maintenance and management of COOLMOS devices.

[0032] Execution steps: By monitoring the chip junction temperature, package stress, and bond wire aging status, correction coefficients are configured. Specifically, if an increase in chip junction temperature is detected, it may lead to a decrease in the performance threshold, so the correction coefficient needs to be increased to adjust the threshold. Then, combining the key package feature parameter set and the corrected performance threshold, a dynamic constraint mechanism for package stress is set. Furthermore, if the package stress is detected to be close to the safety upper limit, the constraint conditions for package stress will be automatically adjusted to prevent further stress increase. Based on the dynamic constraint mechanism for package stress and the bond reliability intervention mechanism, the package performance prediction parameters corresponding to the performance prediction host are synchronously verified. Specifically, parameters such as package stress and bond wire resistance are verified simultaneously to ensure the accuracy and reliability of the prediction results.

[0033] Based on the results of synchronous verification, a performance evaluation report for the target COOLMOS device is generated. This report includes the current performance status of the COOLMOS device and potential risk warnings. In the above steps, by dynamically adjusting performance thresholds and setting dynamic constraint mechanisms, the risks of package stress evolution and bond wire aging can be effectively managed. For example, when the package stress is detected to be approaching the safe upper limit, the dynamic constraint mechanism automatically adjusts the constraint conditions to prevent further stress increase. Simultaneously, the bond reliability intervention mechanism can detect potential bond wire problems in advance and take intervention measures to improve bond wire reliability. Synchronous verification ensures the accuracy and consistency of predicted parameters, thereby improving prediction accuracy and the timeliness of risk warnings. The performance evaluation report provides an important reference for the maintenance and management of COOLMOS devices, helping to promptly identify and address potential problems and ensure the reliable operation of COOLMOS devices.

[0034] Furthermore, the method of this application includes:

[0035] The current erosion state, interface delamination state, and bonding wire material fatigue state are used as dynamic correction factors for the preset performance threshold; based on the dynamic correction factors and combined with the key packaging feature parameter set, the bonding reliability intervention mechanism is set.

[0036] Specifically, current erosion refers to the physical and chemical changes that occur on the surface or inside of a material under long-term current, leading to a decline in material performance. Current erosion may affect the conductivity of bonding wires and chip contact points. Interface delamination refers to the delamination phenomenon at the interface between different materials due to differences in thermal expansion coefficients, mechanical stress, and other factors. Interface delamination may lead to poor contact between the chip and the substrate, affecting the performance and reliability of COOLMOS devices. Bonding wire material fatigue refers to the decline in material performance of bonding wires during long-term use due to repeated thermal cycling and mechanical stress, which may result in failure phenomena such as breakage. The dynamic correction factor is a weighting factor that adjusts the preset performance threshold based on the real-time monitoring of current erosion status, interface delamination status, and bonding wire material fatigue status. This allows the performance threshold to better adapt to changes in actual operating conditions and improves the accuracy of predictions. The bonding reliability intervention mechanism refers to a mechanism that takes early intervention measures against bonding wire aging and potential failure risks, promptly identifying and addressing potential problems with the bonding wires, and improving the reliability of the bonding wires.

[0037] Execution steps: Real-time data is acquired by monitoring current erosion status, interface delamination status, and bonding wire material fatigue status. Specifically, high-precision sensors are used to monitor resistance changes caused by current erosion, capacitance changes caused by interface delamination, and mechanical property changes caused by bonding wire material fatigue. A dynamic correction factor for the preset performance threshold is determined. Combining the dynamic correction factor and the key packaging feature parameter set, a bonding reliability intervention mechanism is set. Furthermore, if the capacitance change caused by interface delamination exceeds a certain threshold, the bonding reliability intervention mechanism is activated to take measures to prevent further delamination. The preset performance threshold is adjusted according to the dynamic correction factor to better adapt to changes in actual operating conditions.

[0038] In the above steps, by introducing current erosion state, interface delamination state, and bonding wire material fatigue state as dynamic correction factors, the performance changes of COOLMOS devices in actual operation are more accurately reflected. The dynamic correction factors can make the preset performance threshold more adaptable to the changes in actual operating conditions, thereby improving the accuracy and reliability of prediction. The bonding reliability intervention mechanism can take timely measures to intervene when potential failure risks are detected. Specifically, when bonding wire material fatigue is detected to cause an increase in resistance, the current load can be automatically adjusted to reduce the stress on the bonding wire, thereby extending the service life of the bonding wire.

[0039] Furthermore, the method of this application includes setting the bonding reliability intervention mechanism as follows:

[0040] Extract bonding degradation features, and determine the potential bonding failure acceleration factor by combining the resistance increment value of the bonding degradation features with the thermal stress level at the current junction temperature; determine the potential bonding failure propagation path by the similarity between the triggering conditions of the historical fracture modes in the bonding degradation features and the current packaging process parameters; set the bonding reliability intervention mechanism according to the potential bonding failure acceleration factor and the potential bonding failure propagation path.

[0041] Specifically, bond degradation characteristics refer to the performance degradation of bonded wires due to various factors during long-term use, including increased resistance and decreased mechanical strength, serving as an important indicator for assessing the health status of bonded wires. Resistance increment refers to the increase in resistance caused by degradation during use, reflecting the degree of aging of the bonded wire and being one of the key parameters for assessing its health status. Thermal stress level refers to the stress level caused by factors such as differences in thermal expansion coefficients at the current junction temperature. Thermal stress level is one of the main factors affecting bonded wire reliability; excessive thermal stress may lead to bonded wire breakage. Potential bond failure acceleration factors refer to factors that may accelerate bonded wire failure under current operating conditions, used to assess the risk of bonded wire failure.

[0042] The triggering conditions of historical fracture modes refer to the specific conditions that lead to bond wire fracture in historical data, including specific temperatures, stress levels, current densities, etc.; potential bond failure propagation paths refer to the propagation paths that may lead to bond wire failure under current packaging process parameters. Potential bond failure propagation paths combine the similarity between the triggering conditions of historical fracture modes and current packaging process parameters to predict possible paths for bond wire failure; bond reliability intervention mechanisms refer to preventive measures taken when potential bond failure risks are detected, including adjusting operating conditions, repairing or replacing bond wires, etc., to improve bond wire reliability.

[0043] Execution steps: By monitoring parameters such as the resistance change and mechanical strength of the bond wires, bond degradation characteristics are extracted. Specifically, a high-precision resistance meter is used to monitor the resistance change of the bond wires and record the resistance increment. Combining the resistance increment of the bond degradation characteristics with the thermal stress level at the current junction temperature, the potential bond failure acceleration factor is determined. The similarity between the triggering conditions of historical fracture modes in the bond degradation characteristics and the current packaging process parameters is analyzed to determine the potential bond failure propagation path. Furthermore, if historical data shows that the bond wires are prone to fracture under high current density and high temperature cycling conditions, and the current packaging process parameters are similar to these conditions, the corresponding propagation path can be determined.

[0044] Based on the potential bond failure acceleration factor and the potential bond failure propagation path, a bond reliability intervention mechanism is set up. For example, if the failure acceleration factor is high and the propagation path is clear, measures such as reducing the operating current and optimizing the packaging process can be taken to improve the reliability of the bond wire. In the above steps, by extracting bond degradation characteristics and calculating the potential bond failure acceleration factor, the potential failure risk of the bond wire can be identified in advance. Determining the potential bond failure propagation path helps to predict the specific failure path, thereby taking targeted intervention measures. Furthermore, if a high increase in bond wire resistance and a high level of thermal stress are detected, the operating current can be automatically adjusted to reduce the stress on the bond wire, thereby extending the service life of the bond wire.

[0045] Furthermore, by associating the target COOLMOS device with factors such as model and process technology, power rating, and application conditions, the key package characteristic parameter set is determined. The method in this application includes:

[0046] The process factors mentioned include data on doping concentration gradient, wafer defect density, and gate oxide thickness collected based on chip-level monitoring nodes, which are deployed on the active region surface of the target COOLMOS device.

[0047] Specifically, chip-level monitoring nodes refer to sensors or monitoring devices deployed on the surface of COOLMOS device chips. These devices are used to collect various parameters related to chip performance in real time, possessing high precision and sensitivity, and providing detailed chip status information. Doping concentration gradient refers to the gradient of dopant atom concentration with position in a semiconductor material. This gradient affects the electrical performance of COOLMOS devices, including conductivity and breakdown voltage. Wafer defect density refers to the number of defects per unit area during wafer manufacturing, including crystal defects and impurity contamination, affecting the performance and reliability of COOLMOS devices. Gate oxide thickness refers to the thickness of the insulating oxide layer between the gate and the semiconductor substrate in a COOLMOS device. Gate oxide thickness has a significant impact on the switching characteristics and reliability of COOLMOS devices. The active region surface refers to the area in a COOLMOS device responsible for the main electrical functions, including the source, drain, and gate. Chip-level monitoring nodes are deployed on the active region surface to monitor the status of these critical areas in real time.

[0048] Execution steps: Deploy high-precision chip-level monitoring nodes on the active region surface of the target COOLMOS device. These nodes can acquire data such as doping concentration gradient, wafer defect density, and gate oxide thickness in real time. Specifically, optical sensors are used to measure the doping concentration gradient, a scanning electron microscope is used to measure the wafer defect density, and an elliptic polarization spectrometer is used to measure the gate oxide thickness. The acquired data is then transmitted via a data bus to the performance prediction host for subsequent analysis and processing.

[0049] In the above steps, by deploying chip-level monitoring nodes on the surface of the active region, key parameters such as doping concentration gradient, wafer defect density, and gate oxide layer thickness are collected in real time. This provides detailed information on the COOLMOS device manufacturing process, helping to evaluate the initial performance and potential reliability issues of the COOLMOS device. Commonly, excessively high doping concentration gradients may lead to non-uniform conductivity of the COOLMOS device, high wafer defect density may lead to decreased reliability of the COOLMOS device, and non-uniform gate oxide layer thickness may lead to unstable switching characteristics of the COOLMOS device. Through this data, the set of key packaging characteristic parameters can be determined more accurately, providing a solid foundation for subsequent dynamic correction and verification.

[0050] Furthermore, the method of this application also includes:

[0051] The power rating factors include bonding wire current density, substrate thermal resistance, and lead frame inductance data collected based on package structure-level monitoring nodes deployed at the connection points between the wire bond and the substrate.

[0052] Specifically, package-level monitoring nodes refer to sensors or monitoring devices deployed on the COOLMOS device package structure to collect various parameters related to package performance in real time. They are typically deployed at the wire bond and substrate connection points and can provide detailed package status information. Wire bond current density refers to the ratio of current flowing through the wire bond to its cross-sectional area, reflecting the wire bond's current carrying capacity during operation. Excessively high current density may cause the wire bond to overheat or even melt. Substrate thermal resistance refers to the degree to which the substrate material impedes heat conduction, reflecting the substrate's heat dissipation performance during operation. High thermal resistance may cause COOLMOS devices to overheat, affecting performance and reliability. Leadframe inductance refers to the inductance value generated by the leadframe during operation, reflecting the leadframe's high-frequency signal transmission characteristics. High inductance may lead to signal distortion and power loss. The wire bond and substrate connection point refers to the connection area between the wire bond and the substrate. Package-level monitoring nodes are deployed at this connection point to monitor the connection status of the wire bond and substrate in real time.

[0053] Execution Steps: Deploy Package Structure-Level Monitoring Nodes: Deploy package structure-level monitoring nodes at the connection points between the wire bond and the substrate. These nodes can collect data such as bond wire current density, substrate thermal resistance, and leadframe inductance in real time. For example, a current sensor is used to measure the bond wire current density, a thermal resistance sensor to measure the substrate thermal resistance, and an inductance sensor to measure the leadframe inductance. The collected data is then transmitted to the performance prediction host via a data bus for subsequent analysis and processing.

[0054] In the above steps, by deploying package-level monitoring nodes at the wire bonding and substrate connection points, key parameters such as bond wire current density, substrate thermal resistance, and leadframe inductance can be acquired in real time. These parameters provide detailed performance information of the COOLMOS device under high-power conditions, helping to evaluate the device's heat dissipation performance and current carrying capacity. For example, excessively high bond wire current density may cause the bond wires to overheat or even melt; excessively high substrate thermal resistance may cause the COOLMOS device to overheat, affecting performance and reliability; and excessively high leadframe inductance may lead to signal distortion and power loss. This data allows for a more accurate determination of the key package characteristic parameter set, providing a solid foundation for subsequent dynamic correction and verification.

[0055] Furthermore, the method of this application also includes:

[0056] The application operating conditions include bus voltage fluctuation, load current transient rate, and ambient temperature cycle data collected by the system application-level monitoring node, which is deployed at the interface between the target COOLMOS device and the external circuit.

[0057] Specifically, system application-level monitoring nodes refer to sensors or monitoring devices deployed at the interface between the COOLMOS device and the external circuit, used to collect various parameters related to the actual application environment of the COOLMOS device in real time; bus voltage fluctuation refers to the change of bus voltage over time in a power system. Specifically, in high-voltage applications, voltage fluctuations may affect the stability and reliability of the COOLMOS device; load current transient rate refers to the rate of change of load current in a short period of time. A high transient rate may cause the COOLMOS device to be subjected to excessive current surges, affecting its performance and lifespan; ambient temperature cycling refers to the change of ambient temperature over time in which the COOLMOS device is located. Temperature cycling may cause thermal fatigue of the COOLMOS device material, affecting its reliability; the external circuit interface refers to the part where the COOLMOS device is connected to the external circuit. System application-level monitoring nodes are deployed at the interface between the target COOLMOS device and the external circuit, and can monitor the actual operating conditions of the COOLMOS device in real time.

[0058] Execution steps: Deploy a system application-level monitoring node at the interface between the target COOLMOS device and the external circuit. The system application-level monitoring node can collect data such as bus voltage fluctuation, load current transient rate, and ambient temperature cycle in real time. Through the system application-level monitoring node, real-time data of bus voltage fluctuation, load current transient rate, and ambient temperature cycle are collected. For example, a voltage sensor is used to measure bus voltage fluctuation, a current sensor is used to measure load current transient rate, and a temperature sensor is used to measure ambient temperature cycle. The collected data is transmitted to the performance prediction host through the data bus for subsequent analysis and processing.

[0059] In the steps described above, by deploying system application-level monitoring nodes at the external circuit interface, key parameters such as bus voltage fluctuations, load current transients, and ambient temperature cycling can be collected in real time. These parameters provide detailed operating condition information for the COOLMOS device in actual use, helping to evaluate its performance and reliability under complex operating conditions. Specifically, bus voltage fluctuations may cause the COOLMOS device to experience excessive voltage stress, load current transients may cause it to experience excessive current surges, and ambient temperature cycling may lead to thermal fatigue of the COOLMOS device material. This data allows for a more accurate determination of the key package characteristic parameter set, providing a solid foundation for subsequent dynamic correction and verification.

[0060] Furthermore, the method of this application includes:

[0061] The bias voltage excitation signal is sent to the chip-level monitoring node, package-level monitoring node, and system application-level monitoring node via the data bus. When the target COOLMOS device is forward-biased, the chip-level monitoring node, package-level monitoring node, and system application-level monitoring node receive the bias voltage excitation signal and use a hierarchical collaborative mechanism based on power loss distribution to perform the allocation and management of performance monitoring tasks.

[0062] Specifically, the bias voltage excitation signal is a specific voltage signal used to activate or excite the monitoring node for data acquisition; forward conduction refers to the state in which current flows from the source to the drain of a COOLMOS device in normal operating mode; the hierarchical collaborative mechanism based on power loss distribution is a data processing and task allocation mechanism used to coordinate the work between monitoring nodes at different levels according to the power loss distribution, to allocate monitoring tasks more efficiently, and to ensure the comprehensiveness and accuracy of data acquisition.

[0063] Execution steps: The bias voltage excitation signal is sent to the chip-level monitoring node, package-level monitoring node, and system application-level monitoring node via the data bus. The bias voltage excitation signal is used to activate the monitoring nodes and put them into data acquisition mode. When the target COOLMOS device is in forward conduction, each monitoring node receives the bias voltage excitation signal and begins to execute performance monitoring tasks. The performance monitoring tasks include collecting data such as doping concentration gradient, wafer defect density, gate oxide layer thickness, current density, substrate thermal resistance, lead frame inductance, bus voltage fluctuation, load current transient rate, and ambient temperature cycling.

[0064] A hierarchical collaborative mechanism based on power loss distribution is used to allocate tasks and process data among monitoring nodes at different levels according to the power loss distribution. In the above steps, a bias voltage excitation signal is sent to ensure that monitoring nodes acquire data at appropriate times, avoiding unnecessary energy consumption and data redundancy. Monitoring during the forward conduction of the COOLMOS device allows for the capture of key performance parameters under normal operating conditions, providing accurate data support for subsequent performance evaluation. The hierarchical collaborative mechanism based on power loss distribution can dynamically adjust the allocation of monitoring tasks according to actual operating conditions, improving monitoring efficiency and data accuracy, thereby enabling a more comprehensive evaluation of the performance and reliability of the COOLMOS device.

[0065] Furthermore, by combining the aforementioned key packaging feature parameter set and setting a dynamic constraint mechanism for packaging stress, the method of this application includes:

[0066] Connect to a historical encapsulation failure event database and extract matching historical events using the encapsulation performance feature matrix; determine the potential performance degradation duration based on the cumulative periodic distribution of encapsulation stress and the current encapsulation stress growth rate of the matching historical events; determine the potential performance risk impact range based on the matching historical events; and set the dynamic constraint mechanism for encapsulation stress based on the potential performance degradation duration and the potential performance risk impact range.

[0067] Specifically, the historical package failure event database is a database that stores detailed information on past package failure events, including the cause, conditions, time, and stress accumulation period of the failure, used to analyze and predict future failure risks; the package performance characteristic matrix is ​​used to evaluate package performance and predict potential risks, and is used to describe and store various characteristic parameters of package performance, including stress, temperature, and current density; the package stress accumulation period distribution refers to the time period distribution of stress accumulation leading to failure in historical package failure events, which can help predict the time range within which current package stress accumulation may lead to failure; the current package stress growth rate refers to the rate at which package stress increases over time under current operating conditions.

[0068] The potential performance degradation duration refers to the expected length of time under current operating conditions during which package performance is expected to begin to decline and may continue to decline. This duration is calculated based on historical data and the current stress growth rate. The potential performance risk impact range refers to the expected range of impact from package performance degradation under current operating conditions. This range is determined based on the impact range of historical failure events and the current accumulation of package stress. The dynamic packaging stress constraint mechanism is a mechanism that dynamically adjusts the constraints on package stress based on real-time monitoring of the package stress state to prevent stress from exceeding safe limits. This mechanism can effectively manage the evolution risk of package stress.

[0069] Execution steps: Connect to a historical packaging failure event database via data bus or network to obtain detailed information on past packaging failure events. Combine this with the packaging performance feature matrix to extract historical events that match the current packaging performance characteristics. Specifically, if the current packaging stress level is high, extract historical failure events with similar stress levels. Based on the cumulative periodic distribution of packaging stress in the matching historical events and the current packaging stress growth rate, determine the potential performance degradation duration. Based on the impact range of the matching historical events, determine the potential impact range of the current packaging performance degradation. Specifically, if stress accumulation in a certain area leads to localized failure, predict the potential impact range of the current packaging performance degradation as that area. Based on the potential performance degradation duration and the potential performance risk impact range, set up a dynamic packaging stress constraint mechanism. In the above steps, by connecting to the historical packaging failure event database and extracting matching historical events, past experience can be used to predict potential risks to the current packaging performance. Determining the potential performance degradation duration and the potential performance risk impact range helps the system take preventative measures to prevent performance degradation and failure. Setting up a dynamic packaging stress constraint mechanism can effectively manage the evolution risk of packaging stress and ensure that packaging performance remains within a safe range.

[0070] Furthermore, by combining the extraction of matching historical events from the packaging performance feature matrix, the method of this application also includes:

[0071] Using the key packaging feature parameter set, the periodicity and doping concentration of the columnar structure in the N-type drift region, the complementary filling ratio and charge balance of the P-type doped region are determined; based on the periodicity and doping concentration of the columnar structure in the N-type drift region, the complementary filling ratio and charge balance of the P-type doped region, feature correlation analysis is performed to construct the packaging performance feature matrix.

[0072] Specifically, the columnar structure period in the N-type drift region refers to the repeating interval of the columnar structure in the N-type drift region. The columnar structure period affects the electrical performance of the COOLMOS device, including resistance and breakdown voltage. The doping concentration in the N-type drift region refers to the concentration of doped atoms in the N-type drift region. The doping concentration affects the conductivity and breakdown voltage of the COOLMOS device. The complementary fill ratio in the P-type doped region refers to the filling ratio of complementary doped atoms in the P-type doped region. The complementary fill ratio affects the electrical performance and reliability of the COOLMOS device. The charge balance in the P-type doped region refers to the balance between positive and negative charges in the P-type doped region. The charge balance affects the stability and reliability of the COOLMOS device. Feature correlation analysis is used to find the correlation between different parameters and construct a packaging performance feature matrix. The packaging performance feature matrix is ​​a multi-dimensional data structure used to store and analyze various characteristic parameters of packaging performance, and is used to predict packaging performance and assess potential risks.

[0073] It should be noted that COOLMOS devices are a type of power MOSFET based on a superjunction structure. By alternating P-type doped regions in the N-type drift region, COOLMOS devices form a superjunction structure, which effectively solves the contradiction between on-resistance and breakdown voltage. Furthermore, during forward conduction, the forward current flow path of COOLMOS devices is not affected by the presence of the P-region, and it can still maintain good conduction performance.

[0074] Based on this, the periodicity and doping concentration of the columnar structure in the N-type drift region, as well as the complementary filling ratio and charge balance of the P-type doped region, are determined through a set of key packaging characteristic parameters. The periodicity and doping concentration of the columnar structure in the N-type drift region, and the complementary filling ratio and charge balance of the P-type doped region can be determined by data collected from chip-level monitoring nodes. Based on the determined periodicity and doping concentration of the columnar structure in the N-type drift region, and the complementary filling ratio and charge balance of the P-type doped region, feature correlation analysis is performed. Furthermore, the relationship between the periodicity and doping concentration of the columnar structure, and the relationship between the complementary filling ratio and charge balance are analyzed. Based on the results of the feature correlation analysis, a packaging performance characteristic matrix is ​​constructed.

[0075] In the above steps, by identifying key parameters and performing feature correlation analysis, a comprehensive packaging performance feature matrix can be constructed to evaluate packaging performance and predict potential risks. Specifically, if the columnar structure period of the N-type drift region is short and the doping concentration is high, it may lead to a lower resistance but also a lower breakdown voltage in the COOLMOS device. Through feature correlation analysis, the relationship between these parameters can be discovered and recorded in the packaging performance feature matrix. The packaging performance feature matrix contains all key parameters and their interrelationships, which are used to evaluate packaging performance and predict potential risks, thus accurately assessing packaging performance and predicting potential risks.

[0076] In summary, the beneficial effects of the embodiments of this application are:

[0077] By employing a data bus to connect to the performance prediction host, and associating the target COOLMOS device's model, process factors, power rating, and application conditions, a set of key packaging characteristic parameters is determined. Based on the target COOLMOS device's rated operating parameters and packaging reliability standards, a preset performance threshold conforming to industry specifications for power COOLMOS devices is determined. Correction coefficients for the preset performance threshold are configured using chip junction temperature, packaging stress, and bond wire aging conditions, and a dynamic packaging stress constraint mechanism is set in conjunction with the key packaging characteristic parameter set. Based on this dynamic packaging stress constraint mechanism and bond reliability intervention mechanism, the corresponding packaging performance prediction parameters of the performance prediction host are synchronously verified, and a performance evaluation report for the target COOLMOS device is output. This application provides a method and apparatus for predicting the packaging performance of COOLMOS devices. It achieves the technical effect of dynamically correcting preset performance thresholds, setting a dynamic packaging stress constraint mechanism, and controlling the risk of packaging stress evolution through dynamic constraints, thereby improving the accuracy of COOLMOS device packaging performance prediction.

[0078] Example 2, based on the same inventive concept as the method for predicting the packaging performance of a COOLMOS device in the foregoing examples, such as... Figure 2 As shown in the figure, this application provides a packaging performance prediction device for COOLMOS devices, wherein the device includes:

[0079] Data bus connectivity module M100: Uses the data bus to connect to the performance prediction host, associates the target COOLMOS device with model process factors, power level factors, and application conditions factors, and determines the set of key package characteristic parameters.

[0080] Preset performance threshold determination module M200: Based on the rated operating parameters and package reliability standards of the target COOLMOS device, determine the preset performance threshold that conforms to the industry specifications for power COOLMOS devices.

[0081] Correction coefficient configuration module M300: Configures the correction coefficient of the preset performance threshold by considering the chip junction temperature state, packaging stress state, and bonding wire aging state, and sets a dynamic constraint mechanism for packaging stress in conjunction with the key packaging feature parameter set.

[0082] Synchronous Verification Module M400: Based on the dynamic constraint mechanism of packaging stress and the bonding reliability intervention mechanism, synchronously verifies the packaging performance prediction parameters corresponding to the performance prediction host, and outputs the performance evaluation report of the target COOLMOS device.

[0083] Furthermore, the COOLMOS device packaging performance prediction device is also used to perform the following method:

[0084] The current erosion state, interface delamination state, and bonding wire material fatigue state are used as dynamic correction factors for the preset performance threshold; based on the dynamic correction factors and combined with the key packaging feature parameter set, the bonding reliability intervention mechanism is set.

[0085] Furthermore, the COOLMOS device packaging performance prediction device is also used to perform the following method:

[0086] Extract bonding degradation features, and determine the potential bonding failure acceleration factor by combining the resistance increment value of the bonding degradation features with the thermal stress level at the current junction temperature; determine the potential bonding failure propagation path by the similarity between the triggering conditions of the historical fracture modes in the bonding degradation features and the current packaging process parameters; set the bonding reliability intervention mechanism according to the potential bonding failure acceleration factor and the potential bonding failure propagation path.

[0087] Furthermore, the data bus connectivity module M100 is used to perform the following method:

[0088] The process factors mentioned include data on doping concentration gradient, wafer defect density, and gate oxide thickness collected based on chip-level monitoring nodes, which are deployed on the active region surface of the target COOLMOS device.

[0089] Furthermore, the data bus connectivity module M100 is also used to perform the following method:

[0090] The power rating factors include bonding wire current density, substrate thermal resistance, and lead frame inductance data collected based on package structure-level monitoring nodes deployed at the connection points between the wire bond and the substrate.

[0091] Furthermore, the data bus connectivity module M100 is also used to perform the following method:

[0092] The application operating conditions include bus voltage fluctuation, load current transient rate, and ambient temperature cycle data collected by the system application-level monitoring node, which is deployed at the interface between the target COOLMOS device and the external circuit.

[0093] Furthermore, the data bus connectivity module M100 is also used to perform the following method:

[0094] The bias voltage excitation signal is sent to the chip-level monitoring node, package-level monitoring node, and system application-level monitoring node via the data bus. When the target COOLMOS device is forward-biased, the chip-level monitoring node, package-level monitoring node, and system application-level monitoring node receive the bias voltage excitation signal and use a hierarchical collaborative mechanism based on power loss distribution to perform the allocation and management of performance monitoring tasks.

[0095] Furthermore, the correction coefficient configuration module M300 is used to perform the following method:

[0096] Connect to a historical encapsulation failure event database and extract matching historical events using the encapsulation performance feature matrix; determine the potential performance degradation duration based on the cumulative periodic distribution of encapsulation stress and the current encapsulation stress growth rate of the matching historical events; determine the potential performance risk impact range based on the matching historical events; and set the dynamic constraint mechanism for encapsulation stress based on the potential performance degradation duration and the potential performance risk impact range.

[0097] Furthermore, the correction coefficient configuration module M300 is also used to perform the following method:

[0098] Using the key packaging feature parameter set, the periodicity and doping concentration of the columnar structure in the N-type drift region, the complementary filling ratio and charge balance of the P-type doped region are determined; based on the periodicity and doping concentration of the columnar structure in the N-type drift region, the complementary filling ratio and charge balance of the P-type doped region, feature correlation analysis is performed to construct the packaging performance feature matrix.

[0099] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Figure 1 The packaging performance prediction method and specific example of a COOLMOS device in Embodiment 1 are also applicable to the packaging performance prediction device of a COOLMOS device in this embodiment. Through the foregoing detailed description of the packaging performance prediction method of a COOLMOS device, those skilled in the art can clearly understand the packaging performance prediction device of a COOLMOS device in this embodiment. Therefore, for the sake of brevity, it will not be described in detail here.

[0100] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0101] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of this application and its equivalents, this application also intends to include such modifications and variations.

Claims

1. A method of predicting the packaging performance of a COOLMOS device, characterized by, The method comprises: Using a data bus to connect a performance prediction host, and determining a key packaging characteristic parameter set associated with a model process factor, a power level factor, and an application working condition factor of a target COOLMOS device; According to rated working parameters and packaging reliability standards of the target COOLMOS device, a preset performance threshold value conforming to a power COOLMOS device industry specification is determined; By means of a chip junction temperature state, a packaging stress state, and a bonding wire aging state, a correction coefficient of the preset performance threshold value is configured, and a packaging stress dynamic constraint mechanism is set in combination with the key packaging characteristic parameter set; Based on the packaging stress dynamic constraint mechanism and a bonding reliability intervention mechanism, a packaging performance prediction parameter corresponding to the performance prediction host is synchronously checked, and a performance evaluation report of the target COOLMOS device is output. The method comprises: Taking a current etching state, an interface delamination state, and a bonding wire material fatigue state as a dynamic correction factor of the preset performance threshold value; Based on the dynamic correction factor, the key packaging characteristic parameter set is combined to set the bonding reliability intervention mechanism; The method for setting the bonding reliability intervention mechanism comprises: Extracting a bonding degradation characteristic, and determining a potential bonding failure acceleration factor by means of a resistance increment value of the bonding degradation characteristic and a thermal stress level under a current junction temperature; Determining a potential bonding failure conduction path by means of a similarity between a trigger condition of a historical fracture mode in the bonding degradation characteristic and a current packaging process parameter; According to the potential bonding failure acceleration factor and the potential bonding failure conduction path, the bonding reliability intervention mechanism is set.

2. The method of predicting the packaging performance of a COOLMOS device according to claim 1, wherein, A key packaging characteristic parameter set is determined in association with a model process factor, a power level factor, and an application working condition factor of a target COOLMOS device, and the method comprises: The model process factor comprises data of a doping concentration gradient, wafer defect density, and gate oxide layer thickness collected based on a chip-level monitoring node arranged on a surface of an active region of the target COOLMOS device.

3. The method of predicting the packaging performance of a COOLMOS device according to claim 2, wherein, The method further comprises: The power level factor comprises data of a bonding wire current density, a substrate thermal resistance, and a lead frame inductance collected based on a packaging structure-level monitoring node arranged at a lead bonding and substrate connection part.

4. The method of predicting the packaging performance of a COOLMOS device according to claim 3, wherein, The method further comprises: The application working condition factor comprises data of bus voltage fluctuation, load current transient rate, and environmental temperature cycle collected based on a system application-level monitoring node arranged at an interface end of the target COOLMOS device and an external circuit.

5. The method of predicting the packaging performance of a COOLMOS device according to claim 4, wherein, The method comprises: Through the data bus, a bias voltage excitation signal is sent to the chip-level monitoring node, the packaging structure-level monitoring node, and the system application-level monitoring node; When the target COOLMOS device is forward conducting, the chip-level monitoring node, the packaging structure-level monitoring node, and the system application-level monitoring node receive the bias voltage excitation signal, and a layered collaborative mechanism based on power loss distribution is used to perform allocation management of a performance monitoring task.

6. The method of predicting the packaging performance of a COOLMOS device according to claim 1, wherein, In combination with the set of key packaging characteristic parameters, a packaging stress dynamic constraint mechanism is set, and the method comprises: Connecting a historical packaging failure event library, and extracting a matching historical event in combination with a packaging performance characteristic matrix; With the packaging stress accumulation period distribution of the matching historical event and the current packaging stress growth rate, a potential performance degradation duration is determined; According to the matching historical event, a potential performance risk influence range is determined; According to the potential performance degradation duration and the potential performance risk influence range, the packaging stress dynamic constraint mechanism is set.

7. The method of predicting the packaging performance of a COOLMOS device according to claim 6, wherein, In combination with the extraction of a matching historical event in a packaging performance characteristic matrix, the method further comprises: Through the set of key packaging characteristic parameters, the columnar structure period and doping concentration of the N-type drift region, and the complementary filling ratio and charge balance degree of the P-type doped region are determined; Based on the columnar structure period and doping concentration of the N-type drift region, and the complementary filling ratio and charge balance degree of the P-type doped region, a feature correlation analysis is performed to construct the packaging performance characteristic matrix.

8. An apparatus for predicting the packaging performance of a COOLMOS device, characterized by Steps of a packaging performance prediction method for a COOLMOS device according to any one of claims 1-7, the device comprising: A data bus communication module: using a data bus communication performance prediction host, associating the model process factors, power level factors, and application working condition factors of a target COOLMOS device, and determining a set of key packaging characteristic parameters; A preset performance threshold determination module: according to the rated working parameters and packaging reliability standards of the target COOLMOS device, determining a preset performance threshold that meets the power COOLMOS device industry specifications; A correction coefficient configuration module: through the chip junction temperature state, packaging stress state, and bonding wire aging state, configuring a correction coefficient for the preset performance threshold, and in combination with the set of key packaging characteristic parameters, setting a packaging stress dynamic constraint mechanism; A synchronous verification module: based on the packaging stress dynamic constraint mechanism and the bonding reliability intervention mechanism, performing synchronous verification on the packaging performance prediction parameters corresponding to the performance prediction host, and outputting a performance evaluation report of the target COOLMOS device; The device is also used to perform: Taking the current etching state, interface delamination state, and bonding wire material fatigue state as dynamic correction factors of the preset performance threshold; based on the dynamic correction factors, in combination with the set of key packaging characteristic parameters, setting the bonding reliability intervention mechanism; Extracting bonding degradation features, with the resistance increment value of the bonding degradation features in combination with the thermal stress level at the current junction temperature, determining a potential bonding failure acceleration factor; with the similarity between the trigger conditions of the historical fracture mode in the bonding degradation features and the current packaging process parameters, determining a potential bonding failure conduction path; according to the potential bonding failure acceleration factor and the potential bonding failure conduction path, setting the bonding reliability intervention mechanism.

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