Photonic integrated circuit chip and manufacturing method thereof
By forming trenches on a semiconductor substrate and fabricating a first waveguide, the problem of optical field leakage in edge couplers is solved, transmission loss is reduced, and the integration and assembly reliability of photonic integrated circuit chips are improved.
Patent Information
- Application Number
- CN202511349020.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-19
- Publication Date
- 2025-12-19
AI Technical Summary
When the mode field diameter of the fiber or laser in the edge coupler is large, the mode field optical field will leak into the semiconductor substrate, resulting in increased transmission loss.
A trench is formed on a semiconductor substrate, and a first waveguide is fabricated in the trench. The semiconductor substrate under the first waveguide is reduced or even completely removed. Optical field leakage is reduced and optical coupling efficiency is improved by forming a spacer layer and a second waveguide in the trench.
It reduces transmission loss at the edge coupling, improves the integration and assembly reliability of photonic integrated circuit chips, and reduces the risk of assembly interference between optical fibers and electrical chips.
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Figure CN121165263A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of photonic integrated circuit chip, and particularly to a photonic integrated circuit chip and a manufacturing method thereof. BACKGROUND
[0002] An edge coupler is a key device for coupling light from an optical fiber or a laser to a photonic chip. When the mode field diameter of the optical fiber or the laser is large, the mode field light field will leak into the semiconductor substrate, causing transmission loss of the edge coupler. SUMMARY
[0003] Embodiments of the present application provide a photonic integrated circuit chip and a manufacturing method thereof, to reduce the transmission loss when the first waveguide is edge-coupled with light, to at least partially solve the above technical problems.
[0004] To achieve the above object, according to a first aspect of the present application, a manufacturing method of a photonic integrated circuit chip is provided, comprising:
[0005] providing a semiconductor substrate, the semiconductor substrate comprising a first surface and a second surface opposite to each other along a first direction;
[0006] removing a portion of the semiconductor substrate at the edge to form a trench, wherein the trench extends into the semiconductor substrate from the first surface along the first direction;
[0007] forming a first waveguide in the trench, the first waveguide being used for edge-coupling with light.
[0008] Optionally, the manufacturing method further comprises:
[0009] forming a spacer layer and one or more second waveguides in the trench, the one or more second waveguides being optically coupled to the first waveguide, and the spacer layer being located at least between the one or more second waveguides and the first waveguide.
[0010] Optionally, at least one of the first waveguide and the second waveguide contains nitrogen element and silicon element.
[0011] Optionally, after forming the trench, before forming the first waveguide in the trench, the manufacturing method further comprises: forming an isolation layer at the bottom of the trench.
[0012] Optionally, the semiconductor substrate is further provided with a buried oxygen layer and a silicon layer, and the silicon layer is located on the side of the buried oxygen layer away from the semiconductor substrate along the first direction; the manufacturing method further comprises:
[0013] removing the buried oxygen layer and the silicon layer at the edge, so that the trench penetrates through the buried oxygen layer and the silicon layer along the first direction.
[0014] Optionally, the manufacturing method further comprises:
[0015] removing part of the silicon layer to form a silicon waveguide; wherein the silicon waveguide is coupled to the first waveguide.
[0016] Optionally, the manufacturing method further comprises thinning the second face of the semiconductor substrate to remove the semiconductor substrate remaining under the first waveguide.
[0017] Optionally, the semiconductor substrate further comprises a buried oxide layer and a silicon layer, the silicon layer being located on a side of the buried oxide layer facing away from the semiconductor substrate along the first direction.
[0018] The manufacturing method further comprises removing part of the silicon layer to form a silicon waveguide; wherein the silicon waveguide is coupled to the first waveguide via one or more second waveguides.
[0019] According to a second aspect of the present application, there is provided a photonic integrated circuit chip, comprising:
[0020] a semiconductor substrate comprising a first face and a second face opposite along a first direction;
[0021] a trench extending from the first face to the second face along the first direction and located at an edge of the semiconductor substrate;
[0022] a first waveguide located within the trench, the first waveguide being configured to edge couple with light.
[0023] Optionally, the photonic integrated circuit chip further comprises:
[0024] one or more second waveguides located within the trench and optically coupled to the first waveguide;
[0025] a spacer layer located at least between the one or more second waveguides and the first waveguide.
[0026] Optionally, at least one of the first waveguide and the second waveguide comprises nitrogen and silicon.
[0027] Optionally, the photonic integrated circuit chip further comprises: an isolation layer located within the trench and located on a side of the first waveguide close to the second face.
[0028] Optionally, the photonic integrated circuit chip further comprises:
[0029] a buried oxide layer located on the first face;
[0030] a silicon waveguide located on a side of the buried oxide layer facing away from the semiconductor substrate and optically coupled to the first waveguide.
[0031] Optionally, the photonic integrated circuit chip further comprises:
[0032] a third waveguide located on a side of the buried oxide layer facing away from the semiconductor substrate along the first direction and optically coupled to the first waveguide and the silicon waveguide.
[0033] Optionally, the third waveguide comprises polysilicon, and the third waveguide is in contact with the silicon waveguide.
[0034] Optionally, the third waveguide contains nitrogen and silicon, and there is a gap between the third waveguide and the silicon waveguide.
[0035] In the photonic integrated circuit chip and the manufacturing method thereof, the first waveguide for edge coupling with light is formed in the trench formed on the semiconductor substrate, so as to reduce or even completely remove the semiconductor substrate under the first waveguide, reduce the light field leakage of the semiconductor substrate under the first waveguide, and further reduce the transmission loss of the first waveguide when performing edge coupling. BRIEF DESCRIPTION OF DRAWINGS
[0036] Figure 1 is a flowchart of the manufacturing method of the photonic integrated circuit chip provided in the example embodiment of the present application;
[0037] Figures 2 to 15 is a process diagram of the manufacturing process of the photonic integrated circuit chip provided in the example embodiment of the present application;
[0038] Figure 16 is a structural diagram of the photonic integrated circuit chip and the electric chip assembled together provided in the example embodiment of the present application;
[0039] Figure 17 is another structural diagram of the photonic integrated circuit chip and the electric chip assembled together provided in the example embodiment of the present application.
[0040] LEGEND OF THE DRAWINGS
[0041] 100, photonic integrated circuit chip; 200, electric chip;
[0042] 10, semiconductor substrate; 10A, first surface; 10B, second surface;
[0043] 11, buried oxide layer;
[0044] 12, silicon layer; 121, silicon waveguide;
[0045] 13, trench; 131, bottom surface of the trench; 132, side surface of the trench;
[0046] 141. Initial isolation layer; 142. Isolation layer;
[0047] 151. First waveguide; 152. Second waveguide; 153. Third waveguide; 154. Polycrystalline silicon layer; 155. Silicon nitride layer;
[0048] 16. Spacing layer;
[0049] 171. Dielectric layer; 172. Conductive structure;
[0050] Z, first direction; X, second direction. Detailed Implementation
[0051] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.
[0052] Figure 1 This is a schematic flowchart of a method for manufacturing a photonic integrated circuit chip provided in an exemplary embodiment of this application.
[0053] Please see Figure 1 This application provides a method for manufacturing a photonic integrated circuit chip, which includes the following steps:
[0054] Step S100: Provide a semiconductor substrate, the semiconductor substrate including a first surface and a second surface opposite to each other along a first direction;
[0055] Step S102: Remove a portion of the semiconductor substrate at the edge to form a trench; wherein the trench extends from the first surface into the semiconductor substrate along the first direction;
[0056] Step S104: Form a first waveguide in the trench. The first waveguide is used for edge coupling with light.
[0057] In the method for manufacturing a photonic integrated circuit chip according to the embodiments of this application, a first waveguide for edge coupling with light is formed in a trench formed on a semiconductor substrate, thereby reducing or even completely removing the semiconductor substrate below the first waveguide, reducing the light field leakage of the semiconductor substrate below the first waveguide, and thus reducing the transmission loss of the first waveguide when performing edge coupling.
[0058] The following combination Figures 2 to 17 The process of manufacturing a photonic integrated circuit chip according to embodiments of this application will be described in detail. Among them, Figures 2 to 15 The diagram shows a cross-sectional structure of the manufacturing process of a photonic integrated circuit chip.Figure 16 and Figure 17 A cross-sectional view of a photonic integrated circuit chip combined with an electrical chip and an optical fiber 300 is shown.
[0059] Referring to Figure 2 , the above step S100 is performed.
[0060] The semiconductor substrate 10 includes a first surface 10A and a second surface 10B opposite to each other along a first direction Z. The first surface 10A can be used to form an electrical circuit structure of the photonic integrated circuit chip 100. The semiconductor substrate 10 can include one or more semiconductor layers, one of which includes but is not limited to silicon. Exemplarily, the semiconductor substrate 10 includes a silicon substrate.
[0061] In some embodiments, referring to Figure 2 , the first surface 10A of the semiconductor substrate 10 can further include a buried oxide layer 11 and a silicon layer 12. Along the first direction Z, the silicon layer 12 is located on a side of the buried oxide layer 11 away from the semiconductor substrate 10. The buried oxide layer 11 can include but is not limited to a silicon oxide (SixOy, not limited to stoichiometry, the same below) and other oxide insulating materials. The semiconductor substrate 10, the buried oxide layer 11 and the silicon layer 12 constitute a silicon-on-insulator (SOI).
[0062] Referring to Figure 3 , the above step S102 is performed.
[0063] Embodiments of the present application remove an edge portion of the semiconductor substrate 10 along a second direction X to form a trench 13 at the edge. The trench 13 can have a groove bottom surface 131 and a groove side surface 132 connected to each other.
[0064] The second direction X intersects the first direction Z. Exemplarily, the second direction X is perpendicular to the first direction Z.
[0065] In some embodiments, referring to Figure 3 , the depth of the trench 13 along the first direction Z through the semiconductor substrate 10 is less than the size of the semiconductor substrate 10 along the first direction Z. In this way, the remaining semiconductor substrate 10 under the trench 13 can provide support for subsequent formation of a first waveguide 151 and other waveguides. The first waveguide 151 serves as an edge coupler or as part of an edge coupler.
[0066] In some embodiments, referring to Figure 3It is also shown that the edge-removed buried oxide layer 11 and the silicon layer 12 are removed so that the trench 13 penetrates through the buried oxide layer 11 and the silicon layer 12 along the first direction Z. In this way, the size of the trench 13 along the first direction Z can be larger, and more optical devices can be subsequently formed in the trench 13 to improve the integration of the photonic integrated circuit chip 100 without increasing the overall thickness of the photonic integrated circuit chip 100.
[0067] In some embodiments, the edge-removed silicon layer 12, the buried oxide layer 11, and the semiconductor substrate 10 can be achieved by an etching process. The etching process includes but is not limited to at least one of a dry etching process and a wet etching process. The dry etching process can include but is not limited to a Bosch process dry etching.
[0068] In some embodiments, referring to Figure 2 and Figure 3 , the manufacturing method can further include removing part of the silicon layer 12 to form a silicon waveguide 121. In some embodiments, the removing part of the silicon layer 12 can be performed before forming the trench 13 and during the process of forming the trench 13.
[0069] In some embodiments, referring to Figures 4 to 5 , before the step S104, the manufacturing method further includes forming an isolation layer 142 at the bottom of the trench 13. In this way, the isolation layer 142 can isolate the first waveguide 151 formed later from the remaining semiconductor substrate 10 under the trench 13, and reduce the risk of damaging the first waveguide 151 when the remaining semiconductor substrate 10 under the trench 13 is removed.
[0070] In some embodiments, referring to Figure 4 and Figure 5 , forming the isolation layer 142 at the bottom of the trench 13 includes forming an initial isolation layer 141 to fill the trench 13, and removing part of the initial isolation layer 141, and the remaining initial isolation layer 141 constitutes the isolation layer 142. In this way, by forming the initial isolation layer 141 and removing part of the initial isolation layer 141, the thickness of the remaining isolation layer 142 can be more easily controlled.
[0071] In some embodiments, the isolation layer 142 can include but is not limited to inorganic insulating materials such as silicon oxide.
[0072] In some embodiments, an organic silicon source gas can be used to react with oxygen or ozone to form the initial isolation layer 141 to fill the trench 13. Since the organic silicon source gas is used as a silicon source, the thickness of the initial isolation layer 141 formed can be thicker, which can better fill the trench 13 with a deeper depth. The organic silicon source gas includes but is not limited to tetraethyl orthosilicate (TEOS).
[0073] In some embodiments, the way to remove part of the initial isolation layer 141 can include, but is not limited to, wet etching, so as to better control the thickness of the isolation layer 142.
[0074] In some embodiments, referring to Figure 6 , the above step S104 is performed.
[0075] In some embodiments of the present application, due to the setting of the isolation layer 142 and its lower refractive index relative to the first waveguide 151, the semiconductor substrate 10 under the first waveguide 151 can be reduced or even completely removed, the light field leakage of the semiconductor substrate 10 under the first waveguide 151 is reduced, and the transmission loss of the first waveguide 151 when performing edge coupling is reduced, that is, the optical insertion loss is lower.
[0076] Furthermore, since the first waveguide 151 in the trench 13 can be closer to the second surface 10B of the semiconductor substrate, when the optical fiber 300 is optically coupled with the first waveguide 151, the optical fiber 300 can also be closer to the second surface 10B. In some examples, when the photonic integrated circuit chip 100 is assembled with an electrical chip, the electrical chip is located above the first surface 10A. Since the optical fiber is closer to the second surface 10B, the distance between the electrical chip and the optical fiber is greater, reducing the risk of assembly interference between the optical fiber 300 and the electrical chip, that is, it is beneficial for the combined assembly of multiple chips.
[0077] In addition, since the first waveguide 151 is below the isolation layer 142, the problem of reliability reduction such as fracture or failure caused by the suspension of the first waveguide 151 below can be improved.
[0078] In some embodiments, the first waveguide 151 can be formed by forming a whole first initial waveguide layer, and then patterning the first initial waveguide layer by using a photolithography process and an etching process.
[0079] In some embodiments, the number of the first waveguide 151 can be one or multiple.
[0080] In some embodiments, referring to Figures 7 to 10The manufacturing method further comprises: forming a spacer layer 16 and one or more second waveguides 152 in the trench 13, the one or more second waveguides 152 being optically coupled to the first waveguide 151, and the spacer layer 16 being located between the one or more second waveguides 152 and the first waveguide 151. In this way, in addition to forming the first waveguide 151 in the trench 13, the one or more second waveguides 152 optically coupled to the first waveguide 151 are also formed, so that more waveguides are integrated in the photonic integrated circuit chip 100 and the layout density of the waveguides and the like is increased, and the integration degree of the photonic integrated circuit chip 100 is improved. Moreover, the light of the first waveguide 151 is transmitted to the subsequently formed silicon waveguide 121 by using the one or more second waveguides 152, so that the transmission flexibility between the light and the photonic integrated circuit chip 100 is improved.
[0081] In some embodiments, referring to Figure 8 The second waveguide 152 is evanescently coupled with the first waveguide 151, so that optical coupling is achieved between the adjacent first waveguide 151 and the second waveguide 152.
[0082] The number of the second waveguide 152 can be one or multiple. In some embodiments, referring to Figure 10 When the number of the second waveguide 152 is multiple, the adjacent second waveguides 152 can be evanescently coupled, so that optical coupling is achieved between the adjacent second waveguides 152.
[0083] In some embodiments, the first waveguide 151 and the second waveguide 152 can comprise the same material, so that the first waveguide 151 and the second waveguide 152 can be formed by using the same manufacturing process, and the forming process of the photonic integrated circuit chip 100 is simplified.
[0084] In some embodiments, the material of the first waveguide 151 can be different from the material of the second waveguide 152.
[0085] In some embodiments, at least one of the first waveguide 151 and the second waveguide 152 contains nitrogen and silicon elements, so as to reduce the transmission loss of at least one of the first waveguide 151 and the second waveguide 152, and reduce the difficulty of forming at least one of the first waveguide 151 and the second waveguide 152. In one example, the first waveguide 151 and the second waveguide 152 both comprise silicon nitride.
[0086] When the number of the second waveguide 152 is one, the spacer layer 16 is located between the adjacent first waveguide 151 and the second waveguide 152, so as to isolate the first waveguide 151 and the second waveguide 152 and control the distance between the first waveguide 151 and the second waveguide 152. Please refer to Figure 10When the number of the second waveguides 152 is multiple, the spacing layer 16 is located between adjacent second waveguides 152 to isolate the adjacent second waveguides 152 and control the distance between the adjacent second waveguides 152.
[0087] In some embodiments, the spacing layer 16 has a refractive index less than the refractive index of the first waveguide 151 and the second waveguide 152 to reduce the loss of the light transmitted by the first waveguide 151 and the second waveguide 152.
[0088] In some embodiments, the spacing layer 16 and the isolation layer 142 can include the same material. In one example, the spacing layer 16 and the isolation layer 142 both include silicon oxide.
[0089] In some embodiments, the spacing layer 16 can be formed by a thin film deposition process such as chemical vapor deposition. When the number of the second waveguides 152 is multiple, the spacing layer 16 and the second waveguide 152 are alternately formed, for example, one spacing layer 16 is formed, then one second waveguide 152 is formed, then another spacing layer 16 is formed, and then another second waveguide 152 is formed.
[0090] In some embodiments, referring to Figures 11 to 13 The manufacturing method can further include: forming a third waveguide 153, the third waveguide 153 is located on the side of the one or more second waveguides 152 away from the first waveguide 151 along the first direction Z, and the third waveguide 153 is optically coupled with the one or more second waveguides 152.
[0091] In some embodiments, referring to Figure 11 and Figure 12 The spacing layer 16 can also be located between adjacent third waveguides 153 and second waveguides 152 to isolate the second waveguides 152 and the third waveguides 153 and adjust the distance between the second waveguides 152 and the third waveguides 153.
[0092] In some embodiments, referring to Figure 12 and Figure 13 The adjacent third waveguides 153 and second waveguides 152 can be evanescently coupled to achieve optical coupling between the third waveguides 153 and the second waveguides 152.
[0093] In some embodiments, referring to Figure 12 and Figure 13 Along the second direction X, the third waveguide 153 is located on the side of the silicon waveguide 121, and the third waveguide 153 is optically coupled with the silicon waveguide 121. In this way, the silicon waveguide 121 is optically coupled with the first waveguide 151 through the third waveguide 153 and the one or more second waveguides 152.
[0094] In some embodiments, the third waveguide 153 can not be formed, and the silicon waveguide 121 is optically coupled with the first waveguide 151 through the one or more second waveguides 152; or the third waveguide 153 and the one or more second waveguides 152 are not formed, and the silicon waveguide 121 is directly optically coupled with the one or more first waveguides 151; or the one or more second waveguides 152 are not formed, and the silicon waveguide 121 is optically coupled with the one or more first waveguides 151 through the third waveguide 153.
[0095] In some embodiments, referring to Figure 12 When the third waveguide 153 can include polysilicon, the third waveguide 153 can be in contact with the silicon waveguide 121 to improve the light transmission efficiency. In one example, the third waveguide 153 can include a polysilicon layer 154.
[0096] In some embodiments, referring again to Figure 13 When the third waveguide 153 can include nitrogen element and silicon element, the third waveguide 153 has a gap with the silicon waveguide 121 to improve the light transmission efficiency. In one example, the third waveguide 153 can include a silicon nitride layer 155.
[0097] In some embodiments, the material of the third waveguide 153 can be the same as the material of the second waveguide 152, and both can be formed by the same manufacturing process, which simplifies the manufacturing process of the photonic integrated circuit chip 100.
[0098] In some embodiments, the first waveguide 151, the one or more second waveguides 152, and the third waveguide 153 can be regarded as components of an edge coupler. Since the first waveguide 151 and the one or more second waveguides 152 are both located in the trench 13, at least part of the edge coupler is also located in the trench 13.
[0099] In some embodiments, referring to Figure 14 and Figure 15 The manufacturing method further includes forming a dielectric layer 171 and a conductive structure 172, the dielectric layer 171 covers the third waveguide 153, the silicon waveguide 121, and the spacing layer 16, and the conductive structure 172 is located in the dielectric layer 171.
[0100] In some embodiments, the dielectric layer 171 can include but is not limited to insulating materials such as silicon oxide. The conductive structure 172 can include metal materials such as copper or aluminum. The conductive structure 172 can be used to electrically connect the photonic integrated circuit chip 100 with other structures.
[0101] In some embodiments, referring to Figure 16 and Figure 17The manufacturing method further includes thinning the second surface 10B of the semiconductor substrate 10 to remove the remaining semiconductor substrate 10 under the first waveguide 151. In this way, by removing the semiconductor substrate 10 under the first waveguide, the optical leakage of the substrate is reduced, and the transmission loss is reduced.
[0102] Based on the same inventive concept, please refer to Figure 16 and Figure 17 The embodiments of the present application also provide a photonic integrated circuit chip 100 to reduce the optical leakage of the substrate and reduce the transmission loss.
[0103] Please refer to Figure 16 and Figure 17 The photonic integrated circuit chip 100 includes a semiconductor substrate 10, a trench 13, and a first waveguide 151. The semiconductor substrate 10 includes a first surface 10A and a second surface 10B opposite to each other along a first direction Z; the trench 13 extends from the first surface 10A to the second surface 10B along the first direction Z, i.e., the trench 13 penetrates through the entire semiconductor substrate 10 along the first direction Z and is located at the edge of the semiconductor substrate 10. The first waveguide 151 is located in the trench 13 and is used for edge coupling with light. Exemplarily, the first waveguide 151 is edge coupled with an optical fiber 300.
[0104] In some embodiments, the photonic integrated circuit chip 100 further includes one or more second waveguides 152 and a spacing layer 16. The one or more second waveguides 152 are located in the trench 13 and are optically coupled to the first waveguide 151. The spacing layer 16 is located at least between the one or more second waveguides 152 and the first waveguide 151.
[0105] In some embodiments, at least one of the first waveguide 151 and the second waveguide 152 contains nitrogen and silicon elements.
[0106] In some embodiments, the photonic integrated circuit chip 100 further includes an isolation layer 142. The isolation layer 142 is located in the trench 13 and is located at the side of the first waveguide 151 close to the second surface 10B.
[0107] In some embodiments, the photonic integrated circuit chip 100 further includes a buried oxide layer 11 and a silicon waveguide 121. The buried oxide layer 11 is located on the first surface 10A. The silicon waveguide 121 is located on the side of the buried oxide layer 11 away from the semiconductor substrate 10 and is optically coupled to the first waveguide 151.
[0108] In some embodiments, the photonic integrated circuit chip 100 can further include a third waveguide 153. The third waveguide 153 is located on the side of the buried oxide layer 11 facing away from the semiconductor substrate 10 along the first direction Z, the third waveguide 153 is located on the side of the silicon waveguide 121 along the second direction X, and the third waveguide 153 is optically coupled to the first waveguide 151 and the silicon waveguide 121. Wherein, the first direction Z intersects the second direction X.
[0109] In some embodiments, the third waveguide 153 can be optically coupled to the first waveguide 151 through one or more second waveguides 152.
[0110] In some embodiments, referring to Figure 16 , the third waveguide 153 includes polycrystalline silicon, and the third waveguide 153 is in contact with the silicon waveguide 121.
[0111] In some embodiments, referring to Figure 17 , the third waveguide 153 contains nitrogen and silicon elements, and the third waveguide 153 has a gap with the silicon waveguide 121.
[0112] In some embodiments, the photonic integrated circuit chip 100 further includes a dielectric layer 171 and a conductive structure 172. The dielectric layer 171 covers the third waveguide 153, the silicon waveguide 121 and the spacing layer 16, and the conductive structure 172 is located in the dielectric layer 171. The photonic integrated circuit chip 100 is connected to other structures such as an electrical chip 200 through the conductive structure 172.
[0113] It should be noted that the manufacturing method of the photonic integrated circuit chip 100 described above is also applicable to the photonic integrated circuit chip 100. In order to simplify the description, it will not be described here.
[0114] In the description of the present application, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined as "first", "second" can explicitly or implicitly include one or more features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise specifically limited.
[0115] In the above embodiments, the description of each embodiment has its own emphasis, and the parts not described in detail in a certain embodiment can refer to the related description of other embodiments.
[0116] The embodiments, implementation manners and related technical features of the present application can be combined, replaced with each other without conflict.
[0117] The above are only the preferred embodiments of the present application, and do not limit the present application in any form, but any simple modification, equivalent change and modification made to the above embodiments without departing from the technical solution of the present application and according to the technical essence of the present application are still within the scope of the technical solution of the present application.
Claims
1. A method for manufacturing a photonic integrated circuit chip, characterized in that, include: A semiconductor substrate is provided, the semiconductor substrate including a first surface and a second surface opposite to each other along a first direction; The edge portion of the semiconductor substrate is removed to form a trench; wherein the trench extends from the first surface into the semiconductor substrate along the first direction; A first waveguide is formed in the trench, and the first waveguide is used for edge coupling with light.
2. The manufacturing method as described in claim 1, wherein, The manufacturing method further includes: A spacer layer and one or more second waveguides are formed in the trench, the one or more second waveguides being optically coupled to the first waveguide, and the spacer layer being located at least between one or more second waveguides and the first waveguide.
3. The manufacturing method as described in claim 2, wherein, At least one of the first waveguide and the second waveguide contains nitrogen and silicon.
4. The manufacturing method as described in claim 1, characterized in that, After the trench is formed but before the first waveguide is formed in the trench, the manufacturing method further includes: An isolation layer is formed at the bottom of the trench.
5. The manufacturing method according to any one of claims 1 to 4, wherein, The semiconductor substrate is further provided with a buried oxide layer and a silicon layer, wherein the silicon layer is located on the side of the buried oxide layer away from the semiconductor substrate along the first direction; The manufacturing method further includes: Remove the buried oxide layer and the silicon layer at the edges so that the trench penetrates the buried oxide layer and the silicon layer along the first direction.
6. The manufacturing method as described in claim 5, wherein, The manufacturing method further includes: A portion of the silicon layer is removed to form a silicon waveguide; wherein the silicon waveguide is coupled to the first waveguide.
7. The manufacturing method according to any one of claims 1 to 4, wherein, The manufacturing method further includes: thinning the second side of the semiconductor substrate to remove the remaining semiconductor substrate below the first waveguide.
8. The manufacturing method as described in claim 2, characterized in that, The semiconductor substrate is further provided with a buried oxide layer and a silicon layer, wherein the silicon layer is located on the side of the buried oxide layer away from the semiconductor substrate along the first direction; The manufacturing method further includes: removing a portion of the silicon layer to form a silicon waveguide; wherein the silicon waveguide is coupled to the first waveguide via one or more second waveguides.
9. A photonic integrated circuit chip, characterized in that, include: A semiconductor substrate, including a first surface and a second surface opposite to each other along a first direction; The trench extends along the first direction from the first surface to the second surface and is located at the edge of the semiconductor substrate; A first waveguide, located within the trench, is used for edge coupling with light.
10. The photonic integrated circuit chip as described in claim 9, characterized in that, Also includes: One or more second waveguides are located within the trench and optically coupled to the first waveguide; A spacer layer is located at least between one or more of the second waveguides and the first waveguide.
11. The photonic integrated circuit chip as described in claim 10, characterized in that, At least one of the first waveguide and the second waveguide contains nitrogen and silicon.
12. The photonic integrated circuit chip as described in claim 9, characterized in that, Also includes: An isolation layer is located within the trench and on the side of the first waveguide closer to the second surface.
13. The photonic integrated circuit chip as described in claim 9, characterized in that, Also includes: An oxide layer is embedded on the first surface; A silicon waveguide is located on the side of the buried oxide layer away from the semiconductor substrate and is optically coupled to the first waveguide.
14. The photonic integrated circuit chip as described in claim 13, characterized in that, Also includes: A third waveguide is located along the first direction on the side of the buried oxide layer away from the semiconductor substrate, and is optically coupled to the first waveguide and the silicon waveguide.
15. The photonic integrated circuit chip as described in claim 14, characterized in that, The third waveguide comprises polycrystalline silicon and is in contact with the silicon waveguide.
16. The photonic integrated circuit chip as described in claim 14, characterized in that, The third waveguide contains nitrogen and silicon elements, and there is a gap between the third waveguide and the silicon waveguide.