Second-level cache device, operation method, processor and electronic equipment

Abstract

The invention discloses a second-level cache device, an operation method, a processor and electronic equipment, and belongs to the technical field of computers. The second-level cache device comprises a storage unit used for backing up label information of first-level cache entries and caching second-level cache entries corresponding to the second-level cache device, and the first-level cache entries are entries cached by the first-level cache device; the processing unit is used for processing the cache consistency monitoring request based on the second-level cache entry cached in the storage unit to obtain a first matching result of the second-level cache device and the cache consistency monitoring request; and processing the cache consistency monitoring request based on the label information of the primary cache entry backed up in the storage unit to obtain a second matching result of the primary cache device and the cache consistency monitoring request. On the basis, the efficiency of obtaining the matching result of the cache device and the cache consistency monitoring request is improved.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a secondary cache device, operating method, processor, and electronic device. Background Technology

[0002] In the field of computer technology, to mitigate the adverse effects of the gap between processor processing speed and memory access speed, a caching system is typically set up between the processor and memory. In some multi-core processors, the caching system includes a L1 cache device private to each core, a L2 cache device private to each core, and a L3 cache device shared by all cores. In some scenarios, to ensure cache coherency, the L3 cache device may send cache coherency snoop requests to all or some of the core-private L2 cache devices.

[0003] In related technologies, a secondary cache device includes a storage unit and a processing unit. The storage unit is used to cache secondary cache entries, and the processing unit is used to obtain the matching result between the secondary cache device and the cache consistency monitoring request based on the secondary cache entries cached in the storage unit. The processing unit is also used to forward the cache consistency monitoring request to the primary cache device that is private to the same core, and to receive the matching result between the primary cache device and the cache consistency monitoring request returned by the primary cache device.

[0004] Therefore, the secondary cache needs to interact with the primary cache to obtain the matching result between the primary cache and the cache consistency monitoring request. This process of obtaining the matching result between the cache devices (primary and secondary caches) and the cache consistency monitoring request is inefficient, resulting in low efficiency in cache consistency processing. Furthermore, the process of the primary cache obtaining the matching result can easily interfere with the primary cache's handling of normal access requests, reducing its efficiency in processing normal access requests. Summary of the Invention

[0005] This application provides a secondary cache device, an operating method, a processor, and an electronic device, which can be used to improve the efficiency of obtaining the matching results between the cache device and the cache consistency monitoring request. The technical solution is as follows:

[0006] On the one hand, embodiments of this application provide a secondary cache device, which includes a storage unit and a processing unit;

[0007] The storage unit is used to back up the tag information of the first-level cache entries and cache the second-level cache entries corresponding to the second-level cache device, wherein the first-level cache entries are the entries cached by the first-level cache device;

[0008] The processing unit is configured to process the cache consistency monitoring request based on the second-level cache entries cached in the storage unit to obtain a first matching result between the second-level cache device and the cache consistency monitoring request; and to process the cache consistency monitoring request based on the tag information of the backed-up first-level cache entries in the storage unit to obtain a second matching result between the first-level cache device and the cache consistency monitoring request.

[0009] In one possible implementation, the processing unit includes a first processing module and a second processing module;

[0010] The first processing module is configured to receive the cache consistency monitoring request sent by the level 3 cache device; process the cache consistency monitoring request based on the level 2 cache entries cached in the storage unit to obtain the first matching result; and forward the cache consistency monitoring request to the second processing module.

[0011] The second processing module is used to receive the cache consistency monitoring request forwarded by the first processing module; process the cache consistency monitoring request based on the tag information of the backed-up first-level cache entries in the storage unit, and obtain the second matching result.

[0012] In one possible implementation, the first processing module is further configured to read the data information of the target second-level cache entry from the storage unit and send response information including the data information of the target second-level cache entry to the third-level cache device when the first matching result indicates that the target second-level cache entry in the second-level cache entry is successfully matched with the cache consistency monitoring request and the cache consistency monitoring request is used to request the return of data information.

[0013] In one possible implementation, the first processing module is further configured to send response information to the third-level cache device to indicate that the second-level cache device has successfully matched, and update the status of the target second-level cache entry, when the first matching result indicates that the target second-level cache entry in the second-level cache entry has successfully matched the cache consistency monitoring request and the cache consistency monitoring request is used to request an update of the status.

[0014] In one possible implementation, the second processing module is further configured to: send a read request to the first-level cache device when the second matching result indicates that the target first-level cache entry in the first-level cache entry successfully matches the cache consistency monitoring request and the cache consistency monitoring request is used to request the return of data information; receive the data information of the target first-level cache entry returned by the first-level cache device; and send response information including the data information of the target first-level cache entry to the first processing module.

[0015] The first processing module is also used to forward the response information, which includes the data information of the target first-level cache entry, to the third-level cache device.

[0016] In one possible implementation, the second processing module is further configured to send response information to the first processing module indicating that the first-level cache device has successfully matched, and send an update request to the first-level cache device when the second matching result indicates that the target first-level cache entry in the first-level cache entry has successfully matched the cache consistency monitoring request and the cache consistency monitoring request is used to request an update of the status of the target first-level cache entry.

[0017] The first processing module is also used to forward the response information indicating that the first-level cache device has successfully matched to the third-level cache device.

[0018] In one possible implementation, the cache consistency monitoring request carries a target physical address, and the second-level cache entry corresponds to tag information, the tag information of the second-level cache entry including the physical index of the second-level cache entry and the physical tag of the second-level cache entry;

[0019] The storage unit is configured to determine a target physical index and a target physical tag based on the target physical address; determine candidate secondary cache entries whose physical index matches the target physical index from the secondary cache entries; and determine the first matching result based on the comparison result between the physical tag of the candidate secondary cache entry and the target physical tag.

[0020] In one possible implementation, the cache consistency monitoring request carries a target physical address, and the tag information of the first-level cache entry includes the virtual index of the first-level cache entry and the physical tag of the first-level cache entry;

[0021] The storage unit is configured to determine a target virtual index and a target physical tag based on the target physical address; determine candidate first-level cache entries in the first-level cache entries whose virtual index matches the target virtual index; and determine the second matching result based on the comparison result of the physical tag of the candidate first-level cache entry and the target physical tag.

[0022] In one possible implementation, the storage unit includes a backup module and a cache module, and the secondary cache device further includes an access request processing module;

[0023] The backup module is used to back up the tag information of the first-level cache entries;

[0024] The caching module is used to cache the second-level cache entries;

[0025] The access request processing module is configured to receive a first access request sent by the first-level cache device, the first access request carrying identification information of the filling position; if there is an access second-level cache entry that is hit by the first access request in the second-level cache entries cached by the cache module, the module fills in the tag information of the access second-level cache entry at the filling position of the backup module, and sends a first access result to the first-level cache device, the first access result including the access second-level cache entry.

[0026] In one possible implementation, the storage unit includes a backup module and a cache module, and the secondary cache device further includes an access request processing module;

[0027] The backup module is used to back up the tag information of the first-level cache entries;

[0028] The caching module is used to cache the second-level cache entries;

[0029] The access request processing module is configured to receive a first access request sent by the first-level cache device, the first access request carrying identification information of the filling position; if there is no second-level cache entry in the second-level cache entries cached by the cache module that is matched by the first access request, send a second access request to the third-level cache device; receive the target cache entry returned by the third-level cache device that is matched by the second access request; fill in the tag information corresponding to the target cache entry in the filling position of the backup module, and send a second access result to the first-level cache device, the second access result including the target cache entry.

[0030] On the other hand, a method for operating a secondary cache device is provided, the method comprising:

[0031] The cache consistency monitoring request is processed by the processing unit in the secondary cache device based on the secondary cache entries cached in the storage unit of the secondary cache device, and a first matching result between the secondary cache device and the cache consistency monitoring request is obtained.

[0032] The processing unit processes the cache consistency monitoring request based on the tag information of the backed-up first-level cache entries in the storage unit, and obtains a second matching result between the first-level cache device and the cache consistency monitoring request.

[0033] On the other hand, a processor is provided, the processor including a level 1 cache device, a level 2 cache device and a level 3 cache device, wherein the level 2 cache device is any of the level 2 cache devices described above.

[0034] On the other hand, an electronic device is also provided, which includes the processor as described above.

[0035] The technical solution provided in this application has at least the following beneficial effects:

[0036] The technical solution provided in this application embodiment is that the storage unit in the secondary cache device is used not only to cache secondary cache entries, but also to back up the tag information of primary cache entries. Based on this, after the processing unit in the secondary cache device obtains the cache consistency monitoring request, it can obtain the matching result between the cache device (primary cache device and secondary cache device) and the cache consistency monitoring request without interacting with the primary cache device, which is highly efficient and thus helps to improve the efficiency of cache consistency processing.

[0037] Furthermore, since the process of obtaining the matching result between the first-level cache device and the cache consistency monitoring request is implemented in the second-level cache device, the process of obtaining the matching result between the first-level cache device and the cache consistency monitoring request will not interfere with the first-level cache device's process of processing normal access requests, thus ensuring the efficiency of the first-level cache device in processing normal access requests.

[0038] Furthermore, the secondary cache device only needs to back up the tag information of the primary cache entries to obtain the matching result between the primary cache device and the cache consistency monitoring request. The data volume of the tag information of the primary cache entries is usually small, and it occupies less storage resources in the secondary cache device, thus having a small impact on the utilization rate of the secondary cache device. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 This is a schematic diagram of the structure of a three-layer caching system provided in an embodiment of this application;

[0041] Figure 2 This is a schematic diagram of the structure of a Dcache module provided in an embodiment of this application;

[0042] Figure 3 This is a schematic diagram of the structure of a secondary cache device provided in an embodiment of this application;

[0043] Figure 4 This is a schematic diagram of the structure of another secondary cache device provided in an embodiment of this application;

[0044] Figure 5 This is a schematic diagram of the structure of another secondary cache device provided in an embodiment of this application;

[0045] Figure 6 This is a schematic diagram of the structure of another secondary cache device provided in an embodiment of this application;

[0046] Figure 7 This is a flowchart illustrating an operation method of a secondary cache device provided in an embodiment of this application;

[0047] Figure 8 This is a schematic diagram of the structure of a processor provided in an embodiment of this application;

[0048] Figure 9 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0049] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0050] In the field of computer technology, to mitigate the adverse effects of the gap between processor processing speed and memory access speed, a cache system is typically placed between the processor and memory. For example, a processor may include an LSU (Load Store Unit) for processing memory access instructions. The LSU is a crucial module determining the processor's memory access performance; it can improve the processing speed of memory access instructions by prioritizing access to cached devices in the cache system. A processor may include multiple cores, each capable of independently executing instructions and processing data; a processor with multiple cores is called a multi-core processor.

[0051] In multi-core processors, the cache system can be a three-tier cache system, comprising a private L1 cache for each core, a private L2 cache for each core, and a shared L3 cache for all cores. In some embodiments, "private" can also be referred to as "dedicated." In some embodiments, the L1 cache can also be represented as an L1 cache, the L2 cache as an L2 cache, and the L3 cache as an L3 cache. The L3 cache is a high-level cache within the processor, located above the L1 and L2 caches, and is used to store data and instructions shared by multiple cores. The L1 cache has a relatively fast access speed and is usually the fastest cache level in the processor. The L2 cache is located outside the processor cores. The role of the L2 cache is to store relatively infrequently used but still frequently accessed data and instructions, improving the processor's data hit rate and overall performance.

[0052] For example, taking a processor with four cores (i.e., a quad-core processor) as an example, the structure of a three-level cache system can be as follows: Figure 1 As shown. In Figure 1 In this processor, the three-level cache system consists of four cores (referred to as core 0, core 1, core 2, and core 3). The three-level cache system includes a private L1 cache for core 0, a private L2 cache for core 0, a private L1 cache for core 1, a private L2 cache for core 1, a private L2 cache for core 2, a private L1 cache for core 2, a private L2 cache for core 3, a private L2 cache for core 3, and a shared L3 cache for all four cores.

[0053] A typical L1 cache consists of an Icache (Instruction Cache) module and a Dcache (Data Cache) module. The Icache module stores instructions to be executed by the processor (e.g., addition instructions, load instructions, store instructions, etc.) for the processor's instruction decoding unit to read. The Dcache module stores data required for processor operations (e.g., operands, operation results, etc.) for the processor's execution unit to read or write. The design of the Dcache module has three core parameters: total capacity, associativity (also known as the number of paths), and cache entry size.

[0054] Total capacity refers to the total amount of data that the Dcache module can store. The total capacity of the Dcache module can be set based on experience or adjusted flexibly according to needs. For example, the total capacity of the Dcache module can be 32K (Kilobyte) or 64K.

[0055] Associativity defines the number of optional storage locations in the Dcache module that a memory data block can be mapped to. Associativity determines the flexibility of the cache address mapping strategy. The associativity of the Dcache module can be set empirically or adjusted flexibly according to requirements. For example, the associativity of the Dcache module can be 4, meaning the cache entries in the Dcache module can be organized in a 4-way set-associative manner; another example is that the associativity of the Dcache module can be 8, meaning the cache entries in the Dcache module can be organized in an 8-way set-associative manner, and so on. Taking 4-way set-associative as an example for further explanation, 4-way set-associative means that the cache area in the Dcache module is divided into multiple groups, each group containing a fixed number of 4 cache entries. A data block in memory, the size of a cache entry, is first mapped to a fixed group through address calculation, and then can be stored in any one of the 4 cache entries within that group.

[0056] The cache entry size refers to the total amount of data that each cache entry in the Dcache module can store. The cache entry size can be set based on experience or adjusted flexibly according to needs. For example, the cache entry size can be 64 bytes. In some embodiments, the cache entry size can be referred to as the cacheline size.

[0057] It's important to note that a complete cache entry consists of two parts: a data area and a control information area. The data area stores the actual data loaded from memory (also known as data information), while the control information area stores metadata (also known as tag information) that manages the cache entry. The cache entry size refers to the amount of data that the data area of ​​the cache entry can store.

[0058] For example, the tag information stored in the control information area may include address identification information, valid bit, dirty bit, consistency status bit, etc.

[0059] Address identification information is used to identify the location of data stored in a cache entry in memory. It is a key part of cache address matching, used to implement the mapping and verification from physical address to cache location. For example, address identification information includes an index and a tag. The index is used to locate the group in which the cache entry belongs, and the tag is used to locate the specific cache entry within the group.

[0060] The valid bit is used to indicate whether the data in a cache entry is valid. If a cache entry is not used or has been invalidated, the valid bit will be set to invalid, and the cache controller will not use the data in that cache entry.

[0061] The dirty bit is used to mark whether the data in a cached entry has been modified but has not yet been written back to memory.

[0062] The consistency status bit is used to store information about cache consistency in a multi-core environment. In some embodiments, the consistency status information can also be called sharing-related status information. For example, the consistency status bit can have four states: 1. M (Modified): The data exists only in the current cache device and has been modified (inconsistent with memory), and is not shared by other cache devices; 2. E (Exclusive): The data exists only in the current cache device, is consistent with memory, and is not shared by other cache devices (can be directly modified to M state); 3. S (Shared): The data has copies in the current cache device and at least one other cache device, and is consistent with memory (other copies must be invalidated before modification); 4. I (Invalid): The data is invalid (may have been modified or discarded by other cores).

[0063] To improve overall processor performance, the address mapping (or organization) of cache entries in the Dcache module is typically done using the VIPT (Virtual Index Physical Tag) method. The core logic of VIPT is to use the low-order bits of the virtual address as the virtual index and the high-order bits of the physical address as the physical tag. In other words, the address identification information in cache entries in the Dcache module includes both the virtual index and the physical tag. Under VIPT, different virtual addresses may map to the same physical address, resulting in the same physical data being cached in multiple different cache entries (cachelines), leading to name conflicts.

[0064] For example, taking a Dcache module with a total capacity of 32K, cache entries organized as 4-way set-associative, cache entry size of 64 bytes, and cache entry address mapping method of VIPT as an example, the structure of the Dcache module can be as follows: Figure 2 As shown.

[0065] according to Figure 2 As can be seen, the address identification information of cached entries in the Dcache module includes a virtual index and a physical tag. The virtual index consists of the lower 13 bits of the virtual address (VA) (which can be represented as [12:0]). The virtual index includes an offset and a virtual index value (tag index). The offset is used to locate the specific byte position of the data stored in the cache line. The offset consists of the lower 6 bits of the virtual address (which can be represented as [5:0]). The lower 3 bits of the offset can be used as a byte offset, and the higher 3 bits can be used as a block offset. The virtual index value is used to quickly locate the target group in the Dcache module and initiate parallel lookups within the group. The virtual index value consists of the 7 bits (from the 7th to the 13th bit of the virtual address, which can be represented as [12:6]). The physical tag consists of 28 bits (bits 13 to 40 of the physical address, which can be represented as [39:12]) and is used to uniquely identify the cache entry that stores the physical memory block within the target group, in order to verify the correctness of the data cached in the cache entry.

[0066] The 7-bit wide virtual index value has 128 possibilities (represented as index 128). Each possibility constitutes a group, meaning there are a total of 128 groups. Each group has one cache entry under each of the four paths (represented as way0, way1, way2, and way3). Under each cache entry, dirty bits and a 28-bit wide physical tag (represented as Tag[27:0]) can be recorded. The tag area in each of the four paths has a capacity of 128×28. The tag area can be represented as Tag RAM (Tag Random Access Memory).

[0067] There are 8 possible block offsets with a width of 3 bits. Each of the 128 groups corresponds to 8 block offset cases under each of the 4 channels. Each of the 128 groups under each of the 4 channels corresponds to 1024 data index cases (represented as index 1024). These 1024 data index cases are used to implement the data index. Each data index case can record 8 bytes (64 bits wide) of data. The specific data can be located within these 8 bytes based on the 3-bit byte offset. The total capacity of the data area in each channel can be represented as 1024 × 64 = 8K, and the 4 channels record a total of 32K of data. The data area in each channel can be represented as Data RAM (Data Random Access Memory).

[0068] The virtual index is the lower 13 bits of the virtual address [12:0], while the smallest granularity of the page table is 4K, corresponding to the lower 12 bits of the address [11:0]. Therefore, the lower 12 bits of the virtual address (represented as VA[11:0]) are the same as the lower 12 bits of the physical address (represented as PA[11:0]), but the 13th bit of the virtual address (represented as VA

[12] ) may be different from the 13th bit of the physical address (represented as PA

[12] ). The 13th bit of the virtual address (represented as VA

[12] ) can be considered as the alias bit. When the 13th bit of the virtual address (represented as VA

[12] ) is different from the 13th bit of the physical address (represented as PA

[12] ), different virtual addresses may be mapped to the same physical address, thus causing the alias problem.

[0069] Currently, in a three-tier cache system, to ensure cache consistency, the level 3 cache sends cache consistency snoop requests to all or some of the core-private level 2 caches. Cache consistency snoop requests are one of the core mechanisms for achieving cache consistency in multi-core processors, primarily used to address the problem of data inconsistency caused by modification or read operations when the same memory data is stored in multiple core-private caches.

[0070] In one related technology, a secondary cache device includes a storage unit and a processing unit. The storage unit is used to cache secondary cache entries, and the processing unit is used to obtain the matching result between the secondary cache device and the cache consistency monitoring request based on the secondary cache entries cached in the storage unit. The processing unit is also used to forward the cache consistency monitoring request to a primary cache device that is private to the same core, and to receive the matching result between the primary cache device and the cache consistency monitoring request returned by the primary cache device.

[0071] Therefore, the secondary cache needs to interact with the primary cache to obtain the matching result between the primary cache and the cache consistency monitoring request. This process of obtaining the matching result between the cache devices (primary and secondary caches) and the cache consistency monitoring request is inefficient, resulting in low efficiency in cache consistency processing. Furthermore, the process of the primary cache obtaining the matching result can easily interfere with the primary cache's handling of normal access requests, reducing its efficiency in processing normal access requests.

[0072] Furthermore, to address the issue of name duplication, the Level 1 cache obtains a match between itself and the cache consistency monitoring request by traversing the alias index entries of cache entries in the Dcache module. The cache consistency monitoring request carries the target physical address, and the alias index entries refer to all entries that might cache data at that target physical address. The virtual index of each alias index entry refers to the virtual index corresponding to a virtual address that might map to that target physical address. The number of alias index entries can be large, requiring the Level 1 cache to traverse a significant number of entries to obtain a match. This results in low efficiency for the Level 1 cache in obtaining the match, further reducing the efficiency of the Level 2 cache in obtaining the match between the cache (Level 1 and Level 2 caches) and the cache consistency monitoring request, and also further reducing the efficiency of the Level 1 cache in processing normal access requests.

[0073] In another related technology, the L2 cache and L1 cache on the same core are designed to be inclusive. That is, the L2 cache caches all cache entries from the L1 cache. Based on this, the L2 cache not only caches its own cache entries but also all cache entries from the L1 cache. The L2 cache can determine the matching result between itself and the cache consistency monitoring request based on its own cache entries, and it can also determine the matching result between the L1 cache and the cache consistency monitoring request based on the L1 cache entries. This improves the efficiency of the L2 cache in obtaining the matching result between the cache units (L1 and L2) and the cache consistency monitoring request to some extent. However, the L2 cache needs to reserve some capacity to cache the L1 cache entries, resulting in a reduction in the effective capacity of the L2 cache for caching its own cache entries, thus reducing the utilization rate of the L2 cache.

[0074] This application provides a secondary cache device that is highly efficient at obtaining the matching results between cache devices (primary and secondary cache devices) and cache consistency monitoring requests. For example, the secondary cache device provided in this application can be a core-private secondary cache device in a three-level cache system of a multi-core processor. For example, if the structures of different core-private secondary cache devices in the three-level cache system are identical, then the secondary cache device provided in this application can be a core-private secondary cache device.

[0075] like Figure 3 As shown, the secondary cache device includes a storage unit 1 and a processing unit 2, which are interconnected.

[0076] The storage unit 1 is used to back up the tag information of the first-level cache entries and the second-level cache entries corresponding to the second-level cache device, wherein the first-level cache entries are the entries cached by the first-level cache device; the processing unit 2 is used to process the cache consistency monitoring request based on the second-level cache entries cached in the storage unit 1 to obtain a first matching result between the second-level cache device and the cache consistency monitoring request; and to process the cache consistency monitoring request based on the tag information of the first-level cache entries backed up in the storage unit 1 to obtain a second matching result between the first-level cache device and the cache consistency monitoring request.

[0077] Based on this structure, after the secondary cache device receives the cache consistency monitoring request, it can obtain the matching result between the cache device (the primary cache device and the secondary cache device) and the cache consistency monitoring request without interacting with the primary cache device. This is highly efficient and helps to improve the efficiency of cache consistency processing.

[0078] Furthermore, since the process of obtaining the matching result between the first-level cache device and the cache consistency monitoring request is implemented in the second-level cache device, the process of obtaining the matching result between the first-level cache device and the cache consistency monitoring request will not interfere with the first-level cache device's process of processing normal access requests, thus ensuring the efficiency of the first-level cache device in processing normal access requests.

[0079] A Level 1 cache entry refers to an entry cached by a Level 1 cache device, which is located on the same core as the Level 2 cache device. For example, the Level 1 cache device includes an Icache module and a Dcache module, and a Level 1 cache entry can refer to an entry cached by the Dcache module within the Level 1 cache device.

[0080] Level 1 cache entries can have tag information and data information. Tag information refers to the metadata that manages the level 1 cache entry, and data information refers to the data loaded from memory into the level 1 cache device. In this embodiment, storage unit 1 in the level 2 cache device only needs to additionally back up the tag information of the level 1 cache entry to obtain the matching result between the level 1 cache device and the cache consistency monitoring request. The amount of data in the tag information of the level 1 cache entry is usually small, occupying less storage resources in the level 2 cache device and having a small impact on the utilization rate of the level 2 cache device.

[0081] The tag information of the backed-up L1 cache entries in storage unit 1 is consistent with the tag information of the L1 cache entries cached in the L1 cache device. For example, the tag information of the L1 cache entries may include, but is not limited to, the address identifier information, valid bit, dirty bit, and consistency status bit of the L1 cache entries. For example, storage unit 1 does not actively maintain the dirty bit information of the L1 cache entries, but passively synchronizes the results cached by the L1 cache device.

[0082] A second-level cache entry refers to a cache entry corresponding to a second-level cache device. For example, a second-level cache entry has tag information and data information. Cache of second-level cache entries by storage unit 1 can mean that storage unit 1 caches the tag information and data information of the second-level cache entries. For example, the tag information of a second-level cache entry refers to the metadata managing the second-level cache entry, and the data information of the second-level cache entry refers to the data loaded from memory into the second-level cache device. For example, the tag information of a second-level cache entry may include address identification information, valid bits, dirty bits, consistency status bits, etc.

[0083] In some embodiments, storage unit 1 can be a single, integrated unit having a first storage space and a second storage space. The first storage space is used to back up the tag information of first-level cache entries, and the second storage space is used to cache second-level cache entries. In this case, storage unit 1 in this application can be obtained by reserving a portion of the storage space in a storage unit in related technologies for backing up the tag information of first-level cache entries.

[0084] In other embodiments, see Figure 4 Storage unit 1 may include a backup module 10 and a cache module 20. The backup module 10 is used to back up the tag information of the first-level cache entries, and the cache module 20 is used to cache the second-level cache entries. That is, storage unit 1 can be equipped with two independent hardware modules to back up the tag information of the first-level cache entries and cache the second-level cache entries respectively. In this case, the storage unit in the related art can be used as the cache module 20 in this application, and an additional backup module 10 is set on this basis to obtain the storage unit 1 in this application.

[0085] For example, the caching module 20 may include a first caching submodule and a second caching submodule. The first caching submodule is used to cache the tag information of the second-level cache entries, and the second caching submodule is used to cache the data information of the second-level cache entries. In some embodiments, the backup module 10 may be represented as L1 tag-copy, the first caching submodule may be represented as L2 tag, and the second caching submodule may be represented as L2 data.

[0086] Cache consistency listener requests are one of the core mechanisms for achieving cache consistency in multi-core processors. They are mainly used to solve the problem of data inconsistency caused by modification or read operations when the same memory data is stored in multiple core-private caches.

[0087] In this embodiment of the application, the processing unit 2 is able to obtain a cache consistency monitoring request. After obtaining the cache consistency monitoring request, the processing unit 2 obtains a first matching result between the second-level cache device and the cache consistency monitoring request based on the second-level cache entries cached in the storage unit 1, and obtains a second matching result between the first-level cache device and the cache consistency monitoring request based on the tag information of the backed-up first-level cache entries in the storage unit 1.

[0088] In some embodiments, processing unit 2 can be a single, integrated unit, meaning that processing unit 2 is a single unit that has the function of obtaining both a first matching result and a second matching result. In this case, processing unit 2 in this application can be obtained by changing the function of processing units in related technologies.

[0089] In other embodiments, see Figure 4 The processing unit 2 may include a first processing module 30 and a second processing module 40. The first processing module 30 is used to obtain a first matching result, and the second processing module 40 is used to obtain a second matching result. That is, the processing unit 2 may have two independent hardware modules to obtain the first matching result and the second matching result respectively. In this case, the processing unit in the related art can be used as the first processing module 30 in this application, and a second processing module 40 is additionally set on this basis to obtain the processing unit 2 in this application. In some embodiments, the first processing module 30 may also be represented as L2 snp, and the second processing module 40 may also be represented as L1 snp.

[0090] In one possible implementation, the first processing module 30 is configured to receive a cache consistency monitoring request sent by the Level 3 cache device; process the cache consistency monitoring request based on the Level 2 cache entries cached in storage unit 1 to obtain a first matching result; and forward the cache consistency monitoring request to the second processing module 40. The second processing module 40 is configured to receive the cache consistency monitoring request forwarded by the first processing module 30; and process the cache consistency monitoring request based on the tag information of the Level 1 cache entries backed up in storage unit 1 to obtain a second matching result. In other words, the first processing module 30 obtains the cache consistency monitoring request by receiving the cache consistency monitoring request sent by the Level 3 cache device; the second processing module 40 obtains the cache consistency monitoring request by receiving the cache consistency monitoring request forwarded by the first processing module 30 from the Level 3 cache device.

[0091] A Level 3 cache is a shared storage device among multiple cores in a multi-core processor. The Level 3 cache can send a cache consistency monitoring request to the Level 2 cache in any scenario where cache consistency needs to be achieved through interaction with the Level 2 cache. For example, if the Level 2 cache is a private cache for the target core, the scenarios in which the Level 3 cache sends a cache consistency monitoring request to the Level 2 cache can include, but are not limited to, the following two:

[0092] Scenario 1: The L3 cache device detects a write operation initiated by the first core against the first cache entry in the private L2 cache device. The data information stored in the first cache entry is in shared state (S), and a copy of the data information stored in the first cache entry exists in the target core's private cache device (L2 cache device and / or L1 cache device).

[0093] Scenario 2: The L3 cache device detects a read operation initiated by the second core to read the first data. Neither the second core's private cache device nor the L3 cache device stores the first data. The target core's private cache device (L2 cache device and / or L1 cache device) caches a valid copy of the first data.

[0094] For example, in the case where storage unit 1 includes a backup module 10 and a cache module 20, after obtaining a cache consistency monitoring request, the first processing module 30 processes the cache consistency monitoring request based on the second-level cache entries cached in the cache module 20 to obtain a first matching result. After obtaining a cache consistency monitoring request, the second processing module 40 processes the cache consistency monitoring request based on the tag information of the first-level cache entries backed up in the backup module 10 to obtain a second matching result.

[0095] In one possible implementation, the second-level cache entry has tag information and data information. The first processing module 30 processes the cache consistency monitoring request based on the second-level cache entry, which means that the first processing module 30 processes the cache consistency monitoring request based on the tag information of the second-level cache entry.

[0096] For example, taking a cache module 20 that includes a first cache submodule and a second cache submodule as an example, the secondary cache device can be as follows: Figure 5 As shown. The three-level cache device sends a cache consistency monitoring request to the first processing module 30. The first processing module 30 processes the cache consistency monitoring request based on the tag information of the second-level cache entries cached by the first cache submodule. The first processing module 30 forwards the cache consistency monitoring request to the second processing module 40. The second processing module 40 processes the cache consistency monitoring request based on the tag information of the first-level cache entries backed up in the backup module 10.

[0097] In an exemplary embodiment, the cache consistency monitoring request carries a target physical address. The target physical address is the memory address of the data that the cache consistency monitoring request needs to monitor; that is, the actual address of the data that the cache consistency monitoring request needs to monitor.

[0098] In an exemplary embodiment, each secondary cache entry corresponds to tag information, which includes the physical index and physical tag of the secondary cache entry; that is, the address mapping method for secondary cache entries is PIPT (Physical Index Physical Tag). The core feature of PIPT is that it directly uses the physical address to match the index and tag of the cache entry.

[0099] For the tag information of the second-level cache entry, which includes the physical index and physical tag of the second-level cache entry, i.e., the address mapping method of the second-level cache entry is PIPT, the process of the processing unit 2 obtaining the first matching result between the second-level cache device and the cache consistency monitoring request includes: the processing unit 2 determines the target physical index and the target physical tag based on the target physical address; determines the candidate second-level cache entry whose physical index matches the target physical index among the second-level cache entries; and determines the first matching result based on the comparison result between the physical tag of the candidate second-level cache entry and the target physical tag.

[0100] Both the target physical index and the target physical tag are determined based on the target physical address. For example, the target physical index and the target physical tag are different sub-addresses within the target physical address. This application does not limit the implementation method of determining the target physical index and the target physical tag based on the target physical address.

[0101] For example, the first part of the target physical address is used as the target physical index, and the second part of the target physical address is used as the target physical label; the first part and the second part are different. For example, the first part and the second part may or may not overlap. For example, the first part and the second part may cover the entire target physical address, or they may only cover a portion of the target physical address. For example, the first part may be the low-order part of the target physical address, and the second part may be the high-order part of the target physical address.

[0102] After determining the target physical index and target physical tag, the physical index of the second-level cache entry is compared with the target physical index. If there is a candidate second-level cache entry whose physical index matches the target physical index, the first matching result is determined based on the comparison result of the physical tag of the candidate second-level cache entry and the target physical tag.

[0103] For example, the number of target physical indexes is one. The existence of a candidate second-level cache entry whose physical index matches the target physical index means that there is a candidate second-level cache entry whose physical index is the target physical index.

[0104] For example, the number of candidate second-level cache entries is at least one, and the comparison results of the physical labels of the candidate second-level cache entries with the target physical label include two types: the physical label of the target second-level cache entry in at least one candidate second-level cache entry is the same as the target physical label; the physical labels of each candidate second-level cache entry are different from the target physical label.

[0105] The first matching result is used to indicate whether there is a second-level cache entry that successfully matches the cache consistency listener request, and when there is a second-level cache entry that successfully matches the cache consistency listener request, it explicitly indicates which second-level cache entry is the one that successfully matches the cache consistency listener request.

[0106] If the comparison result between the physical tags of candidate second-level cache entries and the target physical tag is that the physical tag of the target second-level cache entry in at least one candidate second-level cache entry is the same as the target physical tag, the method for determining the first matching result includes: taking the result indicating that the target second-level cache entry in the second-level cache entry has successfully matched the cache consistency monitoring request as the first matching result. In this case, the cache entry being monitored by the cache consistency monitoring request can be considered to be stored in the second-level cache device. Specifically, the physical index of the target second-level cache entry is the same as the target physical index, and the physical tag of the target second-level cache entry is the same as the target physical tag.

[0107] If the comparison between the physical labels of candidate second-level cache entries and the target physical label shows that the physical labels of all candidate second-level cache entries are different from the target physical label, the method for determining the first matching result includes: taking the result indicating that there is no second-level cache entry that successfully matches the cache consistency monitoring request as the first matching result. In this case, it can be assumed that the cache entry being monitored by the cache consistency monitoring request is not stored in the second-level cache device.

[0108] In some embodiments, there may be no candidate second-level cache entries in the second-level cache entries whose physical index matches the target physical index. In this case, it can be assumed that the cache entry being monitored by the cache consistency monitoring request is not stored in the second-level cache device, and the result used to indicate that there is no second-level cache entry that successfully matches the cache consistency monitoring request is taken as the first matching result.

[0109] For example, in the case where the processing unit 2 includes a first processing module 30 and a second processing module 40, the process of determining the first matching result is performed by the first processing module 30 in the processing unit 2.

[0110] In one possible implementation, the cache consistency listener request carries the target physical address, and the tag information of the first-level cache entry includes the virtual index of the first-level cache entry and the physical tag of the first-level cache entry; that is, the address mapping method of the first-level cache entry is VIPT.

[0111] For the tag information of a Level 1 cache entry, which includes the virtual index and physical tag of the Level 1 cache entry (i.e., the address mapping method of the Level 1 cache entry is VIPT), the process by which processing unit 2 obtains the second matching result between the Level 1 cache device and the cache consistency monitoring request includes: processing unit 2 determines the target virtual index and target physical tag based on the target physical address; determines candidate Level 1 cache entries whose virtual index is any one of the at least two target virtual indexes; and determines the second matching result based on the matching of the physical tag of the candidate Level 1 cache entry with the target physical tag.

[0112] For example, determining the target virtual index based on the target physical address can be achieved by using the virtual index determined based on all virtual addresses that can be mapped to the target physical address as the target virtual index. Determining the virtual index based on any virtual address can be achieved by using the third part of any virtual address as the virtual index. The third part can be any part of any virtual address, and this application embodiment does not limit this. For example, the third part is determined based on parameters such as the associativity under the VIPT method, the cache entry size, and the total capacity of the L1 cache device used to cache L1 cache entries. For example, if the associativity under the VIPT method is 4, the cache entry size is 64 bytes, and the total capacity of the L1 cache device used to cache L1 cache entries is 32K, the third part can be the lower 13 bits of any virtual address.

[0113] For example, the implementation of determining the target physical label based on the target physical address can be as follows: the second part of the target physical address is used as the target physical label. For example, the second part can be the high-order part of the target address.

[0114] After determining the target virtual index and the target physical label, the virtual index of the first-level cache entry is compared with the target virtual index. If there is a candidate first-level cache entry whose virtual index matches the target virtual index, the second matching result is determined based on the comparison result of the virtual label of the candidate first-level cache entry and the target virtual label.

[0115] For example, the number of target virtual indexes is at least one, and the existence of a candidate first-level cache entry whose virtual index matches the target virtual index means that there is a candidate first-level cache entry whose virtual index is any of the target virtual indexes.

[0116] For example, the number of candidate first-level cache entries is at least one, and the comparison results between the physical tags of the candidate first-level cache entries and the target physical tags include two types: the physical tags of the target first-level cache entries in at least one candidate first-level cache entry are the same as the target physical tags; the physical tags of each candidate first-level cache entry are different from the target physical tags.

[0117] The second matching result is used to indicate whether there is a first-level cache entry that successfully matches the cache consistency listener request, and when there is a first-level cache entry that successfully matches the cache consistency listener request, it explicitly indicates which first-level cache entry is the first-level cache entry that successfully matches the cache consistency listener request.

[0118] If the comparison result between the physical tags of candidate first-level cache entries and the target physical tag shows that the physical tag of the target first-level cache entry in at least one candidate first-level cache entry is the same as the target physical tag, the method for determining the second matching result includes: taking the result indicating that the target first-level cache entry in the first-level cache entry has successfully matched the cache consistency monitoring request as the second matching result. In this case, the cache entry being monitored by the cache consistency monitoring request can be considered to be stored in the first-level cache device. Specifically, the virtual index of the target first-level cache entry is the same as any target virtual index, and the physical tag of the target first-level cache entry is the same as the target physical tag.

[0119] If the comparison between the physical labels of candidate first-level cache entries and the target physical label shows that the physical labels of all candidate first-level cache entries are different from the target physical label, the method for determining the second matching result includes: taking the result indicating that there is no first-level cache entry that successfully matches the cache consistency monitoring request as the second matching result. In this case, it can be assumed that the cache entry being monitored by the cache consistency monitoring request is not stored in the first-level cache device.

[0120] In some embodiments, there may be no candidate first-level cache entries in the first-level cache entries that match the target virtual index. In this case, it can be assumed that the cache entry being monitored by the cache consistency monitoring request is not stored in the first-level cache device, and the result used to indicate that there is no first-level cache entry that successfully matches the cache consistency monitoring request is taken as the second matching result.

[0121] For example, in the case where the processing unit 2 includes a first processing module 30 and a second processing module 40, the process of determining the second matching result is performed by the second processing module 40 in the processing unit 2.

[0122] In one possible implementation, after obtaining the first matching result, processing unit 2 needs to perform subsequent processing. The method by which processing unit 2 performs subsequent processing varies depending on the specific circumstances of the first matching result and the cache consistency monitoring request. The specific circumstances of the first matching result and the cache consistency monitoring request include the following cases 1 to 4:

[0123] Case 1: The first matching result indicates that the target second-level cache entry in the second-level cache entry successfully matches the cache consistency listener request, and the cache consistency listener request is used to request the returned data information.

[0124] In this case 1, the processing unit 2 performs the following processing: the processing unit 2 reads the data information of the target second-level cache entry from the storage unit 1 and sends response information including the data information of the target second-level cache entry to the third-level cache device.

[0125] For example, in the case where storage unit 1 includes backup module 10 and cache module 20, processing unit 2 reads the data information of the target second-level cache entry from cache module 20 in storage unit 1. For example, processing unit 2 reads the data information of the target second-level cache entry from the first cache submodule in cache module 20.

[0126] For example, in the case where the processing unit 2 includes a first processing module 30 and a second processing module 40, the implementation method of the processing unit 2 reading the data information of the target second-level cache entry from the storage unit 1 and sending the response information including the data information of the target second-level cache entry to the third-level cache device includes: the first processing module 30 in the processing unit 2 reads the data information of the target second-level cache entry from the storage unit 1 and sends the response information including the data information of the target second-level cache entry to the third-level cache device.

[0127] Scenario 2: The first matching result indicates that the target second-level cache entry in the second-level cache entry successfully matches the cache consistency listener request, and the cache consistency listener request is used to request an update status.

[0128] In this second case, the processing unit 2 performs the following processing: the processing unit 2 sends a response message to the level 3 cache device to indicate that the level 2 cache device has successfully matched, and updates the status of the target level 2 cache entry.

[0129] For example, the response information used to indicate that the second-level cache device has successfully matched does not contain the data information of the target second-level cache entry. That is, after obtaining the first matching result, the processing unit 2 does not need to obtain the data information of the target second-level cache entry, and can directly send the response information to the third-level cache device.

[0130] For example, the status of the target second-level cache entry is recorded in the tag information of the target second-level cache entry. Updating the status of the target second-level cache entry by processing unit 2 means that processing unit 2 updates the status-related information recorded in the tag information of the target second-level cache entry. For example, the status-related information recorded in the tag information of the target second-level cache entry may be at least one of the following: valid bit, dirty bit, and consistency status bit.

[0131] The method by which processing unit 2 updates the status of the target second-level cache entry (what status to update the target second-level cache entry to) can be determined according to the specific circumstances of the cache consistency monitoring request, and this embodiment does not limit it.

[0132] For example, in the case where the processing unit 2 includes a first processing module 30 and a second processing module 40, the processing unit 2 sends a response message to the level 3 cache device to indicate that the level 2 cache device has successfully matched, and updates the status of the target level 2 cache entry. The implementation method includes: the first processing module 30 in the processing unit 2 sends a response message to the level 3 cache device to indicate that the level 2 cache device has successfully matched, and updates the target level 2 cache entry.

[0133] Scenario 3: The first matching result indicates that there is no second-level cache entry that successfully matches the cache consistency monitoring request, and the cache consistency monitoring request is used to request the returned data information.

[0134] In this case 3, the processing unit 2 performs the following processing: the processing unit 2 sends a response message to the level 3 cache device to indicate that the level 2 cache device has failed to match. This response message does not include any data information of any level 2 cache entry.

[0135] For example, in the case where the processing unit 2 includes a first processing module 30 and a second processing module 40, the first processing module 30 in the processing unit 2 sends response information to the level 3 cache device to indicate that the level 2 cache device has failed to match.

[0136] Case 4: The first matching result indicates that there is no second-level cache entry that successfully matches the cache consistency listener request, and the cache consistency listener request is used to request an update status.

[0137] In this scenario 4, processing unit 2 performs subsequent processing as follows: processing unit 2 sends a response message to the level 3 cache device indicating that the level 2 cache device has failed to match. This response message does not include any data information of any level 2 cache entry. Furthermore, processing unit 2 does not need to update the status of any level 2 cache entry.

[0138] For example, in the case where the processing unit 2 includes a first processing module 30 and a second processing module 40, the first processing module 30 in the processing unit 2 sends response information to the level 3 cache device to indicate that the level 2 cache device has failed to match.

[0139] It should be noted that requesting the return of data information and requesting an update of status are two different requirements of the cache consistency monitoring request. Whether the requirement of the cache consistency monitoring request is to request the return of data or to request an update of status may be related to the scenario in which the third-level cache device sends a cache consistency monitoring request to the second-level cache device, and this application embodiment does not limit this.

[0140] For example, in the scenario where the third-level cache device sends a cache consistency monitoring request to the second-level cache device, which is the case of scenario 1 mentioned above, the requirement of the cache consistency monitoring request is to request an update of the status, for example, to request that the status of the cache entry that stores a copy of the data information stored in the first cache entry be updated to an invalid status.

[0141] The scenario where the Level 3 cache device sends a cache consistency monitoring request to the Level 2 cache device is the same as scenario 2 mentioned above. The requirement for the cache consistency monitoring request is to request the return of data information, for example, to request the return of data information of the cache entry that has a valid copy of the first data.

[0142] In one possible implementation, after obtaining the second matching result, processing unit 2 needs to perform subsequent processing. The method by which processing unit 2 performs this subsequent processing varies depending on the specific circumstances of the second matching result and the cache consistency monitoring request. The specific circumstances of the second matching result and the cache consistency monitoring request include the following cases 5 to 8:

[0143] Case 5: The second matching result indicates that the target first-level cache entry in the first-level cache entry successfully matches the cache consistency listener request, and the cache consistency listener request is used to request the returned data information.

[0144] In this case 5, the processing unit 2 performs the following subsequent processing: the processing unit 2 sends a read request to the level 1 cache device, the read request is used to request the read of the data information of the target level 1 cache entry, receives the data information of the target level 1 cache entry returned by the level 1 cache device; and sends response information including the data information of the target level 1 cache entry to the level 3 cache device.

[0145] For example, in the case where processing unit 2 includes a first processing module 30 and a second processing module 40, the implementation of processing unit 2 sending a read request to the first-level cache device and receiving the data information of the target first-level cache entry returned by the first-level cache device includes: the second processing module 40 in processing unit 2 sends a read request to the first-level cache device and receives the data information of the target first-level cache entry returned by the first-level cache device. The implementation of processing unit 2 sending response information including the data information of the target first-level cache entry to the third-level cache device includes: the second processing module 40 in processing unit 2 sends response information including the data information of the target first-level cache entry to the first processing module 30 in processing unit 2; after receiving the response information including the data information of the target first-level cache entry, the first processing module 30 forwards the response information including the data information of the target first-level cache entry to the third-level cache device.

[0146] Case 6: The second matching result indicates that the target first-level cache entry in the first-level cache entry successfully matches the cache consistency listener request, and the cache consistency listener request is used to request an update status.

[0147] In this case 6, the processing unit 2 performs the following subsequent processing: the processing unit 2 sends an update request to the first-level cache device, the update request is used to request an update to the status of the target first-level cache entry, and sends a response message to the third-level cache device to indicate that the first-level cache device has successfully matched.

[0148] For example, in the case where processing unit 2 includes a first processing module 30 and a second processing module 40, the implementation of processing unit 2 sending an update request to the first-level cache device includes: the second processing module 40 in processing unit 2 sending an update request to the first-level cache device. The implementation of processing unit 2 sending response information indicating successful matching of the first-level cache device to the third-level cache device includes: the second processing module 40 in processing unit 2 sending response information indicating successful matching of the first-level cache device to the first processing module 30; and after receiving the response information indicating successful matching of the first-level cache device, the first processing module 30 forwards the response information indicating successful matching of the first-level cache device to the third-level cache device.

[0149] Upon receiving an update request, the Level 1 cache device updates the status of the target Level 1 cache entry. For example, the status of the target Level 1 cache entry is recorded in its tag information. Updating the status of the target Level 1 cache entry means updating the status-related information recorded in the tag information. For example, the status-related information recorded in the tag information of the target Level 1 cache entry may include at least one of a valid bit, a dirty bit, and a consistency status bit.

[0150] For example, the processing unit 2 may perform subsequent processing in a manner that includes updating the status of the target first-level cache entry backed up in the storage unit 1.

[0151] For example, in the case where storage unit 1 includes a backup module 10 and a cache module 20, and processing unit 2 includes a first processing module 30 and a second processing module 40, the processing unit 2 updates the status of the target first-level cache entry backed up in storage unit 1 in the following ways: the second processing module 40 in processing unit 2 updates the status of the target first-level cache entry backed up in backup module 10.

[0152] In this embodiment, the timing of the second processing module 40 updating the status of the target first-level cache entry backed up in the backup module 10 is not limited. For example, the second processing module 40 may update the status of the target first-level cache entry backed up in the backup module 10 before the first-level cache device updates the status of the target first-level cache entry, or after the first-level cache device updates the status of the target first-level cache entry, or during the process of the first-level cache device updating the status of the target first-level cache entry.

[0153] Case 7: The second matching result indicates that there is no first-level cache entry that successfully matches the cache consistency listener request and the cache consistency listener request is used to request the returned data information.

[0154] In this case 7, the processing unit 2 performs the following processing: the processing unit 2 sends a response message to the level 3 cache device to indicate that the level 1 cache device has failed to match. This response message does not include any data information of any level 1 cache entry.

[0155] For example, in the case where the processing unit 2 includes a first processing module 30 and a second processing module 40, the implementation method of the processing unit 2 sending response information indicating that the first-level cache device has failed to match to the third-level cache device includes: the second processing module 40 in the processing unit 2 sends response information indicating that the first-level cache device has failed to match to the first processing module 30, and after receiving the response information indicating that the first-level cache device has failed to match, the first processing module 30 forwards the response information indicating that the first-level cache device has failed to match to the third-level cache device.

[0156] Case 8: The second matching result indicates that there is no first-level cache entry that successfully matches the cache consistency listener request and the cache consistency listener request is used to request an update status.

[0157] In this case 8, the processing unit 2 performs the following processing: the processing unit 2 sends a response message to the level 3 cache device to indicate that the level 1 cache device has failed to match. This response message does not include any data information of any level 1 cache entry.

[0158] For example, in the case where the processing unit 2 includes a first processing module 30 and a second processing module 40, the implementation method of the processing unit 2 sending response information indicating that the first-level cache device has failed to match to the third-level cache device includes: the second processing module 40 in the processing unit 2 sends response information indicating that the first-level cache device has failed to match to the first processing module 30, and after receiving the response information indicating that the first-level cache device has failed to match, the first processing module 30 forwards the response information indicating that the first-level cache device has failed to match to the third-level cache device.

[0159] Furthermore, in this case 8, the processing unit 2 (e.g., the second processing module 40 in the processing unit 2) does not need to update the state of any level 1 cache entry, nor does it need to send an update request to the level 1 cache device.

[0160] In other words, in this embodiment of the application, the processing of the cache consistency monitoring request includes: after the secondary cache device receives the cache consistency monitoring request sent by the tertiary cache device, the first processing module 30 in the secondary cache device queries the tag information of the secondary cache entries cached in the cache module 20; at the same time, the cache consistency monitoring request is forwarded to the second processing module 40, and the second processing module 40 iterates through the tag information of the primary cache entries backed up in the backup module 10.

[0161] If the tag information of the cache entry that successfully matches the cache consistency listener request is stored in the cache module 20, and the cache consistency listener request is used to request the returned data information, then the first processing module 30 will return the data information of the target second-level cache entry (also known as the cacheline that was snooped) that successfully matches the cache consistency listener request to the third-level cache device.

[0162] If the tag information of the cache entry that successfully matches the cache consistency monitoring request is stored in the backup module 10, and the cache consistency monitoring request is used to request returned data information, then the second processing module 40 reads the data information of the target first-level cache entry that successfully matches the cache consistency monitoring request from the Dcache module in the first-level cache device, and returns the data information of the target first-level cache entry to the third-level cache device through the first processing module 30. If no data needs to be returned, the second processing module 40 returns the response information to the third-level cache device through the first processing module 30, and simultaneously updates the status of the corresponding target first-level cache entry in the Dcache module and the backup module 10.

[0163] In one possible implementation, see [link to relevant documentation]. Figure 6 The secondary cache device also includes an access request processing module 50. The access request processing module 50 is connected to both the backup module 10 and the cache module 20.

[0164] The access request processing module 50 is used to receive a first access request sent by the first-level cache device. The first access request carries the identification information of the filling position. If there is an access second-level cache entry that is hit by the first access request in the second-level cache entries cached by the cache module 20, the tag information of the access second-level cache entry is filled in the filling position of the backup module 10, and the first access result is sent to the first-level cache device. The first access result includes the access second-level cache entry.

[0165] The access request processing module 50 is also used to send a second access request to the third-level cache device when there is no second-level cache entry that was hit by the first access request in the second-level cache entries cached by the cache module 20; receive the target cache entry that was hit by the second access request returned by the third-level cache device; fill in the tag information corresponding to the target cache entry in the filling position of the backup module 10; and send the second access result to the first-level cache device, wherein the second access result includes the target cache entry.

[0166] For example, the first access request can be any request to access data, which can refer to reading data or writing data. If the Level 1 cache does not contain the Level 1 cache entry that the processor's access request matches, the Level 2 cache sends the first access request to the Level 2 cache. The processor access request can be any request issued by the processor for accessing data.

[0167] For example, the identification information of the filled position is used to identify the filled position of the tag information in the backup module 10. For example, the identification information of the filled position includes road identification information and location identification information. The road identification information is used to identify any one of the multiple roads in the backup module 10, and the alias bit information is used to identify any filled position under any one road. For example, the location identification information can be alias bit information.

[0168] For example, if there is an access second-level cache entry in the second-level cache entries cached by the cache module 20 that is hit by the first access request, in addition to filling in the tag information of the access second-level cache entry in the filling position of the backup module 10 and sending the first access result to the first-level cache device, the access request processing module 50 will also set the access second-level cache entry cached in the cache module 20 to an invalid state.

[0169] For example, the target cache entry returned by the Level 3 cache device that was hit by the second access request may be a Level 3 cache entry stored in the Level 3 cache device, or it may be a cache entry constructed by the Level 3 cache device based on data information read from memory. This embodiment of the application does not limit this. For example, if the target cache entry hit by the second access request is a Level 3 cache entry stored in the Level 3 cache device, the Level 3 cache device may also set the target cache entry to an invalid state after returning it.

[0170] In this embodiment of the application, when there is no L1 cache entry that is hit by the processor access request (also known as the L1 cache device missing the processor access request), the first cache device sends a first access request to the L2 cache device. The first access request carries the identification information of the filling position, such as the information of the way to be replaced, and the alias bit information.

[0171] Upon receiving the first access request, the access request processing module 50 queries the tag information of the second-level cache entries. If a second-level cache entry is found to be hit by the first access request (also known as a second-level cache entry hitting the first access request), the second-level cache entry is set to an invalid state. Furthermore, based on the way information and alias bit information carried in the first access request, the access request processing module 50 fills the tag information of the accessed second-level cache entry into the corresponding filling position in the backup module 10. The access request processing module 50 also sends the first access result, including the accessed second-level cache entry, to the first-level cache device so that the first-level cache device can store the accessed second-level cache entry as a new first-level cache entry.

[0172] If the second-level cache entry does not contain the entry that was hit by the first access request (also known as a second-level cache entry missing the first access request), the access request processing module 50 requests the next-level cache device (i.e., the third-level cache device). After receiving the target cache entry returned by the third-level cache device, the access request processing module 50 returns the target cache entry to the Dcache module in the first-level cache device based on the second access result. At the same time, according to the way information and alias bit information carried in the first access request, the tag information of the target cache entry is filled into the corresponding filling position in the backup module 10.

[0173] In this embodiment, by backing up the tag information of cache entries in the L2 cache device, the frequency of cache consistency listener requests accessing the L1 cache device can be reduced, effectively improving the processing efficiency of cache consistency listener requests, thereby improving snoop performance and ultimately improving the overall performance of the processor. Even if the cache in the L1 cache device uses the VIPT method to cache data, the L2 cache device can still resolve the name conflict issue by traversing the tag information of the backed-up cache entries.

[0174] In this embodiment, the storage unit in the secondary cache device is used not only to cache secondary cache entries, but also to back up the tag information of primary cache entries. Based on this, after the processing unit in the secondary cache device obtains the cache consistency monitoring request, it can obtain the matching result between the cache device (primary cache device and secondary cache device) and the cache consistency monitoring request without interacting with the primary cache device. This is highly efficient and helps to improve the efficiency of cache consistency processing.

[0175] Furthermore, since the process of obtaining the matching result between the first-level cache device and the cache consistency monitoring request is implemented in the second-level cache device, the process of obtaining the matching result between the first-level cache device and the cache consistency monitoring request will not interfere with the first-level cache device's process of processing normal access requests, thus ensuring the efficiency of the first-level cache device in processing normal access requests.

[0176] Furthermore, the secondary cache device only needs to back up the tag information of the primary cache entries to obtain the matching result between the primary cache device and the cache consistency monitoring request. The data volume of the tag information of the primary cache entries is usually small, and it occupies less storage resources in the secondary cache device, thus having a small impact on the utilization rate of the secondary cache device.

[0177] This application also provides an operation method for a secondary cache device, which can be applied to the secondary cache device described in the above embodiments. See also Figure 7 The operation method of the secondary cache device includes steps 610 and 620:

[0178] Step 610: The processing unit in the secondary cache device processes the cache consistency monitoring request based on the secondary cache entries cached in the storage unit of the secondary cache device, and obtains the first matching result between the secondary cache device and the cache consistency monitoring request.

[0179] In one possible implementation, the cache consistency monitoring request carries the target physical address, and the second-level cache entry has corresponding tag information, which includes the physical index and physical tag of the second-level cache entry.

[0180] The processing unit in the secondary cache device processes the cache consistency monitoring request based on the secondary cache entries cached in the storage unit of the secondary cache device, and obtains a first matching result between the secondary cache device and the cache consistency monitoring request. This includes: determining the target physical index and the target physical tag based on the target physical address by the processing unit; determining candidate secondary cache entries whose physical index matches the target physical index among the secondary cache entries; and determining the first matching result based on the comparison result between the physical tag of the candidate secondary cache entry and the target physical tag.

[0181] Step 620: The processing unit processes the cache consistency monitoring request based on the tag information of the backed-up first-level cache entries in the storage unit to obtain a second matching result between the first-level cache device and the cache consistency monitoring request.

[0182] In one possible implementation, the cache consistency listener request carries the target physical address, and the tag information of the first-level cache entry includes the virtual index and the physical tag of the first-level cache entry.

[0183] The processing unit processes the cache consistency monitoring request based on the tag information of the backed-up L1 cache entries in the storage unit to obtain a second matching result between the L1 cache device and the cache consistency monitoring request. This includes: determining the target virtual index and the target physical tag based on the target physical address; determining candidate L1 cache entries whose virtual index matches the target virtual index in the L1 cache entries; and determining the second matching result based on the comparison result between the physical tag of the candidate L1 cache entry and the target physical tag.

[0184] In one possible implementation, the cache consistency monitoring request is processed by the processing unit in the secondary cache device based on the secondary cache entries cached in the storage unit of the secondary cache device, to obtain a first matching result between the secondary cache device and the cache consistency monitoring request. This includes: receiving the cache consistency monitoring request sent by the tertiary cache device through the first processing module in the processing unit; processing the cache consistency monitoring request based on the secondary cache entries cached in the storage unit to obtain the first matching result; and forwarding the cache consistency monitoring request to the second processing module in the processing unit.

[0185] The processing unit processes the cache consistency monitoring request based on the tag information of the backed-up Level 1 cache entries in the storage unit to obtain a second matching result between the Level 1 cache device and the cache consistency monitoring request. This includes: receiving the cache consistency monitoring request forwarded by the first processing module through the second processing module in the processing unit, processing the cache consistency monitoring request based on the tag information of the backed-up Level 1 cache entries in the storage unit, and obtaining the second matching result.

[0186] In one possible implementation, the method further includes: when the first matching result indicates that the target second-level cache entry in the second-level cache entry is successfully matched with the cache consistency monitoring request and the cache consistency monitoring request is used to request the return of data information, the first processing module reads the data information of the target second-level cache entry from the storage unit and sends response information including the data information of the target second-level cache entry to the third-level cache device.

[0187] In one possible implementation, the method further includes: when the first matching result indicates that the target second-level cache entry in the second-level cache entry is successfully matched with the cache consistency monitoring request and the cache consistency monitoring request is used to request an update of the status, the first processing module sends a response message to the third-level cache device to indicate that the second-level cache device has successfully matched, thereby updating the status of the target second-level cache entry.

[0188] In one possible implementation, the method further includes: when the second matching result indicates that the target first-level cache entry in the first-level cache entry is successfully matched with the cache consistency monitoring request and the cache consistency monitoring request is used to request the return of data information, the second processing module sends a read request to the first-level cache device, the read request being used to request the reading of the data information of the target first-level cache entry; receives the data information of the target first-level cache entry returned by the first-level cache device; sends response information including the data information of the target first-level cache entry to the first processing module; and forwards the response information including the data information of the target first-level cache entry to the third-level cache device through the first processing module.

[0189] In one possible implementation, the method further includes: when the second matching result indicates that the target first-level cache entry in the first-level cache entry matches the cache consistency monitoring request and the cache consistency monitoring request is used to request an update of the status, the second processing module sends response information indicating that the first-level cache device has matched successfully to the first processing module, sends an update request to the first-level cache device, the update request being used to request an update of the status of the target first-level cache entry; and forwards the response information indicating that the first-level cache device has matched successfully to the third-level cache device through the first processing module.

[0190] In one possible implementation, the method further includes: receiving a first access request sent by a first-level cache device through an access request processing module in a second-level cache device, the first access request carrying identification information of the filling position; if there is an access second-level cache entry that is hit by the first access request in the second-level cache entries cached by the cache module in the storage unit, filling in the tag information of the access second-level cache entry in the filling position of the backup module in the storage unit, and sending a first access result to the first-level cache device, the first access result including the access second-level cache entry.

[0191] In one possible implementation, the method further includes: receiving a first access request sent by a first-level cache device through an access request processing module in a second-level cache device, the first access request carrying identification information of the filling position; if there is no second-level cache entry in the cached entries of the cache module in the storage unit that is hit by the first access request, sending a second access request to a third-level cache device; receiving the target cache entry hit by the second access request returned by the third-level cache device; filling in the tag information corresponding to the target cache entry in the filling position of the backup module in the storage unit, and sending a second access result to the first-level cache device, the second access result including the target cache entry.

[0192] The embodiments of the operation method of the above-described secondary cache device belong to the same concept as the embodiments of the secondary cache device described above, and have similar beneficial effects. For technical details not disclosed in the embodiments of the operation method of the secondary cache device, please refer to the description of the embodiments of the secondary cache device in this application for understanding, and will not be repeated here.

[0193] See Figure 8 In one embodiment, a processor 700 is also provided, which includes a Level 1 cache 710, a Level 2 cache 720, and a Level 3 cache 730, wherein the Level 2 cache 720 is any of the Level 2 cache devices described above. In some embodiments, the processor 700 may also be referred to as a processing device, a processing chip, etc.

[0194] In some embodiments, processor 700 may refer to CPU (Central Processing Unit).

[0195] See Figure 9 In one embodiment, an electronic device 800 is also provided, which includes a processor 801. The processor 801 can be a processor provided in the foregoing embodiments (such as...). Figure 8 The processor 700 in the middle.

[0196] Processor 801 includes a Level 1 cache device 8011, a Level 2 cache device 8012, and a Level 3 cache device 8013. The Level 2 cache device 8012 can be the Level 2 cache device provided in the aforementioned embodiments, and the Level 2 cache device 8012 includes, for example: Figure 3 The storage unit 1 and processing unit 2 are shown.

[0197] The electronic device 800 may be, for example, a smartphone, tablet computer, media player, laptop computer, or desktop computer. The electronic device 800 may also be referred to as user equipment, portable terminal, laptop terminal, desktop terminal, or other names. The electronic device 800 may also be a server or any other device that includes the processor 801 described above.

[0198] exist Figure 9 In this process, processor 801 is coupled to memory 802, and it should be understood that electronic device 800 also supports other memory configurations known in the art.

[0199] The memory 802 may include one or more computer-readable storage media, which may be non-transitory, and the computer-readable storage media stores at least one computer program, which is loaded and executed by the processor 801 to enable the electronic device 800 to implement the operation method of any of the above-described secondary cache devices.

[0200] The memory 802 may further include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In some embodiments, the non-transitory computer-readable storage medium in the memory 802 is used to store at least one instruction, which is executed by the processor 801 to enable the electronic device 800 to implement the operation method of the secondary cache device provided in the above method embodiments.

[0201] In one possible implementation, the aforementioned computer-readable storage medium may be a read-only memory (ROM), a random access memory (RAM), a compact disc read-only memory (CD-ROM), magnetic tape, floppy disk, and optical data storage device, etc.

[0202] Figure 9 A display 804 coupled to a processor 801 via a display controller 803 is also shown. In some cases, the electronic device 800 can be used for wireless communication. Figure 9 A speaker 806 and a microphone 807 coupled to a processor 801 via an encoder / decoder 805 are also shown; as well as a wireless antenna 809 coupled to a wireless controller 808.

[0203] Display 804 is used to display a UI (User Interface). This UI may include graphics, text, icons, video, and any combination thereof. When display 804 is a touch screen, it also has the ability to collect touch signals on or above its surface. In this case, display 804 can also provide virtual buttons and / or a virtual keyboard, also known as soft buttons and / or a soft keyboard. In some embodiments, there may be one display 804, disposed on the front panel of electronic device 800; in other embodiments, there may be at least two displays 804, disposed on different surfaces of electronic device 800 or in a folded design; in still other embodiments, display 804 may be a flexible display, disposed on a curved or folded surface of electronic device 800. Furthermore, display 804 may be configured as a non-rectangular, irregular shape, i.e., a non-rectangular screen. Display 804 may be made of materials such as LCD (Liquid Crystal Display) or OLED (Organic Light-Emitting Diode).

[0204] The speaker 806 is used to convert electrical signals from the processor 801 into sound waves. The speaker 806 can be a conventional diaphragm speaker or a piezoelectric ceramic speaker. When the speaker 806 is a piezoelectric ceramic speaker, it can convert electrical signals not only into sound waves that humans can hear, but also into sound waves that humans cannot hear for purposes such as distance measurement.

[0205] Microphone 807 is used to collect sound waves from the user and the environment, and input the sound waves to processor 801 for processing. Multiple microphones 807 can be used for stereo sound acquisition or noise reduction purposes, and can be located in different parts of the electronic device 800. Microphone 807 can also be an array microphone or an omnidirectional microphone.

[0206] The processor 801 and memory 802 may be contained in a system-in-package or system-on-a-chip device.

[0207] Input device 810 and power supply 811 are coupled to system-on-chip device 812. Optionally, as... Figure 9 As shown, when one or more optional boxes are present, the display 804, input device 810, speaker 806, microphone 807, wireless antenna 809, and power supply 811 are external to the system-on-chip device 812. However, each of the display 804, input device 810, speaker 806, microphone 807, wireless antenna 809, and power supply 811 can be coupled to components of the system-on-chip device 812, such as interfaces or controllers.

[0208] The power supply 811 is used to power the various components in the electronic device 800. The power supply 811 can be AC ​​power, DC power, a disposable battery, or a rechargeable battery. When the power supply 811 includes a rechargeable battery, the rechargeable battery can support wired or wireless charging. The rechargeable battery can also be used to support fast charging technology.

[0209] In one possible implementation, the processor 801 and memory 802 may be integrated into any of the following devices: set-top box, server, music player, video player, entertainment unit, navigation device, personal digital assistant (PDA), fixed location data unit, computer, laptop computer, tablet computer, communication device, mobile phone or other similar device.

[0210] The methods described in conjunction with the embodiments of this application can be directly implemented in the software modules executed by the processor 801. The software modules can reside in random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, removable disks, compact disc read-only memory (CDROM), or any other form of storage media known in the art. The storage media is coupled to the processor 801, thereby enabling the processor 801 to read information from and write information to the storage media. Optionally, the storage media can be integrated with the processor 801 as a whole.

[0211] Those skilled in the art will understand that Figure 9 The structures shown do not constitute a limitation on the electronic device. The electronic device may include more or fewer components than shown, or combine certain components, or use different component arrangements.

[0212] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, data stored, data displayed, etc.) and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant countries and regions.

[0213] The terms "first," "second," etc., used in this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. The implementations described in the above exemplary embodiments do not represent all implementations consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application.

[0214] It should be understood that "multiple" as used in this article refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0215] The above description is merely an exemplary embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this application should be included within the protection scope of this application.

Claims

1. A secondary cache device, characterized in that, The secondary cache device includes a storage unit and a processing unit; The storage unit is used to back up the tag information of the first-level cache entries and cache the second-level cache entries corresponding to the second-level cache device, wherein the first-level cache entries are the entries cached by the first-level cache device; The processing unit is used to process the cache consistency monitoring request based on the second-level cache entries cached in the storage unit, and obtain a first matching result between the second-level cache device and the cache consistency monitoring request; The cache consistency monitoring request is processed based on the tag information of the backed-up first-level cache entries in the storage unit to obtain a second matching result between the first-level cache device and the cache consistency monitoring request.

2. The apparatus according to claim 1, characterized in that, The processing unit includes a first processing module and a second processing module; The first processing module is configured to receive the cache consistency monitoring request sent by the level 3 cache device; process the cache consistency monitoring request based on the level 2 cache entries cached in the storage unit to obtain the first matching result; Forward the cache consistency monitoring request to the second processing module; The second processing module is used to receive the cache consistency monitoring request forwarded by the first processing module; The cache consistency monitoring request is processed based on the tag information of the backed-up first-level cache entries in the storage unit to obtain the second matching result.

3. The apparatus according to claim 2, characterized in that, The first processing module is further configured to, when the first matching result indicates that the target second-level cache entry in the second-level cache entry is successfully matched with the cache consistency monitoring request and the cache consistency monitoring request is used to request the return of data information, read the data information of the target second-level cache entry from the storage unit and send response information including the data information of the target second-level cache entry to the third-level cache device.

4. The apparatus according to claim 2, characterized in that, The first processing module is further configured to send response information to the third-level cache device to indicate that the second-level cache device has successfully matched the target second-level cache entry when the first matching result indicates that the target second-level cache entry in the second-level cache entry has successfully matched the cache consistency monitoring request and the cache consistency monitoring request is used to request an update of the status, thereby updating the status of the target second-level cache entry.

5. The apparatus according to claim 2, characterized in that, The second processing module is further configured to, when the second matching result indicates that the target first-level cache entry in the first-level cache entry is successfully matched with the cache consistency monitoring request and the cache consistency monitoring request is used to request the return of data information, send a read request to the first-level cache device, the read request being used to request the reading of the data information of the target first-level cache entry; receive the data information of the target first-level cache entry returned by the first-level cache device; and send response information including the data information of the target first-level cache entry to the first processing module; The first processing module is also used to forward the response information, which includes the data information of the target first-level cache entry, to the third-level cache device.

6. The apparatus according to claim 2, characterized in that, The second processing module is further configured to send response information indicating that the first-level cache device has successfully matched, and send an update request to the first processing module when the second matching result indicates that the target first-level cache entry in the first-level cache entry has successfully matched the cache consistency monitoring request and the cache consistency monitoring request is used to request an update of the status; the second processing module is further configured to send response information indicating that the first-level cache device has successfully matched, and send an update request to the first-level cache device, the update request being used to request an update of the status of the target first-level cache entry. The first processing module is also used to forward the response information indicating that the first-level cache device has successfully matched to the third-level cache device.

7. The apparatus according to any one of claims 1 to 6, characterized in that, The cache consistency monitoring request carries the target physical address, and the second-level cache entry corresponds to tag information. The tag information of the second-level cache entry includes the physical index of the second-level cache entry and the physical tag of the second-level cache entry. The processing unit is configured to determine a target physical index and a target physical tag based on the target physical address; determine candidate secondary cache entries whose physical index matches the target physical index from the secondary cache entries; and determine the first matching result based on the comparison result of the physical tag of the candidate secondary cache entry and the target physical tag.

8. The apparatus according to any one of claims 1 to 6, characterized in that, The cache consistency monitoring request carries the target physical address, and the tag information of the first-level cache entry includes the virtual index of the first-level cache entry and the physical tag of the first-level cache entry; The processing unit is configured to determine a target virtual index and a target physical tag based on the target physical address; determine candidate first-level cache entries in the first-level cache entries whose virtual index matches the target virtual index; and determine the second matching result based on the comparison result of the physical tag of the candidate first-level cache entry and the target physical tag.

9. The apparatus according to any one of claims 1 to 6, characterized in that, The storage unit includes a backup module and a cache module, and the secondary cache device further includes an access request processing module; The backup module is used to back up the tag information of the first-level cache entries; The caching module is used to cache the second-level cache entries; The access request processing module is used to receive a first access request sent by the first-level cache device, wherein the first access request carries the identification information of the filling position; If there is an access second-level cache entry that is hit by the first access request among the second-level cache entries cached by the cache module, the tag information of the access second-level cache entry is filled in the filling position of the backup module, and a first access result is sent to the first-level cache device. The first access result includes the access second-level cache entry.

10. The apparatus according to any one of claims 1 to 6, characterized in that, The storage unit includes a backup module and a cache module, and the secondary cache device further includes an access request processing module; The backup module is used to back up the tag information of the first-level cache entries; The caching module is used to cache the second-level cache entries; The access request processing module is used to receive a first access request sent by the first-level cache device, wherein the first access request carries the identification information of the filling position; If no second-level cache entry is found in the cached second-level cache entries of the cache module that is matched by the first access request, a second access request is sent to the third-level cache device. The system receives the target cache entry returned by the third-level cache device that was hit by the second access request; it fills in the tag information corresponding to the target cache entry at the fill position in the backup module, and sends the second access result to the first-level cache device, wherein the second access result includes the target cache entry.

11. A method for operating a secondary cache device, characterized in that, The method includes: The processing unit in the secondary cache device processes the cache consistency monitoring request based on the secondary cache entries cached in the storage unit of the secondary cache device, and obtains the first matching result between the secondary cache device and the cache consistency monitoring request. The processing unit processes the cache consistency monitoring request based on the tag information of the backed-up first-level cache entries in the storage unit, and obtains a second matching result between the first-level cache device and the cache consistency monitoring request.

12. A processor, characterized in that, The processor includes a level 1 cache, a level 2 cache, and a level 3 cache, wherein the level 2 cache is any one of the level 2 caches described in claims 1-10.

13. An electronic device, characterized in that, The electronic device includes the processor as described in claim 12.

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