Signal separation device and signal separation method
By using a signal separation device in DRAM and changing the phase of the output delayed signal through a buffer, the pulling effect caused by the continuity of DQS signals is solved, achieving effective signal separation and compliance with DRAM specifications.
Patent Information
- Application Number
- CN202411316454.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-06-19
- Filing Date
- 2024-09-20
- Publication Date
- 2025-12-19
AI Technical Summary
The data selection pulse (DQS) signal in dynamic random access memory (DRAM) is a continuous signal, which causes a series of traction effects and affects the signal separation effect.
A signal separation device is used, including a test circuit, a first buffer, and an instruction terminal. The buffer outputs a delayed signal to change the signal phase, ensuring that the pulse value difference between the write level signal and the instruction path signal conforms to the DRAM specification.
This achieves effective separation of the write level signal and the tDQSS signal, meeting DRAM specification requirements and reducing signal interference and latency uncertainty.
Smart Images
Figure CN121171301A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a signal separation device and a signal separation method. Background Technology
[0002] Since the input of the data select pulse (DQS) signal in dynamic random access memory (DRAM) is mostly continuous, and sometimes the DQS signal must be adjusted under certain circumstances, the continuous input DQS signal is often accompanied by a series of traction effects. Summary of the Invention
[0003] This disclosure includes a signal separation device, the device comprising: a memory, the memory including: a test circuit for outputting a test signal; a first buffer for outputting a first delay signal based on the test signal; and an instruction terminal for outputting an instruction path signal based on the test signal and the first delay signal, wherein the first buffer is coupled to the test circuit and the instruction terminal.
[0004] In some embodiments, the memory further includes a second buffer and a write end.
[0005] In some embodiments, the second buffer is used to output a second delayed signal based on the test signal.
[0006] In some embodiments, the write terminal is used to output a write level signal based on the test signal and the first delay signal.
[0007] In some embodiments, the second buffer is coupled to the test circuit and the write terminal.
[0008] In some embodiments, the write level signal includes a first pulse signal and the first pulse signal has a first high pulse value, wherein the instruction path signal includes a second pulse signal and the second pulse signal has a second high pulse value; wherein the first high pulse value is equal to the second high pulse value.
[0009] In some embodiments, the difference between the first high pulse value and the second high pulse value lies in a plurality of N phase periods, where N is a positive integer greater than zero.
[0010] In some embodiments, the N-phase period is related to the first delayed signal and / or the second delayed signal.
[0011] In some embodiments, the memory further includes a first wire and a second wire; wherein the first wire is coupled between the test circuit and the instruction terminal, and wherein the second wire is coupled between the test circuit and the write terminal.
[0012] In some embodiments, the first buffer is located on the first wire, and the second buffer is located on the second wire.
[0013] This disclosure includes a signal separation method, the method comprising: outputting a test signal through a test circuit; outputting a first delayed signal based on the test signal through a first buffer; and outputting a command path signal based on the test signal and the first delayed signal through a command terminal, wherein the first buffer is coupled between the test circuit and the command terminal.
[0014] In some embodiments, the memory includes a test circuit, a first buffer, an instruction terminal, a second buffer, and a write terminal.
[0015] In some embodiments, the above method further includes: outputting a second delayed signal based on the test signal through a second buffer.
[0016] In some embodiments, the above method further includes: outputting a write level signal through the write end based on the test signal and the first delay signal.
[0017] In some embodiments, the second buffer is coupled between the test circuit and the write terminal.
[0018] In some embodiments, the write level signal includes a first pulse signal and the first pulse signal has a first high pulse value, wherein the instruction path signal includes a second pulse signal and the second pulse signal has a second high pulse value; wherein the first high pulse value is equal to the second high pulse value.
[0019] In some embodiments, the difference between the first high pulse value and the second high pulse value lies in a plurality of N phase periods, where N is a positive integer greater than zero.
[0020] In some embodiments, the N-phase period is related to the first delayed signal and / or the second delayed signal.
[0021] In some embodiments, the memory further includes a first wire and a second wire; wherein the first wire is coupled between the test circuit and the instruction terminal, and wherein the second wire is coupled between the test circuit and the write terminal.
[0022] In some embodiments, the first buffer is located on the first wire, and the second buffer is located on the second wire. Attached Figure Description
[0023] The nature of this disclosure is best understood when read in conjunction with the accompanying drawings in the following detailed description. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.
[0024] Figure 1 This is a block diagram illustrating a signal separation device according to one embodiment of the present disclosure.
[0025] Figure 2 This is a block diagram illustrating a signal separation device according to one embodiment of the present disclosure.
[0026] Figure 3 This is a signal timing diagram of multiple data signals of a signal separation device according to one embodiment of the present disclosure.
[0027] Figure 4 This is a flowchart illustrating the steps of a signal separation method according to one embodiment of the present disclosure. Detailed Implementation
[0028] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. Of course, the various components and configurations described are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features are not in direct contact. Additionally, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself determine the relationship between the various embodiments and / or configurations discussed.
[0029] Additionally, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” “top,” “bottom,” and similar terms may be used herein to describe the relationship between one element or feature illustrated in the figures and one or more other elements or features. Besides the orientation depicted in the figures, spatial relative terms are intended to cover different orientations of elements in use or operation. Devices may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein will be interpreted accordingly.
[0030] Figure 1 This is a block diagram illustrating a signal separation device according to one embodiment of the present disclosure. Figure 1 As shown, in some embodiments, the signal separation device 100 includes a memory 110.
[0031] For example, memory 110 may be dynamic random access memory (DRAM), such as DDR3 DRAM, DDR4 DRAM, or DDR5 DRAM, but this disclosure is not limited to this embodiment. In some embodiments, memory 110 may receive data D1, and a processor (e.g., a central processing unit (CPU)) may output data D1.
[0032] In some embodiments, the memory 110 includes a test circuit 111, a first buffer B1, and an instruction terminal 112. The test circuit 111 is used to output a test signal.
[0033] For example, the test signal may be an internal data select pulse (DQS) signal or a data select pulse (DQS) signal, and the test circuit 111 may have a test mode that translates data D1 into a test signal, but this disclosure is not limited to this embodiment. In some embodiments, the DQS signal may be a source synchronization timing reference signal.
[0034] In some embodiments, the first buffer B1 is used to output a first delayed signal based on the test signal.
[0035] For example, the first buffer B1 can be a buffer or an inverter, and the first buffer B1 can be enabled or disabled to change the phase of the test signal. When the first buffer B1 is disabled, the first buffer B1 short-circuits the circuit from the write terminal 113 to the command terminal 112. When the first buffer B1 is enabled, the first buffer B1 delays the test signal to change the phase, but this disclosure is not limited to this embodiment.
[0036] In some embodiments, the instruction terminal 112 is used to output an instruction path signal based on the test signal and the first delay signal.
[0037] For example, the command (CMD) path signal can be a tDQSS signal, and a first system on the chip (System on a Chip, SoC) can receive the command path signal, but this disclosure is not limited to this embodiment. Data is written from the first rising edge of DQS. This time period is called tDQSS. The period of tDQSS can range from 0.75T to 1.25T. In some embodiments, T refers to the length of time in one of a plurality of N-phase periods. The plurality of N-phase periods are defined below regarding Figure 3 Some embodiments are discussed.
[0038] In some embodiments, the input of the first buffer B1 is coupled to the output of the test circuit 111, and the output of the first buffer B1 is coupled to the instruction terminal 112.
[0039] For example, the instruction terminal may have a first wire W1, and a first buffer B1 may be located on the first wire W1, but the present disclosure is not limited to this embodiment.
[0040] In some embodiments, the memory 110 further includes a second wire W2 and a write terminal 113.
[0041] For example, the test circuit 111, the second wire W2, the write terminal 113, the first wire W1, the first buffer B1, and the instruction terminal 112 may be arranged along a first direction (e.g., the X-axis), but this disclosure is not limited to this embodiment.
[0042] Figure 2 This is a block diagram illustrating a signal separation device according to one embodiment of the present disclosure. Figure 2 As shown, in some embodiments, the signal separation device 100A includes a memory 110.
[0043] For example, memory 110 may be DRAM, such as DDR3 DRAM, DDR4 DRAM, or DDR5 DRAM, but this disclosure is not limited to this embodiment. In some embodiments, memory 110 may receive data D1, and a processor (e.g., CPU) may output data D1.
[0044] In some embodiments, the memory 110 includes a test circuit, a first buffer B1, and an instruction terminal 112. The test circuit 111 is used to output a test signal.
[0045] For example, the test signal may be an internal DQS or DQS signal, and the test circuit 111 may have a test mode that translates data D1 into a test signal, but the present disclosure is not limited to this embodiment.
[0046] In some embodiments, the first buffer B1 is used to output a first delayed signal based on the test signal.
[0047] For example, the first buffer B1 can be a buffer or an inverter. The first buffer B1 can change the phase of the test signal by whether or not its own circuit is short-circuited, but the present disclosure is not limited to this embodiment.
[0048] In some embodiments, the instruction terminal 112 is used to output an instruction path signal based on the test signal and the first delay signal.
[0049] For example, the instruction path signal (CMD) can be a tDQSS signal, and the first system on the chip (system-on-a-chip (SoC)) can receive the instruction path signal, but this disclosure is not limited to this embodiment.
[0050] In some embodiments, the first buffer B1 is coupled between the test circuit 111 and the command terminal 112.
[0051] For example, the instruction terminal 112 may have a first wire W1, and the first buffer B1 may be located on the first wire W1, but the present disclosure is not limited to this embodiment.
[0052] In some embodiments, the memory 110 further includes a second buffer B2 and a write terminal 113.
[0053] For example, the write terminal 113 and the instruction terminal 112 may be arranged along a second direction (e.g., the Y-axis), but this disclosure is not limited to this embodiment. In some embodiments, the first direction and the second direction are perpendicular to each other.
[0054] In some embodiments, the second buffer B2 is used to output a second delayed signal based on the test signal.
[0055] For example, the second buffer B2 can be a buffer or an inverter, and the second buffer B2 can be enabled or disabled to change the phase of the test signal. When the second buffer B2 is disabled, it short-circuits the circuit from the write terminal 113 to the command terminal 112. When the second buffer B2 is enabled, it delays the test signal to change its phase, but this disclosure is not limited to this embodiment.
[0056] In some embodiments, the write terminal 113 is used to output a write level signal based on the test signal and the first delay signal.
[0057] For example, a second system on the chip (SoC) may receive a write level signal, but this disclosure is not limited to this embodiment.
[0058] In some embodiments, the input of the second buffer B2 is coupled to the output of the test circuit 111, and the output of the second buffer B2 is coupled to the write terminal 113.
[0059] For example, the write end 113 may have a second wire W2, and the second buffer B2 may be located on the second wire W2, but the present disclosure is not limited to this embodiment.
[0060] In some embodiments, the memory 110 further includes a first wire W1 and a second wire W2. The first wire W1 is coupled between the test circuit 111 and the instruction terminal 112. The second wire W2 is coupled between the test circuit 111 and the write terminal 113.
[0061] In some embodiments, the first buffer B1 is located on the first conductor W1. The second buffer B2 is located on the second conductor W2.
[0062] In some embodiments, Figure 1 or Figure 2 The instruction terminal 112 outputs the instruction path signal, and the instruction path signal can be corresponding to the following... Figure 3 Signal S1 in the middle. Figure 1 or Figure 2 The write terminal 113 outputs a write level signal, and the write level signal can correspond to the following... Figure 3 Signal S2 in the middle.
[0063] In some embodiments, Figure 1 or Figure 2 The instruction terminal 112 outputs the instruction path signal, and the instruction path signal can be corresponding to the following... Figure 3 Signal S2 in the middle. Figure 1 or Figure 2 The write terminal 113 outputs a write level signal, and the write level signal can correspond to the following... Figure 3 Signal S1 in the middle.
[0064] In some embodiments, when resources are limited and the write level signal and instruction path signal need to be separated, the gate delay before instruction pin 112 (or instruction path signal) may be intentionally increased. (However, the relationship between the delay times of the two and the system platform must be confirmed, and it must be ensured that it conforms to the specification definition.)
[0065] Figure 3 This is a signal timing diagram of multiple data signals of a signal separation device according to one embodiment of the present disclosure. Figure 3 As shown, in some embodiments, the signal timing diagram 300 includes multiple signals S0 to S2.
[0066] For example, signal S0 can correspond to Figure 1 or Figure 2 The DQS signal of the test circuit 111 in the middle, signal S1 can correspond to Figure 1 or Figure 2 The write level signal of the write terminal 113, signal S2 can correspond to Figure 1 or Figure 2 The instruction path signal of instruction terminal 112 in the instruction is disclosed, but the content of this disclosure is not limited to this embodiment.
[0067] In some embodiments, the write level signal S1 includes a first pulse signal P1, and the first pulse signal P1 has a first high pulse value h1. The instruction path signal S2 includes a second pulse signal P2, and the second pulse signal P2 has a second high pulse value h2.
[0068] In some embodiments, the first high pulse value h1 is equal to the second high pulse value h2. In some embodiments, the first high pulse value h1 is not equal to the second high pulse value h2.
[0069] In some embodiments, the difference between the first pulse signal P1 and the second pulse signal P2 lies in the presence of multiple N phase periods. N is a positive integer greater than zero.
[0070] For example, the N-phase period may include at least one of the first period PH1 and the second period PH2, and the difference between the first pulse signal P1 and the second pulse signal P2 may be the second period PH2, but the present disclosure is not limited to this embodiment.
[0071] In some embodiments, the N-phase period is related to the first delayed signal and / or the second delayed signal.
[0072] For example, the first delayed signal may have a first delay time, the second delayed signal may have a second delay time, and the N-phase period may be the sum of the first delayed signal and the second delayed signal, but the present disclosure is not limited to this embodiment.
[0073] In some embodiments, the DQS signal S0 includes a start pulse signal P0, and the start pulse signal P0 has a start high pulse value h0.
[0074] In some embodiments, the activation high pulse value h0 is equal to the first high pulse value h1 and / or the second high pulse value h2. In some embodiments, the activation high pulse value h0 is not equal to the first high pulse value h1 and / or the second high pulse value h2.
[0075] In some embodiments, the difference between the start pulse signal P0 and the first pulse signal P1 may be a first period PH1. In some embodiments, the first period PH1 may be equal to the second period PH2. In some embodiments, the first period PH1 may not be equal to the second period PH2.
[0076] In some embodiments, the first period PH1 may be 0.25T, and the second period PH2 may be 0.25T.
[0077] Figure 4 This is a flowchart illustrating the steps of a signal separation method according to one embodiment of the present disclosure. Figure 4 As shown, in some embodiments, the signal separation method 400 includes multiple steps 410 to 430.
[0078] In step 410, a test signal is output through the test circuit.
[0079] refer to Figures 1 to 4 In some embodiments, test circuit 111 outputs a test signal. For example, the operation of signal separation method 400 is similar to... Figure 1 The operation of the signal separation device 100 is described here, and for the sake of brevity, other operations of the signal separation method 400 will be omitted here.
[0080] In step 420, a first delayed signal is output through the first buffer based on the test signal.
[0081] refer to Figures 1 to 4 In some embodiments, the first buffer B1 outputs a first delayed signal based on the test signal. For example, the operation of signal separation method 400 is similar to... Figure 1 The operation of the signal separation device 100 is described here, and for the sake of brevity, other operations of the signal separation method 400 will be omitted here.
[0082] In step 430, the command path signal is output through the command terminal based on the test signal and the first delay signal.
[0083] refer to Figures 1 to 4 In some embodiments, the command terminal 112 outputs a command path signal based on the test signal and the first delay signal. For example, the operation of the signal separation method 400 is similar to... Figure 1 The operation of the signal separation device 100 is described here, and for the sake of brevity, other operations of the signal separation method 400 will be omitted here.
[0084] In some embodiments, the first buffer B1 is coupled between the test circuit 111 and the command terminal 112. For example, the operation of the signal separation method 400 is similar to... Figure 1 The operation of the signal separation device 100 is described here, and for the sake of brevity, other operations of the signal separation method 400 will be omitted here.
[0085] In some embodiments, the memory 110 includes a test circuit 111, a first buffer B1, an instruction terminal 112, a second buffer B2, and a write terminal 113. For example, the operation of the signal separation method 400 is similar to... Figure 1 The operation of the signal separation device 100 is described here, and for the sake of brevity, other operations of the signal separation method 400 will be omitted here.
[0086] In some embodiments, the signal separation method 400 further includes the following steps: outputting a second delayed signal through a second buffer B2 based on the test signal. For example, the operation of the signal separation method 400 is similar to... Figure 1 The operation of the signal separation device 100 is described here, and for the sake of brevity, other operations of the signal separation method 400 will be omitted here.
[0087] In some embodiments, the signal separation method 400 further includes the following steps: outputting a write level signal through a write terminal based on a test signal and a first delay signal. For example, the operation of the signal separation method 400 is similar to... Figure 1 The operation of the signal separation device 100 is described here, and for the sake of brevity, other operations of the signal separation method 400 will be omitted here.
[0088] In some embodiments, the second buffer B2 is coupled between the test circuit 111 and the write terminal 113. For example, the operation of the signal separation method 400 is similar to... Figure 1 The operation of the signal separation device 100 is described here, and for the sake of brevity, other operations of the signal separation method 400 will be omitted here.
[0089] In some embodiments, the write level signal S1 includes a first pulse signal P1, and the first pulse signal P1 has a first high pulse value h1. The instruction path signal S2 includes a second pulse signal P2, and the second pulse signal P2 has a second high pulse value h2.
[0090] For example, the operation of signal separation method 400 is similar to... Figure 1 The operation of the signal separation device 100 is described here, and for the sake of brevity, other operations of the signal separation method 400 will be omitted here.
[0091] In some embodiments, the difference between the first pulse signal P1 and the second pulse signal P2 is a plurality of N phase periods. N is a positive integer greater than zero. For example, the operation of the signal separation method 400 is similar to... Figure 1 The operation of the signal separation device 100 is described here, and for the sake of brevity, other operations of the signal separation method 400 will be omitted here.
[0092] In some embodiments, the plurality of N-phase periods are associated with a first delayed signal and / or a second delayed signal. For example, the operation of signal separation method 400 is similar to... Figure 1 The operation of the signal separation device 100 is described here, and for the sake of brevity, other operations of the signal separation method 400 will be omitted here.
[0093] In some embodiments, the memory 110 further includes a first wire W1 and a second wire W2. The first wire W1 is coupled between the test circuit 111 and the instruction terminal 112. The second wire W2 is coupled between the test circuit 111 and the write terminal 113. For example, the operation of the signal separation method 400 is similar to... Figure 1 The operation of the signal separation device 100 is described here, and for the sake of brevity, other operations of the signal separation method 400 will be omitted here.
[0094] In some embodiments, the first buffer B1 is located on the first conductor W1. The second buffer B2 is located on the second conductor W2. For example, the operation of the signal separation method 400 is similar to... Figure 1 The operation of the signal separation device 100 is described here, and for the sake of brevity, other operations of the signal separation method 400 will be omitted here.
[0095] As can be seen from the above embodiments of this disclosure, the application of this disclosure has the following advantages. The signal separation device and signal separation method in the embodiments of this disclosure can separate the DQS signal to achieve the effect that the write level signal and the tDQSS signal conform to the DRAM specification.
[0096] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures for implementing the same purpose and / or achieving the advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.
[0097] [Symbol Explanation]
[0098] 100, 100A: Signal separation device
[0099] 110: Memory
[0100] 111: Test Circuit
[0101] 112: Command Terminal
[0102] 113: Write end
[0103] 300: Timing Diagram
[0104] 400: Method
[0105] 410, 420, 430: Steps.
Claims
1. A signal separating device, characterized by, The apparatus comprises: a memory comprising: a test circuit to output a test signal; a first buffer to output a first delayed signal according to the test signal; and an instruction end to output an instruction path signal according to the test signal and the first delayed signal, wherein the first buffer is coupled between the test circuit and the instruction end.
2. The apparatus of claim 1, wherein the memory further comprises a second buffer and a write end.
3. The apparatus of claim 2, wherein the second buffer is to output a second delayed signal according to the test signal.
4. The apparatus of claim 3, wherein the write end is to output a write level signal according to the test signal and the first delayed signal.
5. The apparatus of claim 4, wherein the second buffer is coupled between the test circuit and the write end.
6. The apparatus of claim 5, wherein the write level signal comprises a first pulse signal, and the first pulse signal has a first pulse value, wherein the instruction path signal comprises a second pulse signal, and the second pulse signal has a second pulse value; wherein the first pulse value is equal to the second pulse value.
7. The apparatus of claim 6, wherein the first pulse value and the second pulse value differ by a plurality of N phase periods, where N is a positive integer greater than zero.
8. The apparatus of claim 7, wherein the plurality of N phase periods is related to the first delayed signal and / or the second delayed signal.
9. The apparatus of claim 2, wherein the memory further comprises a first wire and a second wire; wherein the first wire is coupled between the test circuit and the instruction end, wherein the second wire is coupled between the test circuit and the write end.
10. The apparatus of claim 9, wherein the first buffer is on the first wire, wherein the second buffer is on the second wire.
11. A method of signal separation, characterized by, The method comprises: outputting, by a test circuit, a test signal; outputting, by a first buffer, a first delayed signal according to the test signal; and outputting, by an instruction end, an instruction path signal according to the test signal and the first delayed signal, wherein the first buffer is coupled between the test circuit and the instruction end.
12. The method of claim 11, wherein the memory comprises the test circuit, the first buffer, the instruction end, a second buffer, and a write end.
13. The method of claim 12, wherein, further comprising: outputting, by the second buffer, a second delayed signal according to the test signal.
14. The method of claim 13, wherein, further comprising: outputting, by the write end, a write level signal according to the test signal and the first delayed signal.
15. The method of claim 14, wherein the second buffer is coupled between the test circuit and the write end.
16. The method of claim 15, wherein the write level signal comprises a first pulse signal, and the first pulse signal has a first pulse value, wherein the instruction path signal comprises a second pulse signal, and the second pulse signal has a second pulse value; wherein the instruction path signal comprises a second pulse signal, and the second pulse signal has a second high pulse value; wherein the first high pulse value is equal to the second high pulse value.
17. The method of claim 16, wherein, the first high pulse value and the second high pulse value differ by a plurality of N phase periods, where N is a positive integer greater than zero.
18. The method of claim 17, wherein, the plurality of N phase periods are related to the first delay signal and / or the second delay signal.
19. The method of claim 12, wherein, the memory further comprises a first wire and a second wire; wherein the first wire is coupled between the test circuit and the instruction terminal, and the second wire is coupled between the test circuit and the write terminal.
20. The method of claim 19, wherein, the first buffer bit is on the first wire, wherein the second buffer bit is on the second wire.