Wafer-level heat dissipation structure and manufacturing method

Abstract

The invention discloses a wafer-level heat dissipation structure and a manufacturing method. The wafer-level heat dissipation structure comprises a heat dissipation substrate, a device wafer and a bonding layer, the heat dissipation substrate is a first silicon wafer with a diamond layer growing on the lower surface, and the upper surface of the heat dissipation substrate is plated with a first copper layer; the device wafer is a second silicon wafer of which the upper surface is integrated with an active device, and the lower surface is plated with a second copper layer; the bonding layer is composed of a Cu-Cu bonding interface formed by the first copper layer and the second copper layer through thermocompression bonding. The method comprises the following steps: growing a diamond layer on the lower surface of a first silicon wafer through MPCVD, and sputtering a Cu layer after the upper surface is thinned; sputtering a Cu layer on the back surface of the second silicon wafer of which the surface is integrated with the active device; and finally realizing interconnection of the Cu layers of the two wafers through thermocompression bonding. The problem of multi-interface thermal resistance caused by a traditional thermal interface material is avoided, an ultra-low thermal resistance path from a chip junction to a diamond heat dissipation surface is constructed, and the method is particularly suitable for thermal management of a high-power-density semiconductor device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor heat dissipation, in particular to a wafer-level heat dissipation structure and a manufacturing method, which are suitable for high-performance chips, power devices and other semiconductor products with high heat dissipation requirements, can effectively improve the heat management efficiency of the device, and guarantee the long-term stable operation of the device. BACKGROUND

[0002] With the rapid development of semiconductor technology towards high integration and high power density, a large amount of heat will be generated during the operation of the chip. If the heat cannot be dissipated in time and effectively, the temperature of the chip will rise, which will not only reduce the working performance of the device and shorten the service life, but also may cause serious faults such as chip burning. At present, the traditional chip heat dissipation mode mainly adopts a multi-layer structure of "chip - heat dissipation paste - heat dissipation sheet" or "chip - thermal interface material - heat dissipation substrate", and the gap between the chip and the heat dissipation component is filled with thermal interface material to realize heat transfer.

[0003] However, the traditional heat dissipation structure has obvious defects: on the one hand, the thermal conductivity of the thermal interface material itself is low, and in the process of multi-layer stacking, each additional layer of thermal interface will increase a thermal resistance link, resulting in a significant reduction in overall heat dissipation efficiency; on the other hand, the thermal interface material is prone to aging, drying and other problems during long-term use, which will cause the interface contact performance to decrease and further aggravate the problem of increased thermal resistance. Especially for high-performance devices at wafer level, the traditional heat dissipation mode cannot meet the demand for low thermal resistance and high reliability of heat dissipation, therefore, developing a wafer-level heat dissipation structure and manufacturing method capable of reducing thermal interface and realizing efficient heat management has become a key problem to be solved in the semiconductor industry. SUMMARY

[0004] The present application aims to overcome the shortcomings of the prior art, and provides a wafer-level heat dissipation structure and manufacturing method, which can reduce the number of thermal interfaces, reduce the overall thermal resistance, realize efficient heat management, and meet the heat dissipation requirements of high-performance semiconductor devices by optimizing the design and manufacturing process of the heat dissipation structure.

[0005] The present application provides a wafer-level heat dissipation structure, which comprises a heat dissipation substrate, a device wafer and a bonding layer, The heat dissipation substrate is a first silicon wafer with a diamond layer grown on the lower surface, and a first copper layer plated on the upper surface; The device wafer is a second silicon wafer with active devices integrated on the upper surface, and a second copper layer plated on the lower surface; The bonding layer is a Cu-Cu bonding interface formed by hot pressing the first copper layer and the second copper layer.

[0006] Further, the thickness of the diamond layer is 20-200 microns; the thickness of the first silicon wafer is 50-300 microns.

[0007] Further, the thickness of the first copper layer and the second copper layer is 1-3 microns.

[0008] Further, the thickness of the bonding layer is 1-5 microns.

[0009] Further, a Cr or Ti seed layer is arranged between the first copper layer and the first silicon wafer or between the second copper layer and the second silicon wafer.

[0010] The application further provides a manufacturing method of the wafer-level heat dissipation structure, comprising the following steps: S1: providing a first silicon wafer and cleaning the same; S2: growing a diamond layer on the lower surface of the first silicon wafer; S3: performing thinning treatment on the upper surface of the first silicon wafer; S4: plating a first copper layer on the upper surface of the thinned first silicon wafer; S5: providing a second silicon wafer integrated with an active device, plating a second copper layer on the back surface of the second silicon wafer after removing the oxide layer on the back surface of the second silicon wafer; S6: aligning the Cu surfaces of the first silicon wafer and the second silicon wafer, performing Cu-Cu thermal pressure bonding to form a bonding layer.

[0011] In step S1, the crystal orientation of the silicon wafer can be <100> or <111> according to requirements; In step S1, the surface of the first silicon wafer is cleaned by using RCA standard cleaning process: first, immerse the first silicon wafer in a cleaning solution with a volume ratio of NH4OH:H2O2:H2O=1:1:5 at 70-80℃ for 10-15 minutes to remove organic contaminants; then immerse the first silicon wafer in a cleaning solution with a volume ratio of HCl:H2O2:H2O=1:1:5 at 70-80℃ for 10-15 minutes to remove metal ions; finally, rinse the first silicon wafer with ultrapure water for 5-10 minutes and dry it with nitrogen to ensure that the surface of the first silicon wafer is free of impurities.

[0012] In step S2, a diamond layer is grown on the lower surface of the first silicon wafer by using a microwave plasma chemical vapor deposition (MPCVD) technique; the specific process parameters are as follows: the reaction gas is a mixed gas of methane (CH4) and hydrogen (H2), wherein the volume fraction of CH4 is 1%-5%, and the total gas flow is 200-500 sccm; the microwave power is 1k-10kW, the deposition pressure is 10-100 kPa, the deposition temperature is 800-1200℃, and the deposition time is 5-24 hours; by controlling the reaction parameters, the thickness of the grown diamond layer is adjusted to ensure that it has excellent thermal conductivity and surface flatness.

[0013] In step S3, the thinning process includes mechanical grinding and chemical mechanical polishing performed in sequence. First, the silicon wafer 1 is thinned to a specified thickness by mechanical grinding (the grinding liquid is silicon carbide abrasive with a particle size of 800-1200 mesh); then chemical mechanical polishing is performed, the polishing liquid is a silica sol polishing liquid (with a particle size of 50-100 nm), the polishing pressure is 0.1-0.3 MPa, the polishing rotation speed is 30-50 rpm, and the polishing time is 10-20 minutes, so that the roughness (Ra) of the upper surface of the silicon wafer 1 is reduced to 0.01-0.05 microns, providing a flat substrate for the subsequent sputtering of the Cu layer.

[0014] In steps S4 and S5, a copper layer is plated by using a magnetron sputtering technique. Before sputtering, the silicon wafer 1 is placed in a sputtering chamber, vacuumed to 1×10 -4 ~5×10 -4 Pa, and then argon (Ar) is introduced as the sputtering gas, with an argon flow of 50-100 sccm and a chamber working pressure of 0.1-0.5 Pa; a Cu target with a purity of 99.999% is used as the sputtering target material, with a sputtering power of 200-500 W and a sputtering time of 5-15 minutes; by adjusting the sputtering parameters, the thickness of the Cu layer is controlled.

[0015] In step S5, a single crystal silicon wafer matching the diameter of the first silicon wafer is selected as the second silicon wafer, and a conventional semiconductor manufacturing process is used to integrate active devices on the upper surface of the silicon wafer 2, forming a complete device structure; after integration, the upper surface of the silicon wafer 2 is protected, and temporary protective tape can be attached to avoid damage to the active devices in subsequent processes.

[0016] The second silicon wafer is soaked in a 5-10% volume fraction hydrofluoric acid solution for 10-30 seconds, then rinsed with ultrapure water and dried with nitrogen to remove the oxide layer on the back of the second silicon wafer, and then a layer of Cu is plated on the back of the second silicon wafer (the side without active devices) using the same magnetron sputtering process as in step S2; the thickness, density and adhesion of the Cu layer are required to be consistent with the first silicon wafer to ensure the reliability of subsequent thermal pressure bonding.

[0017] In step S6, the silicon wafer treated in the foregoing steps is placed on the alignment platform of the thermal pressure bonding equipment, and the first silicon wafer and the second silicon wafer are precisely aligned through an optical alignment system (alignment accuracy ≤1 micron) to ensure that the active device region of the second silicon wafer corresponds to the heat dissipation region of the first silicon wafer, avoiding bonding offset affecting heat dissipation effect.

[0018] After alignment, pressure and temperature are applied to the first silicon wafer and the second silicon wafer for Cu-Cu thermal pressure bonding, the bonding temperature is 300-400℃, the bonding pressure is 5-15 MPa, the bonding time is 30-60 minutes, and the bonding atmosphere is inert gas (such as nitrogen or argon) to avoid oxidation of the Cu coating at high temperature; during the thermal pressure process, atoms in the Cu coating diffuse, forming a seamless bonding layer between the Cu coating of the first silicon wafer and the second silicon wafer, realizing the close combination of the two; after bonding, it is naturally cooled to room temperature to obtain a complete wafer-level heat dissipation structure.

[0019] The size of the silicon wafer is preferably 6-12 inches in diameter and 500-700 microns in thickness.

[0020] Before sputtering the Cu layer, a seed layer of Cr or Ti can be sputtered on the silicon surface to enhance the adhesion between Cu and silicon.

[0021] The diamond layer is polycrystalline diamond; nano-diamond seed treatment is performed before growth to optimize the growth quality.

[0022] The adhesion of the Cu layer to the surface of the silicon wafer is ≥50 MPa.

[0023] As Figure 1As shown, the heat dissipation substrate serves as a heat export carrier of the entire heat dissipation structure, the lower surface of the silicon wafer 1 is grown with a diamond layer, and the upper surface is coated with a Cu layer; wherein the diamond layer has an extremely high thermal conductivity of 1000-2000 W / (m•K) and is the core heat dissipation functional layer for quickly conducting and dissipating heat; the Cu layer serves as a transition layer for thermal compression bonding on one hand to ensure reliable bonding with the silicon wafer 2, and on the other hand can assist in heat transfer from the second silicon wafer to the first silicon wafer. The active device includes a transistor, a diode, and an integrated circuit. The bonding layer does not have additional thermal interface material and is directly tightly combined through the diffusion of metal atoms, has extremely low thermal resistance, and can efficiently transfer the heat generated by the second silicon wafer.

[0024] As shown in Figure 2 a) shows the structure of the first silicon wafer after RCA cleaning, b) shows the structure after growing diamond on the lower surface of the first silicon wafer by MPCVD, c) shows the structure after thinning the upper surface of the first silicon wafer, d) shows the structure after sputtering a Cu layer on the upper surface of the first silicon wafer, e) shows the structure of the second silicon wafer integrated with active devices, f) shows the structure after sputtering a Cu layer on the lower surface of the second silicon wafer, g) shows a schematic diagram of the finally completed wafer-level heat dissipation structure.

[0025] Compared with the prior art, the beneficial technical effects of the present application are embodied in: 1) Cu-Cu thermal compression bonding is adopted to avoid the use of traditional thermal interface material (TIM), reduce the thermal interface, and greatly reduce the interface thermal resistance. A high-efficiency heat dissipation path of "chip active area -> silicon substrate -> Cu bonding layer -> silicon substrate -> diamond" is constructed. Among them, the Cu bonding layer and the diamond layer both have extremely high thermal conductivity, which ensures that the heat can be quickly exported.

[0026] 2) The MPCVD, sputtering, thinning, and thermal compression bonding adopted are mature semiconductor processes, which are easy to integrate into existing production lines to realize wafer-level mass production.

[0027] 3) Cu-Cu bonding not only provides an excellent heat conduction path, but also provides good mechanical connection strength, improving the reliability of the package.

[0028] 4) The structure is particularly suitable for providing an efficient heat dissipation solution for 5G radio frequency devices, lasers, power ICs, and high-performance computing chips. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1The exploded view of the wafer-level heat dissipation structure product prepared in the application; Figure 2 The process flow chart for manufacturing.

[0030] wherein, Figure 1 In the figure, 1-diamond layer, 2-first silicon wafer, 3-bonding layer, 4-second silicon wafer, 5-active region; Figure 2 In the figure, a) shows the structure of the first silicon wafer after RCA cleaning, b) shows the structure after growing diamond on the lower surface of the first silicon wafer by MPCVD, c) shows the structure after thinning the upper surface of the first silicon wafer, d) shows the structure after sputtering Cu layer on the upper surface of the first silicon wafer, e) shows the structure of the second silicon wafer integrated with active devices, f) shows the structure after sputtering Cu layer on the lower surface of the second silicon wafer, g) shows the schematic diagram of the finally completed wafer-level heat dissipation structure. DETAILED DESCRIPTION

[0031] In order to make the above-mentioned purposes, features and advantages of the application more obvious and easy to understand, the specific embodiments of the application will be described in detail below with reference to the accompanying drawings.

[0032] In the following description, many specific details are set forth in order to provide a thorough understanding of the application, but the application can also be practiced without other different ways from those described herein, and those skilled in the art can make similar generalizations without departing from the spirit of the application, therefore the application is not limited to the specific embodiments disclosed below.

[0033] Secondly, the "one embodiment" or "embodiment" referred to herein means that the specific features, structures or characteristics can be included in at least one implementation of the application. "In one embodiment" appearing in different places in the specification does not mean the same embodiment, nor is it an independent or alternative embodiment.

[0034] The embodiments of the application will be described in detail below with reference to the accompanying drawings.

[0035] Embodiment 1 The wafer-level heat dissipation structure manufacturing method comprises the following steps: S1: Select a 6-inch, 600-micron-thick <100> single crystal silicon wafer as the silicon wafer 1, and clean the surface of the silicon wafer 1 by RCA standard cleaning process.

[0036] S2: growing diamond layer by MPCVD technology: the reaction gas is a mixture of methane (CH4) and hydrogen (H2), the volume fraction of CH4 in the reaction gas is 3%, the total flow is 300 sccm, the microwave power is 10 kW, the deposition pressure is 30 kPa, the deposition temperature is 900℃, and the deposition time is 12 hours; finally, a diamond layer with a thickness of 100 microns and Ra=0.3 microns is obtained.

[0037] S3: thinning the upper surface of the silicon wafer 1 to 100 microns by mechanical grinding, and then polishing to Ra=0.03 microns by CMP; S4: coating a first copper layer on the upper surface of the thinned first silicon wafer: using magnetron sputtering to coat Cu, Ar flow is 80 sccm, using a Cu target with a purity of 99.999% as the sputtering target material, working pressure is 0.3 Pa, sputtering power is 350 W, sputtering time is 10 minutes, a Cu coating layer with a thickness of 2 microns is obtained, and the bonding force test is 65 MPa.

[0038] S5: selecting a 6-inch, 700-micron-thick <100> single crystal silicon wafer as the silicon wafer 2, after the power device is integrated on the upper surface, the back surface is cleaned with hydrofluoric acid, and a 2-micron-thick Cu layer is coated on the back surface of the silicon wafer 2 by using the same sputtering process as S3, and the bonding force is 62 MPa.

[0039] S6: after aligning the silicon wafer 1 and the silicon wafer 2, heat pressing and bonding under a nitrogen atmosphere, the bonding temperature is 350℃, the bonding pressure is 10 MPa, and the bonding time is 45 minutes.

[0040] After cooling, it is detected under a high-resolution scanning electron microscope that the bonding layer has good compactness. The interface thermal resistance is tested by the transient thermal reflection method, and the test result is 5×10 -4 K·m 2 / W, compared with the traditional Sn-based solder welding interface heat dissipation structure (thermal resistance 2×10 -3 K·m 2 / W), the thermal resistance is reduced by 75%, and the heat dissipation efficiency is significantly improved.

[0041] Example 2 S1: selecting a 12-inch, 700-micron-thick <111> single crystal silicon wafer as the silicon wafer 1.

[0042] S2: RCA cleaning, then growing diamond layer by MPCVD; CH4 volume fraction 5%, total flow 500 sccm, microwave power 3000 W, deposition pressure 50 kPa, deposition temperature 1000℃, deposition time 6 hours; diamond layer thickness 20 microns, Ra=0.5 microns.

[0043] S3: mechanical grinding to 400 microns, CMP polishing to Ra=0.05 microns; S4: magnetron sputtering Cu on the first silicon wafer after thinning, Ar flow 100 sccm, working pressure 0.5 Pa, sputtering power 500 W, sputtering time 15 minutes, Cu coating thickness 3 microns, bonding strength 70 MPa.

[0044] S5: silicon wafer 2 pretreatment and back Cu coating sputtering: 12 inches, thickness 800 microns of <111> crystal direction silicon wafer 2, after integrated circuit on the upper surface, 3 microns thick Cu coating on the back, bonding strength 68 MPa.

[0045] S6: after aligning silicon wafer 1 and silicon wafer 2, heat pressing bonding under nitrogen atmosphere, bonding temperature 400℃, pressure 15 MPa, time 60 minutes.

[0046] After bonding, detect under high-resolution scanning electron microscope, the bonding layer has good compactness, test the interface thermal resistance by transient thermal reflection method, the test result is 8x10 -4 K·m 2 / W, the heat dissipation performance is stable, which can meet the long-term heat dissipation demand of high-performance integrated circuits.

[0047] The above examples are only part of the application scenarios of the present application, in actual production, the diamond layer thickness, Cu coating parameters and heat pressing bonding process can be adjusted according to wafer size, device type and heat dissipation demand; the present application removes the thermal interface material in the traditional heat dissipation structure through the structural design of "silicon wafer 1 + diamond layer + Cu-Cu bonding + silicon wafer 2", greatly reduces the thermal resistance, realizes wafer-level efficient heat management, and has wide industrial application prospect.

[0048] The above detailed description is a specific description of one feasible embodiment of the present application, which is not used to limit the patent scope of the present application, and equivalent implementation or changes made without departing from the present application shall be included in the scope of the technical solutions of the present application.

[0049] It should be particularly pointed out that the various embodiments listed in the specification and drawings are intended to illustrate the technical solutions of the present application and their advantages, and are not intended to limit the protection scope of the present application. Without departing from the core idea and technical effects of the present application, those skilled in the art can make any form of improvement, replacement, combination or deformation on the structure arrangement, process parameters, material selection, control logic, etc. of the embodiments; any obvious changes based on the same concept should be regarded as equivalent solutions of the present application, and should be included in the protection scope defined by the claims of the present application. The actual protection scope of the present application is subject to the appended claims, and should be correctly understood in combination with the specification and drawings.

Claims

1. A wafer-level heat dissipation structure, characterized in that, This includes the heat dissipation substrate, device wafer, and bonding layer. The heat dissipation substrate is a first silicon wafer with a diamond layer grown on its lower surface and a first copper layer plated on its upper surface. The device wafer is a second silicon wafer with active devices integrated on its upper surface and a second copper layer plated on its lower surface. The bonding layer is composed of a Cu-Cu bonding interface formed by hot-pressing the first copper layer and the second copper layer.

2. The wafer-level heat dissipation structure according to claim 1, characterized in that, The thickness of the diamond layer is 20-200 micrometers; the thickness of the first silicon wafer is 50-300 micrometers.

3. The wafer-level heat dissipation structure according to claim 1, characterized in that, The thickness of both the first copper layer and the second copper layer is 1-3 micrometers.

4. The wafer-level heat dissipation structure according to claim 1, characterized in that, The thickness of the bonding layer is 1-5 micrometers.

5. The wafer-level heat dissipation structure according to claim 1, characterized in that, A Cr or Ti seed layer is provided between the first copper layer and the first silicon wafer or between the second copper layer and the second silicon wafer.

6. A method for fabricating a wafer-level heat dissipation structure as described in any one of claims 1-5, characterized in that, Includes the following steps: S1: Provide the first silicon wafer and perform cleaning; S2: A diamond layer is grown on the lower surface of the first silicon wafer; S3: Thin the upper surface of the first silicon wafer; S4: A first copper layer is deposited on the upper surface of the thinned first silicon wafer; S5: Provide a second silicon wafer with integrated active devices, remove the oxide layer on the back side of the second silicon wafer, and then plate a second copper layer on the back side of the second silicon wafer. S6: Align the Cu surfaces of the first silicon wafer and the second silicon wafer, and perform Cu-Cu hot-press bonding to form a bonding layer.

7. The manufacturing method according to claim 6, characterized in that, In step S2, a diamond layer is grown using microwave plasma chemical vapor deposition.

8. The manufacturing method according to claim 6, characterized in that, In step S3, the thinning process includes sequential mechanical grinding and chemical mechanical polishing.

9. The manufacturing method according to claim 6, characterized in that, In steps S4 and S5, a copper layer is deposited using magnetron sputtering technology.

10. The manufacturing method according to claim 6, characterized in that, In step S6, the pressure for hot-press bonding is 5-15 MPa, the temperature is 300-400℃, and the bonding time is 30-60 minutes.

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