Digital signal amplitude modulation system

Abstract

The invention discloses a digital signal amplitude modulation system which comprises a control module, an adjustable voltage module, a first driving module, a switching circuit and a second driving module. Wherein the control module outputs a voltage control signal to the adjustable voltage module through a first output end, and outputs a first logic signal to the second driving module through a second output end; the adjustable voltage module outputs a second logic signal according to the voltage control signal, and the level value of the second logic signal depends on the voltage control signal; the first driving module enhances the second logic signal and outputs the enhanced second logic signal to the switching circuit; the second driving module receives the first logic signal and outputs two paths of differential signals with opposite phases to the switching circuit; the switching circuit responds to the second logic signal and the differential signal and outputs a third logic signal, the level value of the third logic signal corresponds to the second logic signal, and the phase of the third logic signal is the same as the phase of one signal in the differential signal.

Description

Technical Field

[0001] This invention relates to the field of digital signal processing, and more specifically, to a digital signal amplitude modulation system. Background Technology

[0002] Digital signals are widely used in various electronic devices, including communication equipment and information processing equipment. Compared to analog signals, digital signals have distinct advantages, including stronger anti-interference capabilities, better security, easier storage, and the ability to communicate directly with computers.

[0003] In some application scenarios, digital interfaces have requirements on the amplitude of logic signals, especially in some high-signal-bandwidth scenarios. Custom bus types may require the amplitude of logic signals to reach a certain threshold in order to enable digital signals to have a certain driving capability.

[0004] However, the logic signal levels in current digital circuits are usually fixed. For example, common logic signal levels include 1.2V, 1.8V, 2.5V, 3.3V, and 5V. On the one hand, common digital signal circuits do not have the function of adjusting the amplitude of digital signals, and cannot flexibly control the level according to actual needs. On the other hand, when the frequency of digital signals is very high, it is necessary to ensure that the frequency of the amplitude-modulated digital signal is not affected.

[0005] However, no effective solution has yet been proposed for how to achieve amplitude modulation of digital signals while ensuring that the frequency of the digital signals is not affected. Summary of the Invention

[0006] The purpose of this invention is to provide a digital signal amplitude modulation system that can perform amplitude modulation on digital signals and is applicable to high-frequency scenarios.

[0007] The digital signal amplitude modulation system according to the present invention includes a control module, an adjustable voltage module, a first driving module, a switching circuit, and a second driving module. The control module has a first output terminal and a second output terminal. The control module outputs a voltage control signal to the adjustable voltage module through the first output terminal. The control module outputs a first logic signal to the second driving module through the second output terminal. The adjustable voltage module outputs a second logic signal according to the voltage control signal, the level of the second logic signal depending on the voltage control signal. The first driving module amplifies the second logic signal to improve its driving capability and outputs the amplified second logic signal to the switching circuit. The second driving module receives the first logic signal and outputs two differential signals with opposite phases to the switching circuit. The switching circuit responds to the second logic signal and the differential signals, outputting a third logic signal, wherein the level of the third logic signal corresponds to the second logic signal, and its phase is the same as the phase of one of the differential signals.

[0008] The switching circuit includes a first switching transistor Q1 and a second switching transistor Q2. The second driving module includes a differential amplifier circuit and a fourth switching transistor Q4. One output terminal of the differential amplifier circuit is connected to the first switching transistor Q1 via the fourth switching transistor Q4. The other output terminal of the differential amplifier circuit is connected to the second switching transistor Q2.

[0009] Furthermore, the fourth switch Q4 is turned on or off under the control of the first differential signal output by the differential amplifier circuit; the second switch Q2 is turned on or off under the control of the second differential signal output by the differential amplifier circuit.

[0010] When the level of the first differential signal is high and the fourth switch Q4 is turned on, the first switch Q1 is turned on, the level of the second differential signal is low and the second switch Q2 is turned off.

[0011] The differential amplifier circuit provides the first differential signal to the first switch Q1. Under the action of the second logic signal, the differential signal pulls the level of the first differential signal high to obtain the third logic signal, which is then output through the first switch Q1.

[0012] When the level of the first differential signal is low and the fourth switch Q4 is turned off, the first switch Q1 is turned off, the level of the second differential signal is high and the second switch Q2 is turned on and the switching circuit is grounded, and the third logic signal is low.

[0013] In one embodiment, the second driving module further includes a constant current source and a third switch Q3; wherein the constant current source is connected to the first switch Q1 via the third switch Q3, the state of the third switch Q3 follows that of the fourth switch Q4, and the constant current source is used to maintain the current of the first differential signal when the fourth switch Q4, the third switch Q3, and the first switch Q1 are turned on.

[0014] Furthermore, in one embodiment, the second driving module further includes: a first resistor R5 and a second resistor R8, wherein the second resistor R8 is connected between the third switch Q3 and the fourth switch Q4, the first switch Q1 is a PMOS transistor, the first resistor R5 is connected between the gate and source of the first switch Q1, and the first resistor R5 and the second resistor R8 perform voltage division to control the turn-on voltage of the first switch Q1.

[0015] Furthermore, the second driving module also includes a third resistor R1 and a first capacitor C2; wherein the third resistor R1 is connected between the third switch Q3 and the first switch Q1, and the first capacitor C2 is connected between the gate and the source of the first switch Q1, and the third resistor R1 and the first capacitor C2 form an RC charging circuit.

[0016] Furthermore, the third switch Q3 is an NPN transistor, and the fourth switch Q4 is an NMOS transistor; wherein, the constant current source is connected to the base and emitter of the third switch Q3, and the collector of the third switch Q3 is connected to the first switch Q1; the gate of the fourth switch Q4 receives the first differential signal, and the drain is connected to the emitter of the third switch Q3.

[0017] Furthermore, the constant current source includes an operational amplifier U2, a fourth resistor R9, a fifth resistor R10, a sixth resistor R11, a seventh resistor R7, and a second capacitor C3. The positive input terminal of the operational amplifier U2 is connected to the operating voltage. The positive power input terminal of the operational amplifier U2 is connected to the operating voltage via the fifth resistor R10. One end of the sixth resistor R11 is connected between the fifth resistor R10 and the operating voltage, and the other end is grounded. The negative input terminal of the operational amplifier U2 is connected to the base of the third switching transistor Q3 via the seventh resistor R7. The second capacitor C3 is connected between the negative input terminal and the output terminal of the operational amplifier U2. The fourth resistor R9 is connected between the negative input terminal of the operational amplifier U2 and the emitter of the third switching transistor Q3. The fourth resistor R9, the seventh resistor R7, and the second capacitor C3 constitute a loop compensation circuit for compensating for loop current.

[0018] Furthermore, a first amplifier U4 and a gate buffer resistor R12 are connected in series between the gate of the fourth switch Q4 and the differential amplifier circuit to boost the level of the first differential signal, thereby driving the fourth switch Q4; the second switch Q2 is an NMOS transistor, and the gate of the second switch Q2 is connected to the output terminal of the differential signal amplifier circuit via the gate buffer resistor R2 and the second amplifier U5 to receive the second differential signal; the source of the second switch Q2 is grounded to discharge when the second switch Q2 is turned on, thereby pulling the third logic signal low; the drain of the second switch Q2 is connected to the output terminal of the switching circuit.

[0019] Furthermore, in one embodiment, the digital signal amplitude modulation system according to the present invention may further include: a waveform shaping module connected between the second output terminal of the control module and the second drive module, for edge shaping and / or level conversion of the first logic signal from the control module.

[0020] Through the above technical solution, the switching module can output a third logic signal with the same phase as the first logic signal under the action of the second driving module. The third logic signal is affected by the adjustable voltage module and will be pulled up to the level of the logic signal output by the adjustable voltage module, thereby realizing digital signal amplitude modulation. In addition, most of the devices used in the solution of the present invention are not limited by the operating frequency. Only a few switching devices need to consider the requirements of the high-frequency operating environment. As long as suitable devices for high-frequency operating scenarios are selected for these switching devices, the entire system can realize digital signal amplitude modulation in high-frequency scenarios without affecting the frequency of the output signal. Attached Figure Description

[0021] Figure 1 This is a structural diagram of a digital signal amplitude modulation system according to an embodiment of the present invention;

[0022] Figure 2 This is a circuit diagram of the second driving module and the switching circuit in a digital signal amplitude modulation system according to an embodiment of the present invention. Detailed Implementation

[0023] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0024] In this invention, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the relative positions of the cover opening and closing device in its operating state. "First" and "second" are used only to distinguish identical or similar features and do not indicate order or importance.

[0025] The purpose of this invention is to provide a digital signal amplitude modulation system that can perform amplitude modulation on digital signals and is applicable to high-frequency scenarios.

[0026] like Figure 1 As shown, the digital signal amplitude modulation system according to the present invention includes a control module 1, an adjustable voltage module 2, a first drive module 3, a switching circuit 4, a waveform shaping module 5, a second drive module 6, and a third drive module 7; wherein, the control module 1 has a first output terminal and a second output terminal, the control module 1 outputs a voltage control signal to the adjustable voltage module 2 through the first output terminal; the control module 1 outputs a first logic signal to the waveform shaping module 5 through the second output terminal; the waveform shaping module 5 performs edge shaping and / or level conversion on the first logic signal and outputs it to the second drive module 6; the adjustable voltage module 2 outputs a voltage control signal according to the voltage control signal. The second logic signal is output, and the level of the second logic signal depends on the voltage control signal output by the control module 1. The first drive module 3 enhances the second logic signal to improve its driving capability and outputs the enhanced second logic signal to the switching circuit 4. The second drive module receives the first logic signal and outputs two differential signals with opposite phases to the switching circuit. The switching circuit 4 responds to the second logic signal and the differential signal and outputs a third logic signal to the third drive module 7, wherein the level of the third logic signal corresponds to the second logic signal, and its phase is the same as the phase of one of the differential signals.

[0027] exist Figure 1 In the system shown, control module 1 can be implemented using a programmable logic circuit (IC) or an embedded microprocessor. The first output of control module 1 is connected to adjustable voltage module 2 (connection can be achieved via a data bus). Control module 1 is essentially a logic signal source, and its output is influenced by programming. Typically, the output logic signal level is 1.2V, 1.8V, 2.5V, 3.3V, and 5V, or it can output logic signals at other levels.

[0028] The input of the adjustable voltage module 2 is connected to the control module 1, and the output is connected to the first drive buffer module 3. The function of the adjustable voltage module 2 is to continuously output a logic level signal (e.g., a 6.8V logic level signal) under the control of the control module 1. The level value of this signal depends on the voltage control signal output by the control module 1. The adjustable voltage module 2 can be implemented in various ways; for example, it can be implemented using a programmable digital-to-analog converter (DAC) and an amplifier circuit. To achieve higher performance, enhanced driving capability is required, which can be achieved by adding a drive circuit with a larger slew rate and a larger output current. This part of the circuit mainly affects the control step size, control accuracy, and level range of the logic level.

[0029] The input terminal of the first driving module 3 is connected to the output terminal of the adjustable voltage module 2, and the output terminal of the first driving module 3 is connected to the switching circuit 4. The voltage signal driving capability output by the adjustable voltage module 2 is often weak, generally not exceeding 50mA. The function of the first driving module 3 is to increase the signal current while keeping the signal voltage constant, thereby enhancing the signal driving capability. For example, it can allow the current to reach 1A (or other current values), thus greatly enhancing the signal driving capability, and can be used in long-distance transmission scenarios under capacitive load conditions.

[0030] The input of the second driving module 6 is connected to the output of the waveform shaping module 5. The function of the second driving module 6 is to enhance the driving capability of the logic signal. On the one hand, the second driving module 6 can increase the current of the logic signal; on the other hand, the second driving module 6 also needs to output two signals to the high-speed switching circuit 4 based on the logic signal output by the waveform shaping module. Overall, the function of the second driving module 6 is to convert the logic signal into a driving signal that can drive the switching circuit 4. The switching circuit 4 outputs in a push-pull manner. The two signals output by the second driving module 6 can simultaneously output and control the upper and lower transistors of the high-speed switching circuit, ensuring a smoother output edge transition and better signal integrity. Furthermore, because the second driving module 6 improves the driving capability of the output control signal, the driving signal can also effectively improve the response speed of the switching circuit 4.

[0031] The third driver module 7 can be a high-bandwidth output driver module, with its input connected to the output of the high-speed switching circuit 4. Due to the parasitic impedance of its switching devices, the output speed and driving capability are affected. The output of the preceding stage is not designed to achieve the target voltage parameters. The third driver module 7 mainly amplifies the high-bandwidth signal and enhances the driving capability, achieving the conversion from logic signal input to the target voltage parameter output. To be suitable for different scenarios, the third driver module 7 can have the characteristic of high-bandwidth output.

[0032] The switching circuit 4 includes a first switching transistor Q1 and a second switching transistor Q2. The two transistors use a push-pull configuration to achieve synchronous output of the logic drive signal. That is, if the control module 1 outputs a logic "0" (logic low), the switching circuit 4 will also output a logic low; conversely, if the control module 1 outputs a logic "1", the switching circuit 4 will output a logic high. Considering that the speed of the logic signal may reach frequencies of tens of MHz, the high-speed switching circuit 4 needs to meet the requirements of nanosecond-level switching speed and a voltage withstand capability of over 20V.

[0033] In one embodiment, such as Figure 2As shown, the first driving module 3 can be implemented using amplifier U1. The switching circuit 4 includes a first switching transistor Q1 and a second switching transistor Q2. The first switching transistor Q1 is a PMOS transistor, and the second switching transistor Q2 is an NMOS transistor. Amplifier U1 is connected to the source of the first switching transistor Q1 via filter resistor R3, and the drain of the first switching transistor Q1 serves as the output. In addition, a filter capacitor C1 can be provided. One end of capacitor C1 is connected between resistor R3 and the source of switching transistor Q1, and the other end of capacitor C1 is grounded.

[0034] exist Figure 2 In the illustrated embodiment, the second driving module 6 includes a differential amplifier circuit U3, a constant current source, a third switch Q3, and a fourth switch Q4. One output terminal of the differential amplifier circuit U3 (outputting a first differential signal) is connected to the first switch Q1 via the fourth switch Q4; the other output terminal of the differential amplifier circuit U3 (outputting a second differential signal) is connected to the second switch Q2. The constant current source includes... Figure 2 The operational amplifier U2, resistors R7, R9, R10, R11, capacitor C3, and capacitor C4 are shown.

[0035] exist Figure 2 In the illustrated embodiment, the third switch Q3 is an NPN transistor, and the fourth switch Q4 is an NMOS transistor. The collector of the third switch Q3 is connected to the first switch Q1; the gate of the fourth switch Q4 receives the first differential signal, and its drain is connected to the emitter of the third switch Q3. The positive input terminal of operational amplifier U2 is connected to the operating voltage VCC; the positive input terminal of operational amplifier U2 is connected to the operating voltage VCC via resistor R10; one end of resistor R11 is connected between resistor R10 and the operating voltage VCC, and the other end is grounded; the negative input terminal of operational amplifier U2 is connected to the base of the third switch Q3 via resistor R7; capacitor C3 is connected between the negative input terminal and the output terminal of operational amplifier U2; resistor R9 is connected between the negative input terminal of operational amplifier U2 and the emitter of the third switch Q3. One end of capacitor C4 is connected between resistors R10 and R11, and the other end is grounded, serving a filtering function. Among them, resistor R7 can drive and limit the current of transistor Q3, preventing excessive current from damaging the device. In addition, resistors R9, R7, and capacitor C3 form a loop compensation circuit to compensate for loop current and ensure the working stability of the constant current source circuit.

[0036] In addition, to provide overshoot protection, the second drive module 6 may also include a resistor R1 and a capacitor C2; wherein, the resistor R1 is connected between the gate of the third switch Q3 and the gate of the first switch Q1, and the capacitor C2 is connected between the gate and source of the first switch Q1. The resistor R1 and the capacitor C2 form an RC charging circuit. When the fourth switch Q4 is turned on, this charging circuit allows the voltage across the gate and source of the first switch Q1 to gradually rise from 0 to the MOS startup voltage. The impedance of the first switch Q1 gradually decreases from infinity. When the first switch Q1 is fully turned on, the impedance of the first switch Q1 reaches the minimum Ron on-resistance value of the device. This process can reduce the inrush current caused by the sudden opening of the switch, which may cause a certain voltage overshoot in the output measurement.

[0037] It can be understood that resistors R1 and R5 and capacitor C2 form an overshoot suppression circuit to protect the first switching transistor Q1 and prevent it from being damaged by the high voltage provided by the first driving module 3.

[0038] The output current I of the constant current source is determined by the voltage U at the positive input terminal of amplifier U2 and the resistance R of resistor R8. The current parameter I = U / R. By controlling the current parameter, the RC charging and discharging time T of the overshoot suppression circuit can be controlled, thereby controlling the edge rise slope and time of the switching signal. Figure 2 In the example shown, the positive input voltage U of amplifier U2 is achieved by voltage division through resistors R10 and R11 (in other embodiments not shown, this can be achieved by a DAC chip).

[0039] exist Figure 2 In the embodiment shown, the second driving module 6 further includes a first resistor R5 and a second resistor R8, wherein the second resistor R8 is connected between the third switch Q3 and the fourth switch Q4, and the first resistor R5 is connected between the gate and the source of the first switch Q1. The first resistor R5 and the second resistor R8 achieve voltage division to control the conduction threshold voltage of the first switch Q1.

[0040] In the above embodiment, it can also be considered that resistor R10, resistor R11, capacitor C4, amplifier U2, resistor R7, resistor R9, capacitor C3, switch Q3 and resistor R8 together form a voltage-controlled constant current source.

[0041] In actual operation, the constant current source is connected to the first switch Q1 via the third switch Q3. The state of the third switch Q3 follows that of the fourth switch Q4. The constant current source is used to maintain the current of the first differential signal when the fourth switch Q4, the third switch Q3, and the first switch Q1 are turned on.

[0042] The fourth switch Q4 is turned on or off under the control of the first differential signal output by the differential amplifier circuit; the second switch Q2 is turned on or off under the control of the second differential signal output by the differential amplifier circuit; when the level of the first differential signal is high and the fourth switch Q4 is turned on, the first switch Q1 is turned on, the level of the second differential signal is low and the second switch Q2 is turned off; the differential amplifier circuit provides the first differential signal to the first switch Q1, and the differential signal pulls the level of the first differential signal high under the action of the second logic signal to obtain the third logic signal, which is then output through the first switch Q1; when the level of the first differential signal is low and the fourth switch Q4 is turned off, the first switch Q1 is turned off, the level of the second differential signal is high and the second switch Q2 is turned on and the switching circuit is grounded, and the third logic signal is low.

[0043] Furthermore, an amplifier U4 and a gate buffer resistor R12 are connected in series between the gate of the fourth switch Q4 and the differential amplifier circuit. Amplifier U4 is used to boost the level of the first differential signal, thereby driving the fourth switch Q4. The gate of the second switch Q2 is connected to the output of the differential signal amplifier circuit via the gate buffer resistor R2 and amplifier U5 to receive the second differential signal. Amplifier U5 can boost the level of the second differential signal, thereby driving the second switch Q2. The source of the second switch Q2 is grounded, which is used to discharge when the second switch Q2 is turned on, thereby pulling the third logic signal low (and Q2 can release the charge stored on devices such as switch Q1, making the low-level output more accurate). The drain of the second switch Q2 is connected to the output of the switching circuit. Resistors R12 and R2, as gate buffer resistors of the MOSFET, can form an RC circuit with the parasitic capacitance of the MOSFET, which protects the MOSFET from voltage surges at the moment of turn-on and suppresses the effects of uncertain electrostatic crosstalk.

[0044] In addition, refer to Figure 2 Resistors R4 and R6 can also be included in the circuit. One end of resistor R4 is connected to the drain of the first switching transistor Q1, and the other end serves as the output of the second driving module 6. One end of resistor R6 is connected to the drain of the second switching transistor Q2, and the other end, together with R4, serves as the output of the second driving module 6. R4 acts as an output buffer resistor; its resistance value should not be too large. It can appropriately adjust the signal bandwidth, suppress overshoot of the output signal, and, in the event of an abnormal short circuit at the output, act as a current-limiting resistor to protect the MOSFET from the risk of burnout due to excessive current. The function of R6 is current limiting. The value of R6 can adjust the discharge current (which can be understood as adjusting the discharge speed). When the logic signal is low, it can turn on switch Q2 to discharge quickly, making the falling edge speed of the signal faster and achieving high-speed logic signal processing with performance more consistent with the rising edge.

[0045] Optional, in Figure 2 In the illustrated embodiment, the second driving module 6 may further include a π-type filter (composed of L1, C5, and C6) disposed at the output terminal. This filter can filter out higher frequency signal components, thereby suppressing overshoot of the rising and falling edges of the signal.

[0046] For example, in actual operation, the input terminal of the differential amplifier circuit U3 is used to receive... Figure 1 The logic sequence input to control module 1 (after waveform shaping by waveform shaping module 5) outputs two logic signals with the same amplitude but a phase difference of 180 degrees. These two output signals are respectively converted by amplifiers U4 and U5 to ensure that the converted signal levels meet the requirements for driving switches Q2 and Q4, thereby controlling the on and off states of switches Q2 and Q4. Switch Q4 also controls the on and off states of switch Q1. Ultimately, this achieves signals with the same phase and logic output, with amplitudes consistent with the input regulated voltage.

[0047] Specifically, assuming the adjustable voltage input provided by amplifier U1 is 12V, the highest logic sequence input level provided to differential amplifier circuit U3 is 3.3V. When the logic sequence input of differential amplifier circuit U3 is high, the voltage provided to switch Q4 is a voltage of the same phase, switch Q4 is turned on at the high level and controls switch Q1 to turn on. The signal provided to switch Q2 is a low level signal with 180 degrees opposite phase, switch Q2 is turned off. At this time, the output level of the amplitude-modulated logic sequence will be pulled up from 3.3V to 12V by the adjustable voltage input. On the other hand, when the logic sequence input of differential amplifier circuit U3 is low, the voltage provided to switch Q4 is a low level voltage with the same phase, switch Q4 is turned off and controls switch Q1 to turn off. The signal provided to switch Q2 is a high level signal with 180 degrees opposite phase, switch Q2 is turned on and discharged. At this time, the output level of the amplitude-modulated logic sequence is low.

[0048] In other words, the amplitude of the signal output by the above amplitude modulation system can be precisely adjusted under control, and the phase of the signal is the same as the phase of the logic sequence input. Furthermore, most of the devices used in this invention are not limited by the operating frequency; only the switching transistors Q1-Q4 need to consider the requirements of the high-frequency operating environment. By selecting devices suitable for high-frequency operating scenarios for these switching devices, the entire system can achieve amplitude modulation of digital signals in high-frequency scenarios without increasing costs or affecting the frequency of the output signal.

[0049] It is important to note that Figure 2 The circuit shown is merely one embodiment of the present invention.

[0050] The preferred embodiments of the present invention have been described in detail above with reference to the accompanying drawings; however, the present invention is not limited thereto.

[0051] Within the scope of the technical concept of this invention, various simple modifications can be made to the technical solution of this invention, including combining various specific technical features in any suitable manner.

[0052] To avoid unnecessary repetition, this invention will not describe all possible combinations separately. However, these simple variations and combinations should also be considered as part of the content disclosed in this invention and are all within the scope of protection of this invention.

Claims

1. A digital signal amplitude modulation system, characterized in that, It includes a control module, an adjustable voltage module, a first drive module, a switching circuit, and a second drive module; The control module has a first output terminal and a second output terminal. The control module outputs a voltage control signal to the adjustable voltage module through the first output terminal; the control module outputs a first logic signal to the second drive module through the second output terminal. The adjustable voltage module outputs a second logic signal according to the voltage control signal, and the level value of the second logic signal depends on the voltage control signal; The first driving module enhances the second logic signal to improve its driving capability, and outputs the enhanced second logic signal to the switching circuit. The second driving module receives the first logic signal and outputs two differential signals with opposite phases to the switching circuit; The switching circuit responds to the second logic signal and the differential signal, and outputs a third logic signal, wherein the level value of the third logic signal corresponds to the second logic signal, and the phase is the same as the phase of one of the differential signals.

2. The digital signal amplitude modulation system according to claim 1, characterized in that, The switching circuit includes a first switching transistor Q1 and a second switching transistor Q2, and the second driving module includes a differential amplifier circuit and a fourth switching transistor Q4; One output terminal of the differential amplifier circuit is connected to the first switch Q1 via the fourth switch Q4; the other output terminal of the differential amplifier circuit is connected to the second switch Q2.

3. The digital signal amplitude modulation system according to claim 2, characterized in that, The fourth switch Q4 is turned on or off under the control of the first differential signal output by the differential amplifier circuit; the second switch Q2 is turned on or off under the control of the second differential signal output by the differential amplifier circuit. When the level of the first differential signal is high and the fourth switch Q4 is turned on, the first switch Q1 is turned on, the level of the second differential signal is low and the second switch Q2 is turned off. The differential amplifier circuit provides the first differential signal to the first switch Q1. Under the action of the second logic signal, the differential signal pulls the level of the first differential signal high to obtain the third logic signal, which is then output through the first switch Q1. When the level of the first differential signal is low and the fourth switch Q4 is turned off, the first switch Q1 is turned off, the level of the second differential signal is high and the second switch Q2 is turned on and the switching circuit is grounded, and the third logic signal is low.

4. The digital signal amplitude modulation system according to claim 3, characterized in that, The second drive module also includes: a constant current source and a third switch Q3; The constant current source is connected to the first switch Q1 via the third switch Q3. The state of the third switch Q3 follows that of the fourth switch Q4. The constant current source is used to maintain the current of the first differential signal when the fourth switch Q4, the third switch Q3, and the first switch Q1 are turned on.

5. The digital signal amplitude modulation system according to claim 4, characterized in that, The second driving module further includes: a first resistor R5 and a second resistor R8, wherein the second resistor R8 is connected between the third switch Q3 and the fourth switch Q4, the first switch Q1 is a PMOS transistor, the first resistor R5 is connected between the gate and source of the first switch Q1, and the first resistor R5 and the second resistor R8 perform voltage division to control the conduction voltage of the first switch Q1.

6. The digital signal amplitude modulation system according to claim 5, characterized in that, The second driving module also includes: a third resistor R1 and a first capacitor C2; The third resistor R1 is connected between the third switch Q3 and the first switch Q1, and the first capacitor C2 is connected between the gate and source of the first switch Q1. The third resistor R1 and the first capacitor C2 form an RC charging circuit.

7. The digital signal amplitude modulation system according to claim 4, characterized in that, The third switch Q3 is an NPN transistor, and the fourth switch Q4 is an NMOS transistor; The constant current source is connected to the base and emitter of the third switch Q3, and the collector of the third switch Q3 is connected to the first switch Q1. The gate of the fourth switch Q4 receives the first differential signal, and its drain is connected to the emitter of the third switch Q3.

8. The digital signal amplitude modulation system according to claim 7, characterized in that, The constant current source includes an operational amplifier U2, a fourth resistor R9, a fifth resistor R10, a sixth resistor R11, a seventh resistor R7, and a second capacitor C3; The positive input terminal of the operational amplifier U2 is connected to the operating voltage; The positive input terminal of the operational amplifier U2 is connected to the operating voltage via the fifth resistor R10; one end of the sixth resistor R11 is connected between the fifth resistor R10 and the operating voltage, and the other end is grounded. The negative input terminal of the operational amplifier U2 is connected to the base of the third switching transistor Q3 via the seventh resistor R7; the second capacitor C3 is connected between the negative input terminal and the output terminal of the operational amplifier U2; the fourth resistor R9 is connected between the negative input terminal of the operational amplifier U2 and the emitter of the third switching transistor Q3; the fourth resistor R9, the seventh resistor R7, and the second capacitor C3 form a loop compensation circuit for compensating for loop current.

9. The digital signal amplitude modulation system according to claim 7, characterized in that, The gate of the fourth switch Q4 is connected in series with the differential amplifier circuit, and a first amplifier U4 and a gate buffer resistor R12 are connected in series to boost the level of the first differential signal, thereby driving the fourth switch Q4. The second switch Q2 is an NMOS transistor. The gate of the second switch Q2 is connected to the output of the differential signal amplification circuit via the gate buffer resistor R2 and the second amplifier U5 to receive the second differential signal. The source of the second switch Q2 is grounded to discharge when the second switch Q2 is turned on, thereby pulling the third logic signal low. The drain of the second switch Q2 is connected to the output of the switching circuit.

10. The digital signal amplitude modulation system according to claim 1, characterized in that, Further includes: A waveform shaping module is connected between the second output terminal of the control module and the second drive module, and is used to perform edge shaping and / or level conversion on the first logic signal from the control module.

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