All-digital dual-mode delay line
By using a fully digital dual-mode delay line structure and a serpentine layout design, the adaptability and stability issues of existing delay lines over a wide frequency range are solved, achieving the effects of signal duty cycle symmetry and high-density integration.
Patent Information
- Application Number
- CN202511333078.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-18
- Publication Date
- 2025-12-19
AI Technical Summary
Existing digital delay lines suffer from problems such as unbalanced signal duty cycle, fixed delay range and step size, interconnect delay susceptible to PVT variations, and large footprint, making it difficult to adapt to different application requirements across a wide frequency range.
It adopts a fully digital dual-mode delay line structure, and through the series delay modules and serpentine layout design, combined with control circuits and delay circuits, it realizes flexible switching of signal paths and optimization of interconnection length. It uses standard logic units to construct delay units to ensure signal duty cycle symmetry and timing stability.
It achieves adaptability over a wide frequency range, improves the delay stability and area efficiency of delay lines, reduces manufacturing costs, and enhances system reliability and clock quality.
Smart Images
Figure CN121173264A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application belongs to the technical field of very large scale integrated circuits (VLSI), and relates to a full-digital dual-mode delay line. BACKGROUND
[0002] With the continuous increase of system clock frequency in synchronous very large scale integrated circuits (VLSI), whether the clock signal can be accurately aligned everywhere in the chip becomes increasingly critical. Clock skew and jitter are the main obstacles affecting the performance of high-speed synchronous systems. In the case of increasing frequency, the fixed timing skew will lead to greater relative phase error as the clock period shortens, thereby seriously affecting the setup time and hold time of the system, increasing the data access delay, and reducing the timing accuracy of internal control signals.
[0003] In order to solve the problems caused by clock skew, delay circuits have become an indispensable compensation means in digital systems. Among them, the delay-locked loop (DLL) is a key circuit that can dynamically adjust the delay and resist the influence of process, voltage and temperature (PVT) changes, and is widely used in timing calibration and signal synchronization tasks in the fields of high-speed communication interfaces, storage systems, digital signal processing, etc. One of the core components of DLL is the delay line, whose performance directly determines the delay range, resolution and stability of the DLL.
[0004] Digital delay lines achieve precise controllable signal delay in the digital domain through specific logic structures. At present, the delay units of mainstream digital-controlled delay lines (DCDL) are often cascaded by standard inverters or buffers. Although this structure is simple to implement, it has several inherent defects: First, using a buffer (Buffer) as a delay unit is easy to cause signal duty cycle imbalance. As shown in Figure 2 and Figure 3 , an ideal 50% duty cycle clock signal (Clock A) after passing through the buffer (Buffer1), the rising and falling edges of the output signal (Clock B) are asymmetrically delayed, resulting in a shift in the duty cycle and worsening the clock quality. Although using two series inverters (Inverter) as a delay unit (as shown in Figure 4 , Figure 5 ) can effectively maintain the duty cycle, existing delay line designs still face other challenges.
[0005] Secondly, the existing delay line is mostly designed in a single mode, with fixed delay range and step, which is difficult to flexibly adapt to wide range of clock frequency changes. In high-frequency applications, small delay steps are needed to achieve fine adjustment, while in low-frequency applications, large delay ranges are needed to cover the entire clock period, and the single-mode delay line cannot meet both needs.
[0006] Furthermore, existing delay lines generally employ a linear series structure in their physical layout, meaning the delay cells are arranged sequentially. This layout results in long interconnects between cascaded cells, introducing significant interconnect delays that are susceptible to PVT variations, thus affecting the overall stability and accuracy of the delay line. In addition, using dedicated clock buffers with strong driving capabilities for the delay cells occupies a large chip area, increasing manufacturing costs and hindering high-density integration.
[0007] Therefore, there is an urgent need to design a compact, dynamically adjustable, delay-stable, and signal-integrity-maintaining all-digital delay line structure. Summary of the Invention
[0008] To address the shortcomings of existing technologies, this invention provides a fully digital dual-mode delay line, the technical solution of which is as follows: The system includes several series-connected delay modules. Each delay module includes a control circuit and a delay circuit. The delay circuit receives an input signal and selects either a first signal path or a second signal path based on a mode selection signal of 0 or 1, and outputs a delayed output signal. The control circuit receives the output signal fed back from the delay circuit in the next stage delay module and outputs the logic state of the fed-back output signal or input signal to the output terminal of the control circuit in the current delay module based on an enable signal of 0 or 1.
[0009] Preferably, the first signal path provides a first delay time, and the second signal path includes a delay unit and provides a second delay time, the second delay time being greater than the first delay time.
[0010] Preferably, the delay unit comprises two inverters connected in series.
[0011] Preferably, the multiple delay modules are arranged in a serpentine layout on the physical layout, so that the delay module at the end of the previous row is physically adjacent to the delay module at the beginning of the next row, thereby shortening the interconnection length between the cascaded delay modules.
[0012] Preferably, both the control circuit and the delay circuit are composed of standard logic units, which include inverters and NAND gates.
[0013] Preferably, in the delay circuit, the outputs of the first signal path and the second signal path are input to a logic gate, and the output of the logic gate is then passed through an inverter to generate the output signal of the delay circuit.
[0014] Preferably, the cascading method of the multiple delay modules is as follows: except for the final delay module, the output signal of the delay circuit of each delay module is connected to the input signal terminal of the next delay module; except for the first delay module, the output terminal of the control circuit of each delay module is connected to the feedback signal input terminal of the previous delay module.
[0015] Compared with the prior art, the present invention has at least the following beneficial effects: 1. Wide frequency range adaptability: Through dual-mode design, this delay line can switch between a slow mode that provides long delay time and a fast mode that provides fine adjustment step size, which can adapt to both low-frequency and high-frequency working scenarios at the same time, and the frequency adaptability is significantly enhanced.
[0016] 2. Excellent duty cycle characteristics and timing stability: The core delay path of the delay unit adopts a structure of two series inverters, effectively maintaining the symmetry of the signal duty cycle. At the same time, the innovative serpentine layout minimizes the uncertainty caused by interconnect delay and its PVT variation, improving the overall delay stability and consistency of the delay line.
[0017] 3. High area efficiency and low cost: The delay unit is constructed entirely from standard logic units (inverters, NAND gates) rather than large dedicated clock buffers, which significantly saves chip layout area, reduces manufacturing costs, and facilitates high-density integration.
[0018] 4. Highly symmetrical structural design: The cascaded structure of delay lines and the signal flow design are highly symmetrical. Whether it is an odd-numbered or even-numbered unit, the logical relationship between input and output signals can be guaranteed to be consistent, which simplifies the control logic and improves the reliability of the system. Attached Figure Description
[0019] Figure 1 This is a schematic diagram of the structure of a digital delay phase-locked loop in the prior art; Figure 2 This is a diagram showing the propagation path of the clock edge buffer in the prior art; Figure 3 This is a waveform diagram showing the clock changes at the input and output terminals of a clock edge buffer in the prior art. Figure 4 This is a schematic diagram of the delay unit structure of the all-digital dual-mode delay line according to an embodiment of the present invention; Figure 5 This is a waveform diagram showing the clock changes at the input and output terminals of the delay unit of the all-digital dual-mode delay line according to an embodiment of the present invention. Figure 6 This is a schematic diagram of the structure of the all-digital dual-mode delay line according to an embodiment of the present invention; Figure 7 This is a first signal path diagram of the all-digital dual-mode delay line according to an embodiment of the present invention; Figure 8 This is a second signal path diagram of the all-digital dual-mode delay line according to an embodiment of the present invention; Figure 9 This is a path diagram of the control loop signal under the enable state of the all-digital dual-mode delay line in an embodiment of the present invention; Figure 10 This is a connection diagram of the four-level delay module of a fully digital dual-mode delay line according to a specific embodiment of the present invention; Figure 11 This is a connection diagram of the three-stage delay module of the all-digital dual-mode delay line according to another specific embodiment of the present invention; Figure 12 This is a schematic diagram of the standard cell layout structure inside the delay module of the all-digital dual-mode delay line according to an embodiment of the present invention; Figure 13 This is a schematic diagram of the serpentine arrangement of the delay modules of the all-digital dual-mode delay line according to an embodiment of the present invention. Detailed Implementation
[0020] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.
[0021] Conversely, this invention encompasses any substitutions, modifications, equivalent methods, and solutions made within the spirit and scope of the invention as defined in the claims. Furthermore, to provide a better understanding of the invention, certain specific details are described in detail below. However, those skilled in the art will fully understand the invention even without these detailed descriptions.
[0022] See Figure 6 The diagram shows a fully digital dual-mode delay line according to an embodiment of the present invention, comprising several delay modules connected in series. Each delay module 10 includes a control circuit 11 and a delay circuit 12. The delay circuit 12 receives an input signal and, according to the 0 or 1 of the mode selection signal, selects to output a delayed output signal via a first signal path or a second signal path. The control circuit 11 receives the output signal fed back from the delay circuit 12 in the next-level delay module 10 and, according to the enable signal 0 or 1, outputs the logic state of the fed-back output signal or input signal to the output terminal of the control circuit 11 in the current delay module 10.
[0023] The first signal path provides a first delay time, and the second signal path includes a delay unit and provides a second delay time, which is greater than the first delay time. The delay unit includes two inverters connected in series. Multiple delay modules 10 are arranged in a serpentine layout on the physical layout, such that the delay module 10 at the end of the previous row is physically adjacent to the delay module 10 at the beginning of the next row, thus shortening the interconnection length between the cascaded delay modules 10.
[0024] The delay line of the present invention is composed of multiple dual-mode delay modules 10 connected in series. The circuit structure of each dual-mode delay module 10 is mainly divided into two parts: a control circuit 11 and a delay circuit 12.
[0025] Delay circuit 12: Responsible for implementing the core delay function of the signal. It receives the input signal in and determines the signal transmission path based on the level of the mode selection signal slow_mode.
[0026] When slow_mode is set to logic '0', it enters fast_mode (first signal path). See also Figure 7 At this point, one input of NAND gate NAND2 is clamped high by the slow_mode signal, and its output is determined by the output of the Delay cell. Simultaneously, the in signal is activated through inverter INV1 and NAND gate NAND1. After passing through NAND1, NAND3, and inverter INV2, the in signal reaches the output to_next_cell. Because the signal path is short and does not pass through the core Delay cell, the overall delay time is relatively small.
[0027] When slow_mode is set to logic '1', it enters slow mode (slow_mode) (second signal path). See also Figure 8 At this point, the output of inverter INV1 is low, causing the output of NAND gate NAND1 to be clamped to high, thus blocking the fast mode path. The signal in is forced through the core delay cell, and then sequentially through NAND2, NAND3, and inverter INV2. Because of the additional delay cell in the signal path, the delay time is significantly increased. In this embodiment, the core delay cell is preferably composed of two inverters connected in series to ensure that no duty cycle distortion occurs when the signal passes through. Regardless of the mode, the signal ultimately passes through NAND3 and INV2, ensuring that the logic polarity of the output signal to_next_cell is always opposite to that of the input signal in.
[0028] Control circuit 11: Responsible for controlling the state of the final output "out" of the current delay unit. It receives the feedback signal "from_next_cell" and the enable signal "enable" from the next-level unit.
[0029] When enable is set to logic '1', the delay unit is enabled. See also Figure 9 At this point, the output of inverter INV4 is low, and the output of NAND gate NAND5 is clamped to high. The final output value of out is determined solely by from_next_cell, with the signal path being from_next_cell → INV3 → NAND4 → NAND6 → out.
[0030] When enable is set to logic '0', the delay unit is disabled. At this time, one input of NAND gate NAND4 is low, and its output is clamped high. Therefore, the output 'out' of NAND gate NAND6 is also always high, no longer affected by any input signal, ensuring stable output in the disabled state.
[0031] Delay line design: A complete delay line can be constructed by cascading multiple dual-mode delay modules 10 in a specific manner. See [link to documentation]. Figure 10 Taking a four-level delay line as an example, the input of the entire delay line is the in terminal of the first unit (delay module 0), and the output is the out terminal of the first unit.
[0032] Forward signal path: Except for the last unit, the output to_next_cell of the delay circuit 12 of each stage unit is connected to the input in of the next stage unit, forming a forward propagation chain of the signal.
[0033] Reverse feedback path: Except for the first unit, the output of the control circuit 11 of each level unit is connected to the feedback input from_next_cell of the previous level unit, forming a reverse feedback chain of the signal.
[0034] The input of the entire delay line is the "in" terminal of delay module 0, and the output is the "out" terminal of delay module 0. In terms of structural connections, except for delay module 3, the "to_next_cell" outputs of delay modules 0, 1, and 12 are all connected to the "in" input of the next-stage delay module. Furthermore, except for delay modules 0 and 1, the "out" output of each stage delay module 10 is also connected to the "from_next_cell" input of the previous stage. As mentioned earlier, due to the presence of INV2 in delay circuit 12, the signal polarity of "to_next_cell" is opposite to that of "in"; similarly, in control circuit 11, there is an inverter, making the signal of "from_next_cell" also inversely related to "out". Therefore, in this structure, the signal polarity is restored after passing through two delay modules. This delay line structure is highly symmetrical, and the delay paths are consistent in logic and layout. In theory, this can minimize the offset between the rise time and fall time of the clock signal, effectively control the impact of the delay line on the duty cycle, and improve the clock quality and timing stability of the entire system.
[0035] Since both delay circuit 12 and control circuit 11 contain inverters, the logic polarity of the signal is reversed each time it passes through a delay module 10. Therefore, in the cascaded structure of this invention, the polarity of the signal is restored after passing through one delay module 10 in both the forward and reverse paths, i.e., after a total of two delay modules 10. This design gives the delay lines a high degree of symmetry, ensuring that the logic relationship between the final output signal out and the input signal in remains consistent regardless of whether the total number of delay lines is odd or even. See [link to relevant documentation]. Figure 11 The three-stage delay line also works correctly. Let's take a delay line composed of three delay modules as an example. According to the previous analysis, after the signal passes through an odd number of delay modules, its logic value at the output of `to_next_cell` will be opposite to the signal at the initial input terminal `in`; simultaneously, there is also an inverted signal relationship between `from_next_cell` and `out` in control circuit 11. Therefore, the two inverted processes cancel each other out, and the signal output at the final `out` terminal is consistent with the input terminal `in`. Through this structural design, regardless of whether the number of delay modules 10 is odd or even, it can ensure that the phase difference between the final output signal and the input signal is 2π or an integer multiple thereof, thereby achieving precise and controllable signal delay and meeting the requirements for phase alignment and timing control in high-performance digital circuits.
[0036] Layout design of delay module 10 and delay lines: This invention is applied to solid-state drive controller chips and includes two types of delay lines: 32-level and 128-level. To solve the problem of cell dispersion and impact on performance consistency caused by automatic placement in traditional EDA tools, this invention proposes an optimized physical design method.
[0037] Layout optimization of a single delay module 10: See Figure 12 The 11 standard logic gates (inverters, NAND gates, etc.) that constitute a delay module 10 are manually arranged in a compact layout according to their internal signal flow and logic connection relationships. Units with direct signal interaction are placed as close as possible to form a physically compact and regular delay unit macro module.
[0038] The serpentine layout of the delay lines: See Figure 13 In arranging delay lines composed of multiple delay modules 10 macromodules, this invention creatively employs a serpentine layout. Unlike the traditional unidirectional linear layout, the serpentine layout changes the placement direction of the macromodules at the end of each row, arranging them in a zigzag pattern. This method ensures that the delay module 10 at the end of the previous row is physically adjacent to the delay module 10 at the beginning of the next row, significantly shortening the interconnect length between them. This effectively reduces the additional delay and PVT fluctuations introduced by the interconnects, thereby significantly improving the overall delay stability and consistency of the delay line. To facilitate layout reuse and layout regularity, the number of delay modules 10 arranged in each row is preferably set to the common divisor of the total number of delay line levels.
[0039] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. A fully digital dual-mode delay line, characterized in that, The system includes several series-connected delay modules. Each delay module includes a control circuit and a delay circuit. The delay circuit receives an input signal and selects either a first signal path or a second signal path based on a mode selection signal of 0 or 1, and outputs a delayed output signal. The control circuit receives the output signal fed back from the delay circuit in the next stage delay module and outputs the logic state of the fed-back output signal or input signal to the output terminal of the control circuit in the current delay module based on an enable signal of 0 or 1.
2. The all-digital dual-mode delay line according to claim 1, characterized in that, The first signal path provides a first delay time, and the second signal path includes a delay unit and provides a second delay time, the second delay time being greater than the first delay time.
3. The all-digital dual-mode delay line according to claim 2, characterized in that, The delay unit includes two inverters connected in series.
4. The all-digital dual-mode delay line according to claim 1, characterized in that, The multiple delay modules are arranged in a serpentine layout on the physical layout, so that the delay module at the end of the previous row is physically adjacent to the delay module at the beginning of the next row, thus shortening the interconnection length between the cascaded delay modules.
5. The all-digital dual-mode delay line according to claim 1, characterized in that, Both the control circuit and the delay circuit are composed of standard logic units, which include inverters and NAND gates.
6. The all-digital dual-mode delay line according to claim 1, characterized in that, In the delay circuit, the outputs of the first signal path and the second signal path are input to a logic gate, and the output of the logic gate is then passed through an inverter to generate the output signal of the delay circuit.
7. The all-digital dual-mode delay line according to claim 1, characterized in that, The cascading method of multiple delay modules is as follows: except for the final delay module, the output signal of the delay circuit of each delay module is connected to the input signal terminal of the next delay module; except for the first delay module, the output terminal of the control circuit of each delay module is connected to the feedback signal input terminal of the previous delay module.