Clock offset calibration method and time-interleaved analog-to-digital converter

Abstract

The invention discloses a clock offset calibration method and a time-interleaved analog-to-digital converter, and belongs to the technical field of communication, and the method comprises the steps: obtaining first data sampled and output by each sub analog-to-digital converter; determining second data based on a first difference value of any two adjacent first data on a sampling time sequence; first data sampled and output by the first sub-analog-to-digital converter is used as contrast data, and a first adjustment code of each second sub-analog-to-digital converter is determined based on the contrast data, N-1 pieces of second data in the current clock period and the corresponding relation between each piece of second data and the sub-analog-to-digital converter; and calibrating the clock offset of the corresponding second sub analog-to-digital converter based on each first adjustment code. Compared with a method for carrying out time sequence calibration on different analog-to-digital converters step by step, the clock offset of each second sub analog-to-digital converter is calibrated synchronously, waiting is not needed, the calibration efficiency is high, and the accuracy rate is high.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of communication, more particularly, to a clock offset calibration method and a time-interleaved analog-to-digital converter. BACKGROUND

[0002] High-speed and high-precision data sampling is widely used in the field of wireless communication, and the sampling bandwidth of a single-channel sampling analog-to-digital converter (ADC) cannot meet the growing demand. The use of a time-interleaved (TI) structure can increase the bandwidth and rate without significantly increasing the power consumption. By using two or more sub-ADCs and controlling the phase relationship of the sampling clock, the input signal is sampled simultaneously, and the high-speed sampling is completed by combining the output signals. The sampling bandwidth of a group of time-interleaved ADC (TI-ADC) output signals is N times that of a single ADC, where N is the number of parallel sub-ADCs.

[0003] The scheme of improving the sampling rate by connecting multiple sub-ADCs in parallel can greatly reduce the device power consumption and design difficulty. However, due to the mismatch of the equipment, the asymmetric design of the clock network, and the clock jitter, the sampling intervals of each sub-channel in the time-interleaved ADC structure are inconsistent, which can lead to inaccurate sampling points and affect the signal integrity and the frequency domain signal spurious-free dynamic range. However, the accuracy of the existing clock offset calibration method still needs to be improved. SUMMARY

[0004] The present application proposes a clock offset calibration method and a time-interleaved analog-to-digital converter to improve the above-mentioned defects.

[0005] In a first aspect, the present application provides a clock offset calibration method applied to a time-interleaved analog-to-digital converter, the time-interleaved analog-to-digital converter comprising N sub-analog-to-digital converters, the N sub-analog-to-digital converters comprising 1 first sub-analog-to-digital converter and N-1 second sub-analog-to-digital converters, N being a positive integer greater than 3, the method comprising: obtaining first data sampled and output by each sub-analog-to-digital converter; determining second data based on a first difference value of any two adjacent first data in the sampling time sequence; taking the first data sampled and output by the first sub-analog-to-digital converter as a control data, determining a first adjustment code of each second sub-analog-to-digital converter based on the control data, N-1 second data in the current clock period, and the correspondence between each second data and the sub-analog-to-digital converter; and calibrating the clock offset of the corresponding second sub-analog-to-digital converter based on each first adjustment code.

[0006] Optionally, for one possible implementation, the determining the first adjustment code of each of the second sub-ADCs based on the reference data, the N-1 second data in the current clock cycle and the correspondence between each of the second data and the sub-ADCs comprises: summing the N consecutive second data in the current clock cycle to obtain third data; scaling each of the N-1 second data in the current clock cycle by N to obtain N-1 fourth data, and determining a second adjustment code corresponding to each of the fourth data based on the difference between each of the fourth data and the third data; and determining the first adjustment code of each of the second sub-ADCs based on the reference data, the correspondence between each of the fourth data and the sub-ADCs and the second adjustment code corresponding to each of the fourth data.

[0007] Optionally, for one possible implementation, the scaling each of the N-1 second data in the current clock cycle by N to obtain N-1 fourth data comprises: scaling each of the N-1 second data in the current clock cycle by N to obtain N-1 fourth data.

[0008] Optionally, for one possible implementation, the determining the second adjustment code corresponding to each of the fourth data based on the difference between each of the fourth data and the third data comprises: subtracting each of the fourth data from the third data to obtain a second difference value corresponding to each of the fourth data; summing a preset difference value corresponding to each of the fourth data and the second difference value corresponding to each of the fourth data to obtain a third difference value corresponding to each of the fourth data; determining the second adjustment code corresponding to each of the fourth data based on the third difference value corresponding to each of the fourth data, and taking the third difference value corresponding to each of the fourth data as a new preset difference value corresponding to each of the fourth data.

[0009] Optionally, for one possible implementation, before the determining the second adjustment code corresponding to each of the fourth data based on the third difference value corresponding to each of the fourth data, the method further comprises: filtering the third difference value corresponding to each of the fourth data to obtain valid data corresponding to each of the fourth data, and taking the valid data corresponding to each of the fourth data as a new third difference value corresponding to each of the fourth data.

[0010] Optionally, for one possible implementation, the determining the second adjustment code corresponding to each of the fourth data based on the third difference value corresponding to each of the fourth data comprises: rounding the third difference value corresponding to each of the fourth data to obtain the second adjustment code corresponding to each of the fourth data.

[0011] Optionally, for a possible implementation, the determining the second data based on the first difference value of any two of the first data in the sampling time sequence comprises: taking the absolute value of the first difference value of any two of the first data in the sampling time sequence as a first effective difference value; adding a preset effective difference value corresponding to each of the first effective difference values to the corresponding first effective difference value to obtain a corresponding second effective difference value; determining the average value of each of the second effective difference values based on a preset number corresponding to each of the first effective difference values as the second data, taking the second effective difference value corresponding to each of the first effective difference values as a new preset effective difference value, and adding one to the preset number corresponding to each of the first effective difference values to obtain a new preset number.

[0012] In a second aspect, the application further provides a time-interleaved analog-to-digital converter, comprising: a clock skew calibration circuit and N sub-analog-to-digital converters, wherein N is a positive integer greater than 3, the N sub-analog-to-digital converters comprise one first sub-analog-to-digital converter and N-1 second sub-analog-to-digital converters; the clock skew calibration circuit is connected with the first sub-analog-to-digital converter and the N-1 second sub-analog-to-digital converters respectively, and is configured to: acquire first data sampled and output by each of the sub-analog-to-digital converters; determine second data based on a first difference value of any two of the first data in the sampling time sequence; take the first data sampled and output by the first sub-analog-to-digital converter as a control data, and determine a first adjustment code of each of the second sub-analog-to-digital converters based on the control data, the N-1 second data in a current clock cycle, and a corresponding relationship between each of the second data and the sub-analog-to-digital converter; and calibrate a clock skew of each of the second sub-analog-to-digital converters based on each of the first adjustment codes.

[0013] Optionally, for a possible implementation, the clock skew calibration circuit comprises: a time sequence adjustment module and N first difference value modules; wherein two input ends of each of the first difference value modules are connected with output ends of corresponding two of the sub-analog-to-digital converters respectively, and an output end of each of the first difference value modules is connected with a corresponding input end of the time sequence adjustment module.

[0014] Optionally, for a possible implementation, the clock skew calibration circuit further comprises: a summation module, N-1 gain modules, and N-1 second difference value modules; wherein each input end of the summation module is connected with an output end of a corresponding first difference value module respectively, an output end of the summation module is connected with a first input end of each of the second difference value modules respectively, a second input end of each of the second difference value modules is connected with an output end of a corresponding gain module respectively, an input end of each of the gain modules is connected with an output end of a corresponding first difference value module respectively, and an output end of each of the second difference value modules is connected with a corresponding input end of the time sequence adjustment module.

[0015] Optionally, for one possible implementation, the clock skew calibration circuit further comprises: N-1 loop accumulation modules, N-1 rounding modules; wherein the input end of each loop accumulation module is connected with the output end of the corresponding second difference module, the output end of each loop accumulation module is connected with the input end of the corresponding rounding module, and the output end of each rounding module is connected with the corresponding input end of the timing adjustment module.

[0016] Optionally, for one possible implementation, the clock skew calibration circuit further comprises: N absolute value modules, N accumulation average modules; wherein the input end of each absolute value module is connected with the output end of the corresponding first difference module, the output end of each absolute value module is connected with the input end of the corresponding accumulation average module, and the output end of each accumulation average module is connected with the corresponding input end of the summation module.

[0017] In the embodiments of the present application, the first data of the sampling output of each sub-ADC is acquired; the second data is determined based on the first difference of any two adjacent first data in the sampling timing; the first data of the sampling output of the first sub-ADC is taken as the reference data, and the first adjustment code of each second sub-ADC is determined based on the reference data, N-1 second data in the current clock cycle, and the corresponding relationship between each second data and the sub-ADC; and the clock offset of the corresponding second sub-ADC is calibrated based on each first adjustment code.

[0018] On the one hand, compared with the method of calibrating the timing of different ADCs step by step, the clock offset of each second sub-ADC is calibrated synchronously in the present application, without waiting, and the calibration efficiency is high. On the other hand, the clock offset of each second sub-ADC is calibrated based on the first data output by each sub-ADC in real time, and the accuracy of calibration is improved.

[0019] Other features and advantages of the present application will be set forth in the following description, and in part will become apparent from the description, or can be learned by practice of the present application. The objects and other advantages of the present application will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings. BRIEF DESCRIPTION OF DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort based on these drawings.

[0021] Figure 1 A method flow chart of the clock offset calibration method provided by the embodiment of the present application is shown; Figure 2 A method flow chart of the clock offset calibration method provided by another embodiment of the present application is shown; Figure 3 A method flow chart of the clock offset calibration method provided by another embodiment of the present application is shown; Figure 4 A method flow chart of the clock offset calibration method provided by another embodiment of the present application is shown; Figure 5 A structural block diagram of the time-interleaved analog-to-digital converter provided by the embodiment of the present application is shown; Figure 6 A structural block diagram of the time-interleaved analog-to-digital converter provided by another embodiment of the present application is shown; Figure 7 A structural block diagram of the time-interleaved analog-to-digital converter provided by another embodiment of the present application is shown; Figure 8 A structural block diagram of the time-interleaved analog-to-digital converter provided by another embodiment of the present application is shown; Figure 9 A structural block diagram of the loop filter provided by the embodiment of the present application is shown; Figure 10 A structural block diagram of the time-interleaved analog-to-digital converter provided by another embodiment of the present application is shown; Figure 11 A structural block diagram of the time-interleaved analog-to-digital converter provided by another embodiment of the present application is shown; Figure 12 A structural block diagram of the timing adjustment module provided by the embodiment of the present application is shown. DETAILED DESCRIPTION

[0022] In order to make the person skilled in the art better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, not all the embodiments. The components of the embodiments of the present application described and shown in the drawings can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by the person skilled in the art without creative labor are within the scope of protection of the present application.

[0023] It should be noted that: similar reference numbers and letters represent similar items in the following drawings, therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. Meanwhile, in the description of the present application, the terms "first", "second", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0024] High-speed and high-precision data sampling is widely used in the field of wireless communication, etc. The sampling bandwidth of a single-channel sampling analog-to-digital converter (ADC) cannot meet the growing demand. The use of a time-interleaved (TI) structure can increase the bandwidth and rate without significantly increasing the power consumption. By using two or more sub-ADCs, the input signal is sampled by controlling the phase relationship of the sampling clock, and the high-speed sampling is completed by combining the output signals. The sampling bandwidth of a group of time-interleaved ADC (TI-ADC) output signals is N times that of a single ADC, where N is the number of parallel sub-ADCs.

[0025] The scheme of increasing the sampling rate by connecting multiple sub-ADCs in parallel can greatly reduce the power consumption and design difficulty of the device. However, due to the mismatch of the device, the asymmetric design of the clock network, and the clock jitter, the sampling intervals of each sub-channel in the time-interleaved ADC structure are inconsistent, which can cause inaccurate sampling points, and further affect the signal integrity and the frequency domain signal spurious-free dynamic range.

[0026] Considering that the existence of clock skew can seriously affect the performance of the device, a calibration algorithm is generally used for optimization. At present, the research mainly focuses on digital domain calibration algorithm, because it does not require additional test signals, and can be completely realized in the digital domain, therefore, from the perspective of simplifying circuit design and reducing power consumption, the digital domain calibration algorithm has obvious advantages.

[0027] The main idea of the traditional calibration algorithm is to first regard channel 1 as an ideal channel (there are four channels in total), to perform timing calibration based on the timing of channel 1 on channel 3, then to regard channel 1 and channel 3 as ideal channels, to perform timing calibration on channel 2 based on channel 1 and channel 3, and to perform timing calibration on channel 4 based on channel 1 and channel 3, so as to complete the calibration of the clock offset of the time-interleaved analog-to-digital converter. This method needs to be calibrated in steps, and the calibration efficiency is low. Moreover, in the process of calibrating channel 2 and channel 4, the calibration code of channel 3 needs to be fixed (it cannot be ensured that channel 3 has no clock offset, which reduces the accuracy of the clock offset calibration of channel 2 and channel 4. Therefore, the accuracy of the existing clock offset calibration method still needs to be improved.

[0028] Therefore, in the embodiments of the present application, a clock offset calibration method and a time-interleaved analog-to-digital converter are provided to solve or partially solve the above problems.

[0029] Please refer to Figure 1 which shows a method flowchart of a clock offset calibration method provided by the embodiments of the present application, applied to a time-interleaved analog-to-digital converter, the time-interleaved analog-to-digital converter comprising N sub-analog-to-digital converters, the N sub-analog-to-digital converters comprising one first sub-analog-to-digital converter and N-1 second sub-analog-to-digital converters, N being a positive integer greater than 3, the method specifically comprising steps S101 to S104.

[0030] Step S101: acquiring first data sampled and output by each sub-analog-to-digital converter.

[0031] It should be noted that the first data represents a digital signal obtained by performing analog-to-digital conversion on a sampled analog signal by a sub-analog-to-digital converter, and the digital signal sampled and output by the N sub-analog-to-digital converters in timing is the first data. For example, when N is 4, the first data sampled by the four sub-analog-to-digital converters in a clock cycle are x1, x2, x3 and x4 respectively. For another example, when N is 6, the first data sampled by the six sub-analog-to-digital converters in a clock cycle are x1, x2, x3, x4, x5 and x6 respectively.

[0032] Step S102: determining second data based on a first difference value of any two adjacent first data in sampling timing.

[0033] It can be understood that each sub-ADC samples data in real time, and outputs first data in real time, and the plurality of first data has a sequence in sampling timing. For example, N is 4, the first data sampled by the first sub-ADC at t1 in a clock cycle is x1, the first data sampled by the second sub-ADC at t2 in a clock cycle is x2, the first data sampled by the third sub-ADC at t3 in a clock cycle is x3, and the first data sampled by the fourth sub-ADC at t4 in a clock cycle is x4, t4 lags behind t3, t3 lags behind t2, and t2 lags behind t1.

[0034] In an optional embodiment, two adjacent first data have a sequence, and a first difference value obtained by subtracting the latter first data from the former first data is taken as the second data.

[0035] For example, the first data sampled by the four sub-ADCs in a previous clock cycle are x1, x2, x3 and x4 in sequence, and the first data sampled by the four sub-ADCs in a current clock cycle are x5, x6, x7 and x8 in sequence. The second data are determined to be x1-x2, x2-x3, x3-x4, x4-x5, x5-x6, x6-x7 and x7-x8 respectively.

[0036] In an optional embodiment, two adjacent first data have a sequence, and a first difference value obtained by subtracting the former first data from the latter first data is taken as the second data.

[0037] For example, the first data sampled by the four sub-ADCs in a previous clock cycle are x1, x2, x3 and x4 in sequence, and the first data sampled by the four sub-ADCs in a current clock cycle are x5, x6, x7 and x8 in sequence. The second data are determined to be x2-x1, x3-x2, x4-x3, x5-x4, x6-x5, x7-x6 and x8-x7 respectively.

[0038] In step S103, the first data sampled and output by the first sub-ADC are taken as the reference data, and based on the reference data, the N-1 second data in the current clock cycle and the correspondence between each second data and the sub-ADC, a first adjustment code of each second sub-ADC is determined.

[0039] It should be noted that the reference data represents the first data identified as having no clock offset, i.e., the timing of the first analog-to-digital converter is assumed to have no time offset, and no adjustment is made to the sampling timing of the first analog-to-digital converter. In the process of clock offset calibration, the first data output by the selected first sub-analog-to-digital converter is selected as the reference data, which facilitates providing a reference object for adjusting the sampling timing of the second sub-analog-to-digital converter.

[0040] It can be understood that the plurality of first data has a sequence in the sampling timing, and the second data is determined based on the first difference of the two adjacent first data in the timing. Since each first data corresponds to a sub-analog-to-digital converter, each second data has a corresponding relationship with two different sub-analog-to-digital converters.

[0041] An exemplary first data output by a first sub-analog-to-digital converter is subtracted from a first data output by a second sub-analog-to-digital converter to determine a second data, and the corresponding relationship between the second data and the sub-analog-to-digital converters is that the second data corresponds to the first sub-analog-to-digital converter and the second sub-analog-to-digital converter, and the second data is obtained based on the difference between the first data output by the first sub-analog-to-digital converter and the first data output by the second sub-analog-to-digital converter.

[0042] Another exemplary first data output by a second sub-analog-to-digital converter is subtracted from a first data output by a first sub-analog-to-digital converter to determine a second data, and the corresponding relationship between the second data and the sub-analog-to-digital converters is that the second data corresponds to the first sub-analog-to-digital converter and the second sub-analog-to-digital converter, and the second data is obtained based on the difference between the first data output by the second sub-analog-to-digital converter and the first data output by the first sub-analog-to-digital converter.

[0043] In an optional embodiment, a sum of N consecutive second data in a current clock cycle is taken as third data, and each of the N-1 second data in the current clock cycle is scaled up by a same ratio to obtain N-1 fourth data, a second adjustment code corresponding to each fourth data is determined based on the difference between each fourth data and the third data, and a first adjustment code of each second sub-analog-to-digital converter is determined based on the reference data, the corresponding relationship between each fourth data and the sub-analog-to-digital converter, and the second adjustment code corresponding to each fourth data. For details, please refer to the subsequent introduction.

[0044] Step S104: calibrating the clock offset of the corresponding second sub-analog-to-digital converter based on each first adjustment code.

[0045] It should be noted that the first adjustment code is used to represent the adjustment code of the timing of the second sub-ADC, and the first adjustment code has a corresponding relationship with the timing adjustment amount of the second sub-ADC. For example, the first adjustment code is 8, and the corresponding timing adjustment amount of the second sub-ADC is 2 ns. For another example, the first adjustment code is 4, and the corresponding timing adjustment amount of the second sub-ADC is 1 ns.

[0046] It can be understood that after obtaining the first adjustment code of each second sub-ADC, the first adjustment code is transmitted to the code value conversion module, the code value conversion module converts the first adjustment code into a timing adjustment amount, and the timing adjustment module adjusts the timing of the corresponding second sub-ADC based on the timing adjustment amount. If there is still clock offset after one adjustment, the previous adjustment method is repeated until the timing deviation of each second sub-ADC is 0 or approximately 0, which indicates that the time offset calibration of each second sub-module is completed. Wherein, the timing deviation of the second sub-ADC is 0, which means that the first adjustment code obtained for Q consecutive times is the same value, and the timing deviation of the second sub-ADC is approximately 0, which means that the first adjustment code obtained for Q consecutive times jumps between two adjacent integer code values. Q is a positive integer, and the value of Q is determined according to actual requirements.

[0047] In the embodiment of the application, the first data of the sampling output of each sub-ADC is obtained; the second data is determined based on the first difference value of any two adjacent first data in the sampling timing; the first adjustment code of each second sub-ADC is determined based on the first data of the sampling output of the first sub-ADC as the reference data, the reference data, N-1 second data in the current clock cycle, and the correspondence between each second data and the sub-ADC; and the clock offset of the corresponding second sub-ADC is calibrated based on each first adjustment code.

[0048] On the one hand, compared with the method of calibrating the timing of different ADCs step by step, the clock offset of each second sub-ADC is calibrated synchronously in the application, without waiting, and the calibration efficiency is high. On the other hand, the clock offset of each second sub-ADC is calibrated based on the first data output by each sub-ADC in real time, which improves the accuracy of calibration.

[0049] Please refer to Figure 2 which shows a method flowchart of a clock offset calibration method provided by an embodiment of the application, applied to a time-interleaved ADC, the time-interleaved ADC comprising N sub-ADCs, the N sub-ADCs comprising one first sub-ADC and N-1 second sub-ADCs, and N being a positive integer greater than 3. The method specifically comprises steps S201 to S206.

[0050] Step S201: obtaining first data sampled and output by each sub-ADC.

[0051] Step S202: determining second data based on first difference of any two first data adjacent in sampling timing.

[0052] Step S203: taking the first data sampled and output by the first sub-ADC as reference data, and taking the sum of the second data in the current clock cycle as third data.

[0053] It should be noted that each sub-ADC outputs first data in real time, and the second data is obtained based on the first data, and the third data is the sum of the absolute values of the second data in the current clock cycle.

[0054] For example, N is 4, the first data sampled by the four sub-ADCs in the first clock cycle are x1, x2, x3, x4 in turn, the first data sampled by the four sub-ADCs in the second clock cycle are x5, x6, x7, x8 in turn, and the first data sampled by the four sub-ADCs in the third clock cycle are x9, x10, x11, x12 in turn. If the second clock cycle is the current clock cycle, the second data in the current clock cycle are x4-x5, x5-x6, x6-x7, x7-x8 in turn, and the third data is the sum of the absolute values of the second data, i.e., |x4-x5|+|x5-x6|+|x6-x7|+|x7-x8|. Alternatively, the second data in the current clock cycle are x5-x4, x6-x5, x7-x6, x8-x7 in turn, and the third data is the sum of the absolute values of the second data, i.e., |x5-x4|+|x6-x5|+|x7-x6|+|x8-x7|. Alternatively, the second data in the current clock cycle are x5-x6, x6-x7, x7-x8, x8-x9 in turn, and the third data is the sum of the absolute values of the second data, i.e., |x5-x6|+|x6-x7|+|x7-x8|+|x8-x9|. Alternatively, the second data in the current clock cycle are x6-x5, x7-x6, x8-x7, x9-x8 in turn, and the third data is the sum of the absolute values of the second data, i.e., |x5-x4|+|x6-x5|+|x7-x6|+|x8-x7|.

[0055] Step S204: scaling each of the second data in the current clock cycle by a same ratio to obtain N-1 fourth data, and determining a second adjustment code corresponding to each fourth data based on the difference between each fourth data and the third data.

[0056] It can be known that each second data is positively correlated with the third data, and the value obtained by subtracting each second data from the third data can reflect the clock offset of the corresponding sub-ADC to a certain extent. Therefore, each second data can be amplified to obtain fourth data, and the corresponding second adjustment code obtained by subtracting the fourth data from the third data can more accurately reflect the clock offset of the corresponding sub-ADC of the second data layer.

[0057] It should be noted that N-1 second data can be randomly selected from the N second data in the current clock cycle, and the specific selection can be determined according to the actually obtained second data. For example, N is 4, and the four second data are x1-x2, x2-x3, x3-x4, and x4-x5. Each of x1-x2, x2-x3, and x3-x4 can be amplified at a constant ratio, or each of x2-x3, x3-x4, and x4-x5 can be amplified at a constant ratio, or each of x1-x2, x3-x4, and x4-x5 can be amplified at a constant ratio.

[0058] In an optional embodiment, each of the N-1 second data in the current clock cycle is amplified by M times to obtain N-1 fourth data, and the value of M ranges from 0.6N to 1.5N.

[0059] In an optional embodiment, each of the N-1 second data in the current clock cycle is amplified by N times to obtain N-1 fourth data. The obtained second adjustment code can accurately reflect the clock offset of the corresponding sub-ADC of the second data layer.

[0060] Step S205: Based on the control data, the correspondence between each fourth data and the sub-ADC, and the second adjustment code corresponding to each fourth data, the first adjustment code of each second sub-ADC is determined.

[0061] It should be noted that since each second data has a corresponding relationship with the sub-ADC, and the fourth data is obtained by amplifying the second data, each fourth data also has a corresponding relationship with the sub-ADC.

[0062] The second adjustment code corresponding to the fourth data represents the adjustment code of the sub-ADC corresponding to the fourth data. The first adjustment code of each second sub-ADC can be determined based on the control data, the correspondence between each fourth data and the sub-ADC, and the second adjustment code corresponding to each fourth data.

[0063] An exemplary, N is 4, 4 sub-ADCs in the sampling timing in the order of first sub-ADC, second sub-ADC A, second sub-ADC B and second sub-ADC C, 4 sub-ADCs in the first clock cycle in turn sampling the first data obtained are x1, x2, x3, x4, 4 sub-ADCs in the second clock cycle in turn sampling the first data obtained are x5, x6, x7, x8, the difference between adjacent two first data is calculated: x2-x1=s21, x3-x2=s32, x4-x3=s43, x5-x4=s54, that is, 4 second data obtained in the current clock cycle are s21, s32, s43, s54, respectively, the third data is SS=|s21|+|s32|+|s43|+|s54|, 3 second data s21, s32, s43 in 4 second data are enlarged in proportion to obtain 3 fourth data, 3 fourth data are S21, S32, S43, respectively, and the second adjustment code corresponding to each fourth data is obtained based on 3 fourth data minus the third data, the second adjustment code Q1 corresponding to the fourth data S21 is S21-SS, the second adjustment code Q2 corresponding to the fourth data S32 is S32-SS, and the second adjustment code Q3 corresponding to the fourth data S43 is S43-SS.

[0064] Since the first data sampled and output by the first sub-ADC is x1, which is the reference data, the first adjustment code of each second sub-ADC can be determined according to the reference data x1, the corresponding relationship between each fourth data and the sub-ADC, and the second adjustment code corresponding to the fourth data. Specifically, it can be known that the reference data x1, the sub-ADC corresponding to each fourth data, and the second adjustment code corresponding to each fourth data are known, and an equation group can be constructed based on the above parameters, Wherein, Q1 is the second adjustment code corresponding to the fourth data S21, Q2 is the second adjustment code corresponding to the fourth data S32, Q3 is the second adjustment code corresponding to the fourth data S43, Q1, Q2, Q3 are constants, and since the first data sampled and output by the first sub-ADC is the reference data, Y1 is also a constant, for example, Y1 is 0, then the equation group is a 3-element 3rd order equation, the unknowns are Y2, Y3, Y4, the values of Y2, Y3, Y4 can be solved, Y2 represents the first adjustment code of the second sub-ADC A, Y3 represents the first adjustment code of the second sub-ADC B, and Y4 represents the first adjustment code of the second sub-ADC C. Then, the clock offset of each second sub-ADC is calibrated based on the first adjustment code of each second sub-ADC.

[0065] It should be noted that N in the present application is a positive integer greater than 3, and the embodiment is only an example, and when N is other values, the calibration principle is the same, and the clock offset of each second sub-ADC can be calibrated.

[0066] Step S206: calibrate the clock offset of the corresponding second sub-ADC based on each first adjustment code.

[0067] The present application can calibrate the clock offset of each second sub-ADC in real time, and the calibration efficiency is higher.

[0068] Please refer to Figure 3 , which shows a method flowchart of a clock offset calibration method provided by an embodiment of the present application, applied to a time-interleaved ADC, the time-interleaved ADC comprising N sub-ADCs, the N sub-ADCs comprising one first sub-ADC and N-1 second sub-ADCs, N being a positive integer greater than 3, and the method specifically comprising steps S301 to S308.

[0069] Step S301: obtain first data sampled and output by each sub-ADC.

[0070] Step S302: determine second data based on a first difference value of any two adjacent first data in sampling timing.

[0071] Step S303: take the first data sampled and output by the first sub-ADC as the reference data, and take the sum of the N consecutive second data in the current clock cycle as the third data.

[0072] Step S304: scale up each of the N-1 second data in the current clock cycle by the same ratio to obtain N-1 fourth data, subtract each fourth data from the third data to obtain a second difference value corresponding to each fourth data.

[0073] It should be noted that N-1 second data is scaled up to obtain N-1 fourth data, for each fourth data, the corresponding second difference value is obtained by subtracting the fourth data from the third data.

[0074] Step S305: take the sum of the preset difference value corresponding to each fourth data and the corresponding second difference value as the corresponding third difference value.

[0075] It should be noted that each fourth data corresponds to a preset difference value, and the preset difference value corresponding to each fourth data can be the same or different. For a fourth data, the sum of the preset difference value corresponding to the fourth data and the corresponding second difference value is taken as the third difference value, and the third difference value corresponding to each fourth data can be obtained in the same way.

[0076] Step S306: determining a second adjustment code corresponding to each fourth data based on the third difference value corresponding to each fourth data, and taking the third difference value corresponding to the fourth data as a new preset difference value corresponding to the fourth data.

[0077] The second adjustment code corresponding to each fourth data is determined based on the third difference value corresponding to each fourth data, and the third difference value corresponding to the fourth data is taken as a new preset difference value corresponding to the fourth data.

[0078] For example, for a fourth data in a current clock cycle, the initial preset difference value is 0, and if the third difference value obtained based on the initial preset difference value is 2, then 2 is taken as the new preset difference value. In the next clock cycle, for the fourth data, the preset difference value is 2 when calculating the third difference value, and the fourth data in the previous two clock cycles corresponds to the same sub-ADC.

[0079] Step S307: determining a first adjustment code of each second sub-ADC based on the reference data, the correspondence between each fourth data and the sub-ADC, and the second adjustment code corresponding to each fourth data.

[0080] Step S308: calibrating the clock offset of the corresponding second sub-ADC based on each first adjustment code.

[0081] In the embodiments of the present application, the second adjustment code of each fourth data is accumulated, and the order calibration of each second sub-ADC can be quickly completed.

[0082] In an optional embodiment, before the determination of the second adjustment code corresponding to each fourth data based on the third difference value corresponding to each fourth data, the third difference value corresponding to each fourth data is filtered to obtain effective data corresponding to each fourth data, and the effective data corresponding to each fourth data is taken as a new third difference value.

[0083] In the embodiments of the present application, the third difference value of each fourth data is filtered, which can reduce the jitter of the third difference value.

[0084] For example, the third difference value of the fourth data can be filtered by a loop filter.

[0085] In an alternative embodiment, the determining of the second adjustment code corresponding to each fourth data based on the third difference value corresponding to each fourth data comprises: rounding the third difference value corresponding to each fourth data to obtain the second adjustment code corresponding to each fourth data.

[0086] For example, the third difference value corresponding to each fourth data can be rounded up to obtain the second adjustment code corresponding to each fourth data, or the third difference value corresponding to each fourth data can be rounded down to obtain the second adjustment code corresponding to each fourth data, or the third difference value corresponding to each fourth data can be rounded to obtain the second adjustment code corresponding to each fourth data, which is an integer value, facilitating the subsequent obtaining of the first adjustment code which is an integer.

[0087] Referring to Figure 4 FIG. 1 shows a method flowchart of a clock offset calibration method according to an embodiment of the present application, which is applied to a time-interleaved analog-to-digital converter, the time-interleaved analog-to-digital converter comprising N sub-analog-to-digital converters, the N sub-analog-to-digital converters comprising one first sub-analog-to-digital converter and N-1 second sub-analog-to-digital converters, N being a positive integer greater than 3, the method comprising steps S401 to S406.

[0088] Step S401: obtaining first data sampled and output by each sub-analog-to-digital converter.

[0089] Step S402: taking the absolute value of the first difference value of any two first data adjacent in sampling timing as a first effective difference value.

[0090] According to the foregoing embodiment, the first difference value can be obtained by subtracting the second first data from the first first data, or the first difference value can be obtained by subtracting the first first data from the second first data, and the absolute value of the first difference value is taken as the first effective difference value.

[0091] Step S403: adding a preset effective difference value corresponding to each first effective difference value to the first effective difference value to obtain a second effective difference value corresponding to the first effective difference value.

[0092] Step S404: determining the average value of each second effective difference value as second data based on a preset number corresponding to each first effective difference value, taking the second effective difference value corresponding to each first effective difference value as a new preset effective difference value, and adding one to the preset number corresponding to each first effective difference value to obtain a new preset number.

[0093] For example, the initial preset effective difference value is 0, the initial preset number of times is 1, the first data sampled by the four sub-ADCs in the first clock cycle are x1, x2, x3 and x4 in sequence, and the first data sampled by the four sub-ADCs in the second clock cycle are x5, x6, x7 and x8 in sequence.

[0094] For the first clock cycle, the absolute value of the first difference value of the first data corresponding to the first sub-ADC and the second sub-ADC is the first effective difference value, which is |x2-x1|, the preset effective difference value is 0, the second effective difference value is determined to be |x2-x1|, the preset number of times is 1, the second data is determined to be |x2-x1| / 1 = |x2-x1|, the second effective difference value |x2-x1| is taken as a new preset difference value, and 1+1=2 is taken as a new preset number of times. In the next clock cycle, the absolute value of the first difference value of the first data corresponding to the first sub-ADC and the second sub-ADC is the first effective difference value, which is |x6-x5|, at this time, the preset effective difference value is |x2-x1|, the preset number of times is 2, the second effective difference value is determined to be |x2-x1|+|x6-x5|, and the second data is determined to be (|x2-x1|+|x6-x5|) / 2.

[0095] Step S405: taking the first data sampled and output by the first sub-ADC as reference data, determining a first adjustment code of each second sub-ADC based on the reference data, N-1 second data in the current clock cycle and the correspondence between each second data and the sub-ADC.

[0096] Step S406: calibrating the clock offset of the corresponding second sub-ADC based on each first adjustment code.

[0097] The application accumulates and averages the first data output by each sub-ADC, which can reduce the influence of jitter on the second data and further improve the accuracy of timing calibration of the second sub-ADC.

[0098] Please refer to Figure 5 which shows a time-interleaved ADC 500 provided by an embodiment of the application, characterized in that it comprises: a clock skew calibration circuit 510 and N sub-ADCs, the N sub-ADCs comprising one first sub-ADC 520 and N-1 second sub-ADCs 530, N being a positive integer greater than 3.

[0099] The clock skew calibration circuit 510 is connected to the first sub-ADC 520 and the N-1 second sub-ADCs 530 respectively, and the clock skew calibration circuit 510 is configured to.

[0100] acquire first data of each of the sub-ADC sampling outputs.

[0101] determine second data based on a first difference value of any two of the first data in sampling timing.

[0102] determine a first adjustment code of each of the second sub-ADCs based on the first data of the first sub-ADC sampling output as reference data, the reference data, N-1 of the second data in a current clock cycle, and a corresponding relationship between each of the second data and the sub-ADC.

[0103] calibrate a clock offset of the corresponding second sub-ADC based on each of the first adjustment code.

[0104] Further, refer to Figure 6 which shows a time-interleaved analog-to-digital converter provided by an embodiment of the present application, and the clock skew calibration circuit 510 comprises a timing adjustment module 511 and N first difference modules 512.

[0105] Each of the first difference modules 512 has two input ends connected to output ends of the corresponding two sub-ADCs, and an output end connected to a corresponding input end of the timing adjustment module 511.

[0106] The first difference module 512 is configured to subtract the first data of the outputs of the two sub-ADCs to obtain second data, and transmit the second data to the timing adjustment module 511, and the timing adjustment module 511 determines a first adjustment code of each of the second sub-ADCs 530 based on the second data output by each of the first difference modules 512, reference data of the first sub-ADC, and a corresponding relationship between each of the second data and the sub-ADC.

[0107] In an optional embodiment, the time-interleaved analog-to-digital converter further comprises a code value conversion module and a timing adjustment module, the code value conversion module converts the first adjustment code into a timing adjustment amount, and the timing adjustment module adjusts the timing of the corresponding second sub-ADC based on the obtained timing adjustment amount until the clock offset of the second sub-ADC is 0 or approximately 0, and stops the calibration of the second sub-ADC.

[0108] Further, refer to Figure 7 which shows a time-interleaved analog-to-digital converter provided by an embodiment of the present application, and the clock skew calibration circuit 510 further comprises a summation module 513, N-1 gain modules 514, and N-1 second difference modules 515.

[0109] The input end of the summation module 513 is connected with the output end of the corresponding first difference module 512 respectively, the output end of the summation module 513 is connected with the first input end of each second difference module 515 respectively, the second input end of each second difference module 515 is connected with the output end of the corresponding gain module 514 respectively, the input end of each gain module 514 is connected with the output end of the corresponding first difference module 512 respectively, and the output end of each second difference module 515 is connected with the corresponding input end of the timing adjustment module 511.

[0110] The summation module 513 is used for summing the second data output by each first difference module 512 to obtain third data, and transmitting the third data to each second difference module 515. Each gain module 514 is used for amplifying the received second data by a proportional factor to obtain fourth data, and transmitting the fourth data to the corresponding second difference module 515. Each second difference module 515 is used for subtracting the received fourth data from the third data to obtain a second adjustment code corresponding to each fourth data. The timing adjustment module 511 is used for determining a first adjustment code of each second sub-ADC 530 based on the reference data, the correspondence between each fourth data and the sub-ADC, and the second adjustment code corresponding to each fourth data.

[0111] Further, refer to Figure 8 which shows a time-interleaved analog-to-digital converter provided by an embodiment of the application, and the clock skew calibration circuit 510 further comprises N-1 loop accumulation modules 516 and N-1 rounding modules 517.

[0112] The input end of each loop accumulation module 516 is connected with the output end of the corresponding second difference module 515, the output end of each loop accumulation module 516 is connected with the input end of the corresponding rounding module 517, and the output end of each rounding module 517 is connected with the corresponding input end of the timing adjustment module 511.

[0113] The second difference module 515 is used for subtracting the received fourth data from the third data to obtain a second difference value corresponding to each fourth data. The loop accumulation module 516 is used for taking the sum of each fourth data and the corresponding second difference value as a third difference value. The rounding module 517 is used for rounding the third difference value corresponding to each fourth data to obtain a second adjustment code corresponding to each fourth data, and taking the third difference value corresponding to the fourth data as a new preset difference value corresponding to the fourth data.

[0114] The loop accumulation module 516 is further configured to filter the third difference value corresponding to each fourth data to obtain effective data corresponding to each fourth data, and take the effective data corresponding to each fourth data as a new third difference value corresponding to the fourth data. The timing adjustment module 511 determines the first adjustment code of each second sub-ADC 530 based on the reference data, the correspondence between each fourth data and the sub-ADC, and the second adjustment code corresponding to each fourth data.

[0115] For example, the loop filter is a loop filter, and the structure of the loop filter is as shown in Figure 9 -1 The first-order digital loop filter is equivalent to an accumulator or a discrete-time integrator, and the second-order digital loop filter is equivalent to two accumulators in series and contains two discrete-time integrators. In this embodiment, a second-order loop filter is used, and gain factors K1 and K2 are supported for configuration. By modifying the sizes of K1 and K2, the convergence speed of the filtered output code value and the stability at the time of convergence can be controlled.

[0116] Further, refer to Figure 10 , which shows a time-interleaved analog-to-digital converter provided by an embodiment of the application, and the clock skew calibration circuit 510 further includes N absolute value modules 518 and N accumulation average modules 519.

[0117] The input end of each absolute value module 518 is connected to the output end of the corresponding first difference module 512, the output end of each absolute value module 518 is connected to the input end of the corresponding accumulation average module 519, and the output end of each accumulation average module 519 is connected to the corresponding input end of the summation module 513.

[0118] The absolute value module 518 is configured to take an absolute value of the first data output by the first difference module 512, and the accumulation average module 519 is configured to accumulate and average the data output by the corresponding absolute value module 518 and output the result to the summation module 513 and the corresponding gain module 514.

[0119] Refer to Figure 11 , which shows a time-interleaved analog-to-digital converter provided by an embodiment of the application, and the clock skew calibration circuit 510 further includes N absolute value modules 518 and N accumulation average modules 519. ref ​The first data of the sampling output of ADC1, ADC2 is a second sub-analog-to-digital converter, X2 represents the first data of the sampling output of ADC2, ADC3 is a second sub-analog-to-digital converter, X3 represents the first data of the sampling output of ADC3, ADC4 is a second sub-analog-to-digital converter, X4 represents the first data of the sampling output of ADC4, delay represents a delay of one period, and the adder adjacent to each sub-analog-to-digital converter represents a first difference module. The adder adjacent to ADC1 is used to calculate the difference between X ref The difference between X4 of the previous clock cycle, the summer module represents a summation module, the G module represents a gain module, s2, s3, s4 respectively represent the fourth data of the output of the corresponding gain module, and the adder adjacent to each gain module is a second difference module. e2, e3, e4 respectively represent the second difference corresponding to each fourth data output by each second difference, R2, R3, R4, respectively represent the second adjustment code corresponding to each fourth data, and W2, W3 and W4 respectively represent the first adjustment code corresponding to each fourth data.

[0120] The functions of the parts are as follows: Average module: used for accumulating and averaging the error signal after modulo (absolute value), reducing the jitter of the error signal, increasing its smoothness and statistical ergodicity.

[0121] Loop accumulator module: filters the difference between the single-channel gain signal and the accumulator output summer, reduces the jitter of the error, and controls the convergence speed and fluctuation range of the adaptive code value by configuring the corresponding gain factor. Due to the difference in skew and the sign characteristics of the accumulation result, the input will be negated inside the loop accumulator.

[0122] Integral module: this module will round the output signal, that is, when the error accumulates to a certain value, the code value of the timing correction of the update algorithm will be fed back to the input end to control the data sampling.

[0123] Timing adjustment module: adjusts the channel timing error of the input, obtains the timing skew error of each channel through negation and addition operations, and adjusts the timing skew of the corresponding channel and reference channel.

[0124] The specific steps are as follows: (1) Four-channel time interleaved ADCs sample the signal to obtain timing skew samples (first data).

[0125] (2) Set the reference channel as channel1 (the first sub-analog converter), calculate the difference between channel2, channel3 and channel4, i.e. X2-X1, X3-X2, X4-X3, X5-X4, wherein X5 is the same as X1, which is X ref .

[0126] (3) Take the absolute value of the channel difference obtained by the |·| module to convert the error into a positive value.

[0127] (4) The Average module averages the distance after M times of accumulation, wherein M supports custom configuration, and the size of M value determines the fluctuation of the error.

[0128] (5) Add the 4-channel distance obtained after averaging by the Summer module to obtain the sum of all average values.

[0129] (6) Multiply the distance difference of channel2, channel3 and channel4 by 4 times gain G to obtain S2, S3, S4 (7) Subtract the amplified signals S2, S3, S4 from the sum of the 4-channel distance difference, since the difference between the single-channel average value and all average values is proportional to Timing Skew, the timing error information is obtained.

[0130] (8) Send the error information e2, e3, e4 into the Loop Adder module for filtering to reduce the jitter of the error, and since the sign of the Skew error adjustment information is opposite to e2, e3, e4, the input to the loop filter will be inverted.

[0131] (9) Take the integer of the filter output by the Round module, convert it into an integer code value for adjusting the timing skew R2, R3, R4.

[0132] (10) Because each channel adaptive code value and timing error do not correspond one by one, for example, the channel3 adaptive code value contains the sum of the errors of channel2 and channel3, the adaptive integer code value also needs to be adjusted for timing.

[0133] (11) Send the adjusted code value into the timing error calibration circuit to complete one iteration of the algorithm.

[0134] Wherein, the structure of the timing adjustment module is as Figure 12As shown, the three groups of code values R2, R3 and R4 output by the rounding module are recombined, because they are not one-to-one corresponding to the timing skew, the Timing Skew of each channel is affected by adjacent channels, for example, the adaptive code value result of channel 3 contains the sum of errors of channel 2 and channel 3, the adaptive code value of channel 4 is the sum of errors of channel 1 and channel 4, when channel 1 is fixed, the error adaptive code value of channel 4 and the actual error have a reverse relationship, so the timing adjustment is also needed for the adaptive integer code value. The equation group can be constructed, wherein W1, R2, R3 and R4 are constants, W2, W3 and W4 can be solved. W2 represents an adjustment code of the second channel, W3 represents an adjustment code of the third channel, and W4 represents an adjustment code of the fourth channel.

[0135] When channel 1 is fixed as the reference channel, the error R2 is proportional to -W4, the error R3 is proportional to W2, and the error R4 is proportional to W3-W2, so the adaptive code values of R3 and R4 are added to eliminate the influence of channel 2 on the timing skew of channel 3. Since channel 1 is fixed as the reference channel, the error code value R3 can be directly used as the adjustment code value on the correction circuit, and the error code value R4 needs to be inverted before use because it is proportional to -W4. Through the above operation, the code value is finally adjusted to be one-to-one corresponding to the timing skew of each channel, and finally sent to the correction circuit for error adaptive adjustment.

[0136] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the above-described devices and modules can refer to the corresponding process in the foregoing method embodiments, which will not be described herein.

[0137] In several embodiments provided in the present application, the coupling between the modules can be electrical, mechanical or other forms of coupling.

[0138] In the present embodiment, each module / unit contained in each device / product described in the foregoing embodiments can be a software module / unit, a hardware module / unit, or part of a software module / unit and part of a hardware module / unit.

[0139] For example, for each device, product applied to or integrated in a chip, each module / unit contained therein can be realized by hardware such as circuit, or at least part of the modules / units can be realized by software program running in a processor integrated in the chip, and the remaining (if any) modules / units can be realized by hardware such as circuit; for each device, product applied to or integrated in a chip module, each module / unit contained therein can be realized by hardware such as circuit, and different modules / units can be located in the same component (for example, chip, circuit module, etc.) or different components of the chip module, or at least part of the modules / units can be realized by software program running in a processor integrated in the chip module, and the remaining (if any) modules / units can be realized by hardware such as circuit; for each device, product applied to or integrated in a terminal, each module / unit contained therein can be realized by hardware such as circuit, and different modules / units can be located in the same component (for example, chip, circuit module, etc.) or different components of the terminal, or at least part of the modules / units can be realized by software program running in a processor integrated in the terminal, and the remaining (if any) modules / units can be realized by hardware such as circuit.

[0140] In addition, each functional module in each embodiment of the present application can be integrated in one processing module, or each module can be physically present alone, or two or more modules can be integrated in one module. The integrated module can be realized in the form of hardware or in the form of software functional module.

[0141] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part of the technical features; and these modifications or replacements do not drive the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A clock offset calibration method, characterized by, The method is applied to a time-interleaved analog-to-digital converter, the time-interleaved analog-to-digital converter comprises N sub-analog-to-digital converters, the N sub-analog-to-digital converters comprise one first sub-analog-to-digital converter and N-1 second sub-analog-to-digital converters, N is a positive integer greater than 3, and the method comprises the following steps: obtaining first data sampled and output by each sub-analog-to-digital converter; determining second data based on a first difference value of any two first data adjacent in a sampling time sequence; taking the first data sampled and output by the first sub-analog-to-digital converter as reference data, determining a first adjustment code of each second sub-analog-to-digital converter based on the reference data, N-1 second data in a current clock cycle, and a correspondence between each second data and the sub-analog-to-digital converter; calibrating a clock offset of the corresponding second sub-analog-to-digital converter based on each first adjustment code.

2. The method of claim 1, wherein, The method comprises the following steps: taking a sum of continuous N second data in the current clock cycle as third data; proportionally amplifying each second data in the N-1 second data in the current clock cycle to obtain N-1 fourth data, determining a second adjustment code corresponding to each fourth data based on a difference between each fourth data and the third data; determining a first adjustment code of each second sub-analog-to-digital converter based on the reference data, a correspondence between each fourth data and the sub-analog-to-digital converter, and the second adjustment code corresponding to each fourth data.

3. The method of claim 2, wherein, The method comprises the following steps: amplifying each second data in the N-1 second data in the current clock cycle by N times to obtain N-1 fourth data.

4. The method of claim 2, wherein, The method comprises the following steps: subtracting each fourth data from the third data to obtain a second difference value corresponding to each fourth data; taking a sum of a preset difference value corresponding to each fourth data and the second difference value corresponding to the fourth data as a third difference value corresponding to the fourth data; determining a second adjustment code corresponding to each fourth data based on the third difference value corresponding to each fourth data, and taking the third difference value corresponding to the fourth data as a new preset difference value corresponding to the fourth data.

5. The method of claim 4, wherein, Before the step of determining a second adjustment code corresponding to each fourth data based on the third difference value corresponding to each fourth data, the method further comprises the following steps: filtering the third difference value corresponding to each fourth data to obtain effective data corresponding to each fourth data, and taking the effective data corresponding to each fourth data as a new third difference value corresponding to the fourth data.

6. The method of claim 4, wherein, The method comprises the following steps: Taking each third difference value corresponding to each fourth data as an integer to obtain a second adjustment code corresponding to each fourth data.

7. The method of claim 1, wherein, The second data is determined based on a first difference value of any two first data adjacent in sampling timing. The absolute value of the first difference value of any two first data adjacent in sampling timing is taken as a first effective difference value. A preset effective difference value corresponding to each first effective difference value is added to the corresponding first effective difference value to obtain a corresponding second effective difference value. The average value of each second effective difference value is determined based on a preset number corresponding to each first effective difference value, and the second effective difference value corresponding to each first effective difference value is taken as a new preset effective difference value, and the preset number corresponding to each first effective difference value is increased by one to obtain a new preset number.

8. A time-interleaved analog-to-digital converter, comprising: It comprises: a clock skew calibration circuit and N sub-ADCs, the N sub-ADCs comprising one first sub-ADC and N-1 second sub-ADCs, N being a positive integer greater than 3; the clock skew calibration circuit being connected to the first sub-ADC and the N-1 second sub-ADCs respectively, and being configured to: acquire first data sampled and output by each sub-ADC; determine second data based on a first difference value of any two first data adjacent in sampling timing; take the first data sampled and output by the first sub-ADC as a reference data, and determine a first adjustment code of each second sub-ADC based on the reference data, N-1 second data in a current clock cycle, and a correspondence between each second data and the sub-ADC; calibrate a clock skew of the corresponding second sub-ADC based on each first adjustment code.

9. The time-interleaved ADC of claim 8, wherein: the clock skew calibration circuit comprises a timing adjustment module and N first difference modules; each first difference module has two input terminals connected to output terminals of two corresponding sub-ADCs respectively, and an output terminal connected to a corresponding input terminal of the timing adjustment module.

10. The time-interleaved ADC of claim 9, wherein: the clock skew calibration circuit further comprises a summation module, N-1 gain modules, and N-1 second difference modules; each input terminal of the summation module is connected to an output terminal of a corresponding first difference module, an output terminal of the summation module is connected to a first input terminal of each second difference module, a second input terminal of each second difference module is connected to an output terminal of a corresponding gain module, an input terminal of each gain module is connected to an output terminal of a corresponding first difference module, and an output terminal of each second difference module is connected to a corresponding input terminal of the timing adjustment module.

11. The time-interleaved ADC of claim 10, wherein: The clock skew calibration circuit further comprises N-1 loop accumulation modules and N-1 rounding modules. The input end of each loop accumulation module is connected with the output end of the corresponding second difference module, the output end of each loop accumulation module is connected with the input end of the corresponding rounding module, and the output end of each rounding module is connected with the corresponding input end of the timing adjustment module.

12. The time-interleaved analog-to-digital converter of claim 10, wherein: The clock skew calibration circuit further comprises N absolute value modules and N accumulation average modules. The input end of each absolute value module is connected with the output end of the corresponding first difference module, the output end of each absolute value module is connected with the input end of the corresponding accumulation average module, and the output end of each accumulation average module is connected with the corresponding input end of the summation module.

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