Memory, manufacturing method thereof and memory system

Abstract

The invention provides a memory, a manufacturing method thereof and a memory system. The memory comprises a conductive layer, at least one memory array and at least one first contact structure, wherein the storage array and the first contact structure are located on the same side of the two opposite sides of the conductive layer in the first direction; the first direction is the thickness direction of the conductive layer; the storage array comprises a plurality of capacitor structures; the capacitor structure comprises a first polar plate, a second polar plate and a dielectric layer located between the first polar plate and the second polar plate; the first polar plates of the plurality of capacitor structures in the storage array are in contact with the conductive layer; the first contact structure extends along the first direction, and one of two opposite ends of the first contact structure along the first direction is contacted with the conductive layer.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor technology, and in particular, to a memory and a manufacturing method thereof, and a memory system. BACKGROUND

[0002] With the continuous development of today's science and technology, semiconductor devices are widely used in various electronic devices and electronic products. For example, dynamic random access memory (DRAM) as a kind of volatile memory is a commonly used semiconductor memory device in computers. SUMMARY

[0003] Embodiments of the present disclosure provide a memory and a manufacturing method thereof, and a memory system.

[0004] In a first aspect, embodiments of the present disclosure provide a memory, comprising a conductive layer, at least one memory array, and at least one first contact structure; wherein,

[0005] The memory array and the first contact structure are located on the same side of the conductive layer along a first direction opposite to each other; the first direction is the thickness direction of the conductive layer;

[0006] The memory array comprises a plurality of capacitor structures; the capacitor structure comprises a first electrode plate, a second electrode plate, and a dielectric layer located between the first electrode plate and the second electrode plate; the first electrode plate of the plurality of capacitor structures in the memory array is in contact with the conductive layer;

[0007] The first contact structure extends along the first direction, and one end of the first contact structure opposite to each other along the first direction is in contact with the conductive layer.

[0008] In an optional implementation, the resistivity of the conductive layer is less than the resistivity of the first electrode plate.

[0009] In an optional implementation, the memory comprises a plurality of memory blocks; the plurality of memory blocks are arranged in an array along a second direction and a third direction; the second direction intersects with the third direction, and the second direction and the third direction are both perpendicular to the first direction; the memory block comprises a storage area and a contact area; the contact area is located on at least one side of the storage area in the second direction, and the contact area is located on at least one side of the storage area in the third direction; the storage area of one memory block comprises one memory array; at least one memory block in the plurality of memory blocks comprises the first contact structure, and the first contact structure of the memory block is located in the contact area of the memory block.

[0010] In an alternative implementation, the conductive layer extends along the second direction and the third direction, each of the plurality of memory blocks comprises a portion of the conductive layer, and the first plate of the plurality of capacitive structures in each of the memory blocks is in contact with the conductive layer in the memory block.

[0011] In an alternative implementation, the first contact structure is located in a contact region between two of the memory regions adjacent in the second direction; or, the first contact structure is located in a contact region between two of the memory regions adjacent in the third direction.

[0012] In an alternative implementation, the memory comprises a plurality of memory banks; the memory bank comprises a plurality of the memory blocks, the plurality of memory blocks in the memory bank are arranged in an array along the second direction and the third direction; the memory bank comprises at least one of the first contact structures.

[0013] In an alternative implementation, the memory comprises at least two memory banks arranged along the second direction; the contact region is located on both sides of the memory region in the second direction; the first contact structure in the memory bank is located in a contact region on the outermost side of the memory bank in the second direction; the contact region on the outermost side of the memory bank in the second direction has a dimension in the second direction greater than that of a contact region between two of the memory regions adjacent in the second direction in the memory bank, and / or, the contact region on the outermost side of the memory bank in the second direction has a dimension in the second direction greater than that of a contact region between two of the memory regions adjacent in the third direction in the memory bank.

[0014] In an alternative implementation, the first plate of the plurality of capacitive structures in the memory block is connected; the first plate comprises at least a first portion located in the memory region and extending in a direction perpendicular to the first direction, and a second portion located in the memory region and extending in a direction away from the conductive layer along the first direction; the conductive layer is in contact with at least the first portion.

[0015] In an alternative implementation, the first plate of at least one of the memory blocks in the memory bank further comprises a third portion located in the contact region and extending in a direction perpendicular to the first direction; the second portion of the first plate of at least two of the memory blocks in the plurality of memory blocks in the memory bank is connected through the third portion, and the first plate of the plurality of memory blocks in the memory bank is in contact with the conductive layer.

[0016] In an alternative implementation, the memory bank further comprises:

[0017] a first isolation structure between the conductive layer in the contact region and the third portion of the first plate;

[0018] a second isolation structure between the first contact structure and the first plate.

[0019] In an optional implementation, the conductive layer includes a flat portion and a protruding portion; the flat portion is in the storage region and the contact region, and extends in a direction perpendicular to the first direction; the protruding portion extends in the first direction, and is between the flat portion in the contact region and the first contact structure; the first contact structure is in contact with the protruding portion.

[0020] In an optional implementation, the memory further includes:

[0021] peripheral circuitry and interconnect layers stacked along the first direction; the memory array and the first contact structure are between the interconnect layers and the conductive layer; the interconnect layers are between the peripheral circuitry and the memory array, and between the peripheral circuitry and the first contact structure; the memory array and the peripheral circuitry are coupled through the interconnect layers; another end of the first contact structure opposite to one end of the first contact structure along the first direction is connected with an interconnect line in the interconnect layers.

[0022] In an optional implementation, the memory array further includes:

[0023] a plurality of active pillars extending along the first direction, the active pillars are between the interconnect layers and the capacitor structure; the active pillars include a first electrode, a channel, and a second electrode arranged in sequence along the first direction; one of the first electrode and the second electrode is connected with the second plate of the capacitor structure;

[0024] The memory further includes:

[0025] a bit line structure between the interconnect layers and the active pillars; another of the first electrode and the second electrode is connected with the bit line structure.

[0026] In an optional implementation, the memory further includes a bus layer and a second contact structure; the peripheral circuitry is between the interconnect layers and the bus layer; the second contact structure extends along the first direction, and is between the bus layer and the interconnect layers; one end of the second contact structure opposite to another end of the second contact structure along the first direction is connected with an interconnect line in the interconnect layers, and the other end of the second contact structure along the first direction is connected with a bus line in the bus layer.

[0027] In an alternative embodiment, the memory further comprises:

[0028] a pad-out layer; the peripheral circuit is located between the pad-out layer and the memory array.

[0029] In a second aspect, the embodiments of the present disclosure provide a memory system, comprising:

[0030] at least one memory according to any one of the preceding embodiments;

[0031] a controller coupled to the memory and configured to control the memory.

[0032] In a third aspect, the embodiments of the present disclosure provide a method for manufacturing a memory, comprising:

[0033] forming a memory array; the memory array comprises a plurality of capacitor structures; the capacitor structure comprises a first plate, a second plate, and a dielectric layer between the first plate and the second plate;

[0034] forming a conductive layer and a first contact structure; the memory array and the first contact structure are located on the same side of the conductive layer along a first direction; the first direction is a thickness direction of the conductive layer; the first plate of the capacitor structure in the memory array is in contact with the conductive layer; the first contact structure extends along the first direction, and one end of the first contact structure along the first direction is in contact with the conductive layer.

[0035] In an alternative embodiment, the method for manufacturing a memory further comprises:

[0036] forming a plurality of memory blocks; the plurality of memory blocks are arranged in an array along a second direction and a third direction; the second direction intersects the third direction, and the second direction and the third direction are both perpendicular to the first direction; the memory block comprises a storage area and a contact area; the contact area is located on at least one side of the storage area in the second direction, and the contact area is located on at least one side of the storage area in the third direction;

[0037] the forming of the memory array and the forming of the first contact structure comprise:

[0038] forming one memory array in the storage area of each memory block, and forming the first contact structure in the contact area of at least one memory block.

[0039] In an alternative embodiment, the forming of the conductive layer comprises:

[0040] forming a conductive layer extending along the second direction and the third direction; each of the plurality of memory blocks comprises a portion of the conductive layer, and the first plate of the plurality of capacitive structures in each of the memory blocks is in contact with the conductive layer in the memory block.

[0041] In an alternative embodiment, the memory comprises a plurality of memory banks; the memory bank comprises a plurality of the memory blocks, the plurality of memory blocks in the memory bank are arranged in an array along the second direction and the third direction; the forming the first contact structure comprises:

[0042] forming at least one of the first contact structure in each of the memory banks.

[0043] In an alternative embodiment, the memory comprises at least two memory banks arranged along the second direction; the contact region is located on both sides of the memory region in the second direction; the forming the first contact structure comprises:

[0044] forming the first contact structure in the contact region located at the outermost side of the memory bank in the second direction; the contact region located at the outermost side of the memory bank in the second direction has a dimension in the second direction greater than that of the contact region between two adjacent memory regions in the second direction in the memory bank, and / or the contact region located at the outermost side of the memory bank in the second direction has a dimension in the second direction greater than that of the contact region between two adjacent memory regions in the third direction in the memory bank.

[0045] In an alternative embodiment, the first plate of the plurality of capacitive structures in the memory block is connected; the first plate comprises at least a first portion located in the memory region and extending in a direction perpendicular to the first direction, and a second portion located in the memory region and extending in a direction away from the conductive layer along the first direction;

[0046] the forming the conductive layer comprises:

[0047] forming the conductive layer in contact with at least the first portion.

[0048] In an alternative embodiment, the first plate of at least one of the memory blocks in the memory bank further comprises a third portion located in the contact region and extending in a direction perpendicular to the first direction; the second portion of the first plate of at least two of the memory blocks in the memory bank is connected through the third portion, and the first plate of the plurality of memory blocks in the memory bank is in contact with the conductive layer.

[0049] In an alternative embodiment, the method of fabricating the memory further comprises:

[0050] forming a first isolation structure between the conductive layer in the contact region and the third portion of the first plate;

[0051] forming a second isolation structure between the first contact structure and the first plate.

[0052] In an alternative embodiment, the method of fabricating the memory further comprises:

[0053] forming a peripheral circuit and an interconnect layer stacked along the first direction; the memory array and the first contact structure are between the interconnect layer and the conductive layer; the interconnect layer is between the peripheral circuit and the memory array, and between the peripheral circuit and the first contact structure; the memory array and the peripheral circuit are coupled through the interconnect layer; the other end of the first contact structure along the first direction is connected to the interconnect layer.

[0054] In an alternative embodiment, the method of fabricating the memory further comprises:

[0055] forming a bus layer and a second contact structure; the peripheral circuit is between the interconnect layer and the bus layer; the second contact structure extends along the first direction, and is between the bus layer and the interconnect layer; one end of the second contact structure along the first direction is connected to an interconnect line in the interconnect layer; the other end of the second contact structure along the first direction is connected to a bus in the bus layer.

[0056] In an alternative embodiment, the method of fabricating the memory further comprises:

[0057] forming a pad-out layer; the peripheral circuit is between the pad-out layer and the memory array.

[0058] In the technical solution provided in this disclosure, the first electrode of the capacitor structure can be led out through a conductive layer in contact with the first electrode and a first contact structure in contact with the conductive layer. The conductive layer and the first electrode have a large contact area and a small contact resistance, and the resistivity of the conductive layer is low. This reduces the voltage drop on the power supply path of the upper electrode of the capacitor structure, reduces the voltage difference between the upper electrodes of the capacitor structure at different locations, and improves the reliability of the memory. Furthermore, based on reducing the voltage drop on the power supply path of the upper electrode of the capacitor structure, since the conductive layer can extend to all memory blocks, only one first contact structure is needed to lead out the first electrode in a single memory cell. The first contact structure can be located in the outermost contact area of ​​the memory cell, and the width of the contact area without the first contact structure can be smaller than the width of the contact area with the first contact structure. This not only reduces the number of contact structures used to lead out the upper electrode of the capacitor structure but also reduces the area of ​​the contact area, thereby improving the integration density of the memory and facilitating its miniaturization. Attached Figure Description

[0059] Figure 1 A schematic diagram illustrating the composition of an electronic device provided in an embodiment of this disclosure;

[0060] Figure 2 A schematic diagram illustrating the composition of a memory provided in an embodiment of this disclosure;

[0061] Figure 3 Schematic diagram of the memory structure provided in the embodiments of this disclosure Figure 1 ;

[0062] Figure 4 Schematic diagram of the memory structure provided in the embodiments of this disclosure Figure 2 ;

[0063] Figure 5 A schematic diagram of the specific structure of the memory provided in the embodiments of this disclosure;

[0064] Figure 6 Layout diagram of storage blocks and storage units provided in embodiments of this disclosure Figure 1 ;

[0065] Figure 7 for Figure 6 Cross-sectional view along line AA';

[0066] Figure 8 Layout diagram of storage blocks and storage units provided in embodiments of this disclosure Figure 2 ;

[0067] Figure 9 Schematic diagram of the memory structure provided in the embodiments of this disclosure Figure 3 ;

[0068] Figure 10 A flowchart of a manufacturing method of a memory provided by an embodiment of the present disclosure is shown in FIG. 1 1 ;

[0069] Figure 11 A structure diagram of a forming process of a memory provided by an embodiment of the present disclosure is shown in FIG. 12; Figure 1 ;

[0070] Figure 12 A structure diagram of a forming process of a memory provided by an embodiment of the present disclosure is shown in FIG. 13; Figure 2 ;

[0071] Figure 13 A structure diagram of a forming process of a memory provided by an embodiment of the present disclosure is shown in FIG. 14; Figure 3 ;

[0072] Figure 14 A structure diagram of a forming process of a memory provided by an embodiment of the present disclosure is shown in FIG. 15; Figure 4 ;

[0073] Figure 15 A structure diagram of a forming process of a memory provided by an embodiment of the present disclosure is shown in FIG. 16; Figure 5 ;

[0074] Figure 16 A structure diagram of a forming process of a memory provided by an embodiment of the present disclosure is shown in FIG. 17; Figure 6 ;

[0075] Figure 17 A structure diagram of a forming process of a memory provided by an embodiment of the present disclosure is shown in FIG. 18; Figure 7 ;

[0076] Figure 18 A structure diagram of a forming process of a memory provided by an embodiment of the present disclosure is shown in FIG. 19; Figure 8 ;

[0077] Figure 19 A structure diagram of a forming process of a memory provided by an embodiment of the present disclosure is shown in FIG. 20. Figure 9 . DETAILED DESCRIPTION

[0078] Exemplary embodiments of the present disclosure will be described herein below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it is understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0079] In the following description, numerous specific details are set forth to provide a more thorough understanding of the present disclosure. However, it will be apparent to one of skill in the art upon

[0080] On the drawings, like reference numerals refer to like elements throughout.

[0081] It should be understood that spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device is turned over, then a downward- facing surface can be oriented to be upward-facing. Accordingly, the exemplary term "below" or "beneath" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0082] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0083] Figure 1 A schematic diagram of an electronic device 1 is shown for embodiments of the present disclosure. The electronic device 1 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, a Virtual Reality (VR) device, an Augmented Reality (AR) device, or any other suitable electronic device having a memory therein.

[0084] As Figure 1As shown, the electronic device 1 can include a memory system 10 and a host 20, the memory system 10 can include a controller 110 and a memory 120. The host 20 can include a processor of the electronic device 1, for example, a Central Processing Unit (CPU) or a System on Chip (SoC) (e.g., an Application Processor (AP)). The controller 110 is coupled with the host 20 and the memory 120, and the controller 110 can be configured to communicate with the host 20 and control the memory 120.

[0085] In some embodiments, the controller 110 can be configured to control operations of the memory 120, such as read operations, erase operations, write operations, refresh operations, and the like. In some implementations, the controller 110 is further configured to process Error Correction Code (ECC) on data read from or written to the memory 120. In other implementations, the controller 110 can be further configured to perform any other suitable operations, such as formatting the memory 120.

[0086] In some embodiments, the controller 110 can receive data, commands, and addresses from the host 20 and can send data, commands, and addresses to the memory 120. Specifically, the controller 110 can include a command generator 111, an address generator 112, a device interface 113, and a host interface 114. The controller 110 can receive data, commands, and addresses from the host 20 through the host interface 114, decode the commands received from the host 20 through the command generator 111 to generate access commands CMD, and can provide the access commands CMD to the memory 120 through the device interface 113. The controller 110 can decode the addresses received from the host interface 114 through the address generator 112 to generate addresses ADDR to be accessed in the storage array 121, and can provide the addresses ADDR to be accessed to the memory 120 through the device interface 113. The access commands can be signals instructing the memory 120 to write or read data by accessing one or more storage cells in the storage array 121 corresponding to the addresses ADDR. In addition, the controller 110 can further send refresh commands to the memory 120, the refresh commands can be signals instructing the memory 120 to read out and rewrite data by accessing one or more storage cells in the storage array 121 corresponding to the addresses ADDR.

[0087] In some specific examples, the memory 120 can be a random access memory (RAM), such as a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a static random access memory (SRAM), a double data rate SDRAM (DDR SDRAM), a phase-change random access memory (PRAM), a resistive random access memory (ReRAM), a magnetic random access memory (MRAM), etc. In the following, the memory 120 will be taken as an example of a DRAM.

[0088] In some embodiments, Figure 2 A schematic diagram of a DRAM is shown for the embodiments of the present disclosure. In combination with reference to Figure 1 and Figure 2 The DRAM includes a memory array 121 and a peripheral circuit 122 coupled with the memory array 121, and the peripheral circuit 122 can include a sense amplifier circuit, a row decoder, a column decoder, a data input / output buffer, etc. The memory array 121 includes a plurality of memory cells arranged in an array, a plurality of memory cells in the same row (Row) are coupled with a word line WL, and a plurality of memory cells in the same column (Column) are coupled with a bit line BL. Each memory cell includes a transistor T and a capacitor C. The word line WL is connected to the gate of the transistor T, one of the source and the drain of the transistor T is connected to the bit line BL, the other of the source and the drain of the transistor T is connected to one electrode of the capacitor C, and the other electrode of the capacitor C is connected to a fixed voltage. The memory cell is configured to store 1 or 0 by using the more or less of the charge stored in the capacitor C. By specifying a row address and a column address, each memory cell in the DRAM chip can be independently accessed, and the data stored therein can be read, written, or refreshed.

[0089] In some embodiments, vertical transistors occupy less area than planar transistors, thus improving memory integration. A DRAM memory array may include arrayed memory cells, each of which may include a vertical transistor and a capacitor structure extending vertically connected to the vertical transistor. To further improve memory integration, a three-dimensional memory architecture in which peripheral circuitry and the memory array are stacked vertically has been proposed.

[0090] In some embodiments, to form a three-dimensional memory architecture, a memory array including vertical transistors and bit lines connected to the source or drain of the vertical transistors need to be formed on the front side of a first wafer, and peripheral circuitry is formed on the front side of a second wafer. Then, the front sides of the first and second wafers are bonded together, and a pad lead-out layer is formed on the back side of the first wafer. Power lines and other signal lines are disposed in an interconnect layer between the peripheral circuitry and the memory array. In the above embodiments, the bit lines need to be connected to a sensing amplifier circuit in the peripheral circuitry. However, since the power lines and other signal lines are disposed between the peripheral circuitry and the memory array, the conductive connection between the bit lines and the sensing amplifier circuit needs to pass through multiple interconnect layers in the interconnect layer. On the one hand, this results in a large winding length from the bit lines to the sensing amplifier circuit, which can easily lead to delays and distortions in data signal transmission. On the other hand, the power lines and other signal lines can cause crosstalk to the conductive connection between the bit lines and the sensing amplifier circuit, thereby reducing the sensing margin of the sensing amplifier circuit.

[0091] Figure 3 This is a schematic diagram illustrating a three-dimensional memory architecture according to an embodiment of the present disclosure, such as... Figure 3 As shown, forming a three-dimensional memory architecture may include forming a memory array 200 including vertical transistors 206 and capacitor structures 201 and bit lines 207 on the front side of a first wafer, forming peripheral circuitry 220 on the front side of a second wafer, then bonding the front sides of the first wafer and the second wafer together, thinning the second wafer from its back side, and forming a bus layer 230 including power lines and other signal lines, and a pad lead-out layer 240 on the back side of the second wafer. In the above embodiment, the bus layer 230 and the pad lead-out layer 240 are both located on the back side of the second wafer. The bit lines 207 do not need to pass through power lines and other signal lines to connect to the sensing amplifier circuit in the peripheral circuitry 220. On the one hand, this reduces the winding length of the bit lines 207 to the sensing amplifier circuit; on the other hand, it reduces crosstalk caused by power lines and other signal lines to the conductive connection between the bit lines 207 and the sensing amplifier circuit, reducing the negative impact on the sensing margin.

[0092] However, for Figure 3As shown in the three-dimensional memory architecture, the upper electrodes of the plurality of capacitor structures 201 in the memory array 200 are connected to form a common first plate 202, the first plate 202 is led out through a contact structure 203, a metal line 204 and a contact structure 205, further, the contact structure 205 is connected to the peripheral circuit 220 through the interconnection layer 210, and is connected to a fixed voltage (for example, VCC / 2) through the peripheral circuit 220, to provide the fixed voltage to the first plate 202. However, since the contact area between the contact structure 203 and the first plate 202 and the contact area between the contact structure 203 and the metal line 204 are small and the contact resistance is large, it may cause a large voltage drop on the power supply path of the first plate 202, and the voltage on the upper electrode of the capacitor structure 201 far away from the contact structure 203 in the memory array 200 may be different from the voltage on the upper electrode of the capacitor structure 201 close to the contact structure 203, resulting in reduced reliability of the capacitor structure 201 storing data.

[0093] Therefore, it is necessary to further optimize the arrangement of the power supply path of the upper electrode of the capacitor structure to improve the reliability of the memory. In this regard, the present disclosure proposes the following embodiments.

[0094] The present disclosure provides a memory, comprising a conductive layer, at least one memory array and at least one first contact structure; wherein the memory array and the first contact structure are located on the same side of the conductive layer along a first direction opposite to each other; the first direction is the thickness direction of the conductive layer; the memory array comprises a plurality of capacitor structures; the capacitor structure comprises a first plate, a second plate and a dielectric layer located between the first plate and the second plate; the first plate of the plurality of capacitor structures in the memory array is in contact with the conductive layer; the first contact structure extends along the first direction, and one end of the first contact structure opposite to each other along the first direction is in contact with the conductive layer.

[0095] In some embodiments, Figure 4 Structure diagram of the memory provided by the embodiments of the present disclosure Figure 1 As Figure 4 As shown, the memory comprises a conductive layer 303, a memory array 300 and a first contact structure 304, the memory array 300 and the first contact structure 304 are located on the same side of the conductive layer 303 along a first direction opposite to each other, the first direction is the thickness direction of the conductive layer 303, that is, the Z direction; the memory array 300 comprises a plurality of capacitor structures 301, and the first plate 302 of the plurality of capacitor structures 301 is in contact with the conductive layer 303; the first contact structure 304 extends along the first direction, and one end of the first contact structure 304 opposite to each other along the first direction is in contact with the conductive layer 303.

[0096] In some specific examples, the storage array 300 can include a plurality of array-arranged capacitor structures 301, for example, the storage array 300 can include a plurality of array-arranged capacitor structures 301 along the X direction and the Y direction, the upper electrodes of the plurality of capacitor structures 301 are connected, thereby constituting a first plate 302, the first plate 302 includes a first part 3021 extending along a direction perpendicular to the first direction, and the conductive layer 303 can be in contact with the first part 3021, more specifically, the conductive layer 303 can extend along a direction perpendicular to the first direction and completely cover one side surface of the first part 3021 among the two sides opposite to each other along the first direction, thereby the conductive layer 303 and the first plate 302 can have a larger contact area and a smaller contact resistance, so as to reduce the voltage drop on the power supply path of the first plate 302.

[0097] In some embodiments, the resistivity of the conductive layer 303 is less than the resistivity of the first plate 302.

[0098] In some specific examples, the material of the conductive layer 303 can include copper and / or aluminum, and the material of the first plate 302 can include tungsten and / or germanosilicon.

[0099] In some specific examples, the first contact structure 304 can include a conductive material. Here, the conductive material can be one of a doped semiconductor material (for example, doped silicon, doped germanium, etc.), a conductive metal nitride (for example, titanium nitride, tantalum nitride, etc.), a metal material (for example, tungsten, titanium, tantalum, etc.), and a metal-semiconductor compound (for example, tungsten silicide, cobalt silicide, titanium silicide, etc.).

[0100] In some embodiments, the memory further includes: a peripheral circuit 320 and an interconnection layer 310 stacked along the first direction, the storage array 300 and the first contact structure 304 are located between the interconnection layer 310 and the conductive layer 303, the interconnection layer 310 is located between the peripheral circuit 320 and the storage array 300, and is located between the peripheral circuit 320 and the first contact structure 304, the storage array 300 and the peripheral circuit 320 are coupled through an interconnection line in the interconnection layer 310 and an interconnection structure 311, the other end of the first contact structure 304 along the two opposite ends of the first direction is connected with the interconnection line in the interconnection layer 310, and can be further coupled with a transistor 321 in the peripheral circuit 320 through the interconnection layer 310.

[0101] In some specific examples, the interconnection layer 310 can include a hybrid bonding layer, and the interconnection structure 311 can be a copper-copper bonding structure in the hybrid bonding layer.

[0102] In the embodiments of the present disclosure, the first plate 302 of the plurality of capacitor structures 301 in the storage array 300 can be connected with the interconnection layer 310 through the conductive layer 303 and the first contact structure 304, and coupled with the peripheral circuit 320 through the interconnection layer 310. Compared with the scheme shown in FIG. 2, in the scheme provided by the embodiments of the present disclosure, the first plate 302 can be led out directly through the conductive layer 303 in contact with the first plate 302 and the first contact structure 304 in contact with the conductive layer 303, the conductive layer 303 has a larger contact area with the first plate 302, and the conductive layer 303 has a smaller resistivity relative to the first plate 302, so that the pressure drop on the power supply path of the first plate 302 can be reduced. In addition, due to the reduction of the pressure drop on the power supply path, the difference between the voltages on the upper electrodes of different capacitor structures 301 can also be reduced. In this way, the reliability of the memory can be improved. Figure 3 Compared with the scheme shown in FIG. 2, in the scheme provided by the embodiments of the present disclosure, the first plate 302 can be led out directly through the conductive layer 303 in contact with the first plate 302 and the first contact structure 304 in contact with the conductive layer 303, the conductive layer 303 has a larger contact area with the first plate 302, and the conductive layer 303 has a smaller resistivity relative to the first plate 302, so that the pressure drop on the power supply path of the first plate 302 can be reduced. In addition, due to the reduction of the pressure drop on the power supply path, the difference between the voltages on the upper electrodes of different capacitor structures 301 can also be reduced. In this way, the reliability of the memory can be improved.

[0103] In some embodiments, Figure 5 The specific structure diagram of the memory provided by the embodiments of the present disclosure is described in combination with Figure 4 and Figure 5 The capacitor structure 301 can include the first plate 302, the second plate 3011, and the dielectric layer 3012 between the first plate 302 and the second plate 3011. The storage array 300 further includes a plurality of array-arranged vertical transistors 305, the vertical transistor 305 includes an active pillar 3050 extending along a first direction, the active pillar 3050 is located between the interconnection layer 310 and the capacitor structure 301, the active pillar 3050 includes a first electrode 3051, a channel 3052 and a second electrode 3053 arranged in sequence along the first direction, one of the first electrode 3051 and the second electrode 3053 is connected with the second plate 3011 of the capacitor structure 301, and here, the first electrode 3051 connected with the second plate 3011 of the capacitor structure 301 is taken as an example.

[0104] In some specific examples, the second plate 3011 can serve as a lower electrode of the capacitor structure 301. The material of the dielectric layer 3012 can include a high dielectric constant (High-K) material, for example, the material of the dielectric layer 3012 can include but is not limited to aluminum oxide, zirconium oxide, hafnium oxide, etc. The second plate 3011 can include a conductive material, for example, the material of the second plate 3011 can include titanium nitride.

[0105] In some embodiments, continuing to refer to Figure 4 and Figure 5The memory further includes word line structures 309 and bit line structures 306. Here, the word line structures 309 extend along the Y direction, the bit line structures 306 extend along the X direction, and the word line structures 309 are located on one side of the active pillars 3050 along the X direction. The word line structures 309 can serve as gates and, together with the active pillars 3050, form vertical transistors 305. One vertical transistor 305, together with one capacitor structure 301 connected thereto, forms a memory cell. The bit line structures 306 are located between the interconnection layer 310 and the active pillars 3050, and the other one of the first electrodes 3051 and the second electrodes 3053 is connected to the bit line structures 306. Here, the second electrodes 3053 are connected to the bit line structures 306 as an example. The bit line structures 306 and the word line structures 309 can be connected to the interconnection lines in the interconnection layer 310 through bit line lead-out structures and word line lead-out structures extending along the first direction, respectively, and further coupled to the peripheral circuit 320 through the interconnection layer 310.

[0106] In some specific examples, the word line structures 309 and the bit line structures 306 can include a conductive material. Here, the conductive material can be one of a doped semiconductor material (e.g., doped silicon, doped germanium, etc.), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.), a metal material (e.g., tungsten, titanium, tantalum, etc.), and a metal-semiconductor compound (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.).

[0107] It should be noted that, Figure 5 The specific structure of the memory shown is only an example and does not limit the structure of the memory provided in the present disclosure.

[0108] In some embodiments, referring to Figure 4 The memory further includes a bus layer 330, a pad lead-out layer 340, and a second contact structure 322. The peripheral circuit 320 is located between the interconnection layer 310 and the bus layer 330, and between the pad lead-out layer 340 and the memory array 300. The second contact structure 322 extends along the first direction and is located between the bus layer 330 and the interconnection layer 310. One end of the second contact structure 322 along the first direction is connected to the interconnection lines in the interconnection layer 310, and the other end of the second contact structure 322 along the first direction is connected to the bus in the bus layer 330. Here, the bus in the bus layer 330 can include power lines and other signal lines. The bus in the bus layer 330 can be further connected to the pad lead-out layer 340 through lead-out structures extending along the first direction to realize the pad lead-out of the memory.

[0109] In the embodiments of the present disclosure, the bus layer 330 and the pad-out layer 340 are both arranged on the side of the peripheral circuit 320 far away from the storage array 300 in the two sides opposite to each other in the first direction, so that the bit line structure 306, the word line structure 309 and the first plate 302 can all be coupled with the peripheral circuit 320 through the interconnection layer 310, and the power line does not need to be arranged in the interconnection layer 310, thereby reducing the wire length of the conductive path between the bit line structure 306 and the peripheral circuit 320, the conductive path between the word line structure 309 and the peripheral circuit 320, and the conductive path between the first plate 302 and the peripheral circuit 320, and avoiding crosstalk of the power line to the conductive paths.

[0110] In some embodiments, the memory includes a plurality of memory blocks (Blocks), and the plurality of memory blocks can constitute a memory bank (Bank). In each memory bank, at least one memory block can include Figure 4 The structure is shown.

[0111] In some embodiments, Figure 6 The layout schematic diagram of the memory block and the memory bank provided by the embodiments of the present disclosure is shown. As Figure 6 shown, the memory includes a plurality of memory banks 500, and each memory bank 500 includes a plurality of memory blocks 400. The plurality of memory blocks 400 are arranged in an array along a second direction and a third direction. The second direction intersects the third direction, and both the second direction and the third direction are perpendicular to the first direction. Here, taking the second direction as the X direction and the third direction as the Y direction as an example.

[0112] It should be noted that, in order to facilitate observation, Figure 6 the range of each memory bank 500 and the range of one memory block 400 are indicated by dashed lines, and in some embodiments, there can be no obvious boundary between adjacent two memory banks or between adjacent two memory blocks. In addition, Figure 6 the number of memory banks 500 and the number of memory blocks 400 in each memory bank 500 are only examples, and the present disclosure does not specifically limit the number of memory banks and the number of memory blocks in each memory bank in the memory.

[0113] In some embodiments, continuing to refer to Figure 6 , the memory block 400 includes a storage region 401 and a contact region 402. The contact region 402 is located at least one side of the storage region 401 in the second direction, and the contact region 402 is located at least one side of the storage region 401 in the third direction. At least one memory block 400 in the plurality of memory blocks 400 includes a first contact structure 304, and the first contact structure 304 is located in the contact region 402 of the memory block 400.

[0114] In some embodiments, Figure 7 for Figure 6A cross-sectional view along the line AA’ in combination with reference to Figure 6 and Figure 7 The storage region 401 of one of the storage blocks 400 includes the storage array 300 and a portion of the peripheral circuit 320 corresponding to the storage array 300. Here, the portion of the peripheral circuit 320 corresponding to the storage array 300 can include a column decoder, a sense amplifier circuit, a word line driver, etc.

[0115] In some embodiments, in combination with reference to Figure 6 and Figure 7 The first plate 302 includes a first portion 3021 located in the storage region 401 and extending in a direction perpendicular to the first direction, a second portion 3022 located in the storage region 401 and extending in the first direction and away from the conductive layer 303, and a third portion 3023 located in the contact region 402 and extending in a direction perpendicular to the first direction, the second portion 3022 of the first plate 302 of at least two of the plurality of storage blocks 400 in the memory bank 500 is connected through the third portion 3023, and the first plate 302 of each of the plurality of storage blocks 400 in the memory bank 500 is in contact with the conductive layer 303.

[0116] In the embodiments of the present disclosure, the conductive layer 303 can extend to all the storage blocks 400 in the second direction and the third direction, so that each of the storage blocks 400 includes a portion of the conductive layer 303, and the first plate 302 of each of the plurality of capacitor structures 301 in each of the storage blocks 400 is in contact with the conductive layer 303, that is, the first plate 302 in the plurality of storage blocks 400 can be led out through the conductive layer 303.

[0117] In some embodiments, in combination with reference to Figure 7 The memory bank 500 further includes a first isolation structure 307 between the conductive layer 303 and the third portion 3023 of the first plate 302 in the contact region 402, and a second isolation structure 308 between the first contact structure 304 and the first plate 302.

[0118] In some specific examples, the first isolation structure 307 and the second isolation structure 308 can include a dielectric material, such as one of silicon oxide, silicon nitride, silicon oxynitride, etc.

[0119] In some embodiments, the first contact structure 304 is located in the contact region 402 between two storage regions 401 adjacent in the second direction; or, the first contact structure 304 is located in the contact region 402 between two storage regions 401 adjacent in the third direction.

[0120] In some specific examples, in combination with reference to Figure 6The first contact structure 304 is located in the contact region 402 between two adjacent storage regions 401 in the second direction, so that for each memory bank 500, no additional region needs to be arranged in the third direction, thereby reducing the volume of the memory.

[0121] In some embodiments, the memory bank 500 includes at least one first contact structure 304. Figure 6 For example, each memory bank 500 includes two first contact structures 304, and the first contact structures 304 are located in the contact regions 402 at the outermost sides of the memory bank 500 in the second direction. The size d1 of the contact region 402 at the outermost side of the memory bank 500 and including the first contact structure 304 in the second direction is greater than the size d2 of the contact region 402 between two adjacent storage regions 401 in the memory bank 500 in the second direction, and / or the size d1 of the contact region 402 at the outermost side of the memory bank 500 and including the first contact structure 304 in the second direction is greater than the size d3 of the contact region 402 between two adjacent storage regions 401 in the memory bank 500 in the third direction.

[0122] In some specific examples, the first plates 302 in all the storage blocks 400 in the same memory bank 500 are connected, the first plates 302 can be separated only in the contact region 402 at the boundary of two adjacent memory banks 500, and the first contact structure 304 can be arranged in the contact region 402. Since the conductive layer 303 can extend to each storage block 400 of the memory bank 500 in a direction perpendicular to the first direction, and the first plate 302 in each storage block 400 is in contact with the conductive layer 303, arranging the first contact structure 304 only in the contact region 402 can realize the leading-out of the upper electrodes of all the capacitor structures 301 in the memory bank, and the width of the contact region 402 without the first contact structure 304 can be smaller than the width of the contact region 402 with the first contact structure 304, thereby facilitating the reduction of the size of the memory.

[0123] In the above embodiments, for example, each memory bank 500 includes two first contact structures 304. In other embodiments, as shown in Figure 8 one first contact structure 304 can be arranged in one memory bank 500.

[0124] In some embodiments, the conductive layer 303 can extend to all the memory banks 500, so that the entire memory can also include only one first contact structure 304 for connecting the conductive layer 303 and the interconnection layer 310.

[0125] In Figure 3In the lead-out scheme of the first plate 202 shown in the figure, each storage array 200 needs to be provided with a contact structure 205, while in the lead-out scheme of the first plate 302 provided in the embodiments of the present disclosure, the first plates 302 of the capacitive structures 301 in all the storage arrays 300 in the same memory bank 500 can be led out through the conductive layer 303 in contact with the first plate 302 and the first contact structure 304 in contact with the conductive layer 303. In addition, when the first contact structure 304 is provided in the contact region 402 between two adjacent storage regions 401 in one of the second direction and the third direction, there is no need to provide an additional region in the other of the second direction and the third direction. In this way, not only the number of contact structures used for leading out the upper electrode of the capacitive structure can be reduced, but also the area of the contact region can be reduced, so that the integration of the memory can be improved, and the miniaturization of the memory can be facilitated.

[0126] In the above embodiments, the conductive layer 303 has a flat plate structure as an example, and in other embodiments, as shown in the figure, Figure 9 The conductive layer 303 can include a flat plate part 3031 and a protruding part 3032, wherein the flat plate part 3031 is located in the storage region 401 and the contact region 402 and extends in a direction perpendicular to the first direction; the protruding part 3032 extends in the first direction and is located between the flat plate part 3031 in the contact region 402 and the first contact structure 304, and the first contact structure 304 is in contact with the protruding part 3032. In this way, the size of the first contact structure 304 in the first direction can be reduced, and the voltage drop on the power supply path of the first plate 302 can be further reduced.

[0127] In the embodiments of the present disclosure, the first plate as the upper electrode of the capacitive structure can be led out through the conductive layer in contact with the first plate and the first contact structure in contact with the conductive layer, the contact area between the conductive layer and the first plate is large, and the resistivity of the conductive layer is small, so that the voltage drop on the power supply path of the upper electrode of the capacitive structure can be reduced, the difference between the voltages on the upper electrodes of the capacitive structures in different positions can be reduced, and the reliability of the memory can be improved. In addition, on the basis of reducing the voltage drop on the power supply path of the upper electrode of the capacitive structure, since the conductive layer can extend to all the memory blocks, one memory bank can be provided with only one first contact structure for leading out the first plate, the first contact structure can be provided in the contact region on the outermost side of the memory bank, and the width of the contact region without the first contact structure can be smaller than the width of the contact region with the first contact structure. In this way, not only the number of contact structures used for leading out the upper electrode of the capacitive structure can be reduced, but also the area of the contact region can be reduced, so that the integration of the memory can be improved, and the miniaturization of the memory can be facilitated.

[0128] Based on the similar concept as the above memory, the present disclosure further provides a memory system, the memory system comprising: at least one memory according to any one of the above embodiments; and a controller coupled to the at least one memory and configured to control the memory. For the specific components and functions of the memory system, reference can be made to the above description of the memory system 10 in Figure 1 For brevity, the above description of the memory system 10 in

[0129] Based on the similar concept as the above memory, the present disclosure further provides a manufacturing method of a memory, Figure 10 For brevity, the above description of the memory system 10 in

[0130] Step S10: forming a memory array; the memory array comprising a plurality of capacitor structures; each capacitor structure comprising a first plate, a second plate, and a dielectric layer between the first plate and the second plate;

[0131] Step S20: forming a conductive layer and a first contact structure; the memory array and the first contact structure are located on the same side of the conductive layer along a first direction; the first direction is the thickness direction of the conductive layer; the first plate of each capacitor structure in the memory array is in contact with the conductive layer; the first contact structure extends along the first direction, and one end of the first contact structure along the first direction is in contact with the conductive layer.

[0132] Figures 11 to 19 For brevity, the above description of the memory system 10 in

[0133] In some embodiments, in combination with the above description of the memory array 10, Figure 10 , Figure 5 and Figure 11, the step S10 can include: forming the memory array 300 on the first substrate 600, the memory array 300 being located in the memory region 401. Specifically, forming the array-arranged vertical transistors 305 on the first substrate 600, the vertical transistors 305 including the active pillars 3050 extending along a first direction, the active pillars 3050 including the first electrodes 3051, the channels 3052 and the second electrodes 3053 arranged in sequence along the first direction; forming the capacitor structures 301 on the vertical transistors 305, the capacitor structures 301 including the first plates 302, the second plates 3011 and the dielectric layers 3012 between the first plates 302 and the second plates 3011, the first plates 302 of the plurality of capacitor structures 301 being connected, the second plates 3011 of the capacitor structures 301 being connected with the first electrodes 3051 of the vertical transistors 305. The first plates 302 include the first portions 3021 located in the memory region 401 and extending along a direction perpendicular to the first direction, the second portions 3022 located in the memory region 401 and extending along the first direction, the third portions 3023 located in the contact region 402 and extending along the direction perpendicular to the first direction.

[0134] In some embodiments, with reference to Figure 11 and Figure 12 , the method for manufacturing the memory further includes: etching part of the third portions 3023 in the contact region 402 where the first contact structure is required to be formed, and exposing the first barrier layer 601.

[0135] In some embodiments, with reference to Figure 12 and Figure 13 , the method for manufacturing the memory further includes: forming the second barrier layer 602 covering the first plates 302, the second barrier layer 602 can cover the top surface of the first portions 3021 and the top surface of the third portions 3023. Filling the dielectric material in the contact region 402 to be flush with the top surface of the second barrier layer 602.

[0136] In some embodiments, with reference to Figure 13 and Figure 14 , the method for manufacturing the memory further includes: removing the second barrier layer 602 and part of the dielectric material by a chemical mechanical polishing (CMP) process, the remaining dielectric material constituting the first isolation structures 307 and the second isolation structures 308, the top surface of the first isolation structures 307 and the top surface of the second isolation structures 308 being flush with the top surface of the first portions 3021.

[0137] In some embodiments, with reference to Figure 12 and Figure 15After etching the third part 3023, dielectric material can be directly filled into the contact area 402 to form the first isolation structure 307 and the second isolation structure 308.

[0138] In some embodiments, in conjunction with reference Figure 15 and Figure 16 The execution step S20 may include: forming a conductive layer 303 covering the first isolation structure 307, the second isolation structure 308 and the first portion 3021, wherein the conductive layer 303 is in contact with the first portion 3021, and the first isolation structure 307 is located between the conductive layer 303 and the third portion 3023 of the first electrode plate 302 in the contact area 402.

[0139] In some embodiments, in conjunction with reference Figure 16 , Figure 17 and Figure 5 The method for manufacturing memory also includes: Figure 16 The structure shown is flipped and the first substrate 600 is removed; a bit line structure 306 is formed, which is connected to the second electrode 3053 of the vertical transistor 305. Step S20 may include: forming a first contact structure 304 extending along a first direction, one end of which is in contact with the conductive layer 303 at opposite ends along the first direction, and a second isolation structure 308 located between the first contact structure 304 and the first electrode 302.

[0140] In some embodiments, refer to Figure 17 The method of manufacturing the memory further includes: forming a first sub-interconnect layer 310a, wherein one end of the two opposite ends of the first contact structure 304 along a first direction is connected to an interconnect line in the first sub-interconnect layer 310a, and the first sub-interconnect layer 310a further includes a first sub-interconnect structure 311a connected to the interconnect line.

[0141] In some embodiments, refer to Figure 18 The method of manufacturing the memory further includes: forming a peripheral circuit 320 in a second substrate 700, the peripheral circuit 320 including a plurality of transistors 321, forming a second sub-interconnect layer 310b on the peripheral circuit 320, the second sub-interconnect layer 310b including a second sub-interconnect structure 311b.

[0142] In some embodiments, in conjunction with reference Figure 17 , Figure 18 and Figure 19The manufacturing method of the memory further includes: bonding the first sub-interconnection layer 310a and the second sub-interconnection layer 310b to form the interconnection layer 310, and bonding the first sub-interconnection structure 311a and the second sub-interconnection structure 311b one-to-one to form the interconnection structure 311. The memory array 300, the interconnection layer 310, and the peripheral circuit 320 are arranged in a stack along the first direction, the memory array 300 and the first contact structure 304 are located between the interconnection layer 310 and the conductive layer 303; the interconnection layer 310 is located between the peripheral circuit 320 and the memory array 300, and is located between the peripheral circuit 320 and the first contact structure 304; the memory array 300 and the peripheral circuit 320 are coupled through the interconnection layer 310; and the first contact structure 304 is connected to the interconnection layer 310 at the other end of the two ends opposite to each other along the first direction.

[0143] In some embodiments, referring to Figure 19 The manufacturing method of the memory further includes: thinning the second substrate 700, and then forming the second contact structure 322 extending along the first direction and penetrating through the second substrate 700; and forming the bus layer 330 on the second substrate 700, the peripheral circuit 320 being located between the interconnection layer 310 and the bus layer 330; the second contact structure 322 extending along the first direction and being located between the bus layer 330 and the interconnection layer 310; the second contact structure 322 being connected to the interconnection line in the interconnection layer 310 at one end of the two ends opposite to each other along the first direction; and the second contact structure 322 being connected to the bus in the bus layer 330 at the other end of the two ends opposite to each other along the first direction.

[0144] In some embodiments, referring to Figure 19 The manufacturing method of the memory further includes: forming the pad lead-out layer 340 on the bus layer 330, the peripheral circuit 320 being located between the pad lead-out layer 340 and the memory array 300.

[0145] In some embodiments, the manufacturing method of the memory includes: forming a plurality of memory blocks. The manufacturing method of the memory provided by the above embodiments can be the manufacturing method of one memory block in the memory, and the method of simultaneously forming a plurality of memory blocks will be introduced below.

[0146] In some embodiments, referring to Figure 6 The manufacturing method of the memory includes: forming a plurality of memory blocks 400, the plurality of memory blocks 400 being arranged in an array along a second direction and a third direction, the memory block 400 including a storage area 401 and a contact area 402; the contact area 402 being located at least one side of the storage area 401 in the second direction, and the contact area 402 being located at least one side of the storage area 401 in the third direction.

[0147] In some embodiments, referring to Figure 6 , Figure 10 and Figure 19The specific process of performing step S10 and step S20 can include: simultaneously forming a storage array 300 in the storage region 401 of each storage block 400, and forming the first contact structure 304 in the contact region 402 of at least one storage block 400; forming the conductive layer 303 extending in a direction perpendicular to the first direction, and the conductive layer 303 can extend to all storage blocks 400, and the first electrode plate 302 in each storage block 400 is in contact with the conductive layer 303.

[0148] In the manufacturing method provided in the embodiments of the present disclosure, on one hand, the conductive layer 303 can be directly formed by a deposition process without further patterning the conductive layer 303, and compared with the scheme of first forming a contact structure connected with the first electrode plate and then forming a metal line connected with the contact structure, the process is simpler, and the process cost and process difficulty can be reduced; on the other hand, the conductive layer 303 can form a larger contact area with the first electrode plate 302, so as to reduce the contact resistance and the voltage drop on the power supply path of the first electrode plate 302; on the other hand, the bottom end of the first contact structure 304 falls on the conductive layer 303, and the alignment difficulty in the forming process is greatly reduced.

[0149] In the embodiments of the present disclosure, the deposition process includes but is not limited to chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD) and atomic layer deposition (ALD).

[0150] In some embodiments, in combination with reference to Figure 6 and Figure 19 The plurality of storage blocks 400 constitute a storage bank 500, the contact region 402 forming the first contact structure 304 can be the contact region 402 located at the outermost side of the storage bank 500 in the second direction, and the size d1 of the contact region 402 located at the outermost side of the storage bank 500 in the second direction in the second direction is greater than the size d2 of the contact region 402 between two adjacent storage regions 401 of the storage bank 500 in the second direction, and / or the size d1 of the contact region 402 located at the outermost side of the storage bank 500 in the second direction in the second direction is greater than the size d3 of the contact region 402 between two adjacent storage regions 401 of the storage bank 500 in the third direction.

[0151] In this disclosure embodiment, in conjunction with reference to Figure 6 , Figure 12 and Figure 13 When etching the third portion 3023 of the first electrode plate 302, the etching area can be... Figure 6 In the contact area 402 located on the outermost side of the memory cell 500 in the second direction, etching can form a trench extending in the Y direction to separate the first electrode plates 302 of two adjacent memory cells 500, and then a first contact structure 304 is formed in this area. Since the conductive layer 303 can extend into all memory blocks 400 and the resistivity of the conductive layer 303 is small, there is no need to form a contact structure for leading out the first electrode plates 302 between the two memory areas 401 inside the memory cell 500. Therefore, the width of the contact area 402 located inside the memory cell 500 can be smaller than the contact area 402 located on the outermost side of the memory cell 500 for setting the first contact structure 304, which is beneficial to the miniaturization of the memory.

[0152] The features disclosed in the several device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new device embodiments.

[0153] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0154] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A memory, comprising: The memory includes a conductive layer, at least one storage array and at least one first contact structure; wherein, The storage array and the first contact structure are located on the same side of the conductive layer along a first direction; the first direction is the thickness direction of the conductive layer; The storage array includes a plurality of capacitor structures; the capacitor structure includes a first electrode plate, a second electrode plate and a dielectric layer located between the first electrode plate and the second electrode plate; the first electrode plate of the plurality of capacitor structures in the storage array is in contact with the conductive layer; The first contact structure extends along the first direction, and one end of the first contact structure along the first direction is in contact with the conductive layer.

2. The memory of claim 1, wherein, The resistivity of the conductive layer is less than the resistivity of the first electrode plate.

3. The memory of claim 1, wherein, The memory includes a plurality of storage blocks; the plurality of storage blocks are arranged in an array along a second direction and a third direction; the second direction intersects the third direction, and the second direction and the third direction are both perpendicular to the first direction; the storage block includes a storage area and a contact area; the contact area is located on at least one side of the storage area in the second direction, and the contact area is located on at least one side of the storage area in the third direction; the storage area of one of the storage blocks includes one of the storage arrays; at least one of the storage blocks in the plurality of storage blocks includes the first contact structure, and the first contact structure of the storage block is located in the contact area of the storage block.

4. The memory of claim 3, wherein, The conductive layer extends along the second direction and the third direction, each of the plurality of storage blocks includes a part of the conductive layer, and the first electrode plate of the plurality of capacitor structures in each of the storage blocks is in contact with the conductive layer in the storage block.

5. The memory of claim 4, wherein, The first contact structure is located in the contact area between two adjacent storage areas in the second direction; or, the first contact structure is located in the contact area between two adjacent storage areas in the third direction.

6. The memory of claim 4, wherein, The memory includes a plurality of storage banks; the storage bank includes a plurality of storage blocks, and the plurality of storage blocks in the storage bank are arranged in an array along the second direction and the third direction; the storage bank includes at least one first contact structure.

7. The memory of claim 6, wherein, The memory includes at least two storage banks arranged along the second direction; the contact area is located on both sides of the storage area in the second direction; the first contact structure in the storage bank is located in the contact area on the outermost side of the storage bank in the second direction; the size of the contact area on the outermost side of the storage bank in the second direction in the second direction is greater than the size of the contact area between two adjacent storage areas in the second direction in the second direction in the storage bank, and / or the size of the contact area on the outermost side of the storage bank in the second direction in the second direction is greater than the size of the contact area between two adjacent storage areas in the third direction in the third direction in the storage bank.

8. The memory of claim 6, wherein, a first plate of a plurality of capacitive structures in the memory block is connected; the first plate includes at least a first portion in the storage region and extending in a direction perpendicular to the first direction, and a second portion in the storage region and extending in the first direction and away from the conductive layer; the conductive layer is in contact with at least the first portion.

9. The memory of claim 8, wherein, the first plate of at least one of the memory blocks in the memory bank further includes a third portion in the contact region and extending in a direction perpendicular to the first direction; the second portions of the first plates of at least two of the memory blocks in the memory bank are connected through the third portions, and the first plates of the memory blocks in the memory bank are all in contact with the conductive layer.

10. The memory of claim 9, wherein, the memory bank further includes: a first isolation structure between the conductive layer and the third portion of the first plate in the contact region; a second isolation structure between the first contact structure and the first plate.

11. The memory of claim 3, wherein, the conductive layer includes a flat portion and a protruding portion; the flat portion is in the storage region and the contact region and extends in a direction perpendicular to the first direction; the protruding portion extends in the first direction and is between the flat portion in the contact region and the first contact structure; the first contact structure is in contact with the protruding portion.

12. The memory of claim 1, wherein, the memory further includes: peripheral circuitry and interconnect layers stacked along the first direction; the memory array and the first contact structure are between the interconnect layers and the conductive layer; the interconnect layers are between the peripheral circuitry and the memory array, and between the peripheral circuitry and the first contact structure; the memory array and the peripheral circuitry are coupled through the interconnect layers; another end of the first contact structure opposite to one end of the first contact structure is connected to an interconnect line in the interconnect layers.

13. The memory of claim 12, wherein, the memory array further includes: a plurality of active pillars extending in the first direction, the active pillars are between the interconnect layers and the capacitive structures; the active pillars include a first electrode, a channel, and a second electrode arranged in sequence along the first direction; one of the first electrode and the second electrode is connected to the second plate of the capacitive structure; the memory further includes: a bit line structure between the interconnect layers and the active pillars; another of the first electrode and the second electrode is connected to the bit line structure.

14. The memory of claim 12, wherein, the memory further includes bus layers and second contact structures; the peripheral circuitry is between the interconnect layers and the bus layers; the second contact structures extend in the first direction and are between the bus layers and the interconnect layers; one end of the second contact structures opposite to another end of the second contact structures is connected to an interconnect line in the interconnect layers, and the other end of the second contact structures is connected to a bus line in the bus layers.

15. The memory of claim 12, wherein, the memory further includes: a pad routing layer; the peripheral circuitry is between the pad routing layer and the memory array.

16. A memory system, comprising: comprise: at least one memory as claimed in any of claims 1 to 15; A controller coupled to the memory and configured to control the memory.

17. A method of manufacturing a memory, characterized by: Comprising: forming a memory array; the memory array comprises a plurality of capacitor structures; the capacitor structure comprises a first plate, a second plate, and a dielectric layer between the first plate and the second plate; forming a conductive layer and a first contact structure; the memory array and the first contact structure are located on the same side of the conductive layer along a first direction; the first direction is the thickness direction of the conductive layer; the first plate of the capacitor structure in the memory array is in contact with the conductive layer; the first contact structure extends along the first direction, and one end of the first contact structure along the first direction is in contact with the conductive layer.

18. The method of manufacturing a memory according to claim 17, wherein, The manufacturing method of the memory further comprises: forming a plurality of memory blocks; the plurality of memory blocks are arranged in an array along a second direction and a third direction; the second direction intersects the third direction, and the second direction and the third direction are both perpendicular to the first direction; the memory block comprises a storage area and a contact area; the contact area is located on at least one side of the storage area in the second direction, and the contact area is located on at least one side of the storage area in the third direction; the forming of the memory array and the forming of the first contact structure comprises: forming one memory array in the storage area of each memory block, and forming the first contact structure in the contact area of at least one memory block.

19. The method of manufacturing a memory according to claim 18, wherein, The forming of the conductive layer comprises: forming a conductive layer extending along the second direction and the third direction; each memory block in the plurality of memory blocks comprises a part of the conductive layer, and the first plate of the plurality of capacitor structures in each memory block is in contact with the conductive layer in the memory block.

20. The method of manufacturing a memory according to claim 18, wherein, The memory comprises a plurality of memory banks; the memory bank comprises a plurality of memory blocks, and the plurality of memory blocks in the memory bank are arranged in an array along the second direction and the third direction; the forming of the first contact structure comprises: forming at least one first contact structure in each memory bank.

21. The method of manufacturing a memory according to claim 20, wherein, The memory comprises at least two memory banks arranged along the second direction; the contact area is located on both sides of the storage area in the second direction; the forming of the first contact structure comprises: forming the first contact structure in the contact area located on the outermost side of the memory bank in the second direction; the size of the contact area located on the outermost side of the memory bank in the second direction in the second direction is greater than the size of the contact area between two adjacent storage areas in the second direction in the memory bank in the second direction, and / or the size of the contact area located on the outermost side of the memory bank in the second direction in the second direction is greater than the size of the contact area between two adjacent storage areas in the third direction in the memory bank in the third direction.

22. The method of manufacturing a memory according to claim 20, wherein, The first plate of the plurality of capacitive structures in the memory block is connected; the first plate includes at least a first portion in the memory region and extending in a direction perpendicular to the first direction, and a second portion in the memory region and extending in the first direction and away from the conductive layer; The forming of the conductive layer includes: forming the conductive layer in contact with at least the first portion.

23. The method of manufacturing a memory according to claim 22, wherein, The first plate of at least one of the memory blocks in the memory bank further includes a third portion in the contact region and extending in a direction perpendicular to the first direction; the second portion of the first plate of at least two of the memory blocks in the memory bank is connected through the third portion, and the first plate of each of the memory blocks in the memory bank is in contact with the conductive layer.

24. The method of manufacturing a memory according to claim 23, wherein, The method for manufacturing the memory further includes: forming a first isolation structure between the conductive layer in the contact region and the third portion of the first plate; forming a second isolation structure between the first contact structure and the first plate.

25. The method of fabricating memory according to claim 17, wherein, The method for manufacturing the memory further includes: forming a peripheral circuit and an interconnection layer stacked in the first direction; the memory array and the first contact structure are between the interconnection layer and the conductive layer; the interconnection layer is between the peripheral circuit and the memory array, and between the peripheral circuit and the first contact structure; the memory array and the peripheral circuit are coupled through the interconnection layer; the other end of the first contact structure opposite to one end in the first direction is connected to the interconnection layer.

26. The method of manufacturing a memory according to claim 25, wherein, The method for manufacturing the memory further includes: forming a bus layer and a second contact structure; the peripheral circuit is between the interconnection layer and the bus layer; the second contact structure extends in the first direction and is between the bus layer and the interconnection layer; one end of the second contact structure opposite to the other end in the first direction is connected to an interconnection line in the interconnection layer; the other end of the second contact structure opposite to the one end in the first direction is connected to a bus in the bus layer.

27. The method of fabricating memory cells of claim 25, wherein, The method for manufacturing the memory further includes: forming a pad lead-out layer; the peripheral circuit is between the pad lead-out layer and the memory array.

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