On-chip isolation capacitor structure based on 3D integrated circuit and manufacturing method thereof
By alternately stacking electrode layers and dielectric layers in 3D integrated circuits and connecting capacitor cells using metal interconnect structures, the problem of achieving high capacitance density within a limited chip area has been solved, enabling the fabrication of high-performance, low-cost capacitor structures.
Patent Information
- Application Number
- CN202511320503.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-16
- Publication Date
- 2025-12-19
AI Technical Summary
Achieving high-performance, high-capacitance capacitor structures within a limited chip area is a challenge for miniaturized, high-density integrated circuits. Traditional planar capacitors are limited by two-dimensional layout, making it difficult to simultaneously optimize capacitance density, voltage withstand performance, and reliability.
The on-chip isolation capacitor structure using 3D integrated circuits forms parallel, series, or hybrid networks by alternately stacking electrode layers and dielectric layers in the vertical direction and electrically connecting capacitor units using metal interconnect structures. Different electrodes and dielectric materials can be selected to adjust the capacitance value and withstand voltage.
Significantly improves capacitor density and capacitance value without increasing chip area, meeting the needs of diverse application scenarios, reducing signal delay and power consumption, compatible with standard CMOS processes, and shortening production cycle.
Smart Images
Figure CN121174530A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of capacitors, and in particular to an on-chip isolation capacitor structure based on a 3D integrated circuit and a manufacturing method thereof. BACKGROUND
[0002] With the rapid development of microelectronic technology towards miniaturization and high-density integration, especially in the application scenarios of micro sensors, wearable devices and Internet of Things terminals which have extremely harsh requirements for space size, how to realize a high-performance and large-capacitance capacitor structure in a limited chip area has become a core challenge for those skilled in the art. SUMMARY
[0003] The present application provides an on-chip isolation capacitor structure based on a 3D integrated circuit and a manufacturing method thereof, which solves the technical problem of how to realize a high-capacitance density in a limited chip area, and achieves the technical effects of improving the capacitor density and being compatible with standard integrated circuit processes.
[0004] In order to achieve the above-mentioned purpose, the main technical scheme adopted by the present application includes:
[0005] In a first aspect, the present application provides an on-chip isolation capacitor structure based on a 3D integrated circuit, comprising: a substrate; a capacitor stack provided on the substrate, the capacitor stack being composed of a plurality of electrode layers and a plurality of dielectric layers which are alternately stacked in a direction perpendicular to the substrate; for any dielectric layer, the electrode layer located on the upper surface of the dielectric layer, the electrode layer located on the lower surface of the dielectric layer and the dielectric layer form a capacitor unit; a metal interconnection structure electrically connected to at least two electrode layers in the capacitor stack to electrically connect a plurality of capacitor units.
[0006] The on-chip isolation capacitor structure based on a 3D integrated circuit provided by the present application realizes the technical effects of significantly improving the capacitor density and the capacitor value in a unit chip area by alternately stacking a plurality of electrode layers and dielectric layers in a direction perpendicular to the substrate to build a capacitor stack, and electrically connecting each capacitor unit by using a metal interconnection structure, effectively overcoming the inherent bottleneck of traditional planar capacitors which are limited by two-dimensional layout, and being suitable for advanced electronic systems such as micro sensors, wearable devices and the like which have strict requirements for space and performance.
[0007] Optionally, the metal interconnection structure includes a conductive via, the conductive via penetrating one or more dielectric layers of the capacitor stack and being electrically connected to a specified electrode layer, so that a plurality of capacitor units form a parallel, series or mixed connection capacitor network.
[0008] The conductive via breaks through the two-dimensional plane limitation, connects multiple capacitor units in the vertical direction, improves the total capacitance density without increasing the chip area, and solves the demand for high capacitance of miniaturized devices. The conductive via selectively connects different electrode layers to dynamically configure parallel, series or mixed networks to meet various application scenarios. The conductive via provides the shortest vertical transmission path in the chip, greatly reducing signal delay and power consumption. In addition, the conductive via is compatible with standard CMOS process, without additional packaging or assembly steps, shortening the production cycle.
[0009] Optionally, each of the electrode layers adopts different electrode materials; and / or, each of the dielectric layers adopts different dielectric materials.
[0010] Selecting different dielectric materials can specifically adjust the capacitance value and voltage resistance of each capacitor unit, so that the overall capacitor system realizes higher total capacitance value in limited space, while meeting the specific needs of insulation and voltage resistance of different layers.
[0011] Optionally, the electrode material of the plurality of electrode layers is aluminum or copper; and the dielectric material of the plurality of dielectric layers is one or more of silicon dioxide, silicon nitride, barium titanate or barium aluminum titanate.
[0012] Aluminum and copper have good conductivity and process compatibility, which can ensure efficient conduction of the electrode layer, effectively reduce the parasitic resistance of the interconnection wire, and improve the frequency response and charge and discharge efficiency of the capacitor. Using silicon dioxide or silicon nitride as dielectric material can ensure the insulation reliability of the device. By introducing barium titanate or barium aluminum titanate materials with high dielectric constant in specific layers, the unit area capacitance density can be greatly improved, overcoming the inherent bottleneck of limited capacitor performance of traditional single material.
[0013] Optionally, an insulating layer is arranged between the capacitor stack and the substrate; and an upper surface of the insulating layer is provided with an electrode layer of a bottommost layer in the capacitor stack.
[0014] By arranging an insulating layer between the capacitor stack and the substrate, electrical isolation between the capacitor stack and the substrate is achieved, ensuring the independence and stability of the charge storage of each capacitor unit, and ensuring the reliability of the isolated capacitor in high-integration 3D integrated circuits.
[0015] Optionally, in the capacitor stack, the number of layers of the electrode layers is one more than the number of layers of the dielectric layers.
[0016] Each time a dielectric layer is added, only one electrode layer is added to obtain a complete capacitor unit. By sharing the intermediate electrode layer, the capacitor density is maximized while the vertical space is minimized, providing an optimal stack configuration for high-density three-dimensional integration, overcoming the dependence of traditional planar capacitors on chip area.
[0017] Optionally, the metal interconnection structure electrically interconnects all odd-numbered electrode layers and all even-numbered electrode layers, respectively, to form a parallel capacitor network.
[0018] By interconnecting the odd-numbered electrode layers and the even-numbered electrode layers, each capacitor unit formed by the adjacent odd-numbered electrode layers, even-numbered electrode layers, and intermediate dielectric layers is in parallel, and the total capacitance value is the sum of the individual capacitor units, effectively increasing the overall capacitance value and overcoming the limitations of two-dimensional planar layout on capacitor density.
[0019] Optionally, in the capacitor stack, at least one of the dielectric layers is made of high dielectric constant material.
[0020] By using high dielectric constant materials such as barium titanate, silicon nitride, and barium aluminum titanate in specific layers of the capacitor stack, the capacitance of the capacitor unit in that layer can be increased without increasing the number of layers or volume, thereby breaking through the performance limitations of a single material system and optimizing the overall performance of the capacitor network.
[0021] In a second aspect, the embodiments of the present application provide a manufacturing method of an on-chip isolation capacitor structure based on a 3D integrated circuit, the method comprising: providing a substrate; alternately stacking a plurality of electrode layers and a plurality of dielectric layers in a direction perpendicular to the substrate to form a capacitor stack; wherein for any dielectric layer, the electrode layer on the upper surface of the dielectric layer and the electrode layer on the lower surface of the dielectric layer form a capacitor unit; forming a metal interconnection structure, the metal interconnection structure being electrically connected to at least two electrode layers in the capacitor stack to electrically connect a plurality of capacitor units.
[0022] By alternately stacking electrode and dielectric layers to construct a three-dimensional capacitor stack and using metal interconnection to achieve interlayer electrical connection, the capacitor density and integration level are greatly improved on a unit area of a chip, solving the demand for high capacitance of miniaturized electronic devices.
[0023] Optionally, forming the metal interconnection structure comprises: forming a conductive via through one or more dielectric layers of the capacitor stack; and electrically connecting the specified electrode layer through the conductive via, so that a plurality of capacitor units form a parallel, series, or mixed connection capacitor network.
[0024] By preparing conductive vias in the dielectric layer and precisely connecting specified electrodes, the physical limitations of two-dimensional interconnection are broken through, the signal transmission path is shortened by using vertical interconnection, the parasitic inductance and resistance are reduced, and the high-frequency response speed and energy efficiency of the capacitance network are improved. By connecting specified electrode layers through conductive vias, a parallel, series or mixed capacitance network can be configured on the same physical structure to meet various application scenarios. BRIEF DESCRIPTION OF DRAWINGS
[0025] In order to more clearly illustrate the technical solutions in the specific embodiments or prior art of the present application, the drawings needed in the description of the specific embodiments or prior art will be briefly introduced. Obviously, the drawings described below are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.
[0026] Figure 1 A schematic diagram of an on-chip isolation capacitance structure based on a 3D integrated circuit is provided for the embodiments of the present application.
[0027] Figure 2 A schematic diagram of an on-chip isolation capacitance structure is provided for the embodiments of the present application.
[0028] Figure 3 A flowchart of a manufacturing method of an on-chip isolation capacitance structure based on a 3D integrated circuit is provided for the embodiments of the present application.
[0029] Figure 4 A schematic diagram of an on-chip isolation capacitance structure is provided for the embodiments of the present application. DETAILED DESCRIPTION
[0030] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some embodiments of the present application, not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.
[0031] Capacitors are indispensable passive elements in integrated circuits and are widely used in power decoupling, noise filtering, signal coupling and isolation, analog signal processing and other fields. With the rapid development of microelectronics technology towards miniaturization and high-density integration, especially in the application scenarios of micro-sensors, wearable devices and Internet of Things terminals, which are extremely demanding on space size, how to realize high-performance and large-capacitance capacitance structures in limited chip area has become a core challenge for those skilled in the art.
[0032] Traditional on-chip capacitors mainly adopt planar structures, such as metal-insulator-metal capacitors or polysilicon-insulator-polysilicon capacitors. These technical solutions rely on constructing capacitor plates in the wafer level plane, and the capacitance value is proportional to the plate area. Therefore, in order to obtain a larger capacitance value, it is necessary to occupy more chip area, which is fundamentally contrary to the development trend of integrated circuit miniaturization and high integration. In order to improve the capacitance density in a limited area, the related technology usually selects a single high dielectric constant (high-K) material as the dielectric for the entire capacitor, and at the same time, the thickness of the dielectric layer is thinned. However, excessive thinning of the dielectric layer will sacrifice the withstand voltage characteristics of the capacitor and may cause a sharp increase in leakage current and a decrease in reliability. In addition, the selection of a single dielectric material is difficult to simultaneously optimize multiple performance indicators such as capacitance value, breakdown voltage, and temperature coefficient.
[0033] There is an urgent need in the art for an on-chip capacitor structure and manufacturing method that can truly realize high-density integration, is compatible with advanced integrated circuit manufacturing processes, and can comprehensively optimize capacitance density, withstand voltage performance, and reliability.
[0034] Please refer to Figure 1 , Figure 1 The schematic diagram of the on-chip isolated capacitor structure based on 3D integrated circuit provided by the embodiments of the present application is shown in Figure 1 The on-chip isolated capacitor structure includes: a substrate; a capacitor stack provided on the substrate, the capacitor stack being composed of a plurality of electrode layers and a plurality of dielectric layers alternately stacked in a direction perpendicular to the substrate; for any dielectric layer, the electrode layer located on the upper surface of the dielectric layer, the electrode layer located on the lower surface of the dielectric layer, and the dielectric layer form a capacitor unit; a metal interconnection structure electrically connected to at least two electrode layers in the capacitor stack to electrically connect a plurality of capacitor units.
[0035] The substrate is used to provide mechanical support and electrical isolation for the capacitor stack, and the substrate can be a high-quality silicon wafer. The capacitor stack is used to represent a three-dimensional structure stacked on the substrate by a semiconductor process, and the capacitor stack includes at least one capacitor unit. The semiconductor process used for stacking can be deposition, photolithography or etching. The alternative stacking refers to the stacking of one electrode layer and one dielectric layer in turn to form a plurality of capacitor units in the stack. For the capacitor stack, the top layer is an electrode layer, and the bottom layer is also an electrode layer. Any dielectric layer in the middle and the electrode layers on its upper and lower surfaces together form a capacitor unit. In addition to the electrode layers of the top layer and the bottom layer, any electrode layer located in the middle layer of the capacitor stack belongs to both the upper and lower capacitor units, that is, the electrode layer can be used as the lower electrode layer of the upper capacitor unit and as the upper electrode layer of the lower capacitor unit, and such a shared structure design is conducive to realizing high-density integration. The metal interconnection structure is used to electrically connect the electrode layers in the capacitor stack to electrically connect the individual capacitor units to form a predetermined capacitor network. For example, the metal interconnection structure is used to connect the electrode layers of each odd layer together and the electrode layers of each even layer together to form a parallel capacitor network.
[0036] The on-chip isolation capacitor structure based on a 3D integrated circuit provided by the embodiments of the present application can significantly improve the capacitor density and the capacitor value in a unit chip area by alternately stacking a plurality of electrode layers and dielectric layers in a direction perpendicular to the substrate to form a capacitor stack and electrically connecting the capacitor units by a metal interconnection structure, effectively overcoming the inherent bottleneck of the traditional planar capacitor limited by two-dimensional layout, and being suitable for advanced electronic systems such as miniature sensors and wearable devices with strict requirements for space and performance.
[0037] In some embodiments, the metal interconnection structure includes a conductive via that penetrates one or more dielectric layers of the capacitor stack and is electrically connected to a specified electrode layer to form a parallel, series or mixed connection capacitor network of a plurality of the capacitor units.
[0038] The conductive via is used to electrically connect the electrode layers of different layers of the three-dimensional stack. The conductive via can be a through-silicon via (TSV). The conductive via can be a small hole punched on the dielectric layer by laser or plasma etching, and after depositing an insulating material on the inner wall of the hole, the hole is completely filled with a conductive material. Parallel connection of a plurality of capacitor units can increase the total capacitance while maintaining the withstand voltage. Series connection of a plurality of capacitor units can increase the withstand voltage while reducing the total capacitance. Mixed connection refers to connecting some capacitor units in parallel and then connecting these parallel capacitor units in series to balance the total capacitance and withstand voltage performance. Vertical interconnection of the capacitor units through the conductive via can configure a complex capacitor network according to design requirements.
[0039] In some embodiments, the capacitor stack has 6 electrode layers, forming 5 capacitor units in total, the electrode layer at the top is the first layer electrode layer, and the electrode layer at the bottom is the sixth layer electrode layer. The first, third and fifth layer electrode layers are connected together by conductive vias, and the second, fourth and sixth layer electrode layers are connected together by conductive vias, thereby forming a parallel capacitor network.
[0040] By using conductive vias as vertical interconnection means, the two-dimensional plane restriction is broken, the total capacitance density is improved without increasing the chip footprint by connecting multiple capacitor units in the vertical direction, and the demand for high capacitance of miniaturized devices is met. By selectively connecting different electrode layers through conductive vias, parallel, series or mixed networks can be dynamically configured to meet various application scenarios. Conductive vias provide the shortest vertical transmission path within the chip, greatly reducing signal delay and power consumption. In addition, conductive vias are compatible with standard CMOS processes, eliminating the need for additional packaging or assembly steps, shortening production cycles and reducing production costs.
[0041] In some embodiments, each of the electrode layers uses different electrode materials; and / or, each of the dielectric layers uses different dielectric materials.
[0042] Different dielectric materials have different dielectric constants, voltage withstand capabilities and other characteristics. Selecting different dielectric materials can specifically adjust the capacitance values and voltage withstand capabilities of each capacitor unit, allowing the overall capacitor system to achieve higher total capacitance values in a limited space while meeting the specific needs of insulation and voltage withstand of capacitor units at different layers. Selecting different electrode materials can adapt to the process conditions of capacitor units at different layers, while improving the conductivity and thermal stability of the overall structure. By combining different electrode materials and dielectric materials, the overall performance of the capacitor network can be optimized, achieving performance and functional improvements that cannot be achieved with a single material.
[0043] In some embodiments, low resistivity metals such as copper are selected as electrode materials to reduce interconnection loss and improve frequency characteristics. High dielectric constant materials such as barium titanate are flexibly matched to greatly increase the capacitance density in a limited volume according to the operating voltage and reliability requirements of different capacitor units; high insulation strength materials such as silicon dioxide are used to ensure the voltage withstand and reliability of the capacitor units, ultimately realizing the heterogeneous integration of high density, high performance and high reliability, and meeting the comprehensive index requirements in complex application scenarios.
[0044] In some embodiments, the electrode material of the plurality of electrode layers is aluminum or copper; and the dielectric material of the plurality of dielectric layers is one or more of silicon dioxide, silicon nitride, barium titanate or barium aluminum titanate.
[0045] Aluminum and copper possess excellent conductivity and process compatibility, ensuring efficient conductivity of the electrode layer and compatibility with manufacturing processes such as deposition and etching. They also effectively reduce the parasitic resistance of interconnecting wires, improving the frequency response and charge / discharge efficiency of the capacitor. Silicon dioxide or silicon nitride is used in the dielectric layer to ensure the insulation reliability of the device. Introducing high-dielectric-constant barium titanate or barium aluminotitanate materials in specific layers can significantly increase the capacitance density per unit area, thereby achieving synergistic optimization of high capacitance, low loss, and high reliability in a single structure, overcoming the inherent bottleneck of limited capacitance performance of traditional single materials.
[0046] For some specific implementation methods, please refer to Figure 2 , Figure 2 This is a schematic diagram of the on-chip isolation capacitor structure provided in the embodiments of this application, as shown below. Figure 2 As shown, this 3D integrated circuit has only three parallel capacitor units. A conductor, such as a silicon substrate, exists between the lower electrode layer of the top capacitor unit and the upper electrode layer of the middle capacitor unit. Therefore, an effective capacitor cannot be formed between the lower electrode layer of the top capacitor unit and the upper electrode layer of the middle capacitor unit. Similarly, an effective capacitor cannot be formed between the lower electrode layer of the middle capacitor unit and the upper electrode layer of the bottom capacitor unit. Figure 2 As shown, the bottom capacitor cell consists of a 2-micrometer-thick silicon dioxide dielectric layer and an aluminum electrode. The middle capacitor cell uses a 1.5-micrometer-thick barium titanate dielectric layer and a copper electrode. The top capacitor cell uses a 1-micrometer-thick silicon nitride dielectric layer and an aluminum electrode. Through precise photolithography and etching processes, the metal interconnect structure allows each capacitor cell to be correctly connected to other circuit components. Assume the capacitance of a single-layer capacitor cell is C_single, and its withstand voltage is BV_single. When the three layers of capacitor cells are connected in parallel, the total capacitance is 3 × C_single, and the total withstand voltage is BV_single / 3.
[0047] In some embodiments, an insulating layer is provided between the capacitor stack and the substrate; the upper surface of the insulating layer is provided with the bottom electrode layer of the capacitor stack.
[0048] By placing an insulating layer between the capacitor stack and the substrate, electrical isolation between the capacitor stack and the substrate is achieved, ensuring the independence and stability of charge storage in each capacitor unit and guaranteeing the reliability of the isolation capacitor in highly integrated 3D integrated circuits. The insulating layer can be silicon dioxide; for example, a layer of silicon dioxide can be formed on the substrate through thermal growth or deposition. Depositing the bottom electrode layer of the capacitor stack on the upper surface of the silicon dioxide can achieve good adhesion and low contact resistance, laying the foundation for subsequent high-quality thin film stacking.
[0049] In some embodiments, in the capacitor stack, the number of electrode layers is one more than the number of dielectric layers.
[0050] In the capacitor stack, each of the intermediate electrode layers functions as the electrode plate of both the upper and lower capacitor units, i.e. it is the lower electrode of the upper capacitor unit and the upper electrode of the lower capacitor unit. With each additional dielectric layer, one complete capacitor unit is formed by adding one electrode layer. Therefore, the number of electrode layers is one more than the number of dielectric layers. By sharing the intermediate electrode layers, the capacitor density is maximized while the vertical space is minimized, providing an optimal stack configuration for high-density three-dimensional integration, overcoming the dependence on chip area of traditional planar capacitors.
[0051] In some embodiments, the metal interconnection structure electrically interconnects all the odd-numbered electrode layers and all the even-numbered electrode layers respectively, to form a parallel capacitor network.
[0052] In some embodiments, the metal interconnection structure electrically interconnects all the odd-numbered electrode layers and all the even-numbered electrode layers respectively, to form a parallel capacitor network.
[0053] In some embodiments, the metal interconnection structure electrically interconnects all the odd-numbered electrode layers and all the even-numbered electrode layers respectively, to form a parallel capacitor network.
[0054] In some embodiments, in the capacitor stack, at least one of the dielectric layers is made of high dielectric constant material.
[0055] By using high dielectric constant materials such as barium titanate, silicon nitride and barium aluminum titanate at specific layers of the stack, the capacitance of the capacitor unit at that layer can be increased without increasing the number of layers or the volume, thereby breaking through the performance limitations of a single material system and optimizing the overall performance of the capacitor network.
[0056] In some specific embodiments, high-breakdown-strength silicon dioxide is used in the dielectric layer close to the substrate to withstand higher voltage, ensuring the reliability of the capacitor. High dielectric constant materials are used in the upper layers to provide higher capacitance. This "hybrid stack" strategy can simultaneously achieve high voltage resistance and large capacitance, achieving comprehensive performance that cannot be achieved by a single material.
[0057] Please refer to Figure 3 ,Figure 3 A flow chart of a manufacturing method of the on-chip isolation capacitor structure based on 3D integrated circuits is provided in the embodiments of the present application, as shown in Figure 3 The method comprises: providing a substrate; stacking a plurality of electrode layers and a plurality of dielectric layers alternately on the substrate in a direction perpendicular to the substrate to form a capacitor stack; wherein for any dielectric layer, the electrode layer on the upper surface of the dielectric layer and the electrode layer on the lower surface of the dielectric layer form a capacitor unit with the dielectric layer; and forming a metal interconnection structure electrically connected to at least two electrode layers in the capacitor stack to electrically connect a plurality of capacitor units.
[0058] By stacking electrode layers and dielectric layers alternately to form a three-dimensional capacitor stack and using metal interconnections to realize electrical connection between layers, the capacitance density and integration are greatly improved on a unit area of a chip, and the demand for high capacitance of miniaturized electronic devices is met. By selectively connecting different electrode layers, parallel, series or mixed networks can be flexibly configured, while diversified performance requirements such as high capacitance, high voltage resistance and specific frequency response are considered. The entire process is fully compatible with standard CMOS processes, and no additional packaging steps are required, realizing high-reliability, low-cost and high-performance on-chip passive device manufacturing.
[0059] In some embodiments, the forming of the metal interconnection structure comprises: forming a conductive via through one or more dielectric layers of the capacitor stack; and electrically connecting the conductive via to a specified electrode layer, so that a plurality of capacitor units form a parallel, series or mixed connection capacitor network.
[0060] By preparing a conductive via in a dielectric layer and accurately connecting a specified electrode, the physical limitations of two-dimensional interconnection are broken, the signal transmission path is shortened by using vertical interconnection, the parasitic inductance and resistance are reduced, and the high-frequency response speed and energy efficiency of the capacitor network are improved. By connecting a specified electrode layer through a conductive via, a parallel, series or mixed capacitor network can be configured on the same physical structure to meet diversified application scenarios. The process is fully compatible with standard CMOS processes, and no additional packaging steps are required, so that the three-dimensional capacitor stack can be directly manufactured with transistors and other active devices, providing a high-reliability, high-performance on-chip passive integration solution for advanced microelectronic systems.
[0061] In some embodiments, the thickness of each dielectric layer is accurately controlled according to application requirements to ensure that each capacitor unit can reach the corresponding target capacitance value. The design requirement of the embodiments of the present application is to isolate voltages below 300V, and therefore the dielectric layer does not need to be too thick. Taking silicon dioxide as an example, only 2 microns are needed to meet the voltage resistance requirement of about 1000V.
[0062] In some embodiments, the method for manufacturing a 3D integrated circuit-based on-chip isolation capacitor structure specifically includes the following steps:
[0063] (1) Wafer preparation and oxidation treatment: Select a high-quality silicon wafer and perform oxidation treatment on its surface to grow a silicon dioxide dielectric layer.
[0064] (2) Capacitor electrode deposition: Deposit a metal electrode on the silicon dioxide dielectric layer through physical vapor deposition (PVD) or chemical vapor deposition (CVD) technology.
[0065] (3) Photolithography and pattern transfer: Use photolithography technology to transfer the capacitor pattern to the electrode layer, and remove the excess metal part through dry etching or wet etching to form the capacitor electrode.
[0066] (4) Multi-layer stacking and interconnection: According to the design requirements, alternately stack multiple electrode layers and multiple dielectric layers through a 3D stacking process, and perform metal interconnection between the electrode layers to form a complete capacitor stack.
[0067] (5) Packaging and testing: After completing the capacitor manufacturing, perform chip packaging through traditional packaging technology and perform electrical performance testing to ensure that the capacitance, leakage current, voltage resistance and other performances meet the design requirements.
[0068] Among them, alternately stacking multiple electrode layers and multiple dielectric layers through a 3D stacking process includes: Figure 4 , Figure 4 The schematic diagram of the on-chip isolation capacitor structure provided by the embodiments of the present application is shown in Figure 4 , a deep groove is opened below the even-numbered electrode layer and filled with other dielectric materials to form an intermediate layer, and the material of the intermediate layer includes silicon oxide, single crystal silicon, passivation material, plastic encapsulation material, etc. As shown in Figure 4 , the dielectric layer of the capacitor is formed through the intermediate layer, so that 5-layer capacitor units are realized in the 3D integrated circuit, i.e. effective capacitor units are formed between electrode layers 1-2, 2-3, 3-4, 4-5 and 5-6. When the even-numbered and odd-numbered electrode plates are connected in parallel, 5 parallel capacitor units are formed between electrode layers 1-2, 2-3, 3-4, 4-5 and 5-6, and the total capacitance value is the sum of the 5 capacitor units.
[0069] Although the embodiments of the present application are described in conjunction with the accompanying drawings, various modifications and variations can be made by those skilled in the art without departing from the spirit and scope of the present application, and such modifications and variations fall within the scope defined by the appended claims.
[0070] It should also be noted that the terms "comprising," "including," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises a... " does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the recited element.
[0071] Each of the embodiments in the present specification is described in a progressive manner, and the same or similar parts between the embodiments can be mutually referred to. Each of the embodiments focuses on the difference from other embodiments. In particular, for the glass packaging substrate embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the part of the glass packaging substrate preparation method embodiments.
[0072] The above only describes the embodiments of the present application and is not intended to limit the present application. The present application can have various modifications and changes for those skilled in the art. Any modification, equivalent replacement, improvement, etc. within the spirit and principle of the present application shall be included in the scope of the claims of the present application.
[0073] Although the embodiments of the present application are described in conjunction with the drawings, various modifications and changes can be made by those skilled in the art without departing from the spirit and scope of the present application, and such modifications and changes fall within the scope defined by the appended claims.
Claims
1. A 3D integrated circuit based on-chip isolation capacitor structure, characterized in that, The method comprises: providing a substrate; stacking a plurality of electrode layers and a plurality of dielectric layers alternately in a direction perpendicular to the substrate on the substrate to form a capacitor stack; wherein for any dielectric layer, the electrode layer on the upper surface of the dielectric layer and the electrode layer on the lower surface of the dielectric layer and the dielectric layer form a capacitor unit; forming a metal interconnection structure electrically connected to at least two electrode layers in the capacitor stack to electrically connect a plurality of capacitor units.
2. The on-chip isolation capacitor structure of claim 1, wherein, The metal interconnection structure comprises a conductive via which penetrates one or more dielectric layers of the capacitor stack and is electrically connected to a specified electrode layer, so that a plurality of capacitor units form a parallel, series or mixed connection capacitor network.
3. The on-chip isolation capacitance structure according to claim 1 or 2, wherein, Each of the electrode layers uses different electrode materials; and / or, each of the dielectric layers uses different dielectric materials.
4. The on-chip isolation capacitor structure of claim 1, wherein, The electrode materials of the plurality of electrode layers are aluminum or copper; and the dielectric materials of the plurality of dielectric layers are one or more of silicon dioxide, silicon nitride, barium titanate or barium aluminum titanate.
5. The on-chip isolation capacitor structure of claim 1, wherein, An insulating layer is provided between the capacitor stack and the substrate; the upper surface of the insulating layer is provided with the bottommost electrode layer in the capacitor stack.
6. The on-chip isolation capacitor structure of claim 5, wherein, In the capacitor stack, the number of electrode layers is one more than the number of dielectric layers.
7. The on-chip isolation capacitor structure of claim 6, wherein, The metal interconnection structure electrically interconnects all odd-numbered electrode layers and all even-numbered electrode layers respectively to form a parallel capacitor network.
8. The on-chip isolation capacitor structure of claim 1, wherein, In the capacitor stack, at least one of the dielectric layers uses a high dielectric constant material.
9. A method of fabricating an on-chip isolation capacitor structure based on 3D integrated circuits, the method comprising: The method comprises: providing a substrate; stacking a plurality of electrode layers and a plurality of dielectric layers alternately in a direction perpendicular to the substrate on the substrate to form a capacitor stack; wherein for any dielectric layer, the electrode layer on the upper surface of the dielectric layer and the electrode layer on the lower surface of the dielectric layer and the dielectric layer form a capacitor unit; forming a metal interconnection structure electrically connected to at least two electrode layers in the capacitor stack to electrically connect a plurality of capacitor units.
10. The method of claim 9, wherein, The method comprises: forming a conductive via in one or more dielectric layers of the capacitor stack; electrically connecting the conductive via to a specified electrode layer, so that a plurality of capacitor units form a parallel, series or mixed connection capacitor network.