Instruction scheduling method and device, electronic equipment, storage medium and computer program product

Abstract

The invention discloses an instruction scheduling method and device, electronic equipment, a storage medium and a computer program product, and belongs to the technical field of compiler optimizing.The method comprises the steps that a plurality of instruction groups included in a basic block and the cycle number of each instruction group are obtained, and the instruction groups are scheduled based on the cycle number of each instruction group and the register dependency relationship between instructions in different instruction groups; determining the period of each instruction group in a ready state, determining an instruction group set which is in a ready state in the ith period and is not scheduled, selecting a target instruction group scheduled in the ith period from the instruction group set according to a rule that the chip can execute the instruction groups in parallel after scheduling, updating i to i + N, and executing the step of determining the instruction group set which is in a ready state and is not scheduled in the ith cycle until the scheduling is finished, N being the cycle number of the target instruction group. Therefore, the instruction parallelism degree can be improved on the premise of not changing the code semantics of the basic blocks, the instruction scheduling mode is more reasonable, and the computing performance of a chip can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of compiler optimization, and in particular to an instruction scheduling method and device, an electronic device, a storage medium, and a computer program product. BACKGROUND

[0002] Generally, after a developer develops a program of a computing function, the program can be compiled by means of a compiler to obtain a plurality of basic blocks, each of which can include a plurality of instruction groups, and each of the instruction groups can include at least one instruction. Then, the instructions in the plurality of basic blocks are loaded onto a chip, and the corresponding computation can be performed by using the chip. Since whether the instruction scheduling manner of each basic block is reasonable is closely related to the computing performance of the chip, it is necessary to study how to schedule the instructions in the basic blocks. SUMMARY

[0003] Embodiments of the present application provide an instruction scheduling method and device, an electronic device, a storage medium, and a computer program product, to optimize the instruction scheduling manner of a basic block, thereby improving the computing performance of a chip.

[0004] In a first aspect, an embodiment of the present application provides an instruction scheduling method, comprising: obtaining instruction information of a basic block, wherein the instructions in the basic block are to be executed on a chip, the instruction information comprises a plurality of instruction groups in the basic block and a corresponding cycle number of each instruction group, and each instruction group comprises at least one instruction; determining a cycle in which each instruction group is in a ready state based on the corresponding cycle number of each instruction group and a register dependency relationship between instructions in different instruction groups; determining a set of instruction groups that are in the ready state and have not been scheduled at an i-th cycle, wherein i is a preset value initially; selecting a target instruction group to be scheduled at the i-th cycle from the set of instruction groups according to a rule that the chip can execute instruction groups in parallel after scheduling, and updating i to i+N, wherein N is the corresponding cycle number of the target instruction group; performing the step of determining the set of instruction groups that are in the ready state and have not been scheduled at the i-th cycle until the plurality of instruction groups are all scheduled, and ending the instruction scheduling.

[0005] In a second aspect, an embodiment of the present application provides an instruction scheduling device, comprising: an obtaining module configured to obtain instruction information of a basic block, wherein the instructions in the basic block are to be executed on a chip, the instruction information comprises a plurality of instruction groups in the basic block and a corresponding cycle number of each instruction group, and each instruction group comprises at least one instruction; The determining module is configured to determine, based on the number of periods corresponding to each instruction group and the register dependency between instructions in different instruction groups, a period in which each instruction group is in a ready state; The processing module is configured to determine a set of instruction groups in a ready state and not scheduled at the i th period, where i is a preset value initially; select a target instruction group scheduled at the i th period from the set of instruction groups according to a rule that the chip can execute instruction groups in parallel after scheduling, and update i to i+N, where N is the number of periods corresponding to the target instruction group; and perform the step of determining a set of instruction groups in a ready state and not scheduled at the i th period until the plurality of instruction groups are all scheduled, and end the instruction scheduling.

[0006] In a third aspect, an embodiment of the present application provides an electronic device, including at least one processor, and a memory connected to the at least one processor in communication, wherein: The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor to enable the at least one processor to perform any of the above instruction scheduling methods.

[0007] In a fourth aspect, an embodiment of the present application provides a storage medium, when a computer program in the storage medium is executed by a processor of an electronic device, the electronic device can perform any of the above instruction scheduling methods.

[0008] In a fifth aspect, an embodiment of the present application provides a computer program product, including a computer program, and the computer program is executed by a processor to implement any of the above instruction scheduling methods.

[0009] In this embodiment, instruction information of a basic block is obtained. The instructions in the basic block are to be executed on the chip. The instruction information includes multiple instruction groups and the number of cycles corresponding to each instruction group. Each instruction group includes at least one instruction. Based on the number of cycles corresponding to each instruction group and the register dependencies between instructions in different instruction groups, the number of cycles in which each instruction group is in a ready state is determined, that is, the number of cycles that each instruction group can be scheduled. The set of instruction groups that are in a ready state and have not been scheduled in the i-th cycle is determined. According to the rule that the chip can execute instruction groups in parallel after scheduling, the target instruction group to be scheduled in the i-th cycle is selected from the set of instruction groups. i is updated to i+N. The step of determining the set of instruction groups that are in a ready state and have not been scheduled in the i-th cycle is re-executed until multiple instruction groups are scheduled and the instruction scheduling ends. Initially, i is a preset value such as 0, and N is the number of cycles corresponding to the target instruction group. In this way, by leveraging the register dependencies between instructions in different instruction groups, the schedulable cycles for each instruction group are determined. In each cycle, the target instruction group to be scheduled is selected from the schedulable instruction groups of that cycle according to the rules that the chip can execute instruction groups in parallel after scheduling. It tends to unlock instruction groups that can be parallelized, which can improve instruction parallelism while ensuring that the code semantics of the basic blocks remain unchanged before and after scheduling. The scheduling method is more reasonable and can improve the chip's computing performance. Attached Figure Description

[0010] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments of this application and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 An application scenario diagram provided for an embodiment of this application; Figure 2 A flowchart of an instruction scheduling method provided in an embodiment of this application; Figure 3 A flowchart illustrating a cycle for determining the ready state of each instruction group, provided as an embodiment of this application; Figure 4 An instruction dependency graph of a basic block provided in an embodiment of this application; Figure 5 A flowchart for determining a target instruction group to be scheduled in the i-th cycle is provided as an embodiment of this application; Figure 6 This is a schematic diagram of the structure of an instruction scheduling device provided in an embodiment of this application; Figure 7 This is a schematic diagram of the hardware structure of an electronic device for implementing an instruction scheduling method, provided as an embodiment of this application. Detailed Implementation

[0011] To optimize the instruction scheduling of basic blocks and thereby improve the computing performance of chips, embodiments of this application provide an instruction scheduling method, apparatus, electronic device, storage medium, and computer program product.

[0012] The preferred embodiments of this application are described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit this application. Furthermore, the embodiments and features in the embodiments of this application can be combined with each other without conflict.

[0013] For ease of understanding, the technical terms used in this application are as follows: 1. Basic blocks.

[0014] Basic blocks are a core concept in compiler design, program analysis, and processor microarchitecture, used to divide a program's instruction sequence into well-structured, easily analyzed, and optimized units.

[0015] A basic block consists of a continuous sequence of instructions that satisfies the following three conditions: (1) There is only one entry point: execution can only start from the first instruction of a basic block and cannot jump in from the middle.

[0016] (2) There is only one exit point. All instructions must be executed sequentially during execution and cannot be exited in the middle.

[0017] (3) Once the first instruction is executed, all subsequent instructions will be executed once and only once in sequence.

[0018] The instruction scheduling method in this application embodiment is mainly used in the back-end optimization stage of the compiler. It reduces pipeline pauses and improves instruction-level parallelism by reordering the instructions in the basic block, thereby improving the execution efficiency of the program on the chip.

[0019] 2. Instruction group, and the number of cycles corresponding to the instruction group.

[0020] Generally, if an instruction group contains only one instruction, then the instruction group is a single instruction, such as an instruction to calculate a+b or an instruction to write data to a register. If an instruction group contains at least two instructions, then the instruction group is a set of instructions, such as a matrix multiplication instruction. Typically, a set of instructions includes a main instruction and a configuration instruction for the main instruction.

[0021] The number of cycles corresponding to an instruction set refers to the number of cycles required for a chip to execute an instruction set, which can characterize the execution complexity of the instruction.

[0022] To more clearly illustrate the methods of the embodiments of this application, the application scenarios of the embodiments of this application will be introduced below.

[0023] SeeFigure 1 , Figure 1 This application provides an example of an application scenario diagram, including an electronic device and a chip. The electronic device, such as a desktop computer, laptop computer, or server, can install a compiler; the chip can be a graphics processing unit (GPU), a general-purpose computing on graphics processing units (GPGPU), a tensor processing unit (TPU), a domain-specific architecture (DSA), or other parallel computing processors.

[0024] Generally, after developers complete a program for computing functions, they can compile the program using a compiler in an electronic device to obtain multiple basic blocks. Each basic block can contain multiple instruction sets, and each instruction set can contain at least one instruction. Then, the instructions from the multiple basic blocks are loaded onto a chip, allowing the chip to perform calculations. Since the rationality of the instruction scheduling method for each basic block is closely related to the chip's computing performance, it is necessary to study how to schedule the instructions within the basic blocks.

[0025] After introducing the application scenarios of the embodiments of this application, the instruction scheduling method in the embodiments of this application will be described below with specific examples.

[0026] See Figure 2 , Figure 2 A flowchart of an instruction scheduling method provided in an embodiment of this application is shown. This method is applied to... Figure 1 In an electronic device, the method includes the following steps.

[0027] In step 201, the instruction information of the basic block is obtained. The instructions in the basic block are to be executed on the chip. The instruction information includes multiple instruction groups and the cycle number corresponding to each instruction group. Each instruction group includes at least one instruction.

[0028] When an instruction group contains one instruction, the cycle count for that instruction group is the number of cycles required for the chip to execute that instruction; when an instruction group contains at least two instructions, the cycle count for that instruction group is the number of cycles required for the chip to execute those at least two instructions.

[0029] In step 202, the number of cycles corresponding to each instruction group and the register dependencies between instructions in different instruction groups are used to determine the cycle in which each instruction group is in the ready state.

[0030] The register dependencies between instructions in different instruction groups can include direct register dependencies and indirect register dependencies. That is, in this embodiment, both direct and indirect register dependencies between instructions in different instruction groups are analyzed. This allows for a thorough exploration of the register dependencies between instructions in different instruction groups, and a complete understanding of register dependencies is crucial to ensuring that the semantics of instructions in a basic block are semantically equivalent to the original code after rescheduling.

[0031] In addition, considering that when an instruction set computes a vector, the instruction set only shows the register corresponding to the first element of the vector and the number of elements in the vector, if register dependency analysis is performed only based on the register corresponding to the first element of the instruction set, register dependencies will be missed.

[0032] Therefore, when an instruction set computes a vector, the register dependencies between this instruction set and instructions in other instruction sets can be analyzed based on all the registers corresponding to the vector. Here, all the registers corresponding to the vector are the register corresponding to the first element of the vector, and the M registers that are adjacent to this register in terms of address, where M is the number of elements in the vector.

[0033] It should be noted that in this embodiment, the matrix is ​​treated as a special type of vector. That is, the register dependency analysis is also performed on the matrix in the manner described above.

[0034] In practical applications, the period during which each instruction group is in the ready state is the same as the period during which each instruction group can be scheduled. Figure 3 A flowchart for determining the cycle in which each instruction group is in a ready state, provided for embodiments of this application, includes the following steps.

[0035] In step 2021, an instruction dependency graph of basic blocks is generated, with each instruction group as a vertex and the register dependencies between instructions in different instruction groups as edges.

[0036] Assume a basic block consists of 3 instruction groups, each containing only one instruction: Instruction group 1: Calculate c = a + b; Instruction group 2: Calculate d=2c; Instruction group 3: Calculate f=2e.

[0037] Then, the instruction dependency graph of the basic block is as follows: Figure 4 As shown, ① represents instruction group 1, ② represents instruction group 2, and ③ represents instruction group 3. There is a direct register dependency between the instructions in instruction group 1 and instruction group 2. Therefore, ① and ② are connected by an arrow.

[0038] In step 2022, based on the number of cycles corresponding to each instruction group, the instruction groups in the instruction dependency graph are traversed in a forward direction to obtain the earliest cycle in which each instruction group is in a ready state.

[0039] The earliest cycle in which each instruction group is in the ready state is the earliest cycle in which each instruction group is in the ready state (i.e., the earliest schedulable cycle). Forward traversal is done according to... Figure 4 Traverse in the direction indicated by the middle arrow.

[0040] Assume that the cycle number corresponding to instruction group 1 is 3, the cycle number corresponding to instruction group 2 is 2, and the cycle number corresponding to instruction group 3 is 2.

[0041] Therefore, the earliest cycle in which instruction group 1 is ready is cycle 0. Instruction group 2 can only be executed after instruction group 1 completes (from cycle 0 to cycle 2). Thus, the earliest cycle in which instruction group 2 is ready is cycle 3. Instruction group 3 has no register dependency with other instruction groups. Therefore, the earliest cycle in which instruction group 3 is ready is cycle 0.

[0042] In step 2023, based on the number of cycles of each data processing instruction, the instruction groups in the instruction dependency graph are traversed in reverse to obtain the latest cycle in which each instruction group is in the ready state.

[0043] The latest cycle in which each instruction group is in the ready state is the latest cycle in which each instruction group is in the ready state (i.e., the latest schedulable cycle). Reverse traversal is done according to... Figure 4 The middle arrow indicates the reverse traversal.

[0044] Let's still assume that the cycle number corresponding to instruction group 1 is 3, the cycle number corresponding to instruction group 2 is 2, and the cycle number corresponding to instruction group 3 is 2.

[0045] Since instruction group 1 is the first instruction group, the latest cycle for it to be in the ready state is cycle 0. Instruction group 2 can only be executed after instruction group 1 is completed (from cycle 0 to cycle 2). Therefore, the latest cycle for instruction group 2 to be in the ready state is cycle 3. Instruction group 3 has no register dependency with other instruction groups. Therefore, the latest cycle for instruction group 3 to be in the ready state is cycle 5 (when both instruction group 1 and instruction group 2 have been executed).

[0046] In step 203, the set of instruction groups that are in the ready state and have not been scheduled in the i-th cycle is determined, and i is initially a preset value.

[0047] The preset values ​​are, for example, 0 or 1.

[0048] In step 204, according to the rule that the chip can execute instruction groups in parallel after scheduling, the target instruction group to be scheduled in the i-th cycle is selected from the instruction group set.

[0049] In some embodiments, if the instruction set includes only one instruction group, then this instruction group can be used as the target instruction group for scheduling in the i-th cycle.

[0050] In some embodiments, the instruction set includes at least two instruction sets, which can be determined according to... Figure 5 The process shown determines the target instruction group to be scheduled in the i-th cycle, and the process includes the following steps.

[0051] In step 2041, the reference instruction for each instruction group is determined based on the number of instructions contained in each instruction group.

[0052] For example, if an instruction group contains at least two instructions (usually a main instruction and a configuration instruction for the main instruction), then the main instruction among these at least two instructions can be determined as the reference instruction of the instruction group; if an instruction group contains one instruction, then that instruction can be determined as the reference instruction of the instruction group.

[0053] In step 2042, the scheduling priority score of the instruction group is determined based on the parallel execution characterization information of the reference instruction.

[0054] In some embodiments, the parallel execution characterization information of the reference instruction may include the earliest and latest cycles in which the reference instruction is in a ready state, and the preset access latency of the reference instruction. Furthermore, the scheduling priority of the instruction group corresponding to the reference instruction can be analyzed from at least one of the following dimensions.

[0055] Dimension 1: Whether the reference instruction is located on the critical path of the instruction dependency graph.

[0056] In practical applications, if the earliest and latest cycles of a reference instruction in the ready state are the same, it indicates that the corresponding instruction group is located on the critical path of the instruction dependency graph. If the earliest and latest cycles of a reference instruction in the ready state are different, it indicates that the corresponding instruction group is not located on the critical path of the instruction dependency graph. Instruction groups located on the critical path are more important and can be scheduled with priority compared to instruction groups not located on the critical path. Therefore, if a reference instruction is located on the critical path of the instruction dependency graph, the critical path score of the corresponding instruction group can be determined to be a set value, such as 1000. This helps to improve the scheduling priority of instruction groups located on the critical path of the instruction dependency graph.

[0057] Dimension 2, the relaxation of reference instructions.

[0058] In practical applications, the larger the absolute value of the difference between the earliest and latest cycles of a reference instruction in the ready state, the smaller the slack of the corresponding instruction group; conversely, the smaller the absolute value of the difference, the larger the slack of the corresponding instruction group. Therefore, the slack score of an instruction group can be determined according to the rule that the absolute value of the difference between the earliest and latest cycles of a reference instruction in the ready state is negatively correlated with the slack score of the corresponding instruction group. For example, the slack score of an instruction group = -|earliest cycle of the reference instruction in the ready state - latest cycle of the reference instruction in the ready state|. Another example is that the slack score of an instruction group = 1 / |earliest cycle of the reference instruction in the ready state - latest cycle of the reference instruction in the ready state|. This facilitates increasing the scheduling priority of instruction groups with large slack and decreasing the scheduling priority of instruction groups with small slack.

[0059] In addition, to amplify the impact of the relaxation score, it can be magnified. For example, the relaxation score of an instruction group = -|earliest period when the reference instruction is ready - latest period when the reference instruction is ready| × a preset multiple, such as 10.

[0060] Dimension 3: Delayed access to reference instructions.

[0061] For example, the instruction delay score of an instruction group can be determined according to the rule that the preset access delay of the reference instruction is positively correlated with the instruction delay score. This helps to increase the scheduling priority of the instruction group to which the reference instruction with the longer preset access delay belongs.

[0062] In some embodiments, the preset access latency of a reference instruction can be determined based on the register type and operand type corresponding to the reference instruction. Register types include, for example, Thread Local Registers (TLRs), Warp Scalar Registers (WSRs), Warp Element Registers (WERs), Address Registers (ADRs), Constant Global Registers (CGRs), Mask Registers (MKRs), Indirect Thread Local Registers (ITLRs), Indirect Warp Scalar Registers (IWSRs), and Indirect Control and Status Registers (ICSRs). Operand types include, for example, a single data item or a vector. See Table 1, which shows the direct register access latency for different register types when the operand type of a reference instruction provided in this application is a single data item.

[0063] Table 1

[0064] In this way, considering the differences in direct register access latency corresponding to different register types, it is beneficial to prioritize scheduling instruction groups with long access latency, which not only helps to reduce the situation where high access latency instructions block subsequent instruction groups, but also helps to improve instruction parallelism.

[0065] It should be noted that for any register type, direct register access latency is greater when the operation through the corresponding register is a vector. Furthermore, Table 1 shows the latency of direct register access; indirect register access latency is even greater (typically more than 6 cycles). Specifically, indirect register access includes: ITLR→A1: indirect TLR access depends on address register A1; IWSR→A2: indirect WSR access depends on address register A2; ICSR→A0: indirect CSR access depends on address register A0.

[0066] In practical applications, the instruction latency score of an instruction group can be amplified based on the total number of instructions in the basic block (which reflects the size of the basic block). The amplification factor can be positively correlated with the total number of instructions in the basic block. For example, the amplification factor is 4 when the total number of instructions in the basic block exceeds 50, 3 when the total number of instructions in the basic block exceeds 20 but does not exceed 50, and 2 when the total number of instructions in the basic block exceeds 20.

[0067] In this way, by adjusting the influence of instruction delay score on scheduling priority of instruction group according to the size of basic block, the scheduling order of instruction group can be better matched with the size of basic block, and the scheduling method can be more reasonable.

[0068] Then, the scheduling priority score of the instruction group can be determined based on at least one of the critical path score, slackness score, and instruction latency score. An example is given below.

[0069] Case 1: Determine the scheduling priority score of the instruction group based on any one of the critical path score, slackness score, and instruction delay score.

[0070] Taking the determination of the scheduling priority score of an instruction group based on its critical path score as an example, the scheduling priority score of an instruction group can be calculated as follows: The critical path score of an instruction group = critical path score × critical path weight, where the critical path weight can be predetermined.

[0071] Taking the determination of the scheduling priority score of an instruction group based on its slackness score as an example, the scheduling priority score of an instruction group can be calculated as follows: Instruction group scheduling priority score = instruction group slackness score × slackness weight, where the slackness weight can be predetermined.

[0072] Taking the determination of the scheduling priority score of an instruction group based on its instruction latency score as an example, the scheduling priority score of an instruction group can be calculated as follows: Instruction latency score of instruction group = instruction latency score of instruction group × latency weight, where the latency weight can be predetermined.

[0073] Case 2: Determine the scheduling priority score of the instruction group based on any two of the critical path score, slackness score, and instruction delay score.

[0074] Taking the determination of the scheduling priority score of an instruction group based on its critical path score and slackness score as an example, the scheduling priority score of an instruction group can be calculated as follows: Instruction group scheduling priority score = instruction group critical path score × critical path weight + instruction group slackness score × slackness weight.

[0075] Taking the determination of the scheduling priority score of an instruction group based on its critical path score and instruction latency score as an example, the scheduling priority score of an instruction group can be calculated as follows: Instruction group scheduling priority score = instruction group critical path score × critical path weight + instruction group instruction latency score × latency weight.

[0076] Taking the determination of the scheduling priority score of an instruction group based on its slackness score and instruction latency score as an example, the scheduling priority score of an instruction group can be calculated as follows: Instruction group scheduling priority score = instruction group slackness score × slackness weight + instruction group instruction latency score × latency weight.

[0077] Case 3: Determine the scheduling priority score of the instruction group based on the critical path score, slackness score, and instruction delay score.

[0078] For example, the scheduling priority score of an instruction group = critical path score × critical path weight + slackness score × slackness weight + instruction delay score × delay weight.

[0079] In some embodiments, the parallel execution characterization information of the reference instruction may further include the number of instructions that depend on the reference instruction, the number of instructions that depend on the reference instruction and are in a ready state, and the resource consumption of the reference instruction (such as the computation time consumed, the computational resources consumed, etc.). Furthermore, the scheduling priority of the instruction group corresponding to the reference instruction can be analyzed from at least one of the following dimensions.

[0080] Dimension 4: Readiness of reference instructions.

[0081] In practice, the readiness score of an instruction group can be determined according to the rule that the earliest period in which the reference instruction is in a ready state is negatively correlated with the readiness score. For example, the readiness score of an instruction group = - the earliest period in which the reference instruction is in a ready state.

[0082] Dimension 5: Fan-out of reference instructions (i.e., the number of instructions that depend on reference instructions).

[0083] In practice, the fan-out score of an instruction group can be determined according to the rule that the number of instructions that depend on the reference instruction is positively correlated with the fan-out score. For example, the fan-out score of an instruction group = the number of instructions that depend on the reference instruction.

[0084] It should be noted that when the reference instruction is the main instruction in an instruction group, the number of instructions that depend on the reference instruction is the total number of instructions that depend on all instructions in the instruction group.

[0085] Dimension 6: The readiness of the reference instruction (i.e., the number of instructions that depend on the reference instruction and are in a ready state).

[0086] In practice, the successor readiness score of an instruction group can be determined according to the rule that the number of instructions that depend on the reference instruction and are in a ready state is positively correlated with the successor readiness score. For example, the successor readiness score of an instruction group = the number of instructions that depend on the reference instruction and are in a ready state × the amplification factor, where the amplification factor is, for example, 2.

[0087] Similarly, when the reference instruction is the main instruction in an instruction group, the number of instructions that depend on the reference instruction and are ready refers to the number of instructions that depend on all instructions in the instruction group and are ready.

[0088] Dimension 7: Resource pressure situation of reference instructions.

[0089] Considering that the execution results of instruction groups with high resource consumption may be used by other instruction groups, prioritizing the scheduling of instruction groups with high resource consumption will allow other instruction groups to be scheduled as soon as possible. This helps to avoid situations where some execution units in the chip are overloaded while other execution units are idle.

[0090] Therefore, the resource pressure score of an instruction group can be determined according to the rule that the resource consumption of the reference instruction is positively correlated with the resource pressure score. For example, the resource pressure score of an instruction group = the resource consumption of the reference instruction.

[0091] The resource consumption of the reference instructions can be predetermined. For example, the resource consumption of the General Matrix Multiplication (GEMM) instruction is 6.0, the resource consumption of the Texture Fetch (TEX) instruction is 5.5, the resource consumption of the Arithmetic Logic Unit (ALU) instruction is 6.0, and the resource consumption of the Move (MOV) instruction is 6.0.

[0092] Then, the scheduling priority score of the instruction group can be determined based on at least one of the following: critical path score, slackness score, instruction latency score, instruction group readiness score, fan-out score, successor readiness score, and resource pressure score.

[0093] When determining the scheduling priority score of an instruction group based on one of its scores (critical path score, relaxation score, instruction latency score, instruction group readiness score, fan-out score, successor readiness score, or resource pressure score), the product of this score and a preset factor can be used as the scheduling priority score of the instruction group. The preset factor can be predetermined, and different scores can correspond to the same or different preset factors.

[0094] When determining the scheduling priority score of an instruction group based on at least two of the following scores (critical path score, slackness score, instruction latency score, instruction group readiness score, fan-out score, successor readiness score, and resource pressure score), the weighted sum of these at least two scores can be used as the scheduling priority score of the instruction group. The weight of each score can be predetermined.

[0095] Furthermore, when the scheduling priority score of an instruction group equals the critical path score × critical path weight + slackness score × slackness weight + readiness score × readiness weight + fan-out score × fan-out weight + successor readiness score × successor readiness weight + instruction latency score × latency weight + resource pressure score × resource pressure weight, the critical path weight, slackness weight, readiness weight, fan-out weight, successor readiness weight, latency weight, and resource pressure weight decrease sequentially. Each weight can be preset. This approach considers a comprehensive range of factors, with different weights for each, which helps improve the rationality of instruction scheduling.

[0096] In step 2043, the instruction group with the highest scheduling priority score is selected from each instruction group as the target instruction group to be scheduled in the i-th cycle.

[0097] It should be noted that an instruction group is scheduled within the same cycle, and instructions cannot be inserted into an instruction group, nor can instructions be deleted from an instruction group.

[0098] In step 205, it is determined whether there is an unscheduled instruction group among the multiple instruction groups. If yes, proceed to step 206; otherwise, proceed to step 207.

[0099] In step 206, i is updated to i+N, where N is the cycle number corresponding to the target instruction group, and the process returns to step 203.

[0100] That is, the scheduling cycle is advanced to the (i+N)th cycle.

[0101] In step 207, instruction scheduling ends.

[0102] In some embodiments, the instruction information of the basic block may also include comment instructions in the basic block. If the comment instruction indicates the start of commenting, the comment instruction and the next instruction group adjacent to the comment instruction can be scheduled together, that is, the comment instruction and the next instruction group adjacent to the comment instruction can be scheduled in the same cycle. If the comment instruction indicates the end of commenting, the comment instruction and the previous instruction group adjacent to the comment instruction can be scheduled together, that is, the comment instruction and the previous instruction group adjacent to the comment instruction can be scheduled in the same cycle.

[0103] In some embodiments, the instruction information of a basic block may further include jump instructions within the basic block, and these jump instructions are scheduled last. This ensures the correctness and integrity of program execution.

[0104] In this embodiment, for instruction groups within a basic block, the direct and indirect register dependencies between instructions in different instruction groups are analyzed to obtain a complete register dependency relationship. Based on this complete register dependency relationship, the cycle in which each instruction group is ready (i.e., the schedulable cycle) is determined. In each cycle, the target instruction group to be scheduled is selected from the schedulable instruction groups of that cycle according to the rules that the chip can execute instruction groups in parallel after scheduling. In this way, based on the complete register dependency relationship, the parallelizable instruction groups are unlocked, and instructions that were originally serial can be parallelized while ensuring that the code semantics of the basic block remain unchanged or equivalent before and after scheduling. This improves instruction parallelism, increases code throughput, makes the scheduling method more reasonable, and reduces the total number of execution cycles for the basic block by an average of 5-10%.

[0105] Based on the same technical concept, this application also provides an instruction scheduling device. The principle of the instruction scheduling device in solving the problem is similar to that of the instruction scheduling method described above. Therefore, the implementation of the instruction scheduling device can refer to the implementation of the instruction scheduling method, and the repeated parts will not be described again.

[0106] Figure 6 A schematic diagram of an instruction scheduling device provided in this application embodiment includes: The acquisition module 601 is used to acquire instruction information of a basic block, wherein the instructions in the basic block are to be executed on the chip, and the instruction information includes multiple instruction groups in the basic block and the cycle number corresponding to each instruction group, wherein each instruction group includes at least one instruction. The determination module 602 is used to determine the cycle in which each instruction group is in the ready state based on the cycle number corresponding to each instruction group and the register dependency relationship between instructions in different instruction groups; Processing module 603 is used to determine the set of instruction groups that are ready but not scheduled in the i-th cycle, where i is initially a preset value; according to the rule that the chip can execute instruction groups in parallel after scheduling, it selects the target instruction group to be scheduled in the i-th cycle from the set of instruction groups, updates i to i+N, where N is the cycle number corresponding to the target instruction group; and executes the step of determining the set of instruction groups that are ready but not scheduled in the i-th cycle until all the instruction groups are scheduled and then the instruction scheduling ends.

[0107] In some embodiments, the determining module 602 is specifically used for: An instruction dependency graph of the basic block is generated, with each instruction group as a vertex and the register dependencies between instructions in different instruction groups as edges. Based on the number of cycles corresponding to each instruction group, the instruction groups in the instruction dependency graph are traversed in a forward direction to obtain the earliest cycle in which each instruction group is in a ready state. Based on the cycle number of each data processing instruction, the instruction groups in the instruction dependency graph are traversed in reverse to obtain the latest cycle in which each instruction group is in the ready state.

[0108] In some embodiments, the processing module 603 is specifically used for: If the instruction set includes at least two instruction groups, then a reference instruction for each instruction group is determined based on the number of instructions contained in each instruction group, and a scheduling priority score for the instruction group is determined based on the parallel execution representation information of the reference instruction. From the at least two instruction groups, select the one with the highest scheduling priority score as the target instruction group.

[0109] In some embodiments, the processing module 603 is specifically used for: If the instruction group contains at least two instructions, then the primary instruction among the at least two instructions is determined as the reference instruction of the instruction group. If the instruction group contains a single instruction, then that single instruction is designated as the reference instruction for the instruction group.

[0110] In some embodiments, the parallel execution characterization information of the reference instructions includes the earliest and latest cycles in the ready state, as well as a preset access delay. The processing module 603 is specifically used for: If the earliest and latest periods of the reference instruction being in the ready state are the same, then the critical path score of the instruction group is determined to be a set value. The relaxation score of the instruction group is determined according to the rule that the absolute value of the difference between the earliest and latest cycles in which the reference instruction is in the ready state is negatively correlated with the relaxation score. The instruction delay score of the instruction group is determined according to the rule that the preset access delay of the reference instruction is positively correlated with the instruction delay score. The scheduling priority score is determined based on at least one of the critical path score, the slackness score, and the instruction delay score.

[0111] In some embodiments, the processing module 603 is further configured to: Before determining the scheduling priority score, the instruction latency score of the instruction group is amplified, wherein the amplification factor is positively correlated with the total number of instructions in the basic block.

[0112] In some embodiments, the preset access delay of the reference instruction is determined based on the register type and operand type corresponding to the reference instruction.

[0113] In some embodiments, the parallel execution characterization information of the reference instruction further includes the number of instructions that depend on the reference instruction, the number of instructions that depend on the reference instruction and are in a ready state, and the resource consumption size. The processing module 603 is further configured to: The readiness score of the instruction group is determined according to the rule that the earliest period in which the reference instruction is in a ready state is negatively correlated with the readiness score. The fan-out score of the instruction group is determined according to the rule that the number of instructions that depend on the reference instructions is positively correlated with the fan-out score; The successor readiness score of the instruction group is determined according to the rule that the number of instructions that depend on the reference instruction and are in a ready state is positively correlated with the successor readiness score. The resource pressure score of the instruction group is determined according to the rule that the resource consumption of the reference instruction is positively correlated with the resource pressure score. The scheduling priority score is determined based on at least one of the critical path score, the slackness score, the instruction latency score, the readiness score, the fan-out score, the successor readiness score, and the resource pressure score.

[0114] In some embodiments, the scheduling priority score is determined as follows: The scheduling priority score is obtained by weighted summation of the critical path score, the relaxation score, the readiness score, the fan-out score, the successor readiness score, the instruction delay score, and the resource pressure score, wherein the weights of the critical path score, the relaxation score, the readiness score, the fan-out score, the successor readiness score, the instruction delay score, and the resource pressure score decrease sequentially.

[0115] In some embodiments, when the reference instruction is the main instruction in an instruction group, the instructions that depend on the reference instruction are instructions that depend on all instructions in the instruction group.

[0116] In some embodiments, the register dependencies between instructions in different instruction groups include direct register dependencies and indirect register dependencies.

[0117] In some embodiments, when an instruction group computes a vector, the register dependencies between the instruction group and instructions in other instruction groups are obtained by performing dependency analysis on all registers corresponding to the vector.

[0118] In some embodiments, the instruction information further includes comment instructions in the basic block, and the processing module 603 is further configured to: If the comment instruction indicates the start of commenting, then the comment instruction and the next instruction group adjacent to the comment instruction are scheduled together; If the comment instruction indicates the end of the comment, then the comment instruction and the previous instruction group adjacent to the comment instruction are scheduled together.

[0119] In some embodiments, the instruction information further includes jump instructions in the basic block, which are scheduled last.

[0120] The module division in this application embodiment is illustrative and only represents one logical functional division. In actual implementation, other division methods are possible. Furthermore, the functional modules in each embodiment of this application can be integrated into a single processor, exist as separate physical entities, or be integrated into a single module. Coupling between modules can be achieved through interfaces, typically electrical communication interfaces, but mechanical interfaces or other types of interfaces are also possible. Therefore, modules described as separate components may or may not be physically separate; they can be located in one place or distributed across different locations on the same or different devices. The integrated modules described above can be implemented in hardware or as software functional modules.

[0121] Having introduced the instruction scheduling method and apparatus of exemplary embodiments of this application, we will now introduce an electronic device of another exemplary embodiment of this application.

[0122] like Figure 7 As shown, the electronic device is presented in the form of a general-purpose electronic device. The components of the electronic device may include, but are not limited to: at least one processor 101, at least one memory 102, and a bus 103 connecting different system components (including memory 102 and processor 101).

[0123] Bus 103 represents one or more of several bus structures, including a memory bus or memory controller, peripheral bus, processor, or local bus using any of the various bus structures.

[0124] The memory 102 may include a readable medium in the form of volatile memory, such as random access memory (RAM) 1021 and / or cache memory 1022, and may further include read-only memory (ROM) 1023.

[0125] The memory 102 may also include a program / utility 1025 having a set (at least one) of program modules 1024, including but not limited to: an operating system, one or more application programs, other program modules, and program data, each or some combination of these examples may include an implementation of a network environment.

[0126] The electronic device can also communicate with one or more external devices 104 (e.g., keyboard, pointing device, etc.), one or more devices that enable a user to interact with the electronic device, and / or any device that enables the electronic device to communicate with one or more other electronic devices (e.g., router, modem, etc.). This communication can be performed via input / output (I / O) interface 105. Furthermore, the electronic device can communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public networks, such as the Internet) via network adapter 106. As shown, network adapter 106 communicates with other modules used in the electronic device via bus 103. It should be understood that, although not shown in the figures, other hardware and / or software modules can be used in conjunction with the electronic device, including but not limited to: microcode, device drivers, redundant processors, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0127] It should be noted that, Figure 7 The electronic device described is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments in this application.

[0128] In an exemplary embodiment, a storage medium is also provided, which, when a computer program in the storage medium is executed by a processor of an electronic device, enables the electronic device to perform any of the exemplary methods provided in this application. Optionally, the storage medium may be a non-transitory computer-readable storage medium, such as a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device.

[0129] In an exemplary embodiment, a computer program product is also provided, which implements any of the exemplary methods provided in this application when the computer program is executed by a processor.

[0130] It should be noted that although several modules or sub-modules of the device have been mentioned in the detailed description above, this division is merely exemplary and not mandatory. In fact, according to embodiments of this application, the features and functions of two or more modules described above can be embodied in one module. Conversely, the features and functions of one module described above can be further divided and embodied by multiple modules.

[0131] Furthermore, although the operations of the method of this application are described in a specific order in the accompanying drawings, this does not require or imply that these operations must be performed in that specific order, or that all the operations shown must be performed to achieve the desired result. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0132] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0133] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0134] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, then this application also includes such modifications and variations.

Claims

1. An instruction scheduling method, characterized in that, include: Obtain instruction information of a basic block, wherein the instructions in the basic block are to be executed on the chip, and the instruction information includes multiple instruction groups in the basic block and the cycle number corresponding to each instruction group, wherein each instruction group includes at least one instruction; Based on the number of cycles corresponding to each instruction group and the register dependencies between instructions in different instruction groups, the cycle in which each instruction group is in the ready state is determined. Determine the set of instruction groups that are in the ready state and have not been scheduled in the i-th cycle, where i is a preset value initially; According to the rule that the chip can execute instruction groups in parallel after scheduling, select the target instruction group to be scheduled in the i-th cycle from the instruction group set, update i to i+N, where N is the cycle number corresponding to the target instruction group; The step of determining the set of instruction groups that are in the ready state and have not been scheduled in the i-th cycle is performed until the instruction scheduling ends after all of the instruction groups have been scheduled.

2. The method as described in claim 1, characterized in that, Based on the cycle number corresponding to each instruction group and the register dependencies between instructions in different instruction groups, the cycle in which each instruction group is ready is determined, including: An instruction dependency graph of the basic block is generated, with each instruction group as a vertex and the register dependencies between instructions in different instruction groups as edges. Based on the number of cycles corresponding to each instruction group, the instruction groups in the instruction dependency graph are traversed in a forward direction to obtain the earliest cycle in which each instruction group is in a ready state. Based on the cycle number of each data processing instruction, the instruction groups in the instruction dependency graph are traversed in reverse to obtain the latest cycle in which each instruction group is in the ready state.

3. The method as described in claim 1, characterized in that, According to the rule that the chip can execute instruction groups in parallel after scheduling, the target instruction group to be scheduled in the i-th cycle is selected from the instruction group set, including: If the instruction set includes at least two instruction groups, then a reference instruction for each instruction group is determined based on the number of instructions contained in each instruction group, and a scheduling priority score for the instruction group is determined based on the parallel execution representation information of the reference instruction. From the at least two instruction groups, select the one with the highest scheduling priority score as the target instruction group.

4. The method as described in claim 3, characterized in that, Based on the number of instructions contained in each instruction group, determine the reference instructions for the instruction group, including: If the instruction group contains at least two instructions, then the primary instruction among the at least two instructions is determined as the reference instruction of the instruction group. If the instruction group contains a single instruction, then that single instruction is designated as the reference instruction for the instruction group.

5. The method as described in claim 4, characterized in that, The parallel execution characterization information of the reference instructions includes the earliest and latest cycles in the ready state, as well as a preset access delay. Based on the parallel execution characterization information of the reference instructions, the scheduling priority score of the instruction group is determined, including: If the earliest and latest periods of the reference instruction being in the ready state are the same, then the critical path score of the instruction group is determined to be a set value. The relaxation score of the instruction group is determined according to the rule that the absolute value of the difference between the earliest and latest cycles in which the reference instruction is in the ready state is negatively correlated with the relaxation score. The instruction delay score of the instruction group is determined according to the rule that the preset access delay of the reference instruction is positively correlated with the instruction delay score. The scheduling priority score is determined based on at least one of the critical path score, the slackness score, and the instruction delay score.

6. The method as described in claim 5, characterized in that, Before determining the scheduling priority score, the process also includes: The instruction latency score of the instruction group is amplified, wherein the amplification factor is positively correlated with the total number of instructions in the basic block.

7. The method as described in claim 5, characterized in that, The preset access delay of the reference instruction is determined based on the register type and operand type corresponding to the reference instruction.

8. The method as described in any one of claims 5 to 7, characterized in that, The parallel execution characterization information of the reference instruction also includes the number of instructions that depend on the reference instruction, the number of instructions that depend on the reference instruction and are in a ready state, and the resource consumption. Based on the parallel execution characterization information of the reference instruction, the scheduling priority score of the instruction group is determined, further including: The readiness score of the instruction group is determined according to the rule that the earliest period in which the reference instruction is in a ready state is negatively correlated with the readiness score. The fan-out score of the instruction group is determined according to the rule that the number of instructions that depend on the reference instructions is positively correlated with the fan-out score; The successor readiness score of the instruction group is determined according to the rule that the number of instructions that depend on the reference instruction and are in a ready state is positively correlated with the successor readiness score. The resource pressure score of the instruction group is determined according to the rule that the resource consumption of the reference instruction is positively correlated with the resource pressure score. The scheduling priority score is determined based on at least one of the critical path score, the slackness score, the instruction latency score, the readiness score, the fan-out score, the successor readiness score, and the resource pressure score.

9. The method as described in claim 8, characterized in that, The scheduling priority score is determined according to the following method: The scheduling priority score is obtained by weighted summation of the critical path score, the relaxation score, the readiness score, the fan-out score, the successor readiness score, the instruction delay score, and the resource pressure score, wherein the weights of the critical path score, the relaxation score, the readiness score, the fan-out score, the successor readiness score, the instruction delay score, and the resource pressure score decrease sequentially.

10. The method as described in claim 8, characterized in that, When the reference instruction is the main instruction in an instruction group, the instructions that depend on the reference instruction are the instructions that depend on all instructions in the instruction group.

11. The method as described in claim 2, characterized in that, Register dependencies between instructions in different instruction sets include direct register dependencies and indirect register dependencies.

12. The method as described in claim 2, characterized in that, When an instruction group computes a vector, the register dependencies between the instructions in the instruction group and the instructions in other instruction groups are obtained by performing dependency analysis on all registers corresponding to the vector.

13. The method as described in claim 1, characterized in that, The instruction information also includes comment instructions in the basic block, and further includes: If the comment instruction indicates the start of commenting, then the comment instruction and the next instruction group adjacent to the comment instruction are scheduled together; If the comment instruction indicates the end of the comment, then the comment instruction and the previous instruction group adjacent to the comment instruction are scheduled together.

14. The method as described in claim 1, characterized in that, The instruction information also includes jump instructions in the basic block, which are scheduled last.

15. A command scheduling device, characterized in that, include: An acquisition module is used to acquire instruction information of a basic block, wherein the instructions in the basic block are to be executed on the chip, and the instruction information includes multiple instruction groups in the basic block and the cycle number corresponding to each instruction group, wherein each instruction group includes at least one instruction. The determination module is used to determine the cycle in which each instruction group is in the ready state based on the cycle number corresponding to each instruction group and the register dependencies between instructions in different instruction groups; The processing module is used to determine the set of instruction groups that are in the ready state and have not been scheduled in the i-th cycle, where i is a preset value initially. According to the rule that the chip can execute instruction groups in parallel after scheduling, select the target instruction group to be scheduled in the i-th cycle from the instruction group set, update i to i+N, where N is the cycle number corresponding to the target instruction group; execute the step of determining the set of instruction groups that are in the ready state and have not been scheduled in the i-th cycle, until all the instruction groups are scheduled and then the instruction scheduling ends.

16. An electronic device, characterized in that, include: At least one processor, and a memory communicatively connected to said at least one processor, wherein: The memory stores a computer program that can be executed by the at least one processor to enable the at least one processor to perform the method as described in any one of claims 1-14.

17. A storage medium, characterized in that, When the computer program in the storage medium is executed by the processor of the electronic device, the electronic device is able to perform the method as described in any one of claims 1-14.

18. A computer program product, characterized in that, Includes a computer program that, when executed by a processor, implements the method described in any one of claims 1-14.

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