Semiconductor structure for preparing capacitor

Abstract

The invention provides a semiconductor structure used for preparing a capacitor, the semiconductor structure used for preparing the capacitor comprises a substrate and a groove array, the substrate comprises a plurality of capacitor areas arranged at intervals, each capacitor area comprises a plurality of sub-capacitor areas arranged at intervals and in an array, the groove array is located in the sub-capacitor areas and comprises a plurality of grooves, and the grooves are arranged in the sub-capacitor areas. The plurality of grooves in the same sub-capacitor region are arranged at intervals and have the same arrangement direction, at least two sub-capacitor regions in the plurality of sub-capacitor regions in the same column or the same row have different groove arrangement directions, and at least two adjacent sub-capacitor regions have the same groove arrangement direction. According to the semiconductor structure for preparing the capacitor, stress distribution of different positions of the wafer can be flexibly adjusted, so that uneven stress distribution is eliminated.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit manufacturing technology, and relates to a semiconductor structure for preparing capacitors. Background Technology

[0002] In the manufacturing process of trench capacitors, trench etching and filling introduce non-uniform stress on the wafer, leading to severe wafer warpage and inducing silicon defects such as dislocations, directly affecting device performance. In the prior art, patent number (CN115513169A) discloses... Figure 1 The trench array 9 shown is centrally symmetrically distributed, arranging sub-capacitor segments 90A and 90B in mutually perpendicular directions to cancel out stress in the same direction and alleviate warping. However, in actual processes, the stress amplitude in different regions of the wafer is not uniform. The centrally symmetrical array can only provide "homogenization" adjustment and lacks the flexibility to address local differences, thus making it difficult to eliminate the problem of uneven stress distribution on the wafer.

[0003] Therefore, how to provide a semiconductor structure for fabricating capacitors that can flexibly adjust the stress distribution at different locations on the wafer, and achieve zoned adjustment of stress in different regions to eliminate the problem of uneven stress distribution, has become an important problem that needs to be solved by those skilled in the art.

[0004] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a semiconductor structure for fabricating capacitors, which solves the problem that the centrally symmetric trench array in the prior art lacks flexibility to address local differences and is difficult to eliminate uneven wafer stress distribution.

[0006] To achieve the above and other related objectives, the present invention provides a semiconductor structure for fabricating a capacitor, comprising:

[0007] The substrate includes a plurality of spaced capacitor regions, each of which includes a plurality of spaced sub-capacitor regions arranged in an array. In both the X and Y directions, the size of each capacitor region is not less than four times the size of the smallest sub-capacitor region among the capacitor regions.

[0008] A trench array, located in the sub-capacitor region and including multiple trenches, wherein the multiple trenches in the same sub-capacitor region are spaced apart and have the same arrangement direction, wherein in the multiple sub-capacitor regions located in the same column or the same row, at least two sub-capacitor regions have different trench arrangement directions, and at least two adjacent sub-capacitor regions have the same trench arrangement direction, wherein in any two adjacent sub-capacitor regions, the ratio of the trench length of one sub-capacitor region to the trench length of the other sub-capacitor region is in the range of 0.25 to 4;

[0009] An isolation layer is located on the substrate, and the isolation layer covers the bottom and sidewalls of the trench;

[0010] A stacked layer, located on the isolation layer, fills the trench and includes alternating stacked conductive and dielectric layers.

[0011] Optionally, the stacked layers on each of the sub-capacitor regions do not contact each other, and a sub-capacitor is formed in a corresponding sub-capacitor region of the capacitor region.

[0012] Optionally, the distance between two adjacent sub-capacitor regions is greater than the distance between two adjacent trenches in any one of the sub-capacitor regions.

[0013] Optionally, the length of the trench ranges from 1 μm to 50 μm.

[0014] Optionally, among the multiple sub-capacitor regions located in the same column, at least two of the sub-capacitor regions have mutually perpendicular groove arrangement directions, or at least two of the sub-capacitor regions have the same groove arrangement direction.

[0015] Optionally, among the multiple sub-capacitor regions located in the same row, at least two of the sub-capacitor regions have mutually perpendicular trench arrangement directions, or at least two of the sub-capacitor regions have the same trench arrangement direction.

[0016] Optionally, the capacitor region includes a central region and an edge region surrounding the central region. In each of the sub-capacitor regions located in the edge region of the capacitor region, at least two sub-capacitor regions having the same trench array are included.

[0017] Optionally, in each of the sub-capacitor regions located in the middle region of the capacitor region, the trench length corresponding to at least one of the sub-capacitor regions is greater than the trench length corresponding to each of the sub-capacitor regions in the edge region.

[0018] Optionally, the intermediate region includes two sub-capacitor regions of the same size, spaced apart along the X direction. The two sub-capacitor regions have the same trench array, and the trenches are arranged in the Y direction. The edge region includes twelve sub-capacitor regions of the same size, arranged in a U-shape and centrally symmetrical. Each sub-capacitor region located at one of the four corners of the U-shape has the same trench array, and the trenches are arranged in the Y direction. Each sub-capacitor region located between the four corners of the U-shape has the same trench array, and the trenches are arranged in the X direction. The trench length corresponding to each sub-capacitor region in the intermediate region is twice the trench length corresponding to each sub-capacitor region in the edge region.

[0019] Optionally, among the multiple sub-capacitor regions located in the same column or row, the number of sub-capacitor regions having the same trench array and arranged adjacent to each other does not exceed five.

[0020] The present invention also provides a semiconductor structure for fabricating a capacitor, comprising:

[0021] The substrate includes a plurality of spaced-apart capacitor regions, each capacitor region including two first sub-capacitor regions, four second sub-capacitor regions, and eight third sub-capacitor regions. The two first sub-capacitor regions are disposed in the middle region of the capacitor region and are spaced apart along the X direction. The four second sub-capacitor regions and the eight third sub-capacitor regions are disposed in the edge region of the capacitor region, with the four second sub-capacitor regions located at the four corners of the edge region. The eight third sub-capacitor regions are evenly distributed between the four second sub-capacitor regions, with two adjacent third sub-capacitor regions disposed between every two adjacent second sub-capacitor regions.

[0022] The first trench array is located within the first sub-capacitor region, and the first trench array includes a plurality of first trenches spaced apart and extending along the Y direction.

[0023] The second trench array is located in the second sub-capacitor region, and the second trench array includes a plurality of second trenches that are spaced apart and extend along the Y direction;

[0024] The third trench array is located within the third sub-capacitor region, and the third trench array includes a plurality of spaced third trenches extending along the X direction.

[0025] Optionally, it further includes an isolation layer and a stacked layer on the isolation layer, the isolation layer being located on the substrate and covering the bottom and sidewalls of the first trench, the second trench and the third trench, the stacked layer filling the first trench, the second trench and the third trench and including alternately stacked conductive layers and dielectric layers.

[0026] Optionally, in the X and Y directions, the size of the first sub-capacitor region is twice the size of the second sub-capacitor region, and the size of the third sub-capacitor region is the same as the size of the second sub-capacitor region.

[0027] Optionally, the length of the first trench ranges from 1 μm to 50 μm, the length of the second trench ranges from 1 μm to 50 μm, and the length of the third trench ranges from 1 μm to 50 μm.

[0028] Optionally, the length of the first groove is twice the length of the second groove, and the length of the third groove is the same as the length of the second groove.

[0029] As described above, the semiconductor structure for fabricating capacitors according to the present invention includes a substrate and a trench array. The substrate includes multiple spaced-apart capacitor regions, each capacitor region including multiple spaced-apart sub-capacitor regions arranged in an array. In both the X and Y directions, the size of each capacitor region is not less than four times the size of the smallest sub-capacitor region. The trench array is located within the sub-capacitor regions and includes multiple trenches. Multiple trenches within the same sub-capacitor region are spaced apart and have the same arrangement direction. Among the multiple sub-capacitor regions located in the same column or row, at least two sub-capacitor regions have different trench arrangement directions, and at least two adjacent sub-capacitor regions have the same trench arrangement direction. In any two adjacent sub-capacitor regions, the ratio of the trench length of one sub-capacitor region to the trench length of the other sub-capacitor region ranges from 0.25 to 4. The semiconductor structure for fabricating capacitors according to the present invention can flexibly adjust the stress distribution at different locations on the wafer, achieving zoned adjustment of stress in different regions, thereby eliminating the problem of uneven stress distribution. Attached Figure Description

[0030] Figure 1 The diagram shows a layout of a trench array.

[0031] Figure 2 The diagram shows a process flow chart of the method for fabricating a semiconductor structure for a capacitor according to the present invention.

[0032] Figure 3 The diagram shows a schematic of the substrate structure used in the method for fabricating a semiconductor structure for a capacitor according to the present invention.

[0033] Figure 4 The diagram shown is a schematic of the structure obtained after forming a trench in the method for preparing a semiconductor structure for preparing a capacitor according to the present invention.

[0034] Figure 5 Displayed as Figure 4 An enlarged view of the capacitor region structure shown.

[0035] Figure 6 The diagram shown is a schematic of the structure obtained after forming an isolation layer in the method for preparing a semiconductor structure for a capacitor according to the present invention.

[0036] Figure 7 The diagram shown is a schematic of the structure obtained after forming a stacked layer in the method for preparing a semiconductor structure for preparing a capacitor according to the present invention.

[0037] Figure 8 Displayed as Figure 7 An enlarged view of the capacitor region structure shown.

[0038] Figure 9 Displayed as Figure 8 An enlarged view of the sub-capacitor region structure in the structure shown.

[0039] Figure 10 Displayed as Figure 9 Cross-sectional view of the trench structure shown (along) Figure 9 (in the AA' direction).

[0040] Figure 11 The diagram shows another schematic representation of the semiconductor structure used in the fabrication of capacitors according to the present invention.

[0041] Figure 12 Displayed as Figure 11 An enlarged view of the capacitor region structure shown.

[0042] Explanation of reference numerals in the attached figures

[0043] 1 Substrate

[0044] 2. Capacitor Area

[0045] 3 Sub-capacitor regions

[0046] 3a First Sub-capacitor Region

[0047] 3b Second Sub-capacitor Region

[0048] 3c Third Sub-capacitor Region

[0049] 4. Trench

[0050] 4a First trench

[0051] 4b Second trench

[0052] 4c Third Groove

[0053] 5. Isolation layer

[0054] 6 Stacked layers

[0055] 61 Conductive layer

[0056] 62 Dielectric Layer

[0057] The middle region of the M capacitor region

[0058] O Capacitor region edge area

[0059] L1, L2, L5 trench lengths

[0060] Distance between two adjacent sub-capacitor regions of L3

[0061] L4 Distance between two adjacent trenches

[0062] Steps S1 to S4 Detailed Implementation

[0063] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0064] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.

[0065] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0066] In the detailed description of embodiments of the present invention, for ease of explanation, the schematic diagrams illustrating the device structure may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0067] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0068] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0069] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0070] Example 1

[0071] This embodiment provides a method for fabricating a semiconductor structure for a capacitor. Please refer to [link to relevant documentation]. Figure 2 The diagram shows a process flow chart of a method for fabricating a semiconductor structure for a capacitor according to the present invention, comprising the following steps:

[0072] S1: A substrate is provided, the substrate including a plurality of spaced capacitor regions, the capacitor regions including a plurality of spaced sub-capacitor regions arranged in an array, wherein the size of the capacitor region in the X direction and the Y direction is not less than four times the size of the smallest sub-capacitor region in the capacitor region;

[0073] S2: A trench array is formed in each of the sub-capacitor regions. Multiple trenches located in the same sub-capacitor region are spaced apart and have the same arrangement direction. Among the multiple sub-capacitor regions located in the same column or row, at least two sub-capacitor regions have different trench arrangement directions, and at least two adjacent sub-capacitor regions have the same trench arrangement direction. In any two adjacent sub-capacitor regions, the ratio of the trench length of one sub-capacitor region to the trench length of the other sub-capacitor region is in the range of 0.25 to 4.

[0074] S3: An isolation layer is formed on the substrate, and the isolation layer covers the bottom and sidewalls of the trench;

[0075] S4: A stacked layer is formed on the isolation layer, the stacked layer filling the trench and comprising alternating stacked conductive and dielectric layers.

[0076] The following will combine Figures 3 to 12 The present invention details the various steps of the method for preparing the semiconductor structure for preparing a capacitor.

[0077] Please refer to the following first. Figure 3Step S1 is executed as follows: A substrate 1 is provided, the substrate 1 including a plurality of spaced-apart capacitor regions 2, each capacitor region 2 including a plurality of spaced-apart sub-capacitor regions 3 arranged in an array, wherein the size of each capacitor region 2 is not less than four times the size of the smallest sub-capacitor region 3 in both the X and Y directions. It should be noted that... Figure 3 The sub-capacitor region 3 in the diagram is filled with slanted lines for ease of illustration. Figure 3 The sub-capacitor region 3 in the figure is actually shown as a portion of the substrate 1.

[0078] As an example, the substrate 1 includes a silicon-based substrate.

[0079] Please see again Figures 4 to 5 Step S2: An array of trenches 4 is formed in each of the sub-capacitor regions 3. Multiple trenches 4 located in the same sub-capacitor region 3 are spaced apart and have the same arrangement direction. Among the multiple sub-capacitor regions 3 located in the same column or row, at least two sub-capacitor regions 3 have different trench 4 arrangement directions, and at least two adjacent sub-capacitor regions 3 have the same trench 4 arrangement direction. In any two adjacent sub-capacitor regions 3, the ratio (L1 / L2 or L2 / L1) of the trench length of one sub-capacitor region 3 to the trench length of the other sub-capacitor region 3 is in the range of 0.25 to 4. Figure 4 The diagram shown is a schematic representation of the substrate structure used in the method for fabricating a semiconductor structure for a capacitor according to the present invention. Figure 5 Displayed as Figure 4 An enlarged view of the capacitor region structure shown.

[0080] In other embodiments, each of the sub-capacitor regions 3 within the capacitor region 2 includes the same trench array and different trench arrays, wherein the different trench arrays have at least one type of trench 4 with different parameters, and the same trench array has trench 4 with all parameters being the same, including the number of trenches, trench length, trench width, trench spacing, and arrangement direction, for example... Figure 5 The sub-capacitor regions 3a and 3b have trench arrays with different arrangement directions, and the sub-capacitor regions 3a and 3c have trench arrays with different trench lengths.

[0081] Specifically, the trench 4 can be formed by forming a patterned etch mask layer on the upper surface of the substrate 1, and the pattern in the patterned etch mask layer can be transferred to the upper surface of the substrate 1.

[0082] As an example, the distance L3 between two adjacent sub-capacitor regions 3 is greater than the distance L4 between two adjacent trenches 4 in any one of the sub-capacitor regions 3, wherein the area between two adjacent sub-capacitor regions 3 (i.e., Figure 5 The area corresponding to the length L3 shown is used to isolate the sub-capacitor area 3 and to form contact holes in subsequent processes for electrical connection with external electronic components.

[0083] As an example, the length L1 of the groove 4 ranges from 1μm to 50μm. For example, the length L1 of the groove 4 is 5μm, 15μm, 30μm or 45μm. The length L1 of the groove 4 can be determined according to specific circumstances, and no further restrictions are imposed here.

[0084] As an example, among the sub-capacitor regions 3 located in the same column, at least two sub-capacitor regions 3 have mutually perpendicular groove arrangement directions, or at least two sub-capacitor regions 3 have the same groove arrangement direction; among the multiple sub-capacitor regions 3 located in the same row, at least two sub-capacitor regions 3 have mutually perpendicular groove arrangement directions, or at least two sub-capacitor regions 3 have the same groove arrangement direction. That is, in this embodiment, please refer to... Figure 5 The capacitor regions 3 with different trench arrays are considered as different capacitor regions 3, and the capacitor regions 3 with the same trench array are considered as the same capacitor region 3. The design of the above trench arrangement direction is as follows: along the X direction or Y direction, there must be repeated placement of the same sub-capacitor region 3 and alternating placement of different sub-capacitor regions 3, and at least along one direction (X direction or Y direction), there must be two or more sub-capacitor regions 3 with mutually perpendicular trench arrangement directions.

[0085] For example, please refer to [link / reference]. Figure 5 The capacitor region includes a central region M and an edge region O surrounding the central region M. In each of the sub-capacitor regions 3 of the central region M of the capacitor region 2, there are at least two identical sub-capacitor regions 3c.

[0086] As an example, in each of the sub-capacitor regions 3 in the middle region M of the capacitor region 2, the trench length L5 corresponding to at least one sub-capacitor region 3c is greater than the trench length L1 corresponding to each of the sub-capacitor regions 3a in the edge region O.

[0087] As an example, among the multiple sub-capacitor regions 3 located in the same column or row, the number of sub-capacitor regions 3 having the same trench array and arranged adjacent to each other does not exceed five, that is, there will be no array formed by sub-capacitor regions 3 with the same trench array in one row and six columns or six rows and one column.

[0088] Therefore, the arrangement of the grooves 4 in the above embodiments is in the same direction (e.g., in...). Figure 5 As shown in the X or Y direction, there are two sub-capacitor regions 3 with different arrangement directions (here, "arrangement direction" refers to the extension direction of the trench 4). When a local area of ​​the wafer experiences large tensile or compressive stress in the X direction and significantly exacerbates warping, the number of sub-capacitor regions 3 arranged in the Y direction or the corresponding trench length can be increased in that area, while the number of sub-capacitor regions 3 arranged in the X direction or the corresponding trench length can be reduced. This ensures that the trench 4 extending in the Y direction is dominant in both quantity and geometry, thereby preferentially releasing the stress component in the X direction. Conversely, if the stress in the Y direction is prominent, the adjustment is reversed. In other words, through the above three-in-one free combination of "region-direction-density", the arrangement direction, trench density, and area ratio of the trench array in the sub-capacitor region 3 can be fine-tuned according to the real-time stress map of the wafer, realizing directional and quantitative compensation for the stress magnitude at different locations, and ultimately eliminating the problem of uneven stress distribution on the wafer.

[0089] Please see again Figure 6 Step S3: Form an isolation layer 5 on the substrate 1, and the isolation layer 5 covers the bottom and sidewalls of the trench 4.

[0090] Specifically, the isolation layer 5 serves both to protect the upper surface of the substrate 1 during manufacturing and to isolate the trench structure formed on the substrate 1 from the substrate 1, thereby achieving electrical isolation between the trench structure and the substrate 1. For example, the material of the isolation layer 5 includes insulating materials such as silicon oxide and silicon nitride.

[0091] Please see again Figures 7 to 10 Step S4: A stacked layer 6 is formed on the isolation layer 5. The stacked layer 6 fills the trench 4 and includes alternately stacked conductive layers 61 and dielectric layers 62. Figure 7 The diagram shown is a schematic representation of the structure obtained after forming the stacked layer 6 in the method for fabricating the semiconductor structure of a capacitor according to the present invention. Figure 8 Displayed as Figure 7 An enlarged view of the capacitor region 2 structure shown. Figure 9 Displayed as Figure 8 An enlarged view of the sub-capacitor region 3 structure shown. Figure 10 Displayed as Figure 9 Cross-sectional view of the trench structure shown (along) Figure 9 (in the AA' direction).

[0092] It should be noted that, Figure 10 The diagram shown is a cross-sectional schematic of a single trench structure in the semiconductor structure used to fabricate a capacitor according to the present invention, and is drawn as follows: Figure 8 and Figure 9 This is to facilitate the demonstration of the morphology of the capacitor region 2 and the sub-capacitor region 3, and Figures 7 to 9 The trenches 4 in the figure are all marked with dashed lines because the trenches 4 have been covered by the stacked layer 6. The dashed lines in the figure are only to indicate the location distribution of the trenches 4.

[0093] Specifically, the stacked layer 6 includes multiple conductive layers 61 and dielectric layers 62. In this embodiment, the stacked layer 6 includes four conductive layers 61 and three dielectric layers 62. In other embodiments, the stacked layer 6 may also include other numbers of conductive layers 61 and dielectric layers 62. The conductive layers 61 may be made of doped polysilicon or other suitable conductive materials, and the dielectric layers 62 may be made of silicon dioxide or other suitable dielectric materials.

[0094] For example, please refer to Figure 11 The method also includes a step of photolithography of the stacked layers 6 to form a sub-capacitor in a corresponding sub-capacitor region 3 within the capacitor region 2. The stacked layers within the same sub-capacitor region 3 are interconnected, while the stacked layers in different sub-capacitor regions 3 are separated. For a clearer illustration of the above structure, please refer to [link to relevant documentation]. Figure 12 It showed Figure 11 The enlarged view of the capacitor region 2 structure shown shows that the stacked layers of different sub-capacitor regions 3 are separated from each other, and the separation area exposes the isolation layer 5.

[0095] The semiconductor structure fabrication method for capacitors in this embodiment can flexibly adjust the stress distribution at different locations on the wafer by forming different trench arrays and identical trench arrays in each sub-capacitor region, thereby achieving zoned adjustment of stress in different regions and eliminating the problem of uneven stress distribution.

[0096] Example 2

[0097] This embodiment provides a semiconductor structure for fabricating a capacitor, using the fabrication method for the semiconductor structure for fabricating a capacitor described in Embodiment 1. The semiconductor structure for fabricating a capacitor includes a substrate 1 and a trench array. Please refer to [further details omitted]. Figure 3 The substrate 1 includes a plurality of spaced capacitor regions 2, and each capacitor region 2 includes a plurality of spaced sub-capacitor regions 3 arranged in an array. In both the X and Y directions, the size of each capacitor region 2 is not less than four times the size of the smallest sub-capacitor region 3.

[0098] For details, please refer to [link / reference]. Figure 4The trench array is located in the sub-capacitor region 3 and includes multiple trenches 4. The multiple trenches 4 located in the same sub-capacitor region 3 are spaced apart and have the same arrangement direction. Among the multiple sub-capacitor regions 3 located in the same column or the same row, at least two sub-capacitor regions 3 have different trench arrangement directions, and at least two adjacent sub-capacitor regions 3 have the same trench arrangement direction. In any two adjacent sub-capacitor regions 3, the ratio (L1 / L2 or L2 / L1) of the trench length of one sub-capacitor region 3 to the trench length of the other sub-capacitor region is in the range of 0.25 to 4.

[0099] It should be noted that the semiconductor structure used to prepare the capacitor can also be prepared by other methods, and is not limited to the preparation method described in Example 1.

[0100] Please see again Figure 5 In other embodiments, each of the sub-capacitor regions 3 within the capacitor region 2 includes the same trench array and different trench arrays, wherein the different trench arrays have at least one type of trench 4 with different parameters, and the same trench array has trench 4 with all parameters being the same, including the number of trenches, trench length, trench width, trench spacing, and arrangement direction, for example... Figure 5 In the process, the sub-capacitor region 3 includes a first sub-capacitor region 3a, a second sub-capacitor region 3b, and a third sub-capacitor region 3c. The first sub-capacitor region 3a and the third sub-capacitor region 3c have trench arrays with different arrangement directions, and the first sub-capacitor region 3a and the second sub-capacitor region 3b have trench arrays with different trench lengths.

[0101] For example, please refer to [link / reference]. Figure 10 The semiconductor structure for fabricating the capacitor also includes an isolation layer 5 and a stacked layer 6 on the isolation layer 5. The isolation layer 6 is located on the substrate 1 and covers the bottom and sidewalls of the trench 4. The stacked layer 6 fills the trench 4 and includes alternating stacked conductive layers 61 and dielectric layers 62.

[0102] For example, please refer to [link / reference]. Figure 5 The distance L3 between two adjacent sub-capacitor regions 3 is greater than the distance L4 between two adjacent trenches 4 in any one of the sub-capacitor regions 3, wherein the area between two adjacent sub-capacitor regions 3 (i.e. Figure 5 The area corresponding to the length L3 shown is used to isolate the sub-capacitor area 3 and to form contact holes in subsequent processes for electrical connection with external electronic components.

[0103] As an example, the length L1 of the groove 4 ranges from 1μm to 50μm. For example, the length L1 of the groove 4 is 5μm, 15μm, 30μm or 45μm. The length L1 of the groove 4 can be determined according to specific circumstances, and no further restrictions are imposed here.

[0104] As an example, among the sub-capacitor regions 3 located in the same column, at least two sub-capacitor regions 3 have mutually perpendicular groove arrangement directions, or at least two sub-capacitor regions 3 have the same groove arrangement direction; among the multiple sub-capacitor regions 3 located in the same row, at least two sub-capacitor regions 3 have mutually perpendicular groove arrangement directions, or at least two sub-capacitor regions 3 have the same groove arrangement direction. That is, in this embodiment, please refer to... Figure 5 The capacitor regions 3 with different trench arrays are considered as different capacitor regions 3, and the capacitor regions 3 with the same trench array are considered as the same capacitor region 3. The design of the above trench arrangement direction is as follows: along the X direction or Y direction, there must be repeated placement of the same sub-capacitor region 3 and alternating placement of different sub-capacitor regions 3, and at least along one direction (X direction or Y direction), there must be two or more sub-capacitor regions 3 with mutually perpendicular trench arrangement directions.

[0105] As an example, the capacitor region includes a central region M and an edge region O surrounding the central region M. In each of the sub-capacitor regions 3 of the central region M of the capacitor region 2, at least two sub-capacitor regions 3c having the same trench array are included.

[0106] Specifically, in each of the sub-capacitor regions 3 in the middle region M of the capacitor region 2, the trench length L5 corresponding to at least one sub-capacitor region 3 is greater than the trench length L1 corresponding to each of the sub-capacitor regions 3 in the edge region O, that is, the trench length L5 corresponding to the first sub-capacitor region 3a is greater than the trench length L1 corresponding to the second sub-capacitor region 3b.

[0107] Specifically, the intermediate region M includes two sub-capacitor regions 3 (i.e., the first sub-capacitor region 3a) of the same size, spaced apart along the X direction. The two sub-capacitor regions 3 (i.e., the first sub-capacitor region 3a) have the same trench array, and the trenches are arranged along the Y direction. The edge region O includes twelve sub-capacitor regions 3 of the same size (including the second sub-capacitor region 3b and the third sub-capacitor region 3c). The twelve sub-capacitor regions 3 are arranged in a U-shape and are centrally symmetrically distributed. Each sub-capacitor region located at one of the four corners of the U-shape... Region 3 (i.e., the second sub-capacitor region 3b) has the same trench array and the trenches are all arranged in the Y direction. Each sub-capacitor region 3 (i.e., the third sub-capacitor region 3c) located between the four corners of the U-shaped structure has the same trench array and the trenches are all arranged in the X direction. The trench length L5 corresponding to each sub-capacitor region 3 (i.e., the first sub-capacitor region 3a) located in the middle region is twice the trench length L1 corresponding to each sub-capacitor region 3 (i.e., the second sub-capacitor region 3b or the third sub-capacitor region 3c) in the edge region.

[0108] As an example, among the multiple sub-capacitor regions 3 located in the same column or row, the number of sub-capacitor regions 3 having the same trench array and arranged adjacent to each other does not exceed five, that is, there will be no array formed by sub-capacitor regions 3 with the same trench array in one row and six columns or six rows and one column.

[0109] Therefore, through the arrangement of the grooves 4 in the above embodiments, in the same direction (e.g., in... Figure 5 As shown in the X or Y direction, there are two sub-capacitor regions 3 with different arrangement directions (here, "arrangement direction" refers to the extension direction of the trench 4). When a local area of ​​the wafer experiences large tensile or compressive stress in the X direction and significantly exacerbates warping, the number of sub-capacitor regions 3 arranged in the Y direction or the corresponding trench length can be increased in that area, while the number of sub-capacitor regions 3 arranged in the X direction or the corresponding trench length can be reduced, so that the trench 4 extending in the Y direction is dominant in both quantity and geometry, thereby preferentially releasing the stress component in the X direction; conversely, if the stress in the Y direction is prominent, the adjustment is reversed. In other words, through the above three-in-one free combination of "region-direction-density", the arrangement direction, trench density, and area ratio of the trench array in the sub-capacitor region 3 can be fine-tuned according to the real-time stress map of the wafer, realizing directional and quantitative compensation for the stress magnitude at different locations, so as to flexibly adjust the stress distribution at different locations of the wafer, realize the zonal adjustment of stress in different regions, and ultimately eliminate the problem of uneven stress distribution on the wafer.

[0110] For example, please refer to [link / reference]. Figure 12The stacked layers 6 on each of the sub-capacitor regions 3 do not contact each other, and a sub-capacitor is formed in a corresponding sub-capacitor region 3 in the capacitor region 2.

[0111] The semiconductor structure used to fabricate capacitors in this embodiment includes sub-capacitor regions with different trench arrays and sub-capacitor regions with the same trench array. It can flexibly adjust the stress distribution at different positions on the wafer, realize the zonal adjustment of stress in different regions, and thus eliminate the problem of uneven stress distribution.

[0112] Example 3

[0113] This embodiment provides a semiconductor structure for fabricating a capacitor, using the fabrication method for the semiconductor structure for fabricating a capacitor described in Embodiment 1. Please refer to [link to previous document]. Figure 3 and Figure 5 The capacitor structure, used to fabricate a semiconductor structure for a capacitor, includes a substrate 1, a first trench array, a second trench array, and a third trench array. The substrate 1 includes multiple spaced capacitor regions 3, each capacitor region 3 comprising two first sub-capacitor regions 3a, four second sub-capacitor regions 3b, and eight third sub-capacitor regions 3c. The two first sub-capacitor regions 3a are located in the middle region of the capacitor region and are spaced apart along the X-direction. The four second sub-capacitor regions 3b and the eight third sub-capacitor regions 3c are located in the edge region of the capacitor region, with the four second sub-capacitor regions 3b respectively located at the four corners of the edge region. The eight third sub-capacitor regions 3c... Capacitor regions 3c are evenly distributed among the four second sub-capacitor regions 3b. Two adjacent third sub-capacitor regions 3c are arranged between every two adjacent second sub-capacitor regions 3b. The first trench array is located within the first sub-capacitor region 3a and includes multiple spaced first trenches 4a extending along the Y direction. The second trench array is located within the second sub-capacitor region 3b and includes multiple spaced second trenches 4b extending along the Y direction. The third trench array is located within the third sub-capacitor region 3c and includes multiple spaced third trenches 4c extending along the X direction.

[0114] As an example, referring again to 10, the semiconductor structure for fabricating a capacitor further includes an isolation layer 5 and a stacked layer 6 located on the isolation layer 5. The isolation layer 5 is located on the substrate 1 and covers the bottom and sidewalls of the first trench 4a, the second trench 4b and the third trench 4c. The stacked layer 6 fills the first trench 4a, the second trench 4b and the third trench 4c and includes alternately stacked conductive layers 61 and dielectric layers 62.

[0115] As an example, in the X and Y directions, the size of the first sub-capacitor region 3a is twice the size of the second sub-capacitor region 3b, and the size of the third sub-capacitor region 3c is the same as the size of the second sub-capacitor region 3b.

[0116] As an example, the length L5 of the first groove 4a ranges from 1 μm to 50 μm, the length L1 of the second groove 4b ranges from 1 μm to 50 μm, and the length L2 of the third groove 4c ranges from 1 μm to 50 μm.

[0117] As an example, the length L5 of the first groove 4a is twice the length L1 of the second groove 4b, and the length L2 of the third groove 4c is the same as the length L1 of the second groove 4b.

[0118] The semiconductor structure for fabricating capacitors in this embodiment includes three sub-capacitor regions with different trench arrays. The trench arrays in the first and second sub-capacitor regions are arranged in the same direction, while the trench arrays in the first and third sub-capacitor regions are arranged in different directions. By arranging the three sub-capacitor regions, the stress distribution at different locations on the wafer can be flexibly adjusted, and the stress in different regions can be adjusted in different areas, thereby eliminating the problem of uneven stress distribution.

[0119] In summary, the semiconductor structure for fabricating capacitors according to the present invention includes a substrate and a trench array. The substrate includes multiple spaced-apart capacitor regions, each capacitor region including multiple spaced-apart sub-capacitor regions arranged in an array. In both the X and Y directions, the size of each capacitor region is not less than four times the size of the smallest sub-capacitor region. The trench array is located within the sub-capacitor regions and includes multiple trenches. Multiple trenches within the same sub-capacitor region are spaced apart and have the same arrangement direction. Among the multiple sub-capacitor regions located in the same column or row, at least two sub-capacitor regions have different trench arrangement directions, and at least two adjacent sub-capacitor regions have the same trench arrangement direction. In any two adjacent sub-capacitor regions, the ratio of the trench length of one sub-capacitor region to the trench length of the other sub-capacitor region ranges from 0.25 to 4. The semiconductor structure for fabricating capacitors according to the present invention can flexibly adjust the stress distribution at different locations on the wafer, achieving zoned stress adjustment in different regions, thereby eliminating the problem of uneven stress distribution. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0120] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A semiconductor structure for fabricating capacitors, characterized in that, include: The substrate includes a plurality of spaced capacitor regions, each of which includes a plurality of spaced sub-capacitor regions arranged in an array. In both the X and Y directions, the size of each capacitor region is not less than four times the size of the smallest sub-capacitor region among the capacitor regions. A trench array, located in the sub-capacitor region and comprising multiple trenches, wherein the multiple trenches in the same sub-capacitor region are spaced apart and have the same arrangement direction, wherein in the multiple sub-capacitor regions located in the same column or row, at least two sub-capacitor regions have different trench arrangement directions, and at least two adjacent sub-capacitor regions have the same trench arrangement direction, wherein in any two adjacent sub-capacitor regions, the ratio of the trench length of one sub-capacitor region to the trench length of the other sub-capacitor region ranges from 0.25 to 4.

2. The semiconductor structure for fabricating a capacitor according to claim 1, characterized in that: It also includes an isolation layer and a stacked layer on the isolation layer, the isolation layer being located on the substrate and covering the bottom and sidewalls of the trench, the stacked layer filling the trench and including alternating stacked conductive and dielectric layers.

3. The semiconductor structure for fabricating a capacitor according to claim 1, characterized in that: The distance between two adjacent sub-capacitor regions is greater than the distance between two adjacent trenches in any one of the sub-capacitor regions.

4. The semiconductor structure for fabricating a capacitor according to claim 1, characterized in that: The length of the groove ranges from 1 μm to 50 μm.

5. The semiconductor structure for fabricating a capacitor according to claim 1, characterized in that: Among the multiple sub-capacitor regions located in the same column, at least two of the sub-capacitor regions have mutually perpendicular groove arrangement directions, or at least two of the sub-capacitor regions have the same groove arrangement direction.

6. The semiconductor structure for fabricating a capacitor according to claim 1, characterized in that: Among the multiple sub-capacitor regions located in the same row, at least two of the sub-capacitor regions have mutually perpendicular trench arrangement directions, or at least two of the sub-capacitor regions have the same trench arrangement direction.

7. The semiconductor structure for fabricating a capacitor according to claim 1, characterized in that: The capacitor region includes a central region and an edge region surrounding the central region. Among the sub-capacitor regions located in the central region of the capacitor region, at least two sub-capacitor regions have the same trench array.

8. The semiconductor structure for fabricating a capacitor according to claim 7, characterized in that: In each of the sub-capacitor regions located in the middle region of the capacitor region, the trench length corresponding to at least one of the sub-capacitor regions is greater than the trench length corresponding to each of the sub-capacitor regions in the edge region.

9. The semiconductor structure for fabricating a capacitor according to claim 1, characterized in that: Among the multiple sub-capacitor regions located in the same column or row, the number of sub-capacitor regions having the same trench array and arranged adjacent to each other does not exceed five.

10. A semiconductor structure for fabricating a capacitor, characterized in that, include: The substrate includes a plurality of spaced-apart capacitor regions, each capacitor region including two first sub-capacitor regions, four second sub-capacitor regions, and eight third sub-capacitor regions. The two first sub-capacitor regions are disposed in the middle region of the capacitor region and are spaced apart along the X direction. The four second sub-capacitor regions and the eight third sub-capacitor regions are disposed in the edge region of the capacitor region, with the four second sub-capacitor regions located at the four corners of the edge region. The eight third sub-capacitor regions are evenly distributed between the four second sub-capacitor regions, with two adjacent third sub-capacitor regions disposed between every two adjacent second sub-capacitor regions. The first trench array is located within the first sub-capacitor region, and the first trench array includes a plurality of first trenches spaced apart and extending along the Y direction. The second trench array is located in the second sub-capacitor region, and the second trench array includes a plurality of second trenches that are spaced apart and extend along the Y direction; The third trench array is located within the third sub-capacitor region, and the third trench array includes a plurality of spaced third trenches extending along the X direction.

11. The semiconductor structure for fabricating a capacitor according to claim 10, characterized in that: It also includes an isolation layer and a stacked layer on the isolation layer, the isolation layer being located on the substrate and covering the bottom and sidewalls of the first trench, the second trench and the third trench, the stacked layer filling the first trench, the second trench and the third trench and including alternately stacked conductive layers and dielectric layers.

12. The semiconductor structure for fabricating a capacitor according to claim 10, characterized in that: In the X and Y directions, the size of the first sub-capacitor region is twice the size of the second sub-capacitor region, and the size of the third sub-capacitor region is the same as the size of the second sub-capacitor region.

13. The semiconductor structure for fabricating a capacitor according to claim 10, characterized in that: The length of the first trench ranges from 1 μm to 50 μm, the length of the second trench ranges from 1 μm to 50 μm, and the length of the third trench ranges from 1 μm to 50 μm.

14. The semiconductor structure for fabricating a capacitor according to claim 10, characterized in that: The length of the first groove is twice the length of the second groove, and the length of the third groove is the same as the length of the second groove.

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