Array substrate and display panel

Abstract

The invention discloses an array substrate and a display panel, and belongs to the technical field of display, the array substrate comprises a common line and pixel units, and the common line extends along a first direction; the pixel unit comprises a first sub-pixel and a second sub-pixel, and the first sub-pixel comprises a first pixel electrode and a first pixel driving circuit; the second sub-pixel comprises a second pixel electrode and a second pixel driving circuit, the second pixel electrode and the first pixel electrode are arranged in the second direction, the second direction intersects with the first direction, and the first pixel driving circuit and the second pixel driving circuit are located between the first pixel electrode and the second pixel electrode; in one pixel unit, the common line is located between the first pixel electrode and the second pixel electrode and overlaps with the first pixel driving circuit and the second pixel driving circuit in the thickness direction of the array substrate, so that a first storage capacitor and a second storage capacitor are formed. The aperture opening ratio of the array substrate can be improved, so that the penetration rate of the display panel is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to an array substrate and a display panel. BACKGROUND

[0002] The liquid crystal display panel is formed by an array substrate, a liquid crystal layer and a counter substrate. The array substrate includes an opening area and a non-opening area. The opening area is used for setting pixel electrodes of each sub-pixel, and the non-opening area is used for setting scan lines, common lines and transistors of each sub-pixel. In the non-opening area, a storage capacitor is usually formed by an electrode of the transistor of each sub-pixel and the common line. In the storage capacitor, the spacing between the electrode of the transistor and the common line is the spacing between the two plates of the storage capacitor, and the overlapping area between the electrode of the transistor and the common line is the effective overlapping area between the two plates of the storage capacitor.

[0003] In order to increase the storage capacitor, in the related art, the setting area of the electrode of the transistor of each sub-pixel is increased. With the increase of the setting area of the electrode of each transistor, the area of the non-opening area is also increased. Since the overall size of the array substrate is constant, the area of the opening area is relatively reduced, which reduces the aperture ratio of the array substrate and causes the transmittance of the display panel to be reduced.

[0004] Therefore, it is necessary to provide a new technical solution to solve the above technical problems. SUMMARY

[0005] The purpose of the present application is to provide an array substrate and a display panel, which can improve the aperture ratio of the array substrate and thus improve the transmittance of the display panel.

[0006] To solve the above problems, the technical solution of the present application is as follows: In a first aspect, the present application provides an array substrate, comprising a common line and a pixel unit, wherein the common line extends along a first direction; The pixel unit comprises: a first sub-pixel comprising a first pixel electrode and a first pixel driving circuit; and a second sub-pixel comprising a second pixel electrode and a second pixel driving circuit, wherein the second pixel electrode is arranged along a second direction intersecting the first direction with the first pixel electrode, and the first pixel driving circuit and the second pixel driving circuit are located between the first pixel electrode and the second pixel electrode; In one pixel unit, one common line is located between the first pixel electrode and the second pixel electrode and overlaps with the first pixel driving circuit and the second pixel driving circuit in the thickness direction of the array substrate to form a first storage capacitor and a second storage capacitor.

[0007] In embodiments of the present application, the array substrate further comprises: a first data line extending along the second direction; and a second data line extending along the second direction and spaced apart from the first data line along the first direction, and the second data line and the first data line are provided with the pixel unit therebetween; the first pixel driving circuit comprises a first transistor, an input pole of the first transistor is electrically connected with the first data line, and an output pole of the first transistor is electrically connected with the first pixel electrode; the second pixel driving circuit comprises a second transistor, an input pole of the second transistor is electrically connected with the second data line, and an output pole of the second transistor is electrically connected with the second pixel electrode; in one of the pixel units, a part of the common line between the first pixel electrode and the second pixel electrode overlaps with a part of the output pole of the first transistor in the thickness direction of the array substrate to form the first storage capacitor, and another part of the common line between the first pixel electrode and the second pixel electrode overlaps with a part of the output pole of the second transistor in the thickness direction of the array substrate to form the second storage capacitor.

[0008] In embodiments of the present application, the array substrate further comprises a scan line extending along the first direction; in one of the pixel units, one of the scan lines is located between the first pixel electrode and the second pixel electrode and is electrically connected with the control pole of the first transistor and the control pole of the second transistor respectively, and the scan line is spaced apart from the common line along the second direction.

[0009] In embodiments of the present application, the array substrate comprises a first pixel column, the first pixel column comprises a plurality of the pixel units arranged along the second direction, and one of the first pixel columns is located between the adjacent first data line and the second data line; in one of the pixel units, the distance from the side of the first pixel electrode close to the second pixel electrode to the side of the second pixel electrode close to the first pixel electrode is a first interval; in two adjacent pixel units in the first pixel column, the distance from the side of the first pixel unit close to the second pixel unit to the side of the second pixel unit close to the first pixel unit is a second interval, and the second interval is smaller than the first interval.

[0010] In embodiments of the present application, the array substrate further comprises a common electrode, and the common electrode is electrically connected with the common line; In the first pixel column, a part of the common electrode is arranged between two adjacent pixel units.

[0011] In the embodiments of the present application, the array substrate further comprises a second pixel column, the second pixel column comprising a plurality of pixel units arranged along the second direction; The first data line, the first pixel column, the second data line, and the second pixel column are alternately arranged along the first direction.

[0012] In the embodiments of the present application, the pixel units of the first pixel column are first pixel units, and the pixel units of the second pixel column are second pixel units; The first pixel electrodes of the first pixel units and the second pixel electrodes of the second pixel units are alternately arranged along the first direction; The second pixel electrodes of the first pixel units and the first pixel electrodes of the second pixel units are alternately arranged along the first direction.

[0013] In the embodiments of the present application, the scan line comprises a first scan line; The first scan line comprises a first wide line and a first thin line alternately connected along the first direction, the width of the first wide line being greater than the width of the first thin line; In one of the first pixel units, the first wide line is located between the first pixel electrode and the second pixel electrode, and the first wide line is multiplexed as the control electrode of the first transistor and the control electrode of the second transistor; The first thin line is located between two adjacent second pixel units along the second direction.

[0014] In the embodiments of the present application, the common line is arranged in the same layer as the scan line and is spaced apart from the scan line; The common line comprises a first common line; The first common line comprises a second wide line and a second thin line alternately connected along the first direction, the width of the second wide line being greater than the width of the second thin line; In the first pixel unit, the second wide line is located between the first pixel electrode and the second pixel electrode, and the second wide line respectively overlaps a part of the output electrode of the first transistor and a part of the output electrode of the second transistor in the thickness direction of the array substrate to form the first storage capacitor and the second storage capacitor; The first thin line is located between two adjacent second pixel units along the second direction.

[0015] In an embodiment of the present application, in a plan view of the array substrate, an average width of the second wide line is greater than an average width of the first wide line.

[0016] In an embodiment of the present application, in a plan view of the array substrate, a recess is formed on a side of the first wide line close to the second wide line, a protrusion is formed on a side of the second wide line close to the first wide line, and a part of the protrusion extends into the recess; At least a part of the protrusion respectively overlaps with a part of the output of the first transistor and a part of the output of the second transistor in a thickness direction of the array substrate to form the first storage capacitor and the second storage capacitor.

[0017] In an embodiment of the present application, the first wide line comprises a first gate portion, a connection portion and a second gate portion connected in sequence along the first direction; The first gate portion is formed as the control of the first transistor, and the second gate portion is formed as the control of the second transistor; In a plan view of the array substrate, the first gate portion is disposed beyond the connection portion on a side close to the second wide line, the second gate portion is disposed beyond the connection portion on a side close to the second wide line, and a side of the first gate portion close to the second wide line, a side of the connection portion close to the second wide line and a side of the second gate portion close to the second wide line form the recess.

[0018] In an embodiment of the present application, the output of the first transistor comprises a first output portion and a second output portion connected in sequence, the first output portion extends along the second direction and respectively overlaps with the first gate portion and the second wide line in a thickness direction of the array substrate, the second output portion overlaps with the second wide line in the thickness direction of the array substrate, the second output portion extends along the first direction, and a width of the second output portion increases along a direction away from the first output portion; The output of the second transistor comprises a third output portion and a fourth output portion, the third output portion extends along the second direction and respectively overlaps with the second gate portion and the second wide line in a thickness direction of the array substrate, the fourth output portion overlaps with the second wide line in the thickness direction of the array substrate, the fourth output portion extends along the second direction, and a width of the fourth output portion increases along a direction away from the third output portion.

[0019] In an embodiment of the present application, the first pixel unit further comprises a first connection electrode and a second connection electrode; In one of the first pixel units, The first connection electrode is connected to a side of the first pixel electrode close to the second pixel electrode and is electrically connected to the output terminal of the first transistor, and the first wide line, the second wide line and the first connection electrode overlap in the thickness direction of the array substrate; The second connection electrode is connected to a side of the second pixel electrode close to the first pixel electrode and is electrically connected to the output terminal of the second transistor. In a plan view of the array substrate, the area of the output terminal of the first transistor is less than or equal to the area of the output terminal of the second transistor.

[0020] In an embodiment of the present application, in one of the first pixel units, a part of the second pixel electrode close to the first pixel electrode overlaps with the second wide line in the thickness direction of the array substrate.

[0021] In a second aspect, the present application provides a display panel, comprising an array substrate, the array substrate comprising a common line and a pixel unit, the common line extending along a first direction; The pixel unit comprises: a first sub-pixel comprising a first pixel electrode and a first pixel driving circuit; and a second sub-pixel comprising a second pixel electrode and a second pixel driving circuit, the second pixel electrode being arranged along a second direction with the first pixel electrode, the second direction intersecting the first direction, the first pixel driving circuit and the second pixel driving circuit being located between the first pixel electrode and the second pixel electrode; In one of the pixel units, one of the common lines is located between the first pixel electrode and the second pixel electrode and overlaps with the first pixel driving circuit and the second pixel driving circuit in the thickness direction of the array substrate to form a first storage capacitor and a second storage capacitor.

[0022] In the present application, the area where the first pixel electrode and the second pixel electrode are located is an opening area, and the area where the first pixel driving circuit and the second pixel driving circuit are located is a non-opening area. In one pixel unit of the present application, by arranging the first pixel driving circuit and the second pixel driving circuit between the first pixel electrode and the second pixel electrode, the non-opening area of the two adjacent sub-pixels is arranged between the two opening areas of the two adjacent sub-pixels. Compared with the scheme in the related art that the two adjacent sub-pixels have two opening areas and two non-opening areas, on the one hand, the present application combines the two non-opening areas in the related art into one non-opening area, and on the other hand, the present application makes the adjacent first sub-pixel and the second sub-pixel share the same common line and respectively form the first storage capacitor and the second storage capacitor, thereby relatively reducing the area of the non-opening area in the sub-pixel and relatively increasing the area of the opening area, improving the array substrate transmittance and improving the transmittance of the display panel. At the same time, the common line located between the adjacent first pixel electrode and the second pixel electrode forms the first storage capacitor and the second storage capacitor with the first pixel driving circuit and the second pixel driving circuit, respectively, which can ensure the stability of the storage capacitor of the first sub-pixel and the second sub-pixel of the present application, thereby improving the display effect. BRIEF DESCRIPTION OF DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0024] In order to more completely understand the present application and its beneficial effects, the following will be described in conjunction with the drawings, wherein the same reference numerals in the following description represent the same parts.

[0025] Figure 1 is a plan view of an embodiment of the array substrate of the present application; Figure 2 is an equivalent circuit diagram of the array substrate shown in Figure 1 Figure 3 is a plan view of another embodiment of the array substrate of the present application; Figure 4 is an equivalent circuit diagram of the array substrate shown in Figure 3 is an enlarged view at A; Figure 5 is a color schematic view of Figure 4 Figure 6 is an enlarged view at B; Figure 4 Figure 7 is a plan view of still another embodiment of the array substrate of the present application;​​​ Figure 8 is Figure 6 enlarged view at E in the middle; Figure 9 is Figure 8 a color schematic view.

[0026] BRIEF DESCRIPTION OF DRAWINGS 100, array substrate; X, first direction; Y, second direction; H1, first via; H2, second via; H3, third via; 10, pixel unit; 11, first pixel unit; 12, second pixel unit; 20, first sub-pixel; 21, first pixel electrode; 22, first pixel driving circuit; T1, first transistor; T1D1, first output part; T1D2, second output part; 23, first connection electrode; 30, second sub-pixel; 31, second pixel electrode; 32, second pixel driving circuit; T2, second transistor; T2D1, third output part; T2D2, fourth output part; 33, second connection electrode; 40, common electrode; Com, common line; Com1, first common line; C11, second wide line; C111, protruding part; C12, second thin line; Com2, second common line; Data1, first data line; Data2, second data line; Cst1, first storage capacitor; Cst2, second storage capacitor; Scan, scan line; Scan1, first scan line; S11, first wide line; S111, recessed part; S112, first gate part; S113, connection part; S114, second gate part; S12, first thin line; Scan2, second scan line; PC1, first pixel column; D1, first interval; D2, second interval; PC2, second pixel column. DETAILED DESCRIPTION

[0027] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the present application.

[0028] In the related art, a pixel unit includes a first sub-pixel and a second sub-pixel. The first sub-pixel includes a first pixel electrode and a first pixel driving circuit. The second sub-pixel includes a second pixel electrode and a second pixel driving circuit. In a plan view of the array substrate, the first pixel driving circuit, the first pixel electrode, the second pixel driving circuit, and the second pixel electrode are arranged alternately along a column direction (or a row direction). In order to increase the storage capacitance of the first sub-pixel and the second sub-pixel, the array substrate is further provided with two common lines in the region of one pixel unit. One common line overlaps the first pixel driving circuit to form a first storage capacitance. The other common line overlaps the second pixel driving circuit to form a second storage capacitance. In the related art, the region where the first pixel electrode and the second pixel electrode are located is an opening region, and the region where the first pixel driving circuit and the second pixel driving circuit are located is a non-opening region. In one pixel unit in the related art, there are two opening regions and two non-opening regions, and in the two non-opening regions, a total of two common lines are arranged, and the region where the common lines are located is also a non-opening region, which causes the area of the non-opening region in one pixel unit to be relatively large, and the area of the opening region to be relatively small, resulting in a decrease in the aperture ratio of the array substrate and a decrease in the transmittance of the display panel.

[0029] In the related art, each non-opening region is provided with one scan line. In one pixel unit, two scan lines are usually arranged, one of which is electrically connected to the first pixel driving circuit, and the other of which is electrically connected to the second pixel driving circuit. The region where the scan lines are located is also a non-opening region.

[0030] The present application provides a display panel. The display panel can be applied to a display device. The display device can be a tablet computer, an electronic reader, an electronic display screen, a notebook computer, a mobile phone, an augmented reality (AR) \ virtual reality (VR) device, a media player, a wearable device, a digital camera, a car navigation device, etc.

[0031] Optionally, the display panel is a liquid crystal display panel. The liquid crystal display panel includes an array substrate 100 and an opposite substrate arranged oppositely, and a liquid crystal layer between the array substrate 100 and the opposite substrate.

[0032] Optionally, the present application provides an array substrate 100, which includes a common line Com and a pixel unit 10. The common line Com extends along a first direction X.

[0033] The pixel unit 10 includes one first sub-pixel 20 and one second sub-pixel 30.

[0034] The first sub-pixel 20 includes a first pixel electrode 21 and a first pixel driving circuit 22.

[0035] The second sub-pixel 30 comprises a second pixel electrode 31 and a second pixel driving circuit 32.

[0036] The second pixel electrode 31 is arranged along a second direction Y with the first pixel electrode 21. The second direction Y intersects the first direction X. The first pixel driving circuit 22 and the second pixel driving circuit 32 are located between the first pixel electrode 21 and the second pixel electrode 31.

[0037] In one pixel unit 10, a common line Com is located between the first pixel electrode 21 and the second pixel electrode 31 and overlaps the first pixel driving circuit 22 and the second pixel driving circuit 32 in the thickness direction of the array substrate 100 to form a first storage capacitor Cst1 and a second storage capacitor Cst2.

[0038] In the present embodiment, the region where the first pixel electrode 21 and the second pixel electrode 31 are located is an opening region, and the region where the first pixel driving circuit 22 and the second pixel driving circuit 32 are located is a non-opening region. In one pixel unit 10 of the present embodiment, by arranging the first pixel driving circuit 22 and the second pixel driving circuit 32 between the first pixel electrode 21 and the second pixel electrode 31, the non-opening regions of the two adjacent sub-pixels are arranged between the two opening regions of the two adjacent sub-pixels. Compared with the scheme in the related art that the two adjacent sub-pixels have two opening regions and two non-opening regions, on the one hand, the present embodiment combines the two non-opening regions in the related art into one non-opening region, and on the other hand, the present embodiment makes the adjacent first sub-pixel 20 and the second sub-pixel 30 share the same common line Com to form the first storage capacitor Cst1 and the second storage capacitor Cst2 respectively, thereby relatively reducing the area of the non-opening region in the sub-pixel and relatively increasing the area of the opening region, improving the transmittance of the array substrate 100 and improving the transmittance of the display panel. At the same time, the common line Com located between the adjacent first pixel electrode 21 and the second pixel electrode 31 forms the first storage capacitor Cst1 and the second storage capacitor Cst2 with the first pixel driving circuit 22 and the second pixel driving circuit 32 respectively, which can ensure the stability of the storage capacitors of the first sub-pixel 20 and the second sub-pixel 30 in the present embodiment, thereby improving the display effect.

[0039] Please refer to Figure 2 Optionally, the array substrate 100 further comprises a first data line Data1 and a second data line Data2.

[0040] The first data line Data1 extends along the second direction Y.

[0041] The second data line Data2 extends along the second direction Y and is arranged apart from the first data line Data1 along the first direction X. The pixel unit 10 is arranged between the second data line Data2 and the first data line Data1.

[0042] The first pixel driving circuit 22 includes a first transistor T1. An input terminal of the first transistor T1 is electrically connected with the first data line Data1. An output terminal of the first transistor T1 is electrically connected with the first pixel electrode 21.

[0043] The second pixel driving circuit 32 includes a second transistor T2, an input terminal of the second transistor T2 is electrically connected with the second data line Data2. An output terminal of the second transistor T2 is electrically connected with the second pixel electrode 31.

[0044] In one pixel unit 10, a part of the common line Com between the first pixel electrode 21 and the second pixel electrode 31 overlaps with a part of the output terminal of the first transistor T1 in the thickness direction of the array substrate 100, to form the first storage capacitor Cst1.

[0045] In one pixel unit 10, another part of the common line Com between the first pixel electrode 21 and the second pixel electrode 31 overlaps with a part of the output terminal of the second transistor T2 in the thickness direction of the array substrate 100, to form the second storage capacitor Cst2.

[0046] In the present embodiment, in one pixel unit 10, one common line Com is arranged between the first pixel electrode 21 and the second pixel electrode 31. A part of the common line Com overlaps with the output terminal of the first transistor T1, to form the first storage capacitor Cst1. Another part of the common line Com overlaps with the output terminal of the second transistor T2, to form the second storage capacitor Cst2. Compared with the prior art, in which two common lines Com are needed in one pixel unit 10, the present embodiment only needs one common line Com in one pixel unit 10. Since the area where the common line Com is located is a non-opening area, the present embodiment relatively reduces the area of the non-opening area by reducing one common line Com, so that the area of the opening area is relatively increased. On the premise of ensuring the stability of the storage capacitors of the first sub-pixel 20 and the second sub-pixel 30, the aperture ratio of the array substrate 100 is improved, so that the transmittance and display effect of the display panel are improved.

[0047] Optionally, the display panel of the present application is an in plane switching (IPS) display panel. The array substrate 100 further includes a common electrode 40. The common electrode 40 forms a first liquid crystal capacitor Clc1 with the first pixel electrode 21. The common electrode 40 forms a second liquid crystal capacitor Clc2 with the second pixel electrode 31. The common electrode 40 is electrically connected with the common line Com.

[0048] Please refer to Figure 1Optionally, the array substrate 100 further comprises a scan line Scan. The scan line Scan extends along the first direction X.

[0049] Referring to Figure 2 In one pixel unit 10, one scan line Scan is located between the first pixel electrode 21 and the second pixel electrode 31, and is electrically connected to the control electrode of the first transistor T1 and the control electrode of the second transistor T2 respectively. The scan line Scan is arranged along the second direction Y with the common line Com.

[0050] In the embodiment, in one pixel unit 10, the first sub-pixel 20 and the second sub-pixel 30 adjacent to each other share one scan line Scan. Compared with the prior art in which two scan lines Scan are arranged in one pixel unit 10, the embodiment only needs to arrange one scan line Scan in one pixel unit 10. Since the area where the scan line Scan is located is a non-opening area, the embodiment relatively reduces the area of the non-opening area by reducing one scan line Scan, relatively increases the area of the opening area, improves the aperture ratio of the array substrate 100, and thus improves the transmittance of the display panel.

[0051] Referring to Figure 3 Optionally, the array substrate 100 comprises a first pixel column PC1. The first pixel column PC1 comprises a plurality of pixel units 10 arranged along the second direction Y. One first pixel column PC1 is located between the adjacent first data line Data1 and the second data line Data2.

[0052] In one pixel unit 10, the distance from the side of the first pixel electrode 21 close to the second pixel electrode 31 to the side of the second pixel electrode 31 close to the first pixel electrode 21 is a first interval D1.

[0053] In the adjacent two pixel units 10 in the first pixel column PC1, the distance from the side of the first pixel unit 10 close to the second pixel unit 10 to the side of the second pixel unit 10 close to the first pixel unit 10 is a second interval D2. The second interval D2 is smaller than the first interval D1.

[0054] In the embodiment, since the first pixel driving circuit 22, the second pixel driving circuit 32, the scan line Scan and the common line Com are arranged between the first pixel electrode 21 and the second pixel electrode 31, the first pixel electrode 21 and the second pixel electrode 31 are a non-opening area, and the first interval D1 is the length of the non-opening area inside the pixel unit 10 in the second direction Y.

[0055] The length of the region without the pixel electrode between two adjacent pixel units 10 in the second direction Y is a second interval D2. In this embodiment, the first pixel driving circuit 22, the second pixel driving circuit 32, the scan line Scan and the common line Com in one pixel unit 10 are arranged between the first pixel electrode 21 and the second pixel electrode 31, thereby reducing the second interval D2 between two adjacent pixel units 10, reducing the area of the non-opening region between adjacent pixel units 10, relatively increasing the area of the opening region of the array substrate 100, improving the aperture ratio of the array substrate 100, and thereby improving the transmittance of the display panel.

[0056] Referring to Figure 3 Optionally, the array substrate 100 further includes a second pixel column PC2. The second pixel column PC2 includes a plurality of pixel units 10 arranged along the second direction Y.

[0057] The first data line Data1, the first pixel column PC1, the second data line Data2 and the second pixel column PC2 are alternately arranged along the first direction X.

[0058] In this embodiment, the arrangement sequence of the internal sub-pixels of the second pixel column PC2 is the same as that of the first pixel column PC1, and therefore the second pixel column PC2 can also reduce the area of the non-opening region between adjacent pixel units 10 in the second direction Y. The first pixel column PC1 and the second pixel column PC2 are alternately arranged along the first direction X, which can further increase the area of the opening region of the array substrate 100, further improve the aperture ratio of the array substrate 100, and thereby further improve the transmittance of the display panel.

[0059] Referring to Figure 3 Optionally, the pixel unit 10 of the first pixel column PC1 is a first pixel unit 11, and the pixel unit 10 of the second pixel column PC2 is a second pixel unit 12.

[0060] The first pixel electrode 21 of the first pixel unit 11 and the second pixel electrode 31 of the second pixel unit 12 are alternately arranged along the first direction X.

[0061] The second pixel electrode 31 of the first pixel unit 11 and the first pixel electrode 21 of the second pixel unit 12 are alternately arranged along the first direction X.

[0062] In this embodiment, the non-opening region of the first pixel unit 11 and the non-opening region of the second pixel unit 12 in adjacent first pixel column PC1 and second pixel column PC2 are arranged in the second direction Y.

[0063] At this time, when any one of the common lines Com is located between the first pixel electrode 21 and the second pixel electrode 31 of the first pixel unit 11, the common line Com only overlaps with the output terminal of the first transistor T1 and the output terminal of the second transistor T2 of the first pixel unit 11, and does not overlap with the output terminal of the first transistor T1 and the output terminal of the second transistor T2 of the second pixel unit 12, so that the load (RC Loading) of the common line Com can be reduced.

[0064] Similarly, when any one of the common lines Com is located between the first pixel electrode 21 and the second pixel electrode 31 of the second pixel unit 12, the common line Com only overlaps with the output terminal of the first transistor T1 and the output terminal of the second transistor T2 of the second pixel unit 12, and does not overlap with the output terminal of the first transistor T1 and the output terminal of the second transistor T2 of the first pixel unit 11, so that the load of the common line Com can be reduced.

[0065] Similarly, when any one of the scan lines Scan is located between the first pixel electrode 21 and the second pixel electrode 31 of the first pixel unit 11, the scan line Scan only electrically connects with the control terminal of the first transistor T1 and the control terminal of the second transistor T2 of the first pixel unit 11, and does not electrically connect with the control terminal of the first transistor T1 and the control terminal of the second transistor T2 of the second pixel unit 12, so that the load of the scan line Scan can be reduced.

[0066] Similarly, when any one of the scan lines Scan is located between the first pixel electrode 21 and the second pixel electrode 31 of the second pixel unit 12, the scan line Scan only electrically connects with the control terminal of the first transistor T1 and the control terminal of the second transistor T2 of the second pixel unit 12, and does not electrically connect with the control terminal of the first transistor T1 and the control terminal of the second transistor T2 of the first pixel unit 11, so that the load of the scan line Scan can be reduced.

[0067] In summary, the arrangement mode of the array substrate 100 can reduce the load of each common line Com and scan line Scan, reduce power consumption, reduce the delay of data transmission, and improve display effect.

[0068] Please refer to Figure 4 Optionally, in the first pixel column PC1, a part of the common electrode 40 is arranged between the two adjacent pixel units 10.

[0069] In the embodiment, the display panel is a plane switching type display panel, and the common electrode 40 is arranged in the same layer as the first pixel electrode 21 and the second pixel electrode 31. The common electrode 40 is made of the same material as the first pixel electrode 21 and the second pixel electrode 31. For the sake of distinguishing the common electrode 40 from the first pixel electrode 21 and the second pixel electrode 31, please refer to Figure 5 , the orange pattern is the pattern of the common electrode 40, and the yellow patterns are the patterns of the first pixel electrode 21 and the second pixel electrode 31 respectively.

[0070] In the embodiment, the common electrode 40 between the two adjacent pixel units 10 can form the second liquid crystal capacitor Clc2 with the second pixel electrode 31 of one of the pixel units 10 and form the first liquid crystal capacitor Clc1 with the first pixel electrode 31 of the other pixel unit 10.

[0071] In the embodiment, the common line Com is arranged in a layer different from the common electrode 40, and at least one insulating layer is arranged between the common line Com and the common electrode 40. The first via hole H1 is arranged in the insulating layer, and the common electrode 40 is electrically connected to the common line Com through the first via hole H1.

[0072] Please refer to Figure 6 Optionally, the scan line Scan includes a first scan line Scan1.

[0073] The first scan line Scan1 includes first wide lines S11 and first thin lines S12 alternately connected along the first direction X. The width of the first wide line S11 is greater than the width of the first thin line S12.

[0074] In one first pixel unit 11, the first wide line S11 is located between the first pixel electrode 21 and the second pixel electrode 31. The first wide line S11 is multiplexed as the control electrode of the first transistor T1 and the control electrode of the second transistor T2. The first thin line S12 is located between two adjacent second pixel units 12 along the second direction Y.

[0075] According to the above embodiment, when the first scan line Scan1 is located between the first pixel electrode 21 and the second pixel electrode 31 of the first pixel unit 11, the first scan line Scan1 is only electrically connected to the control electrode of the first transistor T1 and the control electrode of the second transistor T2 of the first pixel unit 11, and is not electrically connected to the control electrode of the first transistor T1 and the control electrode of the second transistor T2 of the second pixel unit 12, so that the load of the first scan line Scan1 can be reduced.

[0076] Therefore, in the embodiment, the first scan line Scan1 includes a first wide line S11 and a first thin line S12. The first wide line S11 is located between the first pixel electrode 21 and the second pixel electrode 31 of the first pixel unit 11. Since the first wide line S11 is multiplexed as the control electrode of the first transistor T1 and the control electrode of the second transistor T2, the width of the first wide line S11 in the second direction Y is relatively large. The first thin line S12 is located between two adjacent second pixel units 12 in the second direction Y. The first thin line S12 does not need to be multiplexed as the control electrode of the transistor, and the width of the first thin line S12 in the second direction Y can be reduced. The width of the first wide line S11 is greater than the width of the first thin line S12. Since the area of the non-opening region of the array substrate 100 is relatively reduced and the area of the opening region of the array substrate 100 is relatively increased when the width of the first thin line S12 is reduced, the aperture ratio of the array substrate 100 can be improved, and the transmittance of the display panel can be improved.

[0077] Optionally, the common line Com is arranged in the same layer as the scan line Scan and is spaced apart.

[0078] In the process of forming the array substrate 100, the common line Com and the scan line Scan are arranged in the same layer. The common line Com and the scan line Scan can be formed in one process, thereby improving the production efficiency, reducing the production cost, and reducing the thickness of the array substrate 100.

[0079] Please refer to Figure 6 Optionally, the common line Com includes a first common line Com1.

[0080] The first common line Com1 includes a second wide line C11 and a second thin line C12 alternately connected in the first direction X. The width of the second wide line C11 is greater than the width of the second thin line C12.

[0081] In the first pixel unit 11, the second wide line C11 is located between the first pixel electrode 21 and the second pixel electrode 31. The second wide line C11 respectively overlaps a part of the output electrode of the first transistor T1 and a part of the output electrode of the second transistor T2 in the thickness direction of the array substrate 100, so as to form the first storage capacitor Cst1 and the second storage capacitor Cst2.

[0082] The first thin line S12 is located between two adjacent second pixel units 12 in the second direction Y.

[0083] According to the above embodiment, when the first common line Com1 is located between the first pixel electrode 21 and the second pixel electrode 31 of the first pixel unit 11, the first common line Com1 only overlaps with the output terminal of the first transistor T1 and the output terminal of the second transistor T2 of the first pixel unit 11, and does not overlap with the output terminal of the first transistor T1 and the output terminal of the second transistor T2 of the second pixel unit 12, so that the load of the first common line Com1 can be reduced.

[0084] Therefore, in the embodiment, the first common line Com1 includes a second wide line C11 and a second thin line C12. The second wide line C11 is located between the first pixel electrode 21 and the second pixel electrode 31 of the first pixel unit 11. Since a part of the second wide line C11 overlaps with the output terminal of the first transistor T1 to form the first storage capacitor Cst1, and another part of the second wide line C11 overlaps with the output terminal of the second transistor T2 to form the second storage capacitor Cst2, the capacitance value of the storage capacitor is related to the effective overlapping area of the second wide line C11, and therefore, the width of the second wide line C11 in the second direction Y needs to be increased to ensure that the capacitance values of the first storage capacitor Cst1 and the second storage capacitor Cst2 meet the use requirements of the array substrate 100. The second thin line C12 is located between two adjacent second pixel units 12 in the second direction Y. The second thin line C12 does not need to overlap with the output terminal of the transistor to form the storage capacitor, and the width of the second thin line C12 in the second direction Y can be reduced. The width of the second wide line C11 is greater than the width of the second thin line C12. Since the area where the second thin line C12 is located is a non-opening area, when the width of the second thin line C12 is reduced, the area of the non-opening area of the array substrate 100 is relatively reduced, and the area of the opening area of the array substrate 100 is relatively increased. The embodiment can improve the aperture ratio of the array substrate 100, thereby improving the transmittance of the display panel.

[0085] Please refer to Figure 7 Optionally, the scan line Scan further includes a second scan line Scan2.

[0086] The second scan line Scan2 includes third thin lines and third wide lines alternately connected in the first direction X, and the width of the third wide line is greater than the width of the third thin line.

[0087] In one second pixel unit 12, the third wide line is located between the first pixel electrode 21 and the second pixel electrode 31. The third wide line is multiplexed as the control terminal of the first transistor T1 and the control terminal of the second transistor T2.

[0088] The third thin line is located between two adjacent first pixel units 11 in the second direction Y.

[0089] According to the analysis of the foregoing embodiment, when the second scan line Scan2 is located between the first pixel electrode 21 and the second pixel electrode 31 of the second pixel unit 12, the second scan line Scan2 is only electrically connected to the control electrode of the first transistor T1 and the control electrode of the second transistor T2 of the second pixel unit 12, and is not electrically connected to the control electrode of the first transistor T1 and the control electrode of the second transistor T2 of the first pixel unit 11, so that the load of the second scan line Scan2 can be reduced.

[0090] Therefore, in the embodiment, the second scan line Scan2 includes a third wide line and a third thin line. The third wide line is located between the first pixel electrode 21 and the second pixel electrode 31 of the second pixel unit 12. Since the third wide line needs to be multiplexed as the control electrode of the first transistor T1 and the control electrode of the second transistor T2, the width of the third wide line in the second direction Y is relatively large. The third thin line is located between two adjacent first pixel units 11 in the second direction Y. The third thin line does not need to be multiplexed as the control electrode of the transistor, and the width of the third thin line in the second direction Y can be reduced. Since the area where the third thin line is located is a non-opening area, when the width of the third thin line is reduced, the area of the non-opening area of the array substrate 100 is relatively reduced, and the area of the opening area of the array substrate 100 is relatively increased. The embodiment can improve the aperture ratio of the array substrate 100, thereby improving the transmittance of the display panel.

[0091] Please refer to Figure 7 Alternatively, the common line Com further includes a second common line Com2. The common line Com includes fourth thin lines and fourth wide lines which are alternately connected in the first direction X, and the width of the fourth wide line is greater than the width of the fourth thin line.

[0092] In a second pixel unit 12, the fourth wide line is located between the first pixel electrode 21 and the second pixel electrode 31. The fourth wide line respectively overlaps a part of the output electrode of the first transistor T1 and a part of the output electrode of the second transistor T2 in the thickness direction of the array substrate 100, so as to form a first storage capacitor Cst1 and a second storage capacitor Cst2.

[0093] The fourth thin line is located between two adjacent first pixel units 11 in the second direction Y.

[0094] Alternatively, the first scan line Scan1, the first common line Com1, the second scan line Scan2, and the second common line Com2 are alternately arranged in the second direction Y.

[0095] In the area where the first pixel column PC1 is located, the first wide line S11, the second wide line C11, the third thin line, and the fourth thin line are alternately arranged in the second direction Y.

[0096] In the region where the second pixel column PC2 is located, the first thin line S12, the second thin line C12, the third wide line and the fourth wide line are arranged alternately in the second direction Y.

[0097] According to the foregoing embodiment analysis, when the second common line Com2 is located between the first pixel electrode 21 and the second pixel electrode 31 of the second pixel unit 12, the second common line Com2 only overlaps with the output terminal of the first transistor T1 and the output terminal of the second transistor T2 of the second pixel unit 12, and does not overlap with the output terminal of the first transistor T1 and the output terminal of the second transistor T2 of the first pixel unit 11, so that the load of the second common line Com2 can be reduced.

[0098] Therefore, in the embodiment, the second common line Com2 includes a fourth wide line and a fourth thin line. The fourth wide line is located between the first pixel electrode 21 and the second pixel electrode 31 of the second pixel unit 12. Since a part of the fourth wide line overlaps with the output terminal of the first transistor T1 to form the first storage capacitor Cst1, and another part of the fourth wide line overlaps with the output terminal of the second transistor T2 to form the second storage capacitor Cst2, the capacitance value of the storage capacitor is related to the effective overlapping area of the fourth wide line. Therefore, the width of the fourth wide line in the second direction Y needs to be increased to ensure that the capacitance values of the first storage capacitor Cst1 and the second storage capacitor Cst2 meet the use requirements of the array substrate 100. The fourth thin line is located between two adjacent first pixel units 11 in the second direction Y. The fourth thin line does not need to overlap with the output terminal of the transistor to form the storage capacitor, and the width of the fourth thin line in the second direction Y can be reduced. Since the region where the fourth thin line is located is a non-opening region, when the width of the fourth thin line is reduced, the area of the non-opening region of the array substrate 100 is relatively reduced, and the area of the opening region of the array substrate 100 is relatively increased. The embodiment can improve the aperture ratio of the array substrate 100, thereby improving the transmittance of the display panel.

[0099] Please refer to Figure 8 Optionally, in the plan view of the array substrate 100, the average width of the second wide line C11 is greater than the average width of the first wide line S11.

[0100] In the present embodiment, in addition to the first wide line S11 being multiplexed as a part of the output of the first transistor T1 and the other part of the output of the second transistor T2, the remaining part of the first wide line S11 can be reduced in width in the second direction Y. In the case where the area of the non-opening region between the first pixel electrode 21 and the second pixel electrode 31 is not changed, due to the reduction in width of the remaining part of the first wide line S11, the width of the second wide line C11 can be increased. The capacitance values of the first storage capacitor Cst1 and the second storage capacitor Cst2 are related to the effective overlapping area of the second wide line C11, and when the width of the second wide line C11 is increased, the first storage capacitor Cst1 and the second storage capacitor Cst2 are also improved. The present embodiment can achieve the increase of the first storage capacitor Cst1 and the second storage capacitor Cst2 without increasing the area of the non-opening region, improve the display effect of the array substrate 100, and do not reduce the aperture ratio of the array substrate 100 and the transmittance of the display panel.

[0101] Referring to Figure 8 Optionally, in the plan view of the array substrate 100, a recessed portion S111 is formed on the side of the first wide line S11 close to the second wide line C11. A protruding portion C111 is formed on the side of the second wide line C11 close to the first wide line S11. Part of the protruding portion C111 extends into the recessed portion S111.

[0102] At least part of the protruding portion C111 respectively overlaps with a part of the output of the first transistor T1 and a part of the output of the second transistor T2 in the thickness direction of the array substrate 100, to form the first storage capacitor Cst1 and the second storage capacitor Cst2.

[0103] In the present embodiment, the recessed portion S111 is formed on the side of the first wide line S11 close to the second wide line C11, to reduce the width of the remaining part of the first wide line S11 in the second direction Y. The protruding portion C111 is formed on the side of the second wide line C11 close to the first wide line S11, to increase the width of the second wide line C11 without changing the area of the non-opening region. The present embodiment can achieve the increase of the first storage capacitor Cst1 and the second storage capacitor Cst2 without increasing the area of the non-opening region, improve the display effect of the array substrate 100, and do not reduce the aperture ratio of the array substrate 100 and the transmittance of the display panel.

[0104] Referring to Figure 9 Optionally, the first wide line S11 includes a first gate portion S112, a connecting portion S113, and a second gate portion S114 connected in sequence along the first direction X.

[0105] The first gate portion S112 is formed as the control electrode of the first transistor T1. The second gate portion S114 is formed as the control electrode of the second transistor T2.

[0106] In the plan view of the array substrate 100, the first gate portion S112 is disposed beyond the connecting portion S113 in the side close to the second wide line C11. The second gate portion S114 is disposed beyond the connecting portion S113 in the side close to the second wide line C11. The first gate portion S112 in the side close to the second wide line C11, the connecting portion S113 in the side close to the second wide line C11, and the second gate portion S114 in the side close to the second wide line C11 form a recessed portion S111.

[0107] In the present embodiment, the connecting portion S113 neither serves as the control electrode of the first transistor T1 nor serves as the control electrode of the second transistor T2, and thus the width of the connecting portion S113 in the second direction Y can be reduced, so that the first gate portion S112 is disposed beyond the connecting portion S113 in the side close to the second wide line C11, and the second gate portion S114 is disposed beyond the connecting portion S113 in the side close to the second wide line C11, to form the recessed portion S111. In the present embodiment, the design of the recessed portion S111 can increase the first storage capacitor Cst1 and the second storage capacitor Cst2 without increasing the area of the non-opening region, improve the display effect of the array substrate 100, and not reduce the aperture ratio of the array substrate 100 and the transmittance of the display panel.

[0108] Please refer to Figure 9 Optionally, the output electrode of the first transistor T1 includes a first output portion T1D1 and a second output portion T1D2 connected in series.

[0109] The first output portion T1D1 extends along the second direction Y and overlaps the first gate portion S112 and the second wide line C11 in the thickness direction of the array substrate 100, respectively.

[0110] The second output portion T1D2 overlaps the second wide line C11 in the thickness direction of the array substrate 100. The second output portion T1D2 extends along the first direction X, and the width of the second output portion T1D2 increases in the direction away from the first output portion T1D1.

[0111] In this embodiment, the second wide line C11 overlaps the first output portion T1D1 and the second output portion T1D2 in the thickness direction of the array substrate 100 to form the first storage capacitor Cst1. The capacitance value of the first storage capacitor Cst1 is related to the effective overlapping area of the second wide line C11, the effective overlapping area of the first output portion T1D1, and the effective overlapping area of the second output portion T1D2. In this embodiment, the width of the second output portion T1D2 increases in the direction away from the first output portion T1D1, and the effective overlapping area of the second output portion T1D2 can be increased, thereby increasing the capacitance value of the first storage capacitor Cst1. This embodiment can increase the first storage capacitor Cst1 without increasing the area of the non-opening region, improve the display effect of the array substrate 100, and does not reduce the aperture ratio of the array substrate 100 and the transmittance of the display panel.

[0112] The output terminal of the second transistor T2 includes a third output portion T2D1 and a fourth output portion T2D2.

[0113] The third output portion T2D1 extends along the second direction Y and overlaps the second gate portion S114 and the second wide line C11 in the thickness direction of the array substrate 100, respectively.

[0114] The fourth output portion T2D2 overlaps the second wide line C11 in the thickness direction of the array substrate 100. The fourth output portion T2D2 extends along the second direction Y, and the width of the fourth output portion T2D2 increases in the direction away from the third output portion T2D1.

[0115] In this embodiment, the second wide line C11 overlaps the third output portion T2D1 and the fourth output portion T2D2 in the thickness direction of the array substrate 100 to form the second storage capacitor Cst2. The capacitance value of the second storage capacitor Cst2 is related to the effective overlapping area of the second wide line C11, the effective overlapping area of the third output portion T2D1, and the effective overlapping area of the fourth output portion T2D2. In this embodiment, the width of the fourth output portion T2D2 increases in the direction away from the third output portion T2D1, and the effective overlapping area of the fourth output portion T2D2 can be increased, thereby increasing the capacitance value of the second storage capacitor Cst2. This embodiment can increase the second storage capacitor Cst2 without increasing the area of the non-opening region, improve the display effect of the array substrate 100, and does not reduce the aperture ratio of the array substrate 100 and the transmittance of the display panel.

[0116] Please refer to Figure 9 Optionally, the first pixel unit 11 further includes a first connection electrode 23 and a second connection electrode 33.

[0117] In a first pixel unit 11, The first connection electrode 23 is connected to the first pixel electrode 21 on the side close to the second pixel electrode 31 and is electrically connected to the output terminal of the first transistor T1. The first wide line S11 and the second wide line C11 overlap the first connection electrode 23 in the thickness direction of the array substrate 100.

[0118] The second connection electrode 33 is connected to the second pixel electrode 31 on the side close to the first pixel electrode 21 and is electrically connected to the output terminal of the second transistor T2.

[0119] In the plan view of the array substrate 100, the area of the output terminal of the first transistor T1 is smaller than or equal to the area of the output terminal of the second transistor T2.

[0120] In the present embodiment, the first connection electrode 23 is provided in the same layer as the first pixel electrode 21 and is integrally connected thereto, and the first connection electrode 23 and the first pixel electrode 21 are made of the same material and can be formed simultaneously by one process, thereby improving the production efficiency and reducing the production cost. The second connection electrode 33 is provided in the same layer as the second pixel electrode 31 and is integrally connected thereto, and the second connection electrode 33 and the second pixel electrode 31 are made of the same material and can be formed simultaneously by one process, thereby improving the production efficiency and reducing the production cost.

[0121] Further, the first connection electrode 23, the first pixel electrode 21, the second connection electrode 33, and the second pixel electrode 31 can be formed simultaneously by one process, thereby further improving the production efficiency and reducing the production cost.

[0122] In the present embodiment, at least one insulating layer is provided between the first connection electrode 23 and the output terminal of the first transistor T1. The second via hole H2 is provided in the insulating layer, and the first connection electrode 23 is electrically connected to the output terminal of the first transistor T1 through the second via hole H2.

[0123] In the present embodiment, at least one insulating layer is provided between the second connection electrode 33 and the output terminal of the second transistor T2. The third via hole H3 is provided in the insulating layer, and the second connection electrode 33 is electrically connected to the output terminal of the second transistor T2 through the third via hole H3.

[0124] In the embodiment, the first connection electrode 23 needs to cross the first wide line S11 to be electrically connected with the output terminal of the first transistor T1 to form the first storage capacitor Cst1 with the second wide line C11. However, when the first connection electrode 23 crosses the first wide line S11, a storage capacitor is formed between the first connection electrode 23 and the first wide line S11 in addition to the first storage capacitor Cst1 in the first sub-pixel 20. The second connection electrode 33 does not need to cross the first wide line S11 and can be directly electrically connected with the output terminal of the second transistor T2. Therefore, in order to reduce the difference of the overall storage capacitors of the first sub-pixel 20 and the second sub-pixel 30, the area of the output terminal of the first transistor T1 is set to be less than or equal to the area of the output terminal of the second transistor T2 in the embodiment. When the area of the output terminal of the first transistor T1 is less than the area of the output terminal of the second transistor T2, the first storage capacitor Cst1 is less than the second storage capacitor Cst2, but since the first sub-pixel 20 further has the storage capacitor formed by the overlap of the first connection electrode 23 and the first wide line S11, the storage capacitors of the first sub-pixel 20 and the second sub-pixel 30 are similar, and the display effect can be improved.

[0125] Optionally, in the first pixel unit 11, a portion of the second pixel electrode 31 close to the first pixel electrode 21 overlaps the second wide line C11 in the thickness direction of the array substrate 100.

[0126] In the embodiment, the portion of the second pixel electrode 31 close to the first pixel electrode 21 overlaps the second wide line C11 in the thickness direction of the array substrate 100, so that the second storage capacitor Cst2 is increased without increasing the area of the non-opening region, the display effect can be improved, and the aperture ratio of the array substrate 100 and the transmittance of the display panel are not reduced.

[0127] In the description of the present application, the terms “first” and “second” are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with “first” and “second” can explicitly or implicitly include one or more features. In the description of the present application, the meaning of “a plurality of” is two or more, unless otherwise specifically limited.

[0128] In the above embodiments, the description of each embodiment has its own emphasis, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0129] The embodiments, implementation manners and related technical features of the present application can be combined or replaced with each other without conflict.

[0130] The above are only the preferred embodiments of the present application, and do not limit the present application in any form, but any simple modification, equivalent change and modification made to the above embodiments without departing from the technical solution of the present application and according to the technical essence of the present application are still within the scope of the technical solution of the present application.

Claims

1. An array substrate, characterized in that, It includes a common line and pixel units, wherein the common line extends along a first direction; The pixel unit includes: A first sub-pixel, including a first pixel electrode and a first pixel driving circuit; and A second sub-pixel includes a second pixel electrode and a second pixel driving circuit. The second pixel electrode and the first pixel electrode are arranged along a second direction, which intersects with the first direction. The first pixel driving circuit and the second pixel driving circuit are located between the first pixel electrode and the second pixel electrode. In one of the pixel units, a common line is located between the first pixel electrode and the second pixel electrode, and overlaps with the first pixel driving circuit and the second pixel driving circuit respectively in the thickness direction of the array substrate to form a first storage capacitor and a second storage capacitor.

2. The array substrate as described in claim 1, characterized in that, The array substrate further includes: The first data line extends along the second direction; and The second data line extends along the second direction and is spaced apart from the first data line along the first direction, and the pixel unit is disposed between the second data line and the first data line; The first pixel driving circuit includes a first transistor, the input of the first transistor is electrically connected to the first data line, and the output of the first transistor is electrically connected to the first pixel electrode. The second pixel driving circuit includes a second transistor, the input of which is electrically connected to the second data line, and the output of which is electrically connected to the second pixel electrode. In one of the pixel units, a portion of the common line located between the first pixel electrode and the second pixel electrode overlaps with a portion of the output electrode of the first transistor in the thickness direction of the array substrate to form the first storage capacitor; another portion of the common line located between the first pixel electrode and the second pixel electrode overlaps with a portion of the output electrode of the second transistor in the thickness direction of the array substrate to form the second storage capacitor.

3. The array substrate as described in claim 2, characterized in that, The array substrate further includes scan lines that extend along a first direction; In one pixel unit, a scan line is located between the first pixel electrode and the second pixel electrode, and is electrically connected to the control electrode of the first transistor and the control electrode of the second transistor, respectively. The scan line and the common line are spaced apart along the second direction.

4. The array substrate as described in claim 3, characterized in that, The array substrate includes a first pixel column, which includes a plurality of pixel units arranged along the second direction, and one first pixel column is located between adjacent first data lines and second data lines; In one pixel unit, the distance from the side of the first pixel electrode near the second pixel electrode to the side of the second pixel electrode near the first pixel electrode is a first spacing; In two adjacent pixel units in the first pixel column, the distance from the side of the first pixel unit closest to the second pixel unit to the side of the second pixel unit closest to the first pixel unit is the second spacing, which is smaller than the first spacing.

5. The array substrate as described in claim 4, characterized in that, The array substrate further includes a common electrode, which is electrically connected to the common line. In the first pixel column, a portion of the common electrode is provided between two adjacent pixel units.

6. The array substrate as described in claim 4, characterized in that, The array substrate further includes a second pixel column, which includes a plurality of pixel units arranged along the second direction; The first data line, the first pixel column, the second data line, and the second pixel column are arranged alternately along the first direction.

7. The array substrate as described in claim 6, characterized in that, The pixel unit in the first pixel column is a first pixel unit, and the pixel unit in the second pixel column is a second pixel unit; The first pixel electrode of the first pixel unit and the second pixel electrode of the second pixel unit are alternately arranged in the first direction; The second pixel electrode of the first pixel unit and the first pixel electrode of the second pixel unit are alternately arranged in the first direction.

8. The array substrate as claimed in claim 7, characterized in that, The scan line includes a first scan line; The first scan line includes a first wide line and a first thin line alternately connected along the first direction, wherein the width of the first wide line is greater than the width of the first thin line; In a first pixel unit, the first wide line is located between the first pixel electrode and the second pixel electrode, and the first wide line is multiplexed as the control electrode of the first transistor and the control electrode of the second transistor. The first thin line is located between two adjacent second pixel units in the second direction.

9. The array substrate as described in claim 8, characterized in that, The common line is on the same layer as the scan line and is spaced apart; The common line includes a first common line; The first common line includes a second wide line and a second thin line alternately connected along the first direction, wherein the width of the second wide line is greater than the width of the second thin line; In the first pixel unit, the second wide line is located between the first pixel electrode and the second pixel electrode, and the second wide line overlaps with a portion of the output electrode of the first transistor and a portion of the output electrode of the second transistor in the thickness direction of the array substrate to form the first storage capacitor and the second storage capacitor. The first thin line is located between two adjacent second pixel units in the second direction.

10. The array substrate as claimed in claim 9, characterized in that, In a plan view of the array substrate, the average width of the second wide line is greater than the average width of the first wide line.

11. The array substrate as claimed in claim 10, characterized in that, In a plan view of the array substrate, a recess is formed on the side of the first wide line near the second wide line, and a protrusion is formed on the side of the second wide line near the first wide line, with a portion of the protrusion extending into the recess. At least a portion of the protrusion overlaps with a portion of the output electrode of the first transistor and a portion of the output electrode of the second transistor in the thickness direction of the array substrate to form the first storage capacitor and the second storage capacitor.

12. The array substrate as claimed in claim 11, characterized in that, The first wide line includes a first gate portion, a connecting portion, and a second gate portion connected sequentially along the first direction; The first gate portion is formed as the control electrode of the first transistor, and the second gate portion is formed as the control electrode of the second transistor; In a plan view of the array substrate, the first gate portion is disposed on the side near the second wide line that extends beyond the side of the connection portion near the second wide line, and the second gate portion is disposed on the side near the second wide line that extends beyond the side of the connection portion near the second wide line. The recess is formed on the side of the first gate portion near the second wide line, the side of the connection portion near the second wide line, and the side of the second gate portion near the second wide line.

13. The array substrate as claimed in claim 12, characterized in that, The output of the first transistor includes a first output portion and a second output portion connected together. The first output portion extends along a second direction and overlaps with the first gate portion and the second wide line in the thickness direction of the array substrate, respectively. The second output portion overlaps with the second wide line in the thickness direction of the array substrate. The second output portion extends along the first direction, and the width of the second output portion increases in the direction away from the first output portion. The output of the second transistor includes a third output portion and a fourth output portion; the third output portion extends along the second direction and overlaps with the second gate portion and the second wide line in the thickness direction of the array substrate, respectively; the fourth output portion overlaps with the second wide line in the thickness direction of the array substrate; the fourth output portion extends along the second direction; and the width of the fourth output portion increases in the direction away from the third output portion.

14. The array substrate as claimed in claim 9, characterized in that, The first pixel unit further includes a first connecting electrode and a second connecting electrode; In one of the first pixel units The first connection electrode is connected to the side of the first pixel electrode near the second pixel electrode and is electrically connected to the output electrode of the first transistor. The first wide line, the second wide line and the first connection electrode overlap in the thickness direction of the array substrate. The second connection electrode is connected to the side of the second pixel electrode close to the first pixel electrode and is electrically connected to the output electrode of the second transistor; In a plan view of the array substrate, the area of ​​the output electrode of the first transistor is less than or equal to the area of ​​the output electrode of the second transistor.

15. The array substrate as claimed in claim 14, characterized in that, In one of the first pixel units, a portion of the second pixel electrode near the first pixel electrode overlaps with the second wide line in the thickness direction of the array substrate.

16. A display panel, characterized in that, Includes the array substrate as described in any one of claims 1-15.

Images