Debug information acquisition method, pcie controller, processor and data processing device

Abstract

The present disclosure relates to a debugging information acquisition method, a PCIe controller, a processor and a data processing device. The method comprises: collecting, by a DMA module built in the PCIe controller, debugging information of the PCIe controller to form at least one debugging information chain based on time sorting, wherein the debugging information comprises clock information, and the debugging information further comprises at least one of state information and error TLP information; and sending, by the DMA module, the at least one debugging information chain to a system bus to be stored in a system bus memory. The present disclosure utilizes the DMA module built in the PCIe controller to realize real-time recording of dynamic debugging information of the PCIe controller, and further based on the recorded debugging information of multiple different time slices, helps to improve the analysis accuracy of related error information.

Description

Technical Field

[0001] This disclosure relates to the field of PCIe controller debugging technology, and in particular to a debugging information acquisition method, a PCIe controller, a processor, and a data processing device. Background Technology

[0002] PCIe (Peripheral Component Interconnect Express) is a high-speed serial computer expansion bus standard used to connect various internal computer components (such as graphics cards, hard drives, network cards, etc.), and has become a core technology for data transmission in modern computer systems.

[0003] In existing systems, as the entry point for artificial intelligence chips, the PCIe controller plays a crucial role in identifying the cause of system errors by analyzing the matching relationship between requests and responses. This is because the PCIe controller can easily be used to analyze the system error. Therefore, the PCIe controller's debug logging function is very important. It can not only eliminate the faults of the PCIe controller itself, but also help to locate the root cause of the error at the system level.

[0004] In related technologies, the methods for obtaining debugging information for PCIe controllers mostly involve static debugging information obtained from relevant status registers at the current moment. Real-time recording only captures the current state of the PCIe controller, such as the header information of the TLP (Transaction Layer Packet) for the first UR (Unsupported Request Response) response, as defined by the PCIe protocol's AER (Advanced Error Reporting) function. Another example is the status recording function of LTSSM (Link Training and Status State Machine) implemented in current related technologies. The TLP is the basic information unit in the PCIe bus used to transmit actual data and commands. It is generated and processed at the Transaction Layer and is the core carrier for data interaction between PCIe devices. Debugging technology is crucial for high-speed interface data path type IP (Intellectual Property) cores. Sufficient debugging information helps to locate complex problems, thereby ensuring chip quality.

[0005] The main drawback of these technologies is the poor completeness of debugging information recording; earlier-acquired debugging information can be overwritten by later-acquired information. In more complex error scenarios, insufficient debugging information can significantly increase the complexity of error analysis, leading to a significant decrease in debugging efficiency and making it difficult to locate the root cause of errors.

[0006] Because the debugging method of the relevant technology is a static debug record register scheme, the size and content of the debug record register are completely fixed after the hardware is manufactured. The recorded content is small and cannot be dynamically expanded according to the actual error scenario.

[0007] In summary, the relevant technologies have the drawback of limited debug logging content, which makes it difficult to fully acquire comprehensive and multi-faceted debugging information. Furthermore, in practical use, it is impossible to dynamically adjust the expected content and quantity of debug information to be logged. Summary of the Invention

[0008] In view of this, the present disclosure provides a debugging information acquisition method, a PCIe controller, a processor, and a data processing device to realize the real-time recording of dynamic debugging information, and thereby help improve the accuracy of the analysis of relevant error information based on the debugging information recorded in multiple different time slices.

[0009] According to one aspect of the embodiments of this disclosure, a method for obtaining debugging information is provided, including:

[0010] The debugging information of the PCIe controller is collected through the DMA module built into the PCIe controller, forming at least one debugging information chain based on time ordering. The debugging information includes clock information and at least one of status information and error TLP information.

[0011] The DMA module sends at least one debug information chain to the system bus for storage in the system bus memory.

[0012] In one possible implementation, the debugging information chain includes:

[0013] The start identifier field is used to identify the head of the debug information chain;

[0014] The end identifier field is used to identify the end of the debugging information chain;

[0015] A timestamp identifier field, located after the start identifier field, is used to identify the time when the debug information chain was generated; and,

[0016] At least one of the status information field group and the error TLP information field group is located between the timestamp identifier field and the end identifier field.

[0017] In one possible implementation, the status information field group includes at least one status information field obtained by the DMA module at the generation time of the debugging information chain identified by the timestamp identifier field.

[0018] The error TLP information field group includes at least one error TLP information field obtained by the DMA module at the time of generation of the debug information chain identified by the timestamp identifier field.

[0019] In one possible implementation, the start identifier field includes index information, which is used to characterize the position of the start identifier field in the debug information chain within the at least one debug information chain;

[0020] The end identifier field includes the number of error TLP messages contained in the debug information chain to which the end identifier field is located.

[0021] In one possible implementation, the method further includes:

[0022] The acquisition control registers for the acquisition time, status information, and error TLP information of the DMA module are configured so that the DMA module can acquire the clock information, status information, and error TLP information based on the configured information.

[0023] In one possible implementation, the system bus includes at least one of a memory bus and a control bus.

[0024] In one possible implementation, the method further includes:

[0025] Configure the system bus object sent by the DMA module so that the DMA module sends the debug information chain to the configured main bus, and if it fails to send the debug information chain to the main bus, sends at least one debug information chain to the configured secondary bus;

[0026] The main bus is one of the memory bus and the control bus, and the secondary bus is the other of the memory bus and the control bus.

[0027] In one possible implementation, the system bus memory is configured with a debug information chain storage space, and the at least one debug information chain is stored in the debug information chain storage space;

[0028] The storage mode of the at least one debug information chain in the debug information chain storage space is configured as one of the following: non-overwrite storage mode, ring overwrite storage mode, and specified number of debug information chains storage mode;

[0029] Wherein, when the storage mode is configured as the non-overwrite storage mode, the at least one debug information chain is stored sequentially in the debug information chain storage space, and storage stops when the debug information chain storage space is full;

[0030] When the storage mode is configured as the ring-overlay storage mode, the at least one debug information chain is stored sequentially in the debug information chain storage space. When the debug information chain storage space is full, the latest debug information chain overwrites the earliest debug information chain stored in the debug information chain storage space.

[0031] When the storage mode is configured as the specified number of debug information chains storage mode, the at least one debug information chain is stored sequentially in the debug information chain storage space until the storage of the last debug information chain of the specified number of debug information chains is completed, at which point storage stops.

[0032] According to another aspect of the embodiments of this disclosure, a PCIe controller is provided, comprising:

[0033] The DMA module, built into the PCIe controller, is used to collect debugging information from the PCIe controller, form at least one debugging information chain based on time order, and send the at least one debugging information chain to the system bus for storage in the system bus memory. The debugging information includes clock information and at least one of status information and error TLP information.

[0034] According to another aspect of the present disclosure, a processor is provided, including the PCIe controller as described above.

[0035] According to another aspect of the present disclosure, a data processing apparatus is provided, including the processor described above.

[0036] As can be seen from the above scheme, the debugging information acquisition method, PCIe controller, processor and data processing device disclosed herein realize the storage of at least one debugging information chain in memory, which is arranged in chronological order of the PCIe controller. The relevant debugging analysis device no longer needs to be directly connected to the relevant registers in the PCIe controller to obtain static debugging information. The relevant debugging analysis device can obtain a large amount of debugging information generated in chronological order from the memory for analysis, trace the historical causes and changes of the error, and help to accurately analyze the location and root cause of the error. Attached Figure Description

[0037] Figure 1 This is a schematic flowchart illustrating a debugging information acquisition method according to an illustrative embodiment;

[0038] Figure 2 This is a schematic diagram illustrating a general structure of a complete debugging information chain according to an illustrative embodiment;

[0039] Figure 3A This is a schematic diagram of the configuration structure for the first specific application scenario of the debugging information chain;

[0040] Figure 3B This is a schematic diagram of the configuration structure for the second specific application scenario of the debugging information chain;

[0041] Figure 3C This is a schematic diagram of the configuration structure for the third specific application scenario of the debugging information chain;

[0042] Figure 3D This is a schematic diagram of the configuration structure for the fourth specific application scenario of the debugging information chain;

[0043] Figure 4A This is a schematic diagram illustrating the structure of a start identifier field according to an illustrative embodiment;

[0044] Figure 4B This is a schematic diagram illustrating the structure of an end identifier field according to an illustrative embodiment;

[0045] Figure 5A This is a schematic diagram illustrating the address space distribution of the debug information chain in the memory bus address space according to an illustrative embodiment;

[0046] Figure 5B This is a schematic diagram illustrating the address space distribution of the debug information chain in the control bus address space according to an illustrative embodiment;

[0047] Figure 6 This is a schematic diagram illustrating the initialization process of a PCIe controller when using the debugging information acquisition method of the present disclosure according to an illustrative embodiment;

[0048] Figure 7 This is a schematic diagram of a PCIe controller according to an illustrative embodiment.

[0049] In the attached diagram, the component names represented by each number are as follows:

[0050] 1. Start identifying the field,

[0051] 1_1, Start Marker

[0052] 1_2, Index Information

[0053] 2. Timestamp identifier field,

[0054] 2_1, the value of the first timestamp register,

[0055] 2_2, the value of the second timestamp register,

[0056] 3. Status information field group,

[0057] 3_1, First Status Information Field

[0058] 3_2, Second Status Information Field

[0059] 3_N-2, the (N-2)th state information field,

[0060] 3_N-1, the (N-1)th state information field,

[0061] 3_N, the Nth state information field,

[0062] 4. Error TLP information field group,

[0063] 4_1, Error 1 TLP Information Field,

[0064] 4_2, Error 2 TLP Information Field,

[0065] 4_M, the Mth error TLP information field,

[0066] 5. End identifier field,

[0067] 5_1, End marker,

[0068] 5_2. Information on the number of error TLP messages.

[0069] 701, DMA module,

[0070] 702, PCIe controller,

[0071] 703. System Bus Memory

[0072] 7031, Memory Bus Memory,

[0073] 7032, Control Bus Memory. Detailed Implementation

[0074] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided with reference to the accompanying drawings and embodiments.

[0075] As used in the specification and claims of this disclosure, “coupled (or connected)” may refer to any direct or indirect means of connection. For example, if a first device is coupled (or connected) to a second device, it should be interpreted as the first device being directly connected to the second device, or the first device being indirectly connected to the second device through other devices or some means of connection.

[0076] This disclosure provides a debugging information acquisition method, a PCIe controller, a processor, and a data processing device to acquire and store at least one piece of debugging information from the PCIe controller in chronological order based on demand settings. This information is used for the acquisition and analysis of debugging information in at least one time slice as needed during the debugging process. By providing a solution for real-time acquisition and storage of dynamic debugging information based on time evolution, this method helps to improve the speed of finding the source of error information and the accuracy of error information analysis, thereby contributing to a comprehensive improvement in debugging effectiveness.

[0077] Figure 1 This is a schematic flowchart illustrating a debugging information acquisition method according to an illustrative embodiment, such as... Figure 1 As shown, the debugging information acquisition method mainly includes the following steps 101 to 102.

[0078] Step 101: Collect debugging information from the PCIe controller through the DMA (Direct Memory Access) module built into the PCIe controller, and form at least one debugging information chain (also known as a debug chain) based on time ordering. The debugging information includes clock information, and also includes at least one of status information and error TLP information.

[0079] Step 102: Send at least one debug information chain to the system bus via the DMA module for storage in the system bus memory.

[0080] At least one debug information chain stored in the system bus memory is available for the debug device to retrieve at any time.

[0081] The DMA module, also known as the DMA engine, is a dedicated hardware controller. In related technologies, the DMA module allows external devices in the computer (such as hard drives, network cards, sound cards, GPUs, etc.) to directly read and write data with memory without continuously occupying the resources of the central processing unit. Therefore, the DMA module can free up the central processing unit, improve data read and write speed, and thus help improve the overall system performance.

[0082] The debugging information acquisition method of this disclosure stores at least one debugging information chain of the PCIe controller in memory, arranged chronologically. The relevant debugging analysis device no longer needs to directly connect to the relevant registers in the PCIe controller to obtain static debugging information. Instead, the debugging analysis device can obtain a large amount of time-series-generated debugging information from the memory for analysis, tracing the historical causes and changes of errors, and helping to accurately analyze the location and root cause of errors. In this disclosure embodiment, the debugging information chain for the PCIe controller is generated and transmitted by a DMA module, thus eliminating the need to occupy resources of the central processing unit in the system and reducing system overhead caused by acquiring debugging information.

[0083] To accurately define each debugging information chain and facilitate the accurate acquisition of relevant debugging information, in this illustrative embodiment, the debugging information chain includes a start (Start) identifier field, an end (End) identifier field, and a timestamp identifier field. The debugging information chain also includes at least one of a status information field group and an error TLP information field group. The start identifier field identifies the head of the debugging information chain; that is, it is located at the beginning of the chain, marking its starting position. The end identifier field identifies the tail of the chain; that is, it is located at the end of the chain, marking its ending position. The timestamp identifier field follows the start identifier field and identifies the time when the debugging information chain was generated; that is, it also identifies the time when the relevant debugging information in this chain was collected. At least one of the status information field group and the error TLP information field group is located between the timestamp identifier field and the end identifier field, and at least one of these groups contains the main content of the debugging information recorded in the debugging information chain. In an illustrative embodiment, when the debug information chain includes both a status information field group and an error TLP information field group, depending on the configuration, the status information field group may be located before the error TLP information field group, or the status information field group may be located after the error TLP information field group.

[0084] In an illustrative embodiment, the status information field group includes at least one status information field obtained by collecting at least one status information through the DMA module at the generation time of the debug information chain identified by the timestamp identifier field; the error TLP information field group includes at least one error TLP information field obtained by collecting at least one error TLP information through the DMA module at the generation time of the debug information chain identified by the timestamp identifier field.

[0085] Figure 2 This is a schematic diagram illustrating a general structure of a complete debugging information chain according to an illustrative embodiment. For example... Figure 2 As shown in the illustrative embodiment, the debug information chain includes a start identifier field 1, a timestamp identifier field 2, a status information field group 3, an error TLP information field group 4, and an end identifier field 5.

[0086] The start identifier field 1 is located at the head of the debug information chain and is used to identify the head of the debug information chain.

[0087] The timestamp identifier field 2, located after the start identifier field 1, is used to identify the generation time of the debug information chain. The time recorded in timestamp identifier field 2 originates from the relevant timestamp register in the PCIe controller. According to the design, in the illustrative embodiment, the number of timestamp registers in the PCIe controller can be one or more. When there is only one timestamp register in the PCIe controller, the content of timestamp identifier field 2 originates from that single timestamp register. For example, if there are two timestamp registers in the PCIe controller, the time in the PCIe controller is composed of the times recorded by both timestamp registers; therefore, the content of timestamp identifier field 2 originates from both timestamp registers. Figure 2 The first timestamp register value is 2_1 and the second timestamp register value is 2_2, as shown in the figure.

[0088] Status information field group 3 is located after timestamp identifier field 2. Status information field group 3 includes at least one status information field obtained from at least one status information piece collected by the DMA module at the generation time of the debug information chain identified by timestamp identifier field 2. For example... Figure 2As shown, status information field group 3 includes N status information fields, from the first status information field 3_1 to the Nth status information field 3_N. Each status information field contains one status information entry, meaning that status information field group 3 records N status information entries, where the number N can be set as needed. In the illustrative embodiment, the status information originates from relevant status registers in the PCIe controller. Specifically, depending on the settings, the status information recorded in the status registers of the PCIe controller needs to be collected during debugging, and each status information field records the status information recorded in these required status registers. For example... Figure 2 The status information field group 3 shown includes the first status information field 3_1, the second status information field 3_2, ... the Nth status information field 3_N. The first status information field 3_1, the second status information field 3_2, ... the Nth status information field 3_N respectively record the information of the first status register, the second status register, ... the Nth status register.

[0089] Error TLP information field group 4 follows status information field group 3. Error TLP information field group 4 includes at least one error TLP information field obtained from at least one error TLP message collected by the DMA module at the time of generation of the debug information chain identified by timestamp identifier field 2. For example Figure 2 As shown, Error TLP information field group 4 includes M error TLP information fields, from the first error TLP information field 4_1 to the Mth error TLP information field 4_M. Each error TLP information field contains one error TLP message, meaning that error TLP information field group 4 records M error TLP messages. The number of error TLP messages is variable; at some times, no error TLP messages may be generated, and at other times, multiple error TLP messages may be generated. These error TLP messages help analyze the root cause of errors during debugging. Therefore, the value of M is not fixed; when no error TLP messages are present in the debugging information chain, M is 0. For example... Figure 2 The error TLP information field group 4 shown includes the first error TLP information field 4_1, the second error TLP information field 4_2, ... the Mth error TLP information field 4_M. The first error TLP information field 4_1, the second error TLP information field 4_2, ... the Mth error TLP information field 4_M respectively record the first error TLP information, the second error TLP information, ... the Mth error TLP information.

[0090] The end identifier field 5 is located after the error TLP information field group 4, that is, the end identifier field 5 is located at the end of the debug information chain and is used to identify the end of the debug information chain.

[0091] Figure 3AThis is a schematic diagram of the configuration structure for the first specific application scenario of the debugging information chain, such as... Figure 3A As shown, in the first application scenario, the debug information chain can be configured to include only some status information fields in status information field group 3, for example... Figure 3A The diagram shows only the (N-2)th state information field 3_N-2, the (N-1)th state information field 3_N-1, and the Nth state information field 3_N. The state information in these fields represents a portion of the total state information that the DMA module can collect during debugging. For example, the DMA module can collect the 1st, 2nd, ..., Nth state register information of the PCIe controller. However, for debugging purposes, the DMA module only collects the (N-2)th, (N-1)th, and Nth state register information as the state information recorded in the (N-2)th, (N-1)th, and Nth state information fields 3_N-2, 3_N-1, and 3_N, respectively. Figure 3A As shown, in the first application scenario, the debug information chain is also configured to collect error TLP information. Therefore, the debug information chain in the first application scenario also includes error TLP information field group 4.

[0092] Figure 3B This is a schematic diagram of the configuration structure for the second specific application scenario of the debugging information chain, such as... Figure 3B As shown, in the second application scenario, the debug information chain can be configured to exclude group 3 (status information field) as needed. Meanwhile, as... Figure 3B As shown, in the second application scenario, the debug information chain is also configured to collect error TLP information. Therefore, the debug information chain in the second application scenario only contains error TLP information field group 4. This second specific application scenario is suitable for the requirement of only collecting error TLP information.

[0093] Figure 3C This is a schematic diagram of the configuration structure for the third specific application scenario of the debugging information chain, such as... Figure 3C As shown, in the third application scenario, the debug information chain can be configured to include only some status information fields in status information field group 3, for example... Figure 3C The diagram shows only the (N-2)th state information field 3_N-2, the (N-1)th state information field 3_N-1, and the Nth state information field 3_N. Also, as... Figure 3CAs shown, in the third application scenario, the debug information chain is also configured not to collect error TLP information. Therefore, the debug information chain in the third application scenario does not include error TLP information field group 4.

[0094] Figure 3D This is a schematic diagram of the configuration structure for the fourth specific application scenario of the debugging information chain, as shown below. Figure 3D As shown, in the fourth application scenario, the debug information chain can be configured to include all status information fields in status information field group 3, for example... Figure 3D The diagram shows all status information fields, including the first status information field 3_1, the second status information field 3_2, ..., the Nth status information field 3_N. Also, as... Figure 3D As shown, in the fourth application scenario, the debug information chain is also configured not to collect error TLP information. Therefore, the debug information chain in the fourth application scenario does not include error TLP information field group 4.

[0095] The debugging information acquisition method of this disclosure implements the storage of at least one debugging information chain in memory, which arranges the debugging information of the PCIe controller in chronological order. Therefore, the stored at least one debugging information chain forms a complete dynamic debugging information record. Based on any debugging information chain extracted from it, the debugging information at a certain time slice in the dynamic debugging information record can be obtained at any time. In order to quickly determine the position of the extracted debugging information chain among multiple debugging information chains, and then determine the position of the debugging information in the extracted debugging information chain in the entire dynamic debugging information record, so as to confirm the stage of the extracted debugging information in the debugging process, in the illustrative embodiment, the start identifier field includes index information. The index information is used to characterize the position of the debugging information chain where the start identifier field is located in at least one debugging information chain.

[0096] Under normal operating conditions, PCIe controllers generally do not generate error TLP messages. Furthermore, certain problems with the PCIe controller may also not generate error TLP messages. Therefore, during debugging, the obtained debug information chain may or may not contain error TLP messages. If error TLP messages are present, the number of error TLP messages may be one or multiple. Thus, there is a need for debugging based on error TLP messages. Therefore, in application scenarios where debugging is based on error TLP messages, debug information chains containing error TLP messages receive more attention than those without. It is necessary to quickly determine the debug information chain containing error TLP messages from multiple debug information chains, and the number of error TLP messages contained within that chain. Based on this, in the illustrative embodiment, the end identifier field includes the number of error TLP messages contained in the debug information chain containing the end identifier field. This approach allows for a quick preview of the number of error TLP messages in the debug information chain from the end identifier field, without having to scan or read the specific data structure of the debug information chain to determine the number of error TLP messages. This speeds up the filtering efficiency of the debug information chain and thus helps improve debugging efficiency.

[0097] Figure 4A This is a schematic diagram illustrating the structure of the start identifier field according to an illustrative embodiment. Figure 4B This is a schematic diagram illustrating the structure of an end identifier field according to an illustrative embodiment. For example... Figure 4A , Figure 4B As shown in the illustrative embodiment, the start identifier field 1 and the end identifier field 5 may include a pre-agreed start identifier 1_1 and end identifier 5_1, for example... Figure 4A The start identifier 1_1 shown is "FFFF_FFFF" (hexadecimal representation) and Figure 4B The end identifier 5_1 shown is "FFFF_FFFE". In addition, after the start identifier 1_1 and the end identifier 5_1, the start identifier field 1 and the end identifier field 5 each contain index information 1_2 and error TLP information quantity information 5_2, for example... Figure 4A As shown, index information 1_2 is also included after "FFFF_FFFF". Figure 4B As shown, after "FFFF_FFFE", there is also the quantity information 5_2 of error TLP information. In the illustrative embodiment, the index information 1_2 and the quantity information 5_2 of error TLP information can be configured as a 32-bit record width.

[0098] In the illustrative embodiment, combined with Figure 2 , Figures 3A to 3D As shown in this embodiment, the start identifier field 1 and end identifier field 5 of the debug information chain can easily identify the head and tail of the debug information chain from the memory, making it easier to distinguish from other debug information chains. Wherein, as Figure 4A , Figure 4B As shown, the start identifier field 1 contains the index information 1_2 of the debug information chain to which the start identifier field 1 belongs, while the end identifier field 5 contains the quantity information 5_2 of error TLP information contained in the debug information chain to which the end identifier field 5 belongs. In the illustrative embodiment, during debugging, the index information 1_2 in the start identifier field 1 of the first debug information chain is 0. For each subsequent debug information chain, the index information 1_2 in the corresponding debug information chain is increased by 1 based on the index information 1_2 of the previous debug information chain. Based on the embodiment where the start identifier field 1 occupies a 32-bit width, the maximum number of records that the index information 1_2 of the debug information chain can record can reach 2. 32 A single line can satisfy almost any debugging need, but in practical applications it is almost impossible to achieve 2 lines. 32 In the illustrative embodiment, once the number of recorded debug information chains reaches 2... 32 If no error TLP is received at the time recorded in the timestamp field 2 of the current debug information chain, then the index information 1_2 of the newly generated debug information chain will start counting from 0 again. Additionally, the index information 1_2 in the start identifier field 1 helps the relevant debug program calibrate whether the currently processed debug information chain is correct, and also helps to accurately determine the position of the current debug information chain together with the time recorded in the timestamp identifier field 2 of the debug information chain. Regarding the number of error TLP messages 5_2 in the end identifier field 5, if no error TLP is received at the time recorded in the timestamp identifier field 2 of the current debug information chain, then the number of error TLP messages 5_2 of the current debug information chain is 0. The number of error TLP messages 5_2 helps the relevant debug program parse out exactly how many error TLP messages exist in the debug information chain.

[0099] In the debugging information chain, the timestamp identifier field 2 must exist. The time information recorded therein can identify which moment the debugging information chain corresponds to, making it easy to define a unique time identity for each debugging information chain.

[0100] In the illustrative embodiment, the status information field is set according to the design of different PCIe controllers or different actual use scenarios. It depends on which status register values ​​need to be included in the debug information chain. By selecting the start and end positions of the status registers that need to be debugged, it is possible to select only some of the status register values ​​(i.e., status information) to be included in the debug information chain. This makes it easier to filter out the status information of the status registers needed for debugging, thereby avoiding the use of unhelpful status register values ​​in the memory of the debug information chain.

[0101] The number of error TLP messages is at least 0. These are header messages of TLPs that may be cached during the generation and transmission of a debug message chain. Because the generation of error TLP messages during the generation and transmission of a debug message chain cannot be accurately predicted, the number of error TLP messages is not fixed. Therefore, the number of error TLP messages is carried by the end identifier field 5. If no error TLP is received within the time period of the generation and transmission of a debug message chain, then the error TLP message count information 5_2 in the end identifier field 5 of this debug message chain is 0.

[0102] Regarding the possible forms of the debugging information chain Figure 2 The complete structure of the debugging information chain is given. Figures 3A to 3D The structure of several incomplete debugging information chains is then given. Figure 3A The image shows the debug information chain after filtering the debug registers (i.e., the status registers from which status information needs to be obtained). The start and end positions of the debug registers in this debug information chain can be flexibly selected according to requirements. Figure 3B The result shown does not include a debug register; it only contains timestamp information and error TLP information. Figure 3C The result shown does not contain error TLP information, and the debug register is also a debug information chain after the debug register has been filtered. Figure 3D The example shown does not include error TLP information. The debug register is a complete debug register chain, which includes all status registers in the PCIe controller that require status information. In actual use, the debug program can be configured to adjust the debug information chain according to actual debugging needs, thus flexibly adapting to different debugging requirements.

[0103] above Figures 3A to 3D This only lists a few possible forms of debug information chains. In actual use, you can choose to obtain different combinations of status information from various debug registers according to your needs, so as to achieve further fine-grained filtering of debug registers and form a more flexible configuration of debug information chains.

[0104] Based on the above description, in the illustrative embodiment, the debugging information acquisition method of this disclosure further includes: configuring the acquisition time, status information acquisition control register, and error TLP information acquisition control register of the DMA module, so that the DMA module acquires clock information, status information, and error TLP information based on the configured information. The storage information in the status information acquisition control register is used to indicate which status registers in the PCIe controller's status information to acquire, and the error TLP information acquisition control register is used to indicate whether error TLP information acquisition is enabled.

[0105] To prevent the debugging information chain from failing to be stored due to problems with the bus or memory, the debugging information acquisition method of this disclosure also includes a scheme for storing and backing up the debugging information chain.

[0106] In an illustrative embodiment, the system bus includes at least one of a memory bus and a control bus. In this way, the debug information chain can be configured to transmit to at least one of the memory bus and the control bus as needed.

[0107] In an illustrative embodiment, the debugging information acquisition method of this disclosure may further include: configuring the system bus object sent by the DMA module, such that the DMA module sends a debugging information chain to the configured main bus, and if sending the debugging information chain to the main bus fails, sending at least one debugging information chain to the configured secondary bus; wherein the main bus is one of the memory bus and the control bus, and the secondary bus is the other of the memory bus and the control bus. In a specific application scenario, whether writing information to the memory is successful can be determined by the response information returned by the memory. Based on this, whether sending the debugging information chain to the main bus fails can be determined by the response information returned by the main bus. For example, if no response information is received from the main bus within a specified time, it can be considered that the debugging information chain has failed to be sent to the main bus; or, if the response information returned by the main bus indicates that the memory storage has failed, it can also be considered that the debugging information chain has failed to be sent to the main bus. Based on this, in the illustrative embodiment, if the failure to send the debug information chain to the main bus is detected from the main bus, it indicates that it may be related to the main bus. At this time, the debug information chain cannot be transmitted to the main bus memory via the main bus. In this case, the DMA module can send the debug information chain to the secondary bus. The relevant program can monitor whether the debug information chain fails to be sent to the main bus, and when the failure to send the debug information chain to the main bus is detected, the DMA module is controlled to send the debug information chain to the secondary bus.

[0108] In an illustrative embodiment, the main bus is a memory bus and the secondary bus is a control bus. Based on this, the debugging information acquisition method of this disclosure embodiment may further include: configuring the system bus object sent by the DMA module so that the DMA module sends the debugging information chain to the configured memory bus, and in the event that the debugging information chain fails to be sent to the memory bus, sending at least one debugging information chain to the configured system bus.

[0109] In an illustrative embodiment, the main bus is a control bus and the secondary bus is a memory bus. Based on this, the debugging information acquisition method of this disclosure embodiment may further include: configuring the system bus object sent by the DMA module so that the DMA module sends the debugging information chain to the configured control bus, and in the event that the debugging information chain fails to be sent to the control bus, sending at least one debugging information chain to the configured memory bus.

[0110] In an embodiment based on a system bus including at least one of a memory bus and a control bus, the system bus memory includes at least one of a memory bus memory and a control bus memory. The memory bus memory can be referred to as RAM, and the control bus memory is a memory coupled to the control bus and primarily used for storing control instructions and other content. Typically, the RAM's storage space is significantly larger than the control bus memory's storage space. To ensure sufficient storage space for the debugging information chain without affecting the storage and transmission of instructions and other information on the control bus, in the illustrative embodiment, a scheme where the main bus is the memory bus and the secondary bus is the control bus is preferred.

[0111] In an illustrative embodiment, the system bus memory is configured with a debug information chain storage space, and at least one debug information chain is stored in the debug information chain storage space. Based on this, the memory bus memory and / or the control bus memory are configured with debug information chain storage spaces, and according to the settings, at least one debug information chain is stored in the debug information chain storage space of the memory bus memory and / or the debug information chain storage space of the control bus memory.

[0112] Figure 5A This is a schematic diagram illustrating the address space distribution of the debug information chain in the memory bus address space according to an illustrative embodiment. Figure 5B This is a schematic diagram illustrating the address space distribution of the debug information chain in the control bus address space, according to an illustrative embodiment. For example... Figure 5A As shown, in the illustrative embodiment, a "memory bus address space for DMA module access" is allocated in the memory bus address space. In this "memory bus address space for DMA module access," the debug information chain for timestamp 0, the debug information chain for timestamp 1, ..., the debug information chain for timestamp n are stored in the order of the timestamps, where n is an integer greater than 1. For example... Figure 5B As shown in the illustrative embodiment, a "control bus address space for DMA module access" is allocated in the control bus address space. In this "control bus address space for DMA module access", the debug information chain of timestamp 0, the debug information chain of timestamp 1, ..., the debug information chain of timestamp n are stored in the order of the timestamps.

[0113] Regarding whether the actual DMA module sends the debug information chain to the memory bus or the control bus, to adapt to various debugging needs, in the illustrative embodiment, the relevant registers for bus selection can be configured to allow the DMA module to send the debug information chain to the appropriate bus. In actual debugging, preferably, the debug information chain is sent to the memory bus. However, if a memory bus failure prevents access to the memory bus, the debug information chain is switched to being sent to the control bus, thus enabling the control bus to serve as a backup for the memory bus to store the debug information chain.

[0114] Regarding the allocated bus address space, such as Figure 5A , Figure 5B As shown, the maximum number of debug information chains that can be stored can be determined by considering the space occupied by a single debug information chain and the bus address space allocated to the DMA module. Assuming the address space allocated to the DMA module is 4MB (megabytes) and a single debug information chain occupies 4KB (kilobytes), then a maximum of 1024 debug information chains can be stored in this 4MB address space. In practical use, if the number of debug information chains exceeds 1024, then the storage configuration of subsequent debug information chains becomes an issue.

[0115] In an illustrative embodiment, in the debugging information acquisition method of this disclosure, at least one debugging information chain is configured in the debugging information chain storage space as one of the following: non-overlapping storage mode, ring-overlapping storage mode, or storage mode specifying the number of debugging information chains.

[0116] In the illustrative embodiment, when the storage mode is configured to not overwrite the storage mode, at least one debug information chain is stored sequentially in the debug information chain storage space, and storage stops when the debug information chain storage space is full. This approach ensures that the earliest generated debug information chain is not overwritten.

[0117] In an illustrative embodiment, when the storage mode is configured as a ring-overlay storage mode, at least one debug information chain is stored sequentially in the debug information chain storage space. When the debug information chain storage space is full, the latest debug information chain overwrites the earliest debug information chain stored in the debug information chain storage space. This method ensures that the most recently generated debug information chain is not discarded.

[0118] In the illustrative embodiment, when the storage mode is configured to store a specified number of debug information chains, at least one debug information chain is stored sequentially in the debug information chain storage space until the storage of the last debug information chain of the specified number of debug information chains is completed. For example, if P debug information chains are specified, storage stops when the storage of the Pth debug information chain is completed, where P is an integer greater than or equal to 1. This method allows for obtaining the required number of debug information chains as needed. In the illustrative embodiment, there is a special case where the debug information chain storage space is full but the configured number of debug information chains has not been reached. In this case, a circular overlay storage mode is used, where the latest debug information chain overwrites the earliest debug information chain position stored in the debug information chain storage space, until the storage of the last debug information chain is completed.

[0119] The three methods described above can be configured as needed. In practical applications, since the memory address space is typically large, there is usually ample space available for the debug information chain. If the allocated space is large, the issue of debug information chain overwriting can be disregarded. Overwriting of the debug information chain should only be considered when the available access space for the DMA module is insufficient.

[0120] Figure 6 This is a schematic diagram illustrating the initialization process of a PCIe controller when using the debugging information acquisition method of this disclosure according to an illustrative embodiment, as shown below. Figure 6 As shown, when using the debugging information acquisition method of this disclosure embodiment, the initialization process of the PCIe controller may include the following steps 601 to 604.

[0121] Step 601: Select a suitable configuration structure for the debug information chain, and then proceed to step 602.

[0122] The configuration structure of the debugging information chain can be found in [reference needed]. Figure 2 , Figures 3A to 3D In addition to the configuration structure shown, other configuration structures can be configured according to the needs of actual application scenarios.

[0123] Step 602: Select the bus accessed by the DMA module in the memory bus and control bus, and then proceed to step 603.

[0124] For example, the memory bus can be selected as the bus accessed by the DMA module, and the DMA module can then send the debug information chain to the memory bus for storage in memory.

[0125] Step 603: Select the address space size to allocate to the DMA module, and then proceed to step 604.

[0126] Step 604: Select the storage mode for the debug information chain in the allocated address space.

[0127] For example, one can choose from three storage modes: no overwrite storage mode, ring overwrite storage mode, and storage mode that specifies the number of debug information chains.

[0128] After completing steps 601 to 604, the DMA module can be activated at the required time to obtain debugging information from the PCIe controller.

[0129] In an illustrative embodiment, a PCIe controller is also provided. Figure 7 This is a schematic diagram of the PCIe controller shown according to an illustrative embodiment, as follows: Figure 7 As shown, it includes a DMA module 701. The DMA module 701 is built into the PCIe controller 702 and is used to collect debugging information from the PCIe controller 702, form at least one debugging information chain based on time ordering, and send at least one debugging information chain to the system bus for storage in the system bus memory 703. The debugging information includes clock information, and the debugging information also includes at least one of status information and error TLP information.

[0130] In an illustrative embodiment, the system bus includes at least one of a memory bus and a control bus. The system bus memory 703 includes a memory bus memory 7031 coupled to the memory bus and a control bus memory 7032 coupled to the control bus. When the DMA module 701 sends at least one debug information chain to the memory bus, at least one debug information chain is stored in the memory bus memory 7031. When the DMA module 701 sends at least one debug information chain to the control bus, at least one debug information chain is stored in the control bus memory 7032, so that the debug device can retrieve it at any time.

[0131] For any parts of the PCIe controller not described in detail in the above embodiments, please refer to the relevant descriptions in the debugging information acquisition method of the above embodiments, which will not be repeated here.

[0132] The debugging information acquisition method and PCIe controller of this disclosure define a flexible and controllable debugging information chain structure, which facilitates the selection of appropriate debugging information according to needs and selectively filters out unnecessary information, thereby helping to reduce the length of the debugging information chain and increase the density of useful information. The debugging information chain consists of a start identifier field, a timestamp identifier field, a status information field group, an error TLP information field group, and an end identifier field. The start identifier field includes index information that helps locate the relative position of any debugging information chain, facilitating rapid location of the required debugging information chain. The timestamp identifier field helps to clarify the relative time of the status information and error TLP information recorded in the debugging information chain. The status information can be selectively configured as needed; the user can choose to obtain the corresponding status information from the debug register in the PCIe controller and store it in the debugging information chain. The number of error TLP information obtained during the acquisition of information for a segment of the debugging information chain is recorded in the end identifier field, thereby facilitating the differentiation of the boundaries of multiple debugging information chains and the number of error TLP information within each debugging information chain. Because the acquisition of information in the debugging information chain is a time-varying process, new error TLP information may be generated at any time during the formation of a certain debugging information chain. Therefore, when generating the end identifier field at the end of the information acquisition in the debugging information chain, the number of obtained error TLP information should be recorded in the end identifier field at the same time, rather than recorded in other places in the debugging information chain. This is beneficial for coordinating with the continuous generation process of the debugging information chain content, and it is not necessary to insert the number of error TLP information separately in a certain place inside the debugging information chain. From this perspective, it helps to realize the streaming generation of the debugging information chain.

[0133] To address potential faults in the memory bus, this disclosure provides two optional storage paths for the transmission of debugging information: the memory bus address space and the control bus address space, thereby facilitating adaptability to various debugging scenarios and requirements.

[0134] To address the potential issue of insufficient address space allocated to the DMA module, which could lead to memory overflow of the debug information chain, this disclosure provides three storage modes: non-overwrite storage mode, ring-overwrite storage mode, and specified debug information chain quantity storage mode, which can flexibly meet the needs of different application scenarios.

[0135] To address the issue that existing solutions in related technologies can only read static debugging information at a certain moment, this embodiment incorporates a DMA module within the PCIe controller, enabling the transmission of real-time dynamic debugging information to the memory bus or control bus. Multiple debugging information chains are stored sequentially according to their generation time, thus allowing for dynamic changes in debugging information over time. Furthermore, the content recorded in the debugging information chains can be flexibly configured as needed, greatly facilitating the debugging process of the PCIe controller.

[0136] The debugging information acquisition method and PCIe controller of this disclosure solve the problems of insufficient debugging information and lack of dynamic changes in the debugging information of PCIe controllers in related technologies.

[0137] In illustrative embodiments, depending on the design, at least one of the PCIe controller, DMA module, system bus, and bus memory can be implemented as a combination of multiple hardware, firmware, and software (i.e., programs).

[0138] In terms of hardware, at least one of the PCIe controller, DMA module, system bus, and bus memory can be implemented as logic circuits on an integrated circuit. For example, the relevant functions of at least one of the PCIe controller, DMA module, system bus, and bus memory can be implemented in various logic blocks, modules, and circuits within one or more hardware controllers, microcontrollers, hardware processors, microprocessors, application-specific integrated circuits (ASICs), digital signal processors (DSPs), field-programmable gate arrays (FPGAs), central processing units (CPUs), or other processing units. The relevant functions of at least one of the PCIe controller, DMA module, system bus, and bus memory can be implemented as hardware circuits, such as various logic blocks, modules, and circuits in an integrated circuit, using hardware description languages ​​(such as Verilog HDL or VHDL) or other suitable programming languages.

[0139] In software or firmware form, the functionality of at least one of the PCIe controllers, DMA modules, system buses, and bus memories can be implemented as programming codes. For example, at least one of the PCIe controllers, DMA modules, system buses, and bus memories can be implemented using general programming languages ​​(such as C, C++, or assembly language) or other suitable programming languages. The programming codes can be recorded and stored in a non-transitory machine-readable storage medium. In some embodiments, the non-transitory machine-readable storage medium includes, for example, semiconductor memory and / or a storage device. An electronic device (e.g., a CPU, hardware controller, microcontroller, hardware processor, or microprocessor) can read and execute the programming codes from the non-transitory machine-readable storage medium to implement the functionality of at least one of the PCIe controllers, DMA modules, system buses, and bus memories.

[0140] In the illustrative embodiments, the debugging information acquisition method and PCIe controller of this disclosure are applicable to SoC chips, etc., wherein the SoC chip can be any one of CPU (Central Processing Unit), GPU (Graphics Processing Unit), TPU (Tensor Processing Unit), NPU (Neural Network Processing Unit), DPU (Deep Learning Processing Unit), APU (Accelerated Processing Unit), and GPGPU (General-Purpose computing on Graphics Processing Unit).

[0141] In an illustrative embodiment, a processor is also provided that includes the PCIe controller described in the above embodiments.

[0142] In an illustrative embodiment, the processor can be any one of a CPU, GPU, TPU, NPU, DPU, APU, and GPGPU.

[0143] In an illustrative embodiment, a data processing device is also provided, which includes the processor described in the above embodiments.

[0144] In an illustrative embodiment, the data processing device can be any one of a GPU card, TPU card, NPU card, DPU card, APU card, and GPGPU card.

[0145] The above description is merely a preferred embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for acquiring debugging information, characterized in that, include: The debugging information of the PCIe controller is collected through the DMA module built into the PCIe controller, forming at least one debugging information chain ordered in chronological order based on the time dimension. The debugging information includes clock information and at least one of status information and error TLP information. The at least one debug information chain is sent to the system bus through the DMA module and stored in the system bus memory. The stored at least one debug information chain constitutes a complete dynamic debug information record. The debugging information chain includes: The start identifier field is used to identify the head of the debug information chain; The end identifier field is used to identify the end of the debugging information chain; A timestamp identifier field, located after the start identifier field, is used to identify the time when the debug information chain was generated; and, At least one of the status information field group and the error TLP information field group is located between the timestamp identifier field and the end identifier field.

2. The debugging information acquisition method according to claim 1, characterized in that: The status information field group includes at least one status information field obtained by the DMA module based on at least one status information acquired at the time of generation of the debugging information chain identified by the timestamp identifier field. The error TLP information field group includes at least one error TLP information field obtained by the DMA module at the time of generation of the debug information chain identified by the timestamp identifier field.

3. The debugging information acquisition method according to claim 1, characterized in that: The start identifier field includes index information, which is used to characterize the position of the start identifier field in the debug information chain within the at least one debug information chain; The end identifier field includes the number of error TLP messages contained in the debug information chain to which the end identifier field is located.

4. The debugging information acquisition method according to claim 1, characterized in that, The method further includes: The acquisition control registers for the acquisition time, status information, and error TLP information of the DMA module are configured so that the DMA module can acquire the clock information, status information, and error TLP information based on the configured information.

5. The debugging information acquisition method according to claim 1, characterized in that: The system bus includes at least one of a memory bus and a control bus.

6. The debugging information acquisition method according to claim 5, characterized in that, The method further includes: Configure the system bus object sent by the DMA module so that the DMA module sends the debug information chain to the configured main bus, and if it fails to send the debug information chain to the main bus, sends at least one debug information chain to the configured secondary bus; The main bus is one of the memory bus and the control bus, and the secondary bus is the other of the memory bus and the control bus.

7. The debugging information acquisition method according to claim 1, characterized in that: The system bus memory is configured with a debug information chain storage space, and the at least one debug information chain is stored in the debug information chain storage space. The storage mode of the at least one debug information chain in the debug information chain storage space is configured as one of the following: non-overwrite storage mode, ring overwrite storage mode, and specified number of debug information chains storage mode; Wherein, when the storage mode is configured as the non-overwrite storage mode, the at least one debug information chain is stored sequentially in the debug information chain storage space, and storage stops when the debug information chain storage space is full; When the storage mode is configured as the ring-overlay storage mode, the at least one debug information chain is stored sequentially in the debug information chain storage space. When the debug information chain storage space is full, the latest debug information chain overwrites the earliest debug information chain stored in the debug information chain storage space. When the storage mode is configured as the specified number of debug information chains storage mode, the at least one debug information chain is stored sequentially in the debug information chain storage space until the storage of the last debug information chain of the specified number of debug information chains is completed, at which point storage stops.

8. A PCIe controller, characterized in that, include: The DMA module, built into the PCIe controller, is used to collect debugging information from the PCIe controller, form at least one debugging information chain ordered sequentially based on the time dimension, and send the at least one debugging information chain to the system bus for storage in the system bus memory. The stored at least one debugging information chain constitutes a complete dynamic debugging information record. The debugging information includes clock information, and the debugging information also includes at least one of status information and error TLP information. The debugging information chain includes: The start identifier field is used to identify the head of the debug information chain; The end identifier field is used to identify the end of the debugging information chain; A timestamp identifier field, located after the start identifier field, is used to identify the time when the debug information chain was generated; and, At least one of the status information field group and the error TLP information field group is located between the timestamp identifier field and the end identifier field.

9. A processor, characterized in that, Includes the PCIe controller as described in claim 8.

10. A data processing device, characterized in that, Includes the processor as described in claim 9.

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