Memory management method, memory management unit, chip and electronic device

Abstract

The disclosure provides a memory management method, a memory management unit, a chip and an electronic device. The memory management method comprises: receiving a command from a host device; matching the command with a tag array to obtain a matching result; if the matching is successful, generating corresponding read address information according to the hit tag, accessing a first memory according to the read address information to obtain corresponding cache line page table information, and converting virtual address information into physical address information according to the cache line page table information; if the matching fails, initiating a read page table command for accessing a second memory to obtain corresponding page table information according to the command, obtaining replacement cache line information corresponding to the page table information in the first memory, writing the page table information into the first memory according to the replacement cache line information, and updating the tag array. The disclosure improves the page table hit rate by using a preset cache line replacement strategy, meets the high-performance application requirements, and effectively reduces the power consumption and area of the IOMMU.

Description

Technical Field

[0001] This disclosure belongs to the field of memory management technology, and specifically relates to memory management methods, memory management units, chips, and electronic devices. Background Technology

[0002] The Memory Management Unit (MMU) is a component that translates virtual addresses (VA) accessed by the CPU into physical addresses (PA).

[0003] In the field of SOC chips, in addition to the traditional CPU components, there are other peripherals inside the chip, such as image signal processors, display engine processors, video codecs, and artificial intelligence neural network processors, which can serve as master devices.

[0004] Within a System-on-a-Chip (SoC) architecture, there are numerous master devices, especially in larger SoCs. Using traditional MMU (Memory Management Unit) components suitable for the CPU to manage the memory of these many master devices results in high costs in terms of area and power consumption. If multiple master devices each use their own MMU, the required area and power consumption would be even higher. Therefore, how to enable multiple master devices to share a single MMU is a problem that needs to be solved.

[0005] Generally speaking, the three parameters of a chip—performance, power consumption, and area—are interdependent. Improving performance requires a larger area and higher power consumption; achieving a balance among these three is a problem to be solved. Summary of the Invention

[0006] The purpose of this disclosure is to provide a memory management method, a memory management unit, a chip, and an electronic device to solve the problem that the PPA (Performance, Power, Area) of chips in the prior art cannot be balanced.

[0007] In a first aspect, this disclosure provides a memory management method, the method comprising: receiving a command from a master device, the command including virtual address information and a device number of the master device; matching the command with a tag array to obtain a matching result, the tag array including a plurality of tags, the tags including the virtual address information and the device number; if the matching result indicates a successful match, generating corresponding read address information according to the matched tag, accessing a first memory according to the read address information to obtain corresponding cache line page table information, and converting the virtual address information into physical address information according to the cache line page table information, the first memory storing a cache line page table for the master device; and if the matching result indicates a failed match, initiating a read page table command according to the command to access a second memory to obtain corresponding page table information, obtaining replacement cache line information corresponding to the page table information in the first memory, writing the page table information into the first memory according to the replacement cache line information, and updating the tag array, the second memory storing a page table for the master device.

[0008] In one implementation of the first aspect, accessing the first memory to obtain the corresponding cache line page table information according to the read address information includes: if a hit is successful, reading the corresponding cache line page table from the first cache space of the first memory according to the read address information, wherein the first cache space is the cache space configured for the master device in the first memory; and extracting the corresponding cache line page table information according to the cache line page table.

[0009] In one implementation of the first aspect, initiating a page table read command to access the second memory to obtain corresponding page table information according to the command includes: if a hit fails, initiating the page table read command according to the command; and receiving the corresponding page table information from the second memory according to the page table read command.

[0010] In one implementation of the first aspect, obtaining the replacement cache line information corresponding to the page table information in the first memory includes: if a cache line hit fails, initiating a cache line replacement command according to the command; and finding the corresponding cache line information in the cache line list of the master device according to the cache line replacement command and a preset cache line replacement strategy, as the replacement cache line information, wherein the cache line list of the master device is determined by the address storage space configured by the first memory for the master device.

[0011] In one implementation of the first aspect, writing the page table information into the first memory according to the replacement cache line information includes: obtaining a write address corresponding to the replacement cache line information; obtaining write data corresponding to the page table information; and writing the write data into the first memory according to the write address to replace the cache line corresponding to the replacement cache line information.

[0012] In one implementation of the first aspect, updating the tag array includes: updating the tag array according to the replacement cache line information and the page table information to obtain an updated tag array, wherein the memory management method further includes: matching the command with the updated tag array to convert the virtual address information into physical address information according to the page table information, so as to facilitate cyclic scheduling of address information conversion for the master device.

[0013] In one implementation of the first aspect, matching the command with the tag array to obtain a matching result includes: matching the virtual address information of the command with the virtual address information of the tag to obtain a first matching result; matching the device number of the command with the device number of the tag to obtain a second matching result; when both the first matching result and the second matching result are successful, the matching result is a successful match; otherwise, the matching result is a failed match.

[0014] In one implementation of the first aspect, receiving a command from a master device includes: receiving one or more commands from one or more master devices; converting the one or more commands into input command information, the input command information including the one or more commands in a streaming structure; and sequentially retrieving the commands from the input command information for matching with the tag array.

[0015] In one implementation of the first aspect, the memory management method further includes: configuring corresponding address storage spaces for one or more master devices in the first memory, wherein the address storage space includes a plurality of cache line page table information, and the cache line page table information includes a plurality of page table information; and dividing the address storage space into page table levels according to the needs of the one or more master devices.

[0016] In one implementation of the first aspect, configuring corresponding address storage space in the first memory for one or more master devices includes: dividing the first memory into a first storage space; and configuring the first storage space to the first master device among the one or more master devices.

[0017] In one implementation of the first aspect, configuring corresponding address storage space in the first memory for one or more master devices includes: dividing the first memory into a first storage space, a second storage space, and a third storage space; configuring the first storage space for the first master device among the one or more master devices; configuring the second storage space for the second master device among the one or more master devices; and configuring the third storage space for the first master device and the second master device.

[0018] In one implementation of the first aspect, configuring corresponding address storage space in the first memory for one or more master devices includes: dividing the first memory into a first storage space and a second storage space; configuring the first storage space to the first master device among the one or more master devices; and configuring the second storage space to the second master device among the one or more master devices.

[0019] In one implementation of the first aspect, configuring corresponding address storage space in the first memory for one or more master devices includes: dividing the first memory into a first storage space; and configuring the first storage space to a first master device and a second master device among the one or more master devices.

[0020] In one implementation of the first aspect, partitioning the address storage space at the page table level according to the needs of the one or more master devices includes at least one of the following: partitioning the corresponding address storage space into a first-level page table according to the needs; partitioning the corresponding address storage space into a second-level page table according to the needs; and partitioning the corresponding address storage space into a multi-level page table according to the needs.

[0021] In one implementation of the first aspect, the first memory is disposed in a conversion backstop buffer, and the second memory is disposed outside the conversion backstop buffer.

[0022] Secondly, this disclosure provides a memory management unit, comprising: an input command cache module configured to receive commands from a master device, the commands including virtual address information and a device number of the master device; and a core processing module configured to: match the commands with a tag array to obtain a matching result, the tag array including a plurality of tags, the tags including the virtual address information and the device number; if the matching result indicates a successful match, generate corresponding read address information according to the matched tag, access a first memory according to the read address information to obtain corresponding cache line page table information, and process the virtual address information according to the cache line page table information. Address information is converted into physical address information. The first memory stores a cache line page table for the master device. If the matching result indicates a matching failure, a read page table command is initiated to access the second memory to obtain the corresponding page table information. Replacement cache line information corresponding to the page table information is obtained from the first memory. The page table information is written into the first memory according to the replacement cache line information, and the tag array is updated. The second memory stores a page table for the master device. The first memory is located inside the memory management unit, and the second memory is located outside the memory management unit.

[0023] In one implementation of the second aspect, the memory management unit further includes: an output command cache module configured to cache and output the physical address information and the page table read command; and a pass-through logic module configured to output the physical address information to the bus for accessing memory, and configured to send the page table read command to a corresponding port for obtaining the page table information.

[0024] In one implementation of the second aspect, the core processing module includes: a cyclic pipelined address command cache, configured to store the commands and pipelined control information for controlling various components in the memory management unit; a tag array module, configured to store the tags, match the commands with the tag array to obtain matching results, generate corresponding read address information based on the matched tags, and be configured to update the tag array based on the replacement cache line information and the page table information to obtain an updated tag array; a page table command cache, configured to store the virtual address information, and initiate a read page table command based on the commands if a match fails; a conversion backup buffer, including a storage control unit and the first memory, configured to store the cache line page table, and configured to access the cache line page table based on the read address information to obtain corresponding cache line page table information, and convert the virtual address information into the physical address information based on the cache line page table information or the page table information; and a replacement unit, configured to determine the replacement cache line information in the first memory, and write the page table information into the first memory based on the replacement cache line information.

[0025] Thirdly, this disclosure provides a chip comprising: one or more master devices; memory; and a memory management unit according to the above description, coupled to the one or more master devices and coupled to the memory via a system bus.

[0026] Fourthly, this disclosure provides an electronic device comprising: a memory configured to store an executable program; and a processor configured to execute the program to cause the electronic device to perform the memory management method described above.

[0027] According to embodiments of this disclosure, a circuit structure and method suitable for multiple master devices sharing an IOMMU master control pipeline are proposed, effectively reducing the area and power consumption of the IOMMU. A circuit structure and method suitable for multiple master devices sharing IOMMU page tables are proposed, effectively reducing the IOMMU area while still meeting high-performance application requirements. A method for multiple master devices to dynamically share and exclusively occupy a portion of the TLB internal page table space is proposed, improving the IOMMU internal memory hit rate and fully utilizing the IOMMU's energy efficiency. A page table cache replacement algorithm for multiple master devices is proposed, making page table replacement more reasonable and the IOMMU's internal TLB cache more efficiently used. Attached Figure Description

[0028] Figure 1 This diagram shows the structure of the IOMMU for multiple master devices.

[0029] Figure 2 The diagram shown is a structural schematic of a shared IOMMU according to an embodiment of the present disclosure.

[0030] Figure 3 The diagram shown is a circuit schematic of an IOMMU according to an embodiment of the present disclosure.

[0031] Figure 4 The diagram shown is a flowchart of a memory management method according to an embodiment of the present disclosure.

[0032] Figure 5 The diagram illustrates the division of the address space range of the internal TLB of the IOMMU by multiple master devices according to an embodiment of the present disclosure.

[0033] Figure 6 The diagram shown is a structural schematic of a memory management unit according to an embodiment of the present disclosure.

[0034] Figure 7 The diagram shown is a structural schematic of the core processing module according to an embodiment of the present disclosure.

[0035] Figure 8 The diagram shown is a structural schematic of a memory management unit according to an embodiment of the present disclosure in another embodiment.

[0036] Figure 9 The diagram shown is a schematic representation of the structure of a chip according to an embodiment of the present disclosure.

[0037] Figure 10 The diagram shows a comparison of the area of ​​a multi-master IOMMU structure according to an embodiment of the present disclosure with that of a conventional IOMMU scheme.

[0038] Figure 11 The diagram shows a power consumption comparison between a multi-master IOMMU structure according to an embodiment of the present disclosure and a conventional IOMMU scheme.

[0039] Figure 12 The diagram shows a performance comparison between a multi-master IOMMU structure according to an embodiment of the present disclosure and a conventional IOMMU scheme.

[0040] Figure 13 The diagram shown is a structural schematic of an electronic device according to an embodiment of the present disclosure. Detailed Implementation

[0041] The following specific examples illustrate the implementation of this disclosure. Those skilled in the art can easily understand other advantages and effects of this disclosure from the content disclosed in this specification. This disclosure can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this disclosure. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.

[0042] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this disclosure. Therefore, the drawings only show the components related to this disclosure and are not drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0043] First, the technical terms used in this disclosure will be explained.

[0044] IOMMU: Input / Output Memory Management Unit, which provides address mapping and translation services.

[0045] DTE base: Used to store the physical address of the first-level table (i.e., DTE) for IOMMU to query.

[0046] DTE: Device Table Entry, first-level table entry. Each entry stores the physical address of the next-level (second-level) PTE table entry.

[0047] PTE: Page Table Entry, a second-level table entry, each entry stores the physical address of the data page it manages.

[0048] Page: A page is a small block of physical memory.

[0049] TLB: Translation Lookaside Buffer, is a part of computer memory management hardware used to speed up the translation process from virtual addresses to physical addresses.

[0050] In traditional SoC architectures, components with host device functions (such as traditional CPUs, image signal processors, display engine processors, video codecs, and AI neural network processors) directly access physical addresses. However, this often requires the operating system to allocate a large, contiguous address space for them. We know that the smallest unit an operating system can allocate at one time is a page (4KB). If a large, contiguous address space is used, memory becomes scarce and fragmentation becomes severe during the execution of complex programs. Programs sometimes cannot obtain a sufficiently large contiguous address space when requesting memory, which severely limits the application scenarios of such host-device processors. Furthermore, address access security is not easily guaranteed.

[0051] In some embodiments, to address this issue, an MMU (Master Module) is placed between the host processor and the bus within the SOC architecture, such as... Figure 1 As shown. This type of MMU is named Memory Management Unit, or IOMMU, also known as Input / Output Memory or Memory Management Unit, and provides address mapping and translation services.

[0052] Figure 1 This is a structural diagram showing the IOMMU of multiple master devices. (Example) Figure 1 As shown, each master device has its own dedicated IOMMU controller. Clearly, adding an IOMMU will impact system access performance, speed, area, and power consumption compared to the original configuration. Using a traditional CPU-specific IOMMU would incur significant area and power consumption costs. Therefore, compared to the configuration without an IOMMU, it is necessary to optimize both area and power consumption with minimal performance loss. This is a fundamental problem that needs to be solved in this field.

[0053] In addition, there are numerous master devices within a SoC, especially in larger SoCs where there are often dozens of master devices. If each master device has its own dedicated IOMMU controller, it will inevitably lead to a waste of IOMMU hardware resources. If multiple master devices of the same type can share the IOMMU, it will greatly reduce the area and power consumption of the IOMMU section. However, how to ensure that there is no performance loss, or even some performance improvement in certain scenarios, are new challenges facing IOMMU design.

[0054] Figure 2 The diagram shown is a schematic representation of a system architecture of a shared IOMMU as described in an embodiment of this disclosure. Figure 2As shown, considering the functions that an IOMMU needs to perform, sharing the IOMMU circuitry among multiple IOMMU devices of the same type, with similar requirements, or even those that are absolutely mutually exclusive based on application scenarios would be a good choice. However, from a practical standpoint, this type of IOMMU architecture inherently suffers from congestion when multiple master devices arbitrate the IOMMU, leading to a performance degradation. How can we ensure that performance loss is minimal?

[0055] Generally speaking, the three parameters of a chip—performance, power consumption, and area—are interdependent. Improving performance often requires a larger chip area and higher power consumption. How can we ensure a trade-off between these three factors?

[0056] This invention addresses the issue that multiple master devices sharing the same IOMMU page table may experience mutual replacement, leading to a significant drop in the cache hit rate within the IOMMU. To resolve this hit rate problem, a method is proposed to dynamically divide the page table usage range within the IOMMU. This effectively reduces the hit rate drop based on the scenario and optimizes power consumption and area.

[0057] The IOMMU's function is to map virtual addresses (VAs) to physical addresses (PAs). This operation is performed through table lookups; the more complex the mapping rules, the larger the space occupied by the mapping table. As the virtual address space (VA) expands in later IOMMUs, two-level access methods are often insufficient, sometimes requiring three or even four levels of page tables. Multi-level access methods inevitably increase the design complexity of the IOMMU, making the solution a challenge.

[0058] The present disclosure provides a memory management method, a memory management unit, a chip, and an electronic device, which solve the problem that the PPA (Performance, Power, and Area) of chips cannot be balanced in the prior art.

[0059] Figure 3 The diagram shown is a circuit schematic of an IOMMU according to an embodiment of the present disclosure. Figure 3As shown in the diagram, this embodiment provides a circuit diagram of an IOMMU, which includes: an input command cache module 100, a core processing module 110, an output command cache module 120, and a pass-through logic module 130. The core processing module 110 internally includes a cyclic pipelined address command cache 111, a page table command cache 112, a tag array 113, a TLB (Track Block Translation) cache 114, and a multi-master LRU (Least Recently Used) replacement unit 115.

[0060] In some embodiments, the IOMMU needs to interconnect with multiple master devices during use, thus requiring a CrossBar module 140. This module is responsible for converting multiple master devices into a single master device channel. The single master device channel can indicate which master device initiated the command by defining a multi-bit identifier, similar to the extension of the ID identifier on the AXI bus. This method effectively solves the arbitration and queuing problems of commands initiated by multiple master devices.

[0061] In some embodiments, the input command cache module 100 is coupled to an external bus interface with master device functionality via its input terminal, typically an AXI bus, but not limited to it. For multi-master device command identification, we use an extended ID to identify which master device the command originates from. For ease of reference later, we will uniformly name this extended ID the device number. Register configuration commands are also transmitted through this port. The difference from the command stream is that register configuration does not need to be written to the command cache; it is directly parsed and configured into internal registers. The input command cache module 100 outputs multiple virtual address commands (VAs, generally referring to virtual addresses in the following text) that need to be mapped by master devices via its output terminal. The input command cache module 100 is responsible for caching virtual addresses sent from external master devices and parsing and translating register configuration commands, directly sending the configuration results to the registers without caching.

[0062] In some embodiments, the cyclic pipelined address command buffer 111 receives input virtual address commands from the multi-master device IOMMU via its input terminal. Taking the AXI bus as an example, it can store input write address commands or read address commands. The cyclic pipelined address command buffer 111 outputs pipelined control information of each component within the multi-master device IOMMU via its output terminal. The cyclic pipelined address command buffer 111 is used to schedule and implement cyclic multi-stage pipelined operation within the IOMMU.

[0063] Pipeline characteristics generally refer to a three-stage pipeline. The first stage pipeline immediately compares the incoming command with the tag array. The second stage pipeline performs a table lookup if a match is found. The third stage pipeline performs address translation on the page table data retrieved from the lookup table and prepares the result to write to the output command buffer.

[0064] The circular characteristic means that if the command fails to match, or if the page table needs to be looked up multiple times, the original command VA needs to be written back to the address command cache, hence the circular characteristic.

[0065] Compared to a single-master IOMMU, a multi-master device not only needs to store the VA virtual address, but also needs to store extended identification information.

[0066] In some embodiments, the page table command cache 112 receives virtual address information of multiple master devices via an input terminal and outputs virtual address information of multiple master devices via an output terminal. The page table command cache 112 is responsible for caching the virtual address information of master devices. The purpose of caching is that when a command is initiated, the corresponding response data cannot be returned immediately and needs to wait for a period of time. During this period, the initiated command needs to be saved by a caching module. This module implements this function.

[0067] In some embodiments, the tag array 113 receives virtual address information from multiple master devices via its input terminal and outputs a TLB cache address, a hit determination, and a read enable signal via its output terminal. The tag array 113 is used to match the virtual addresses of multiple master devices in parallel with the unique identifier records of the master devices, and simultaneously provide the matching result (i.e., hit information). If a match is found, a matching number is given, which is then encoded to obtain the TLB cache address. This address is used to prepare for subsequent TLB queries. If a hit occurs, the TLB cache read enable signal becomes valid.

[0068] In some embodiments, the TLB cache 114 receives the TLB cache address, page table data returned by the response channel, TLB read enable signal, and write enable signal via its input terminal, and outputs the read page table data returned by the TLB via its output terminal. The TBL (Translation Backup Buffer) is responsible for temporarily storing page table information. It typically has a small storage space and is responsible for storing the most recently used page table data, similar to the cache structure on the CPU.

[0069] In some embodiments, the multi-master LRU replacement unit 115 receives returned page table data via its input and is coupled to the page table command cache. The multi-master LRU replacement unit 115 outputs the TLB write address to be replaced and the page table write data via its output. If the response channel returns page table data, the multi-master LRU replacement unit 115 is used to synchronously retrieve the corresponding page table command from the page table command cache, then write it back to the corresponding position in the TLB cache according to the newly generated TLB address to be replaced, and simultaneously update the tag array.

[0070] In some embodiments, the output command caching module 120 receives a newly obtained conversion command via an input terminal and outputs a new command to an external bus via an output terminal for caching output commands.

[0071] In some embodiments, the pass-through logic module 130 receives the original input command and the latest converted command via its input terminal, and outputs the actual command to the external port via its output terminal. The pass-through logic module 130 is used to directly pass through the original command when the multi-master device IOMMU is not enabled, and when enabled, the output command comes from the output command buffer module 120 and the output command buffer.

[0072] The following will describe in detail, with reference to the accompanying drawings, the principles and implementation methods of a memory management method, memory management unit, chip and electronic device of this embodiment, so that those skilled in the art can understand the technical solution of this disclosure without creative effort.

[0073] The technical solutions in the embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0074] like Figure 4 As shown, this embodiment provides a memory management method. The memory management method includes the following steps S210 to S240.

[0075] Step S210: Receive a command from the master device, the command including the virtual address information and device number of the master device.

[0076] In some embodiments, if there is only one master device, then the commands of that master device are received.

[0077] In some embodiments, if multiple master devices exist and concurrent access to the IOMMU is required, the IOMMU is not directly connected to the multiple master devices, but rather interconnected through the CrossBar 140 module. This design allows for flexible support of multiple configurable master devices sharing IOMMU access, significantly saving space.

[0078] When multiple master devices access the IOMMU in parallel, after arbitration at the intersection 140, one command is initiated at a time. These commands form a streaming structure and are sequentially sent to the input command buffer 100 of the IOMMU of the multiple master devices.

[0079] Step S220: Match the command with the tag array to obtain the matching result. The tag array includes several tags, and the tags include the virtual address information and the device number.

[0080] In some embodiments, the virtual address information of multiple master devices in parallel and the unique identifier (device number) of the master devices are matched once with the virtual address information and device number of the master devices recorded in the tag array, and the matching result (i.e., hit information) is given. If a match is found, the matching tag number is given, and the tag number is then encoded to obtain the address of the TLB cache. This address is used to prepare for subsequent TLB queries. If a hit occurs, the read enable signal of the TLB cache is valid.

[0081] Step S230: If the matching result indicates a successful match, generate corresponding read address information based on the matched tag, access the first memory based on the read address information to obtain the corresponding cache line page table information, and convert the virtual address information into physical address information based on the cache line page table information. The first memory stores a cache line page table for the master device.

[0082] In some embodiments, the first memory here may be the TLB cache or cache inside the IOMMU, responsible for storing the most recently used page table information. It should be noted that the first memory here is described using the TLB cache inside the IOMMU as an example.

[0083] Step S240: If the matching result indicates a matching failure, initiate a page table read command to access the second memory to obtain the corresponding page table information according to the command, obtain the replacement cache line information corresponding to the page table information in the first memory, write the page table information into the first memory according to the replacement cache line information, and update the tag array. The second memory stores the page table for the master device.

[0084] In some embodiments, the second memory here is the IOMMU external memory, used to store detailed page table information of each master device.

[0085] In one embodiment of this disclosure, step 230, which involves accessing the first memory based on the read address information to obtain the corresponding cache line page table information, may include steps S310 to S320.

[0086] In step S310, if the hit is successful, the corresponding cache line page table is read from the first cache space of the first memory according to the read address information. The first cache space is the cache space configured for the master device in the first memory.

[0087] In step S320, the corresponding cache line page table information is extracted according to the cache line page table.

[0088] In some embodiments, if a match is successful, the pipeline branch proceeds to the successful match branch, where the read address information of the TLB cache is generated using the tag array number. Next, the corresponding cache page table is read from the TLB, the corresponding page table information is extracted, and after a simple translation, the actual physical address (PA) information is obtained and sent to the output command cache.

[0089] It should be noted that the device number information corresponding to this command and other auxiliary information of the bus are also written into the output command buffer. For example, if it is an AXI bus, it should also include AXI-related burst type, len, size, etc., so that the command output information of the AXI bus can be correctly recovered at the command output end.

[0090] In one embodiment of this disclosure, initiating a page table read command to access the second memory to obtain corresponding page table information according to the command includes steps S410 to S420.

[0091] In step S410, if the hit fails, the page table read command is initiated according to the command.

[0092] In step S420, the corresponding page table information is received from the second memory according to the page table read command.

[0093] In some embodiments, if a match fails, the pipeline enters a pipeline branch indicating a failed match. This means the page table information to be queried is not in the TLB cache, so a page table command needs to be directly sent to the external cache to read the page table information. This command information is placed in the output command buffer 120, and then, after being judged by the pass-through channel 130, it is directly sent to the external port for memory access operation. Based on the returned page table information, the corresponding physical address PA information can be calculated, thus completing a virtual address VA to physical address PA translation operation.

[0094] In one embodiment of this disclosure, obtaining replacement cache line information in the first memory corresponding to the page table information includes steps S510 to S520.

[0095] In step S510, if the hit fails, a cache line replacement command is initiated according to the command.

[0096] In step S520, the corresponding cache line information is found in the cache line list of the main device according to the cache line replacement command and the preset cache line replacement strategy, and is used as the replacement cache line information.

[0097] In some embodiments, the cache line list of the master device is determined by the address storage space configured for the master device by the first memory.

[0098] In some embodiments, when a match fails, one of the cache lines in the TLB cache 114 needs to be replaced. So, which cache line needs to be replaced? The replacement strategy here is to use the multi-master device LRU replacement unit 115. For multi-master devices, each master device maintains an LRU replacement weight list. The specific replacement strategy can be described as follows.

[0099] In some embodiments, for each master device, after initialization, it can be numbered in ascending order according to the specified TLB depth, such as numbering values ​​0, 1, 2, 3...N. This ensures that whenever a page table needs to be replaced, only the position of the page table with the lowest number needs to be found to complete the replacement. Assuming the minimum weight to be replaced is located at TLB depth K, after the replacement, the weight at position K is updated to the maximum value N, and the weights at other positions are reduced by 1. To ensure a more effective replacement strategy, if there is a TLB hit each time, assuming the hit position is M, then the weights of other positions that originally had a weight higher than M are reduced by 1, while the weights of positions with a weight lower than M remain unchanged. In addition, there is a special scenario where the software configuration IOMMU needs to invalidate (Zap) a certain cache line inside the TLB. In this case, the weight update strategy will be adjusted. Suppose the position is K and its current weight is E. Then all other positions with values ​​less than E will have their weights increased by 1. The weights of the positions that were originally greater than E will remain unchanged, while the weight at position K will be directly updated to the minimum value.

[0100] In some embodiments, after the strategy of dynamically adaptively updating weights is executed, the page table data returned from the external cache (i.e., cache line) can be used as write data. At the same time, the multi-master device LRU replacement unit 115 also generates the corresponding write address, so that the new page table information can be written to the specified TLB location, completing an update operation. Simultaneously, the corresponding physical address PA information can also be calculated based on the feedback page table information, thus completing a virtual address VA to physical address PA conversion operation.

[0101] In one embodiment of this disclosure, writing the page table information into the first memory according to the replacement cache line information includes steps S610 to S630.

[0102] In step S610, the write address corresponding to the replacement cache line information is obtained.

[0103] In step S620, write data corresponding to the page table information is obtained.

[0104] In step S630, the write data is written into the first memory according to the write address to replace the cache line corresponding to the replacement cache line information.

[0105] In one embodiment of this disclosure, updating the tag array includes step S710.

[0106] In step S710, the tag array is updated according to the replacement cache line information and the page table information to obtain the updated tag array.

[0107] In some embodiments, the memory management method may further include: in step S720, matching the command with the updated tag array to convert the virtual address information into physical address information according to the page table information, so as to facilitate cyclic scheduling for address information conversion of the master device.

[0108] In some embodiments, after the dynamic adaptive weight update strategy is executed, the page table data returned from the external cache (i.e., cache line) can be used as write data. Simultaneously, the multi-master LRU replacement unit 115 generates a corresponding write address, thus writing the new page table information to the specified TLB location and completing an update operation. In this embodiment, the failed master device command is stored in the cyclic pipeline address command cache 111, and the updated tag array is used to facilitate the re-cyclic scheduling of the master device, thereby ensuring multi-level page table access for the master device.

[0109] This disclosure utilizes the internal TLB cache of the designed IOMMU for dynamic updates and employs an optimized LRU replacement strategy for multiple master devices. After testing, compared with the traditional approach, power consumption is effectively reduced, performance is significantly improved, and the cache miss rate is very low, which can meet the performance requirements of multi-master IOMMU.

[0110] In one embodiment of this disclosure, matching the command with the tag array to obtain a matching result includes steps S810 to S840.

[0111] In step S810, the virtual address information of the command is matched with the virtual address information of the tag to obtain a first matching result.

[0112] In step S820, the device number of the command is matched with the device number of the tag to obtain a second matching result.

[0113] In step S830, when both the first matching result and the second matching result are successful, the matching result is considered a successful match.

[0114] In step S840, otherwise the matching result is a failed match.

[0115] It should be noted that a master device is considered to have successfully matched a tag array only if the virtual address information and device number in the master device's command match the virtual address information and device number in the tag array simultaneously. Otherwise, the match is considered to have failed. This ensures the normal operation of multiple master devices and avoids situations where master devices are matched incorrectly.

[0116] In one embodiment of this disclosure, receiving a command from the master device includes steps S910 to S930.

[0117] In step S910, one or more commands are received from one or more master devices.

[0118] In step S920, the one or more commands are converted into input command information, the input command information including the one or more commands in a streaming structure.

[0119] In step S930, the commands are sequentially obtained from the input command information for matching with the tag array.

[0120] In one embodiment of this disclosure, the memory management method further includes steps S1010 to S1020.

[0121] In step S1010, a corresponding address storage space is configured in the first memory for one or more master devices. The address storage space includes several cache line page table information, and the cache line page table information includes several page table information.

[0122] In step S1020, the address storage space is divided into page table levels according to the needs of the one or more master devices.

[0123] It should be noted that the first memory here is the TLB cache inside the IOMMU as an example.

[0124] In some embodiments, before the IOMMU operates, the CPU needs to allocate page table cache space for each master device based on the second memory. This cache space is responsible for storing the response page table information. This space can be shared or dedicated, offering great flexibility and being entirely controlled by software. The second memory is an external cache used to store detailed page table information for the master devices.

[0125] Next, configure an IOMMU for each master device and allocate the address space range of the TLB inside the IOMMU for each master device, that is, configure a corresponding address storage space for each master device.

[0126] In some embodiments, if there is only one master device, the first memory is used to configure the corresponding address storage space for that master device.

[0127] In some embodiments, the entire address space of the internal TLB of the IOMMU can be allocated to the master device; or an appropriate address space range can be allocated according to the actual needs of the master device.

[0128] In some embodiments, if there are at least two master devices, the first memory is used to configure corresponding address storage space for each master device.

[0129] Figure 5 This diagram illustrates the division of the address space range of the internal TLB of the IOMMU by multiple master devices according to an embodiment of this disclosure. Assuming the cumulative TLB space depth is L, and it is divided into three regions M, N, and K, with L = M + N + K, it can store a maximum of M + N + K page table cache lines. Each page table cache line can contain one or more page table entries. The length of each cache line is approximately proportional to the burst length of accessing DDR memory, thus making access more user-friendly.

[0130] The following example illustrates the partitioning method by dividing the TLB space into two regions and using the IOMMU of a dual-master device. It includes the following three use cases.

[0131] Scenario 1: Partially Shared Scenario. First, depth M identifies the shared page table cache line area, which is the area where multiple master devices share page tables. This means that this part of the page table can be shared or replaced by all devices. Then, the range of depth N identifies the cache line area exclusively used by master device 1, and the range of depth K identifies the cache line area exclusively used by master device 2.

[0132] The exclusive zones here are considered a correct match only if they can be matched with the corresponding master device. If the device number cannot be matched, but the virtual address has been matched, then it is not considered a successful match.

[0133] Scenario 2: Fully Shared Scenario. If region M is expanded to the entire TLB space, i.e., M=L, N=K=0, then this is a scenario of fully shared page table space. In this case, multiple master devices fully share the TLB space. This configuration can achieve a high IOMMU matching rate in some situations, making it suitable for scenarios where multiple master devices of the same type are performing the same task.

[0134] Scenario 3: Completely Exclusive Scenario. If the M region is reduced to 0, i.e., M=0 and N+K=L, then each master device uses its own TLB space, completely independent and without interference. This scenario is suitable for situations where the memory access behaviors of multiple master devices are completely inconsistent. The advantage of doing so is to prevent mutual page table eviction within the TLB, which could affect IOMMU performance.

[0135] After the TLB page table space is initially partitioned across multiple master devices, the dedicated space within each master device is then dynamically partitioned into multi-level page tables. For example, some page tables are suitable for large page access of 4MB, so they can all be allocated according to level 1 page tables. In scenarios where some page tables require a mix of level 1 and level 2, they can be further partitioned according to requirements. This allocation mechanism is very flexible, with the sole purpose of improving the IOMMU page table hit rate and adapting to various application scenarios.

[0136] After configuring and partitioning the page table space of the IOMMU, configure and enable the page table translation function of the multi-master device IOMMU.

[0137] In one embodiment of this disclosure, configuring corresponding address storage space for one or more master devices in the first memory includes steps S1110 to S1120.

[0138] In step S1110, the first memory is divided into a first storage space.

[0139] In step S1120, the first storage space is configured to the first master device among the one or more master devices.

[0140] In one embodiment of this disclosure, configuring corresponding address storage space for one or more master devices in the first memory includes steps S1210 to S1240.

[0141] In step S1210, the first memory is divided into a first storage space, a second storage space, and a third storage space.

[0142] In step S1220, the first storage space is configured to the first master device among the one or more master devices.

[0143] In step S1230, the second storage space is configured to the second master device among the one or more master devices.

[0144] In step S1240, the third storage space is configured for the first master device and the second master device.

[0145] In one embodiment of this disclosure, configuring corresponding address storage space for one or more master devices in the first memory further includes steps S1310 to S1330.

[0146] In step S1310, the first memory is divided into a first storage space and a second storage space.

[0147] In step S1320, the first storage space is configured to the first master device among the one or more master devices.

[0148] In step S1330, the second storage space is configured to the second master device among the one or more master devices.

[0149] In one embodiment of this disclosure, configuring corresponding address storage space for one or more master devices in the first memory includes steps S1410 to S1420.

[0150] In step S1410, the first memory is divided into a first storage space.

[0151] In step S1420, the first storage space is configured to the first master device and the second master device among the one or more master devices.

[0152] In one embodiment of this disclosure, partitioning the address storage space at the page table level according to the needs of the one or more master devices includes at least one of the following steps S1510 to S1530.

[0153] In step S1510, a first-level page table is partitioned for the corresponding address storage space according to the requirements.

[0154] In step S1520, a second-level page table is partitioned for the corresponding address storage space according to the requirements.

[0155] In step S1530, multi-level page tables are partitioned for the corresponding address storage space according to the requirements.

[0156] In one embodiment of this disclosure, the first memory is disposed in a conversion backstop buffer, and the second memory is disposed outside the conversion backstop buffer.

[0157] The scope of protection of the memory management method described in this disclosure is not limited to the execution order of the steps listed in this embodiment. Any solution implemented by adding, subtracting, or replacing steps in the prior art based on the principles of this disclosure is included within the scope of protection of this disclosure.

[0158] This disclosure also provides a memory management unit that can implement the memory management method described in this disclosure. However, the implementation apparatus for the memory management method described in this disclosure includes, but is not limited to, the structure of the memory management unit listed in this embodiment. Any structural modifications and substitutions of the prior art made in accordance with the principles of this disclosure are included within the protection scope of this disclosure.

[0159] like Figure 6 As shown, this embodiment provides a memory management unit, which includes an input command cache module 210 and a core processing module 220.

[0160] The input command caching module 210 is configured to receive commands from the master device, the commands including the virtual address information and device number of the master device.

[0161] The core processing module 220 is configured to match the command with a tag array to obtain a matching result. The tag array includes several tags, and each tag includes the virtual address information and the device number.

[0162] Furthermore, the core processing module 220 is configured to, if the matching result indicates a successful match, generate corresponding read address information based on the matched tag, access the first memory based on the read address information to obtain the corresponding cache line page table information, and convert the virtual address information into physical address information based on the cache line page table information. The first memory stores a cache line page table for the master device.

[0163] In addition, the core processing module 220 is configured to, if the matching result indicates a matching failure, initiate a page table read command to access the second memory to obtain the corresponding page table information, obtain replacement cache line information corresponding to the page table information in the first memory, write the page table information into the first memory according to the replacement cache line information, and update the tag array. The second memory stores the page table for the master device, wherein the first memory is located inside the memory management unit, and the second memory is located outside the memory management unit.

[0164] like Figure 6 As shown, the memory management unit 20 may further include: an output command cache module 230 and a pass-through logic module 240.

[0165] The output command caching module 230 is configured to cache and output the physical address information and the page table read command.

[0166] The pass-through logic module 240 is configured to output the physical address information to the bus for accessing memory, and is configured to send the page table read command to the corresponding port for obtaining the page table information.

[0167] like Figure 7 As shown, the core processing module 220 includes: a cyclic pipelined address command cache 2210, a tag array module 2220, a page table command cache 2230, a translation backup buffer 2240, and a replacement unit 2250.

[0168] The cyclic pipelined address command cache 2210 is configured to store the commands and pipeline control information for controlling the various components in the memory management unit.

[0169] The tag array module 2220 is configured to store the tags, match the command with the tag array to obtain a matching result, generate corresponding read address information based on the matched tag, and update the tag array based on the replacement cache line information and the page table information to obtain the updated tag array.

[0170] The page table command cache 2230 is configured to store the virtual address information, and if a hit fails, it initiates the page table read command according to the command.

[0171] The conversion backup buffer 2240 includes a storage control unit and the first memory, is configured to store the cache line page table, and is configured to access the cache line page table according to the read address information to obtain the corresponding cache line page table information, and convert the virtual address information into the physical address information according to the cache line page table information or the page table information.

[0172] The replacement unit 2250 is configured to determine the replacement cache line information in the first memory and write the page table information into the first memory according to the replacement cache line information.

[0173] It should be noted that the functions or operations of the input command cache module 210, core processing module 220, output command cache module 230, pass-through logic module 240, and the loop pipelined address command cache 2210, tag array module 2220, page table command cache 2230, translation backup buffer 2240 and replacement unit 2250 in the core processing module 220, as described in this embodiment, correspond one-to-one with the steps in the memory management method described above, and therefore will not be repeated here.

[0174] Figure 8 The diagram shown is a structural schematic of the memory management unit described in this disclosure in another embodiment. (Refer to...) Figure 8The input command cache module 100 receives one or more commands from one or more master devices. Each command includes the virtual address information and device number of the master device. The commands are sent to the tag array module 113 in the core processing module through the multiplexer MUX to match the commands with the tag array to obtain the matching result.

[0175] If the matching result is successful, the corresponding read address information is generated according to the matched tag. The TLB cache 114 is accessed according to the read address information to obtain the corresponding cache line page table information. The virtual address information is converted into physical address information according to the cache line page table information. The physical address information is output to the pass-through logic module 130 through the output command cache module 120. The physical address information is then output to the system bus through the pass-through logic module 130 for memory access.

[0176] If the matching result is a failure, a page table read command is initiated through the page table command cache 112 to access the external cache to obtain the corresponding page table information. This page table read command is placed in the output command cache module 120, and then sent directly to the external port for accessing the external cache after being judged by the pass-through channel 130. The corresponding page table information is received from the external cache through the response channel.

[0177] If a match fails, a cache line replacement command is initiated according to the command. Based on the cache line replacement command and the preset cache line replacement strategy, the multi-master device LRU replacement unit 115 finds the corresponding cache line information in the cache line list of the master device and uses it as the replacement cache line information.

[0178] The page table information is written into the TLB cache 114 according to the replacement cache line information, and the tag array is updated.

[0179] Upon failure of a match, the present embodiment stores the failed master device command in the cyclic pipeline address command cache 111 and utilizes the updated tag array to facilitate the cyclic scheduling of the master device again, thereby ensuring multi-level page table access of the master device.

[0180] like Figure 9 As shown, this disclosure also provides a chip, the chip 30 including one or more host devices 310, memory 320, and the memory management unit 20 described above, coupled to the one or more host devices 310 and coupled to the memory 320 via a system bus.

[0181] The following examples illustrate the comparison of the area, power consumption, and performance of the multi-master IOMMU structure described in this disclosure with traditional IOMMU solutions.

[0182] Figure 10 This diagram illustrates a comparison of the area of ​​the multi-master IOMMU structure described in this embodiment and a traditional IOMMU solution. Figure 10 As shown in the figure, the horizontal axis represents the number of IOMMU instantiations, which can be 1, 2, 3, or 4. The vertical axis represents the area, where it is assumed that the area unit of the IOMMU in the traditional scheme is 1. The dashed line represents the area data of the traditional IOMMU, and the solid line represents the area data of the present invention.

[0183] Depend on Figure 10 It's easy to see that when the number of master devices sharing the IOMMU increases, this invention doesn't significantly increase the IOMMU area. This is because it uses a multi-master device shared IOMMU interface. The slight increase in area is mainly due to three factors: First, the externally integrated CROSS BAR has area overhead. Second, the multi-master device IOMMU needs to store device number information, which is unnecessary in a traditional single-master device IOMMU. Third, the LRU replacement strategy requires separate queue maintenance. However, these overheads are very small compared to a single-master device IOMMU (i.e., a traditional IOMMU) because the TLB portion, which accounts for the majority of the area, is completely shared, and the internal cache structure of the IOMMU device is almost entirely reused. In summary, this effectively avoids a significant increase in area.

[0184] Figure 11 This diagram illustrates a power consumption comparison between the multi-master IOMMU structure described in this embodiment and a traditional IOMMU solution. Figure 11 As shown, because the area increase is relatively small, the increase in power consumption is directly proportional to the area in the same scenario when considering IOMMU usage. Assuming the power consumption of a single-master IOMMU is 1 unit, then the power consumption of a single-master IOMMU multiplied after being replicated multiple times. However, because multi-master IOMMUs use a shared circuit structure, their power consumption does not increase significantly.

[0185] Figure 12 This diagram illustrates a performance comparison between the multi-master IOMMU architecture described in this embodiment and a traditional IOMMU solution. Figure 12As shown, the multi-master IOMMU circuit of this invention, as described above, features a structure with dynamic page table sharing and exclusive flexible control, which can be flexibly configured according to requirements. Furthermore, an improved LRU replacement algorithm is proposed, incorporating the replacement strategy after cache line invalidation of the IOMMU. Therefore, the performance comparison with traditional IOMMU solutions is as follows: the horizontal axis in the graph represents the number of commands initiated by the IOMMU, and the vertical axis represents the cache hit rate. A higher hit rate indicates better IOMMU performance. It can be seen that the solid line portion of this invention achieves a hit rate of almost 95% or higher in various scenarios, while the traditional solution exhibits significant hit rate fluctuations in certain scenarios. Therefore, the multi-master shared IOMMU structure proposed in this invention has a better PPA (Power, Performance, and Area) evaluation compared to traditional methods.

[0186] In summary, the memory management method, memory management unit, chip, and electronic device described in this disclosure effectively reduce the area and power consumption of the IOMMU by proposing a circuit structure and method suitable for multiple master devices to share the IOMMU master control pipeline. By proposing a circuit structure and method suitable for multiple master devices to share the IOMMU page table, high-performance application requirements can still be met while effectively reducing the IOMMU area. By proposing a method for multiple master devices to dynamically share and exclusively occupy a portion of the TLB internal page table space, the hit rate of the IOMMU internal memory is improved, fully utilizing the IOMMU's energy efficiency. By proposing a page table cache replacement algorithm for multiple master devices, page table replacement is made more reasonable, and the use of the IOMMU's internal TLB cache is more efficient.

[0187] In the several embodiments provided in this disclosure, it should be understood that the disclosed systems, apparatuses, or methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules / units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or units may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection of apparatuses or modules or units may be electrical, mechanical, or other forms.

[0188] The modules / units described as separate components may or may not be physically separate. The components shown as modules / units may or may not be physical modules; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules / units can be selected to achieve the objectives of the embodiments of this disclosure, depending on actual needs. For example, the functional modules / units in the various embodiments of this disclosure may be integrated into one processing module, or each module / unit may exist physically separately, or two or more modules / units may be integrated into one module / unit.

[0189] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this disclosure.

[0190] like Figure 13 As shown in the illustration, this disclosure also provides an electronic device 40, which includes a memory 410 and a processor 420. The memory 410 is configured to store an executable program. The processor 420 is configured to execute the program to cause the electronic device to perform the memory management method described above.

[0191] This disclosure also provides a computer-readable storage medium. Those skilled in the art will understand that all or part of the steps in the methods of the above embodiments can be implemented by a program instructing a processor. The program can be stored in a computer-readable storage medium, which is a non-transitory medium, such as random access memory, read-only memory, flash memory, hard disk, solid-state drive, magnetic tape, floppy disk, optical disk, and any combination thereof. The storage medium can be any available medium accessible to a computer or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., digital video disc (DVD)), or a semiconductor medium (e.g., solid-state drive (SSD)).

[0192] This disclosure also provides a computer program product comprising one or more computer instructions. When the computer instructions are loaded and executed on a computing device, all or part of the processes or functions described in this disclosure are generated. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, or data center to another via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means.

[0193] When the computer program product is executed by a computer, the computer performs the method described in the foregoing method embodiments. The computer program product can be a software installation package; when the foregoing method is required, the computer program product can be downloaded and executed on the computer.

[0194] The descriptions of the processes or structures corresponding to the above figures each have their own emphasis. For parts of a process or structure that are not described in detail, please refer to the relevant descriptions of other processes or structures.

[0195] The above embodiments are merely illustrative of the principles and effects of this disclosure and are not intended to limit this disclosure. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this disclosure. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this disclosure should still be covered by the claims of this disclosure.

Claims

1. A memory management method, characterized in that, include: Receive a command from the master device, the command including the virtual address information and device number of the master device; The command is matched with a tag array to obtain a matching result. The tag array includes several tags, and each tag includes the virtual address information and the device number. If the matching result indicates a successful match, corresponding read address information is generated based on the matched tag. The first memory is accessed based on the read address information to obtain the corresponding cache line page table information. The virtual address information is converted into physical address information based on the cache line page table information. The first memory stores the cache line page table for the master device. as well as If the matching result indicates a matching failure, a page table read command is initiated to access the second memory to obtain the corresponding page table information according to the command. Replacement cache line information corresponding to the page table information is obtained from the first memory. The page table information is written into the first memory according to the replacement cache line information, and the tag array is updated. The second memory stores the page table for the master device.

2. The memory management method according to claim 1, characterized in that, Accessing the first memory based on the read address information to obtain the corresponding cache line page table information includes: If the cache hit is successful, the corresponding cache page table is read from the first cache space of the first memory according to the read address information. The first cache space is the cache space configured for the master device in the first memory; and Extract the corresponding cached page table information based on the cached page table.

3. The memory management method according to claim 1, characterized in that, Initiating a page table read command to access the second memory and obtain the corresponding page table information according to the command includes: If the hit fails, initiate the page table read command according to the given command; and The corresponding page table information is received from the second memory according to the page table read command.

4. The memory management method according to claim 1, characterized in that, Obtaining the replacement cache line information corresponding to the page table information in the first memory includes: If the hit fails, a cache line replacement command will be initiated according to the command described above; and According to the cache line replacement command and the preset cache line replacement strategy, the corresponding cache line information is found in the cache line list of the master device and used as the replacement cache line information. The cache line list of the master device is determined by the address storage space configured by the first memory for the master device.

5. The memory management method according to claim 1, characterized in that, Writing the page table information into the first memory according to the replacement cache line information includes: Obtain the write address corresponding to the replaced cache line information; Obtain the write data corresponding to the page table information; and The write data is written into the first memory according to the write address to replace the cache line corresponding to the replacement cache line information.

6. The memory management method according to claim 1, characterized in that, Updating the tag array includes: The tag array is updated based on the replacement cache line information and the page table information to obtain the updated tag array. The memory management method described therein also includes: The command is matched with the updated tag array to convert the virtual address information into physical address information according to the page table information, so as to facilitate cyclic scheduling of address information conversion for the master device.

7. The memory management method according to claim 1, characterized in that, Matching the command with the tag array to obtain the matching results includes: The virtual address information of the command is matched with the virtual address information of the tag to obtain a first matching result; The device number of the command is matched with the device number of the tag to obtain a second matching result; When both the first matching result and the second matching result are successful, the matching result is considered a successful match; and Otherwise, the matching result is a failure.

8. The memory management method according to claim 1, characterized in that, Receiving commands from the master device includes: Receive one or more commands from one or more master devices; Convert the one or more commands into input command information, the input command information including the one or more commands in a streaming structure; and The commands are retrieved sequentially from the input command information for matching with the tag array.

9. The memory management method according to claim 1, characterized in that, Also includes: In the first memory, corresponding address storage spaces are configured for one or more master devices. The address storage spaces include several cache line page table information entries, each of which includes several page table entries. The address storage space is divided into page table levels according to the needs of one or more master devices.

10. The memory management method according to claim 9, characterized in that, Configuring corresponding address storage space for one or more master devices in the first memory includes: The first memory is divided into a first storage space; and The first storage space is configured to the first master device among the one or more master devices.

11. The memory management method according to claim 9, characterized in that, Configuring corresponding address storage space for one or more master devices in the first memory includes: The first memory is divided into a first storage space, a second storage space, and a third storage space; The first storage space is configured to the first master device among the one or more master devices; Configure the second storage space to the second master device among the one or more master devices; and The third storage space is configured for the first master device and the second master device.

12. The memory management method according to claim 9, characterized in that, Configuring corresponding address storage space for one or more master devices in the first memory includes: The first memory is divided into a first storage space and a second storage space; Configure the first storage space to the first master device among the one or more master devices; and The second storage space is configured to the second master device among the one or more master devices.

13. The memory management method according to claim 9, characterized in that, Configuring corresponding address storage space for one or more master devices in the first memory includes: The first memory is divided into a first storage space; and The first storage space is configured to the first master device and the second master device among the one or more master devices.

14. The memory management method according to claim 9, characterized in that, The address storage space is partitioned at the page table level according to the needs of one or more master devices, including at least one of the following: Based on the aforementioned requirements, a first-level page table is partitioned for the corresponding address storage space; Based on the aforementioned requirements, a two-level page table is partitioned for the corresponding address storage space; and Based on the aforementioned requirements, multi-level page tables are partitioned for the corresponding address storage space.

15. The memory management method according to claim 1, characterized in that, The first memory is located in the conversion backup buffer, and the second memory is located outside the conversion backup buffer.

16. A memory management unit, characterized in that, include: An input command caching module is configured to receive commands from the master device, the commands including the virtual address information and device number of the master device; as well as The core processing module is configured as follows: The command is matched with a tag array to obtain a matching result. The tag array includes several tags, and each tag includes the virtual address information and the device number. If the matching result indicates a successful match, corresponding read address information is generated based on the matched tag. The first memory is accessed based on the read address information to obtain the corresponding cache line page table information. The virtual address information is converted into physical address information based on the cache line page table information. The first memory stores the cache line page table for the master device. as well as If the matching result indicates a matching failure, a page table read command is initiated to access the second memory to obtain the corresponding page table information, and replacement cache line information corresponding to the page table information is obtained from the first memory. The page table information is then written into the first memory based on the replacement cache line information, and the tag array is updated. The second memory stores the page table for the master device. The first memory is located inside the memory management unit, and the second memory is located outside the memory management unit.

17. The memory management unit according to claim 16, characterized in that, Also includes: The output command caching module is configured to cache and output the physical address information and the page table read command; as well as The pass-through logic module is configured to output the physical address information to the bus for accessing memory, and is configured to send the page table read command to the corresponding port for obtaining the page table information.

18. The memory management unit according to claim 16, characterized in that, The core processing module includes: A circular pipeline address command cache is configured to store the commands and pipeline control information for controlling the various components in the memory management unit; The tag array module is configured to store the tags, match the command with the tag array to obtain the matching result, generate corresponding read address information based on the matched tag, and update the tag array based on the replacement cache line information and the page table information to obtain the updated tag array. The page table command cache is configured to store the virtual address information, and if a hit fails, the page table read command is initiated according to the command. A translation backup buffer, including a storage control unit and the first memory, is configured to store the cache line page table and is configured to access the cache line page table according to the read address information to obtain corresponding cache line page table information, and to convert the virtual address information into the physical address information according to the cache line page table information or the page table information; and The replacement unit is configured to determine the replacement cache line information in the first memory and write the page table information into the first memory according to the replacement cache line information.

19. A chip, characterized in that, include: One or more master devices; Memory; as well as The memory management unit according to any one of claims 16 to 18 is coupled to the one or more master devices and coupled to the memory via a system bus.

20. An electronic device, characterized in that, include: The memory is configured to store executable programs; as well as A processor is configured to execute the program to cause the electronic device to perform the memory management method according to any one of claims 1 to 15.

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