A test system for parallel interface NOR FLASH memory

Abstract

The application relates to the technical field of memory testing, and discloses a test system for a parallel interface NOR FLASH memory, which comprises the following steps: collecting test data of a test data block in a storage area and verification information of a check operation in a NOR FLASH memory test process, judging whether the test data block has errors; dividing the test data block with errors to determine secondary to-be-analyzed test data blocks; marking target test data, identifying high-frequency error test data, dividing the secondary to-be-analyzed test data block that needs to be adjusted into a tertiary to-be-analyzed test data block, repeatedly judging and dividing until the data block cannot be continuously divided or the judgment results of the data block are all no division, setting a block verification mode of a marching method, and using the marching method to evaluate the durability of the parallel interface NOR FLASH memory. The application can adaptively set the block verification mode, and improves the accuracy of durability test results.

Description

Technical Field

[0001] This invention relates to the field of memory testing technology, and more specifically to a testing system for parallel interface NOR FLASH memory. Background Technology

[0002] Parallel interface refers to a data transfer method between memory and an external system that uses parallel processing. NOR FLASH is a non-volatile memory technology that allows data to be retained after power loss, enabling long-term data storage such as firmware storage and embedded systems. A test system for parallel interface NOR FLASH memory is a specialized combination of equipment and software used to verify whether the performance indicators of the parallel interface NOR FLASH memory meet specified standards. When testing parallel interface NOR FLASH memory, to verify the device's durability, large-scale read, write, and erase operations are required, typically achieved using a synchronous method.

[0003] When evaluating the endurance of parallel interface NOR FLASH memory using the homogeneous method, setting the data within a single storage cell as test data yields the best results. However, large-scale repetitive tests are too time-consuming and inefficient. Conversely, when the amount of data within a storage cell is too large, the data granularity is insufficient, requiring recursive iteration to accurately locate error information. This recursive iteration process also impacts test efficiency. Therefore, a more scientific method of partitioning data into storage cells for verification is needed to improve the efficiency of the homogeneous method while ensuring the effectiveness of data testing. Summary of the Invention

[0004] This invention provides a test system for parallel interface NOR FLASH memory to solve the problem that unreasonable block verification method settings lead to poor efficiency in evaluating the durability of parallel interface NOR FLASH memory using the synchronous method. The specific technical solution adopted is as follows:

[0005] One embodiment of the present invention provides a test system for parallel interface NOR FLASH memory, the system comprising the following modules:

[0006] The data acquisition module is used to collect test data of each test data block of the same preset size in the storage area and verification information of each verification operation during the testing of the parallel interface NOR FLASH memory, and to determine whether there are errors in the test data block.

[0007] The error test data block partitioning module is used to partition the test data blocks containing errors based on the differences in verification information during storage and verification operations. Based on the differences in verification information during verification operations and storage of the partitioned test data blocks, the module determines the secondary test data blocks to be analyzed.

[0008] The durability testing and evaluation module is used to designate any test data within the secondary test data block as the target test data. Based on the judgment results of whether there are errors in all test data blocks containing the target test data, the number of test data contained in all test data blocks containing the target test data, and the identification of high-frequency error test data, it determines whether to adjust the size of the secondary test data block based on the number of times errors exist in the test data blocks containing all different high-frequency error test data within the secondary test data block, and the analysis time of the secondary test data block. If so, it divides the secondary test data block into tertiary test data blocks, determines whether to adjust the size of the tertiary test data blocks, and divides the adjusted tertiary test data blocks into quaternary test data blocks. This process is repeated until the data block cannot be further divided or the judgment result for the data block is always "no division". This implements the setting of the block-based verification method using the synchronous method to evaluate the durability of the parallel interface NOR FLASH memory.

[0009] Furthermore, the specific methods for determining whether the test data block contains errors are as follows:

[0010] The test data block contains an error when the hash value of the test data block is different from that of the storage area during the verification operation.

[0011] Furthermore, the specific method for dividing the test data blocks containing errors into erroneous test data blocks based on the differences in verification information during storage and verification operations includes:

[0012] Based on the differences in the verification information of the test data of the test data block with errors in the storage area and during the verification operation, determine the degree of error of the test data block in the storage area during a verification operation.

[0013] The test data blocks corresponding to verification operations with an error severity less than or equal to the first preset threshold are divided into two test data blocks; the test data blocks corresponding to verification operations with an error severity less than or equal to the second preset threshold and greater than the first preset threshold are divided into four test data blocks; and the test data blocks corresponding to verification operations with an error severity greater than the second preset threshold are divided into eight test data blocks.

[0014] Furthermore, the method for determining the degree of error is as follows:

[0015] The absolute value of the difference between the hash value of the verification information of the test data in the storage area and the hash value of the verification information after a verification operation of the test data in the storage area is denoted as the error level of the test data in a verification operation.

[0016] Furthermore, the method for determining the secondary test data block to be analyzed is as follows:

[0017] When the hash value of the partitioned test data block is different from that in the storage area during the verification operation, the partitioned test data block contains an error.

[0018] All test data blocks containing errors after partitioning are recorded as secondary test data blocks to be analyzed.

[0019] Furthermore, the specific method for identifying high-frequency erroneous test data based on the judgment results of whether there are errors in all test data blocks containing the target test data and the number of test data contained in all test data blocks containing the target test data includes:

[0020] Calculate the probability of a problem with the target test data based on the judgment results of whether there are errors in all test data blocks containing the target test data and the number of test data contained in all test data blocks containing the target test data.

[0021] Test data within the secondary test data block to be analyzed that has a problem probability greater than or equal to the preset problem probability threshold are all recorded as high-frequency error test data.

[0022] Furthermore, the method for determining the problem probability of the target test data is as follows:

[0023] The reciprocal of the length of the interval in which the test data block containing the target test data is judged to have an error is recorded as the first score when the test data block containing the target test data is judged to have an error. The sum of the first scores when all the test data blocks containing the target test data are judged to have an error is recorded as the first cumulative sum of the target test data.

[0024] The number of times the test data block containing the target test data is checked for errors is recorded as the first count of the target test data.

[0025] The ratio of the first cumulative sum to the first number of the target test data is denoted as the problem probability of the target test data.

[0026] Furthermore, the specific method for determining whether to adjust the size of the secondary test data block based on the number of times errors exist in the test data blocks containing all different high-frequency error test data within the secondary test data block to be analyzed, and the analysis time of the secondary test data block to be analyzed, includes:

[0027] Any high-frequency error test data is denoted as the target high-frequency error test data. The ratio of the number of times the test data block containing the target high-frequency error test data is judged to have an error to the first time of the target high-frequency error test data is denoted as the error probability of the target high-frequency error test data.

[0028] Based on the error probability of two different high-frequency error test data and the number of times that the test data blocks containing the two different high-frequency error test data are both judged to have errors, calculate the clumping probability of the two different high-frequency error test data.

[0029] The maximum value of the clumping probability of all different high-frequency error test data within the secondary test data block to be analyzed is denoted as the comprehensive clumping probability of the secondary test data block to be analyzed.

[0030] The partitioning interval of the secondary test data block is determined based on the time for calculating the overall clumping probability of the secondary test data block to be analyzed and the partitioning time of the test data block containing the error.

[0031] When the overall clumping probability of the secondary test data block to be analyzed is greater than or equal to the partitioning interval, the secondary test data block to be analyzed is divided into two cubic test data blocks to be analyzed; when the overall clumping probability of the secondary test data block to be analyzed is less than the partitioning interval, the secondary test data block to be analyzed is not adjusted.

[0032] Furthermore, the formula for calculating the clumping probability is:

[0033] ;

[0034] in, Indicates the first The first high-frequency error test data and the first The probability of clumping in the high-frequency error test data; the probability of clumping in the first high-frequency error test data; The first high-frequency error test data and the first The number of times each high-frequency error test data point was found to contain an error was consistent with the number of times the test data point contained an error. The ratio of the first occurrence of each high-frequency error test data point is denoted as the i-th. The and the first Simultaneous error probability of high-frequency error test data. Indicates the first The and the first Simultaneous error probability of high-frequency error test data; Indicates the first The and the first The maximum error probability of a high-frequency error test dataset; Indicates the first The first high-frequency error test data and the first Between high-frequency error test data The sum of the error probabilities of a number of high-frequency error test data.

[0035] Furthermore, the method for determining the interval time for dividing the secondary test data block to be analyzed is as follows:

[0036] The time interval between calculating the overall clumping probability of the secondary test data block to be analyzed and the time of partitioning the test data block containing the erroneous data block to be analyzed is denoted as the partitioning interval time of the secondary test data block to be analyzed.

[0037] The beneficial effects of this invention are:

[0038] This application determines the verification result based on the difference between the verification information of the test data block and the sector address test data verification. It identifies and divides erroneous test data blocks, obtains all secondary test data blocks to be analyzed, and performs finer-grained analysis and further division on the divided erroneous test data blocks. This avoids lengthy global checks on erroneous test data blocks, improving the testing efficiency of the testing system. Specifically, based on the number of test data blocks containing the target test data when it is determined to have an error, it identifies high-frequency erroneous test data in the secondary test data blocks to be analyzed. Based on the number of times each high-frequency erroneous test data block within the secondary test data blocks to be analyzed is determined, and the analysis time of the secondary test data blocks to be analyzed is used to determine whether the size of the secondary test data blocks to be analyzed needs to be adjusted. The secondary test data blocks to be analyzed that need adjustment are divided into tertiary test data blocks to be analyzed. This judgment and division is repeated until the data blocks cannot be further divided or the judgment result of the data blocks is always no division. This implements the setting of a synchronous block verification method and uses the synchronous method to evaluate the parallel interface NOR. This paper addresses the issue of inefficient performance evaluation of parallel interface NOR FLASH memory due to improper block verification method settings, thereby improving the accuracy and stability of endurance testing for parallel interface NOR FLASH memory. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 This is a flowchart illustrating a test system for a parallel interface NOR FLASH memory, provided as an embodiment of the present invention.

[0041] Figure 2 This is a schematic diagram of a test system for a parallel interface NOR FLASH memory, provided as an embodiment of the present invention. Detailed Implementation

[0042] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0043] Please see Figure 1 It illustrates a flowchart of a test system for a parallel interface NOR FLASH memory according to an embodiment of the present invention. Figure 2 The diagram illustrates a test system for a parallel interface NOR FLASH memory according to an embodiment of the present invention. The system includes: a data acquisition module, an error test data block partitioning module, and a durability test evaluation module.

[0044] The data acquisition module, during the testing of the parallel interface NOR FLASH memory, collects the test data of each test data block of the same preset size in the storage area and the verification information of each verification operation to determine whether there are errors in the test data block.

[0045] This embodiment selects the Xilinx XC7K325T-2FFG900 FPGA chip as the main controller, combined with a parallel I / O architecture, as the test system for the parallel interface NOR FLASH memory. Specifically, it selects seven SOP-56 packaged, 16-bit parallel interface NOR Flash memories to verify the automated read, write, erase, and programming functions of the parallel interface NOR FLASH memory. Among them, an N25Q256A83SF SPI NOR Flash device is used to load the FPGA firmware, realizing a plug-and-play test environment. The FPGA firmware refers to the configuration data and control program used for the FPGA field-programmable gate array. The address lines and control signals between the four test fixtures and the FPGA are multiplexed, but the data signals adopt an independent connection design to realize 64-bit parallel data transmission, which is suitable for high-bandwidth access scenarios. The control and data signals of the other three test fixtures are completely independently connected to the FPGA for independent testing and data programming operations.

[0046] The initialization and connection configuration of the test system includes two steps: fixture connection and I / O configuration. Specifically: fixture connection involves using a custom test fixture to connect the SOP-56 packaged NOR Flash memory under test to the test system, ensuring that each pin is correctly connected to the corresponding FPGA I / O; I / O configuration involves configuring the FPGA-side I / O standards and level matching relationships to ensure reliable data interaction and timing matching.

[0047] The testing process of the testing system includes system startup and device identification, erasure test, data writing and reading verification, multi-mode data verification test, and data burning.

[0048] The system startup and device identification process involves automatically reading the Flash device ID information and verifying whether the ID information matches a supported model. If identification fails, the current test is interrupted and marked as "Test Failed." The erase test performs a full address space erase operation on the supported Flash device model and monitors the erase duration and status. If the erase is successful and the time taken does not exceed 120 seconds, the test proceeds to the next stage; otherwise, the test terminates and is marked as "Erasing Failed." The data write and read verification process involves writing test data sequentially into the entire Flash address space in 256-byte units, immediately reading the written data, and performing address-by-address comparison verification. If the full address space data consistency verification passes, the test continues. If any inconsistency is found, the test is terminated and marked as "read / write failed". The multi-mode data verification test involves sequentially performing write and read comparison tests on the Flash in four modes: all 1s, all 0s, checkerboard, and reverse checkerboard. A complete erase is performed before each mode. After that, the data write, read, and comparison process is executed. If data verification fails in any mode, it is marked as "test failed". The data programming function allows the user to select the target programming data in a binary file. The system automatically loads it into the FPGA memory. According to the selected Flash channel configuration, the system writes the data into the full address space of the target Flash. After programming is completed, the system automatically reads the Flash data and performs a bit-level comparison with the original binary file.

[0049] The test system's status indication and fault tolerance mechanism are designed for fault detection and handling. Specifically, the test system monitors in real time whether there are anomalies such as timeouts or data inconsistencies during the erasure, writing, and reading processes, and has an automatic interruption and error reporting mechanism.

[0050] The testing system automatically records test data for each Flash chip under different operating modes. The test data specifically includes: data reading, data writing, and data erasing. Specifically, data reading includes the time required to read, the number of read errors, and whether errors exist; data writing includes the write latency and data write error detection results; and data erasing includes the erasure duration and erasure success rate.

[0051] All test data can be exported and used for further statistical analysis and device performance evaluation.

[0052] First, the size of the test data block is preset. The size of the test data block should effectively cover the changes in data, but should not be too large to avoid increasing the complexity of calculation and erasure operations. In this embodiment, each test data block contains 64 test data items. Test data blocks are generated according to the size of the test data block and written to each sector. Verification information of the test data at each sector address is then obtained.

[0053] Among them, a sector is a storage area in Flash; the process of obtaining verification information is achieved through the data writing and reading verification process. When performing an erase test, due to the special characteristic that data in Flash can only change unidirectionally from 1 to 0, but 0 cannot directly become 1, an erase operation needs to be performed first, and data can only be rewritten after erasure.

[0054] When verifying the test data for each sector address, the verification result can be determined by the hash value between the verification information of the test data block. If the hash value of the test data block during the verification operation is the same as that in the storage area, the verification passes, and the test data block contains no errors. If the hash value of the test data block during the verification operation is different from that in the storage area, the verification fails, and the test data block contains errors. Specifically, this embodiment verifies the test data for each sector address using the moving-inverse method. Verification is performed by analyzing the reverse sequence of the test data block. Compared to traditional bit-by-bit checking, this method can more efficiently detect data errors and reduce unnecessary operations. The moving-inverse method for verifying test data is a well-known technique and will not be elaborated further.

[0055] To reduce time and resource consumption during the erasure operation, incomplete test data blocks are not erased to improve overall efficiency. Instead, a moving-inversion method is used to erase incomplete test data blocks. The use of this method is a well-known technique and will not be elaborated further.

[0056] The verification information for the sector address test data is a binary sequence. Specifically, when verifying the test data, the value corresponding to successful verification is 1, and the value corresponding to unsuccessful verification is 0.

[0057] At this point, the test data of each test data block during the testing process of the test system is stored in the storage area, and the verification information of each verification operation is obtained, as well as the judgment result of whether there are errors in the test data block.

[0058] The error test data block segmentation module divides the test data of the error test data blocks into error test data blocks based on the differences in verification information in the storage area and during verification operations. Based on the differences in verification information of the segmented test data blocks during verification operations and storage areas, it determines the secondary test data blocks to be analyzed.

[0059] The analysis is based on the verification results of the test data in the test data blocks. When errors occur in the test data of a test data block, the size of the test data block or the verification strategy is adjusted. The verification results of the test data verification information determine whether an error exists in the test data block. For example, if errors are concentrated in certain specific test data blocks, these blocks can be divided into smaller parts to increase the verification accuracy. Simultaneously, when dividing these test data blocks, the time complexity of data operations in different test data blocks needs to be analyzed to improve the efficiency of the testing system while ensuring verification effectiveness.

[0060] If there are no errors in the test data block, the size of the test data block is not adjusted, and the time spent determining whether to adjust the size of the test data block is extracted.

[0061] If there are no errors in the test data block, the size of the test data block needs to be adjusted.

[0062] The absolute value of the difference between the hash value of the verification information of the test data in the storage area and the hash value of the verification information after a verification operation of the test data in the storage area is denoted as the error level of the test data in a verification operation.

[0063] The greater the difference between the hash value of the test data in the test data block during the verification operation and the hash value of the corresponding verification information in the storage area, the more severe the error generated by the test data in the test data block during the verification operation. In this case, the degree of error in the verification operation is greater.

[0064] A first preset threshold and a second preset threshold are set. Both the first preset threshold and the second preset threshold are preset parameter values. In this embodiment, the value of the first preset threshold is 0.3 and the value of the second preset threshold is 0.7.

[0065] Specifically, in one embodiment of this application, the test data blocks containing errors are divided as follows: test data blocks corresponding to verification operations with an error level less than or equal to a first preset threshold are divided into two test data blocks; test data blocks corresponding to verification operations with an error level less than or equal to a second preset threshold and greater than the first preset threshold are divided into four test data blocks; and test data blocks corresponding to verification operations with an error level greater than the second preset threshold are divided into eight test data blocks.

[0066] For example, each test data block in this embodiment contains 64 test data. When the error level of the verification operation is less than or equal to the first preset threshold, the test data block corresponding to the verification operation is divided into two test data blocks. That is, the first 32 test data contained in the original test data block is the first test data block divided into two test data blocks, and the third 64 test data contained in the original test data block is the second test data block divided into two test data blocks.

[0067] Erroneous test data blocks are erased to facilitate subsequent re-verification of the evenly divided test data blocks. For test data blocks without errors, the moving inversion method is used to verify the test data without erasing.

[0068] The system verifies whether the partitioned test data block contains errors based on the hash value obtained during the verification operation and in the storage area. Specifically, if the hash value obtained during the verification operation and in the storage area are the same, the verification passes, and the partitioned test data block contains no errors. In this case, the size of the partitioned test data block is not adjusted, and the time spent determining whether to adjust the size of the partitioned test data block is extracted. If the hash value obtained during the verification operation and in the storage area are different, the verification fails, and the partitioned test data block contains errors.

[0069] By performing finer-grained analysis on the erroneous test data blocks after partitioning and then further partitioning them, we can avoid performing lengthy global checks on the erroneous test data blocks and improve the testing efficiency of the testing system.

[0070] All adjacent test data blocks that are not further divided are merged into a single test data block. Test data blocks containing errors after division are designated as secondary test data blocks to be analyzed.

[0071] It is understood that test data blocks that are not further divided are the test data blocks that have passed verification.

[0072] At this point, all secondary test data blocks to be analyzed have been obtained.

[0073] The durability testing and evaluation module designates any test data within the secondary test data block as the target test data. Based on the judgment results of whether there are errors in all test data blocks containing the target test data, and the number of test data contained in all test data blocks containing the target test data, it identifies high-frequency error test data. Based on the number of times errors are judged in all test data blocks containing different high-frequency error test data within the secondary test data block, and the analysis time of the secondary test data block, it determines whether the size of the secondary test data block should be adjusted. If so, the secondary test data block is divided into tertiary test data blocks. It then determines whether the size of the tertiary test data blocks should be adjusted, and divides the adjusted tertiary test data blocks into quaternary test data blocks. This process is repeated until the data blocks cannot be further divided or the judgment result for the data blocks is always "no division". This implements the setting of the block-based verification method using the synchronous method, and uses the synchronous method to evaluate the durability of the parallel interface NOR FLASH memory.

[0074] Record any one of the test data points within the secondary test data block as the target test data.

[0075] The reciprocal of the length of the interval in which the test data block containing the target test data is judged to contain an error is denoted as the first score when the test data block containing the target test data is judged to contain an error. The sum of all the first scores when the test data block containing the target test data is judged to contain an error is denoted as the first sum of the target test data. The number of times the test data block containing the target test data is judged to contain an error is denoted as the first number of the target test data. The ratio of the first sum of the target test data to the first number of the target test data is denoted as the problem probability of the target test data.

[0076] It is important to understand that the longer the interval in the test data block where the target test data is located is judged to contain errors, the less the target test data will be affected by the errors; the interval length of the test data block where the target test data is located is the number of test data contained in the test data block where the target test data is located.

[0077] The same method can be used to obtain the problem probability of each test data in the secondary test data block to be analyzed.

[0078] Test data within the secondary test data block to be analyzed that has a problem probability greater than or equal to the problem probability threshold are all recorded as high-frequency error test data.

[0079] The problem probability threshold is a preset threshold, and in this embodiment, the problem probability threshold is set to 0.1.

[0080] Record any high-frequency error test data as the target high-frequency error test data. Determine the number of times an error exists based on the test data block where the target high-frequency error test data is located, and calculate the error probability of the target high-frequency error test data.

[0081] The ratio of the number of times the test data block containing the target high-frequency error test data is judged to contain an error to the first occurrence of the target high-frequency error test data is denoted as the error probability of the target high-frequency error test data.

[0082] Based on the error probabilities of two different high-frequency error test data and the number of times that the test data blocks containing the two different high-frequency error test data are both judged to contain errors, calculate the clumping probability of the two different high-frequency error test data.

[0083] ;

[0084] in, Indicates the first The first high-frequency error test data and the first The probability of clumping in the high-frequency error test data; the probability of clumping in the first high-frequency error test data; The first high-frequency error test data and the first The number of times each high-frequency error test data point was found to contain an error was consistent with the number of times the test data point contained an error. The ratio of the first occurrence of each high-frequency error test data point is denoted as the i-th. The and the first Simultaneous error probability of high-frequency error test data. Indicates the first The and the first Simultaneous error probability of high-frequency error test data; Indicates the first The and the first The maximum error probability of a high-frequency error test dataset; Indicates the first The first high-frequency error test data and the first Between high-frequency error test data The sum of the error probabilities of a number of high-frequency error test data.

[0085] The maximum value of the clumping probability of all different high-frequency error test data within the secondary test data block to be analyzed is recorded as the comprehensive clumping probability of the secondary test data block to be analyzed. The time for calculating the comprehensive clumping probability of the secondary test data block to be analyzed is extracted. The time interval between the time for calculating the comprehensive clumping probability of the secondary test data block to be analyzed and the time for dividing the test data block containing the error into the secondary test data block to be analyzed is recorded as the division interval time of the secondary test data block to be analyzed.

[0086] When the overall clumping probability of the secondary test data block is greater than or equal to the partitioning interval, the size of the secondary test data block needs to be adjusted, and the secondary test data block is divided into two cubic test data blocks. When the overall clumping probability of the secondary test data block is less than the partitioning interval, the size of the secondary test data block is not adjusted, and the evaluation time for "not adjusting the size of the secondary test data block" is extracted.

[0087] Adjacent test data blocks that are not resized and are adjacent to each other, along with all adjacent test data blocks that are not further divided, are merged into a single test data block.

[0088] Following the same method used to determine whether a secondary test data block should be divided into a tertiary test data block, the determination of whether the tertiary test data block should be further divided is continued. For tertiary test data blocks whose size needs to be adjusted, the tertiary test data block is divided into two quaternary test data blocks. For tertiary test data blocks whose size does not need to be adjusted, the time for obtaining the evaluation of "not adjusting the size of the tertiary test data block" is extracted.

[0089] Repeat the above steps to continue judging whether the four test data blocks to be analyzed should be further divided, and divide the four test data blocks to be analyzed that need to be adjusted in size, until the data blocks can no longer be divided or no further division is needed, thus realizing the setting of the block verification method.

[0090] The above-mentioned block verification method is used as the block verification method of the homogeneous method. The endurance of the parallel interface NOR FLASH memory is evaluated using the homogeneous method, and the endurance test results of the parallel interface NOR FLASH memory are obtained.

[0091] This completes the endurance test of the parallel interface NOR FLASH memory.

[0092] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A test system for parallel interface NOR FLASH memory, characterized in that, The system includes the following modules: The data acquisition module is used to collect the verification information of the test data of each test data block of the same preset size in the storage area and the verification information of each verification operation during the testing of the parallel interface NOR FLASH memory, and to determine whether there are errors in the test data block. The error test data block partitioning module is used to partition the test data blocks containing errors based on the differences in verification information during storage and verification operations. Based on the differences in verification information during verification operations and storage of the partitioned test data blocks, the module determines the secondary test data blocks to be analyzed. The durability testing and evaluation module is used to designate any test data within the secondary test data block as the target test data. Based on the judgment results of whether there are errors in all test data blocks containing the target test data, the number of test data contained in all test data blocks containing the target test data, and the identification of high-frequency error test data, it determines whether to adjust the size of the secondary test data block based on the number of times errors exist in the test data blocks containing all different high-frequency error test data within the secondary test data block, and the analysis time of the secondary test data block. If so, it divides the secondary test data block into tertiary test data blocks, determines whether to adjust the size of the tertiary test data blocks, and divides the adjusted tertiary test data blocks into quaternary test data blocks. This process is repeated until the data block cannot be further divided or the judgment result for the data block is always "no division". This implements the setting of the block-based verification method using the synchronous method to evaluate the durability of the parallel interface NOR FLASH memory.

2. The test system for a parallel interface NOR FLASH memory according to claim 1, characterized in that, The specific methods for determining whether the test data block contains errors are as follows: The test data block contains an error when the hash value of the test data block is different from that of the storage area during the verification operation.

3. The test system for a parallel interface NOR FLASH memory according to claim 1, characterized in that, The method for dividing erroneous test data blocks based on the differences in verification information during storage and verification operations of test data in erroneous test data blocks includes the following specific methods: Based on the differences in the verification information of the test data of the test data block with errors in the storage area and during the verification operation, determine the degree of error of the test data block in the storage area during a verification operation. The test data blocks corresponding to verification operations with an error level less than or equal to the first preset threshold are divided into two test data blocks. The test data blocks corresponding to verification operations with an error level less than or equal to the second preset threshold and greater than the first preset threshold are divided into four test data blocks; the test data blocks corresponding to verification operations with an error level greater than the second preset threshold are divided into eight test data blocks.

4. A test system for a parallel interface NOR FLASH memory according to claim 3, characterized in that, The method for determining the degree of error is as follows: The absolute value of the difference between the hash value of the verification information of the test data in the storage area and the hash value of the verification information after a verification operation of the test data in the storage area is denoted as the error level of the test data in a verification operation.

5. A test system for a parallel interface NOR FLASH memory according to claim 1, characterized in that, The method for determining the secondary test data block to be analyzed is as follows: When the hash value of the partitioned test data block is different from that in the storage area during the verification operation, the partitioned test data block contains an error. All test data blocks containing errors after partitioning are recorded as secondary test data blocks to be analyzed.

6. A test system for a parallel interface NOR FLASH memory according to claim 1, characterized in that, The method for identifying high-frequency erroneous test data based on the judgment results of whether there are errors in all test data blocks containing the target test data and the number of test data contained in all test data blocks containing the target test data includes the following specific methods: Calculate the probability of a problem with the target test data based on the judgment results of whether there are errors in all test data blocks containing the target test data and the number of test data contained in all test data blocks containing the target test data. Test data within the secondary test data block to be analyzed that has a problem probability greater than or equal to the preset problem probability threshold are all recorded as high-frequency error test data.

7. A test system for a parallel interface NOR FLASH memory according to claim 2, characterized in that, The method for determining the problem probability of the target test data is as follows: The reciprocal of the length of the interval in which the test data block containing the target test data is judged to have an error is recorded as the first score when the test data block containing the target test data is judged to have an error. The sum of the first scores when all the test data blocks containing the target test data are judged to have an error is recorded as the first cumulative sum of the target test data. The number of times the test data block containing the target test data is checked for errors is recorded as the first count of the target test data. The ratio of the first cumulative sum to the first number of the target test data is denoted as the problem probability of the target test data.

8. A test system for a parallel interface NOR FLASH memory according to claim 7, characterized in that, The specific method for determining whether to adjust the size of the secondary test data block based on the number of times errors exist in the test data blocks containing all different high-frequency error test data within the secondary test data block to be analyzed, and the analysis time of the secondary test data block to be analyzed, includes the following: Any high-frequency error test data is denoted as the target high-frequency error test data. The ratio of the number of times the test data block containing the target high-frequency error test data is judged to have an error to the first time of the target high-frequency error test data is denoted as the error probability of the target high-frequency error test data. Based on the error probability of two different high-frequency error test data and the number of times that the test data blocks containing the two different high-frequency error test data are both judged to have errors, calculate the clumping probability of the two different high-frequency error test data. The maximum value of the clumping probability of all different high-frequency error test data within the secondary test data block to be analyzed is denoted as the comprehensive clumping probability of the secondary test data block to be analyzed. The partitioning interval of the secondary test data block is determined based on the time for calculating the overall clumping probability of the secondary test data block to be analyzed and the partitioning time of the test data block containing the error. When the overall clumping probability of the secondary test data block to be analyzed is greater than or equal to the partitioning interval, the secondary test data block to be analyzed is divided into two cubic test data blocks to be analyzed; when the overall clumping probability of the secondary test data block to be analyzed is less than the partitioning interval, the secondary test data block to be analyzed is not adjusted.

9. A test system for a parallel interface NOR FLASH memory according to claim 8, characterized in that, The formula for calculating the clumping probability is: ； in, Indicates the first The first high-frequency error test data and the first The probability of clumping in the high-frequency error test data; the probability of clumping in the first high-frequency error test data; The first high-frequency error test data and the first The number of times each high-frequency error test data point was found to contain an error was consistent with the number of times the test data point contained an error. The ratio of the first occurrence of each high-frequency error test data point is denoted as the i-th. The and the first Simultaneous error probability of high-frequency error test data. Indicates the first The and the first Simultaneous error probability of high-frequency error test data; Indicates the first The and the first The maximum error probability of a high-frequency error test dataset; No. The first high-frequency error test data and the first Between high-frequency error test data The sum of the error probabilities of a number of high-frequency error test data.

10. A test system for a parallel interface NOR FLASH memory according to claim 9, characterized in that, The method for determining the interval time for dividing the secondary test data block to be analyzed is as follows: The time interval between calculating the overall clumping probability of the secondary test data block to be analyzed and the time of partitioning the test data block containing the erroneous data block to be analyzed is denoted as the partitioning interval time of the secondary test data block to be analyzed.

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