A method, apparatus, device and medium for generating an admittance matrix

Abstract

The application discloses a kind of admittance matrix generation method, device, equipment and medium, it is related to power system computing technical field, the method includes: when the operating state of first circuit is normal, obtain the first system information in first circuit, based on the self-admittance of each node in first circuit and the mutual admittance between nodes, obtain first node admittance matrix;When the operating state of first circuit is abnormal, determine the fault point of first circuit;Obtain the first fault information corresponding to the fault point;Based on first fault information and first system information, the fault equivalent impedance that negative sequence network and zero sequence network are equivalent to positive sequence network is calculated;Based on fault equivalent impedance and first fault information, the first node admittance matrix is corrected, and target node admittance matrix is obtained.The method realizes the accurate generation of admittance matrix, improves the efficiency and precision of new energy power grid short-circuit current calculation.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power system calculation, and in particular to a method and device for generating a nodal admittance matrix, an apparatus and a medium. BACKGROUND

[0002] With the transformation of energy structure, the penetration rate of distributed energy represented by photovoltaic and wind power in power systems continues to increase. A large number of distributed generation units are connected to urban power grids, making the distribution network gradually evolve from a traditional one-way radial network into a complex network structure containing a large amount of bidirectional power flow. This change has put forward new requirements for the operation analysis and control protection of power grids.

[0003] Short-circuit current calculation is the basis for power grid planning and design, safety and stability analysis, and relay protection setting. The accuracy of the calculation results directly depends on the accurate modeling of the network structure of the power grid, and the nodal admittance matrix is the core mathematical model for describing the network topology and element parameters and performing short-circuit current calculation. In traditional power grids, the network structure is relatively fixed, and the construction of the admittance matrix mainly relies on manual modeling, which is a clear process.

[0004] However, under the background of high penetration of new energy, the traditional admittance matrix construction and short-circuit calculation method faces challenges: first, the fault response characteristics of new energy generation units are fundamentally different from those of traditional synchronous generators, and their output current during a fault is affected by internal control strategies, making their equivalent model more complex; second, new energy access points are scattered and numerous, resulting in frequent changes in the topology of the power grid; therefore, the method of identifying the association between nodes and branches one by one to form the admittance matrix is inefficient and prone to errors, and it is difficult to meet the needs of rapid analysis. SUMMARY

[0005] The present application provides a method and device for generating a nodal admittance matrix, which can accurately generate a nodal admittance matrix suitable for short-circuit current calculation in a high-penetration new energy power grid, solving the problem of low efficiency and error-prone of traditional manual modeling in the face of complex and variable new energy access scenarios.

[0006] To achieve the above-mentioned purpose, the present application adopts the following technical solutions:

[0007] In a first aspect, the present application provides a method for generating a nodal admittance matrix, the method comprising:

[0008] When the operating state of the first circuit is normal, obtaining first system information in the first circuit, calculating the self-admittance of each node and the mutual admittance between nodes in the first circuit based on the first system information, and obtaining a first nodal admittance matrix;

[0009] When the first circuit operating state is abnormal, a fault point of the first circuit is determined; first fault information corresponding to the fault point of the first circuit is acquired;

[0010] The fault equivalent impedance is calculated based on the first fault information and the first system information.

[0011] The first node admittance matrix is corrected based on the fault equivalent impedance and the first fault information, to obtain a target node admittance matrix.

[0012] In some possible implementation manners, the self-admittances of each node in the first circuit and the mutual admittances between nodes are calculated based on the first system information, to obtain the first node admittance matrix, including:

[0013] A zero matrix of a corresponding dimension is initialized according to the number of nodes of the first circuit;

[0014] The self-admittance of each node in the first circuit is calculated.

[0015] The mutual admittance between associated nodes in the first circuit is calculated.

[0016] The calculated self-admittance of each node in the first circuit and the mutual admittance between associated nodes in the first circuit are filled into corresponding positions of the zero matrix, to obtain the first node admittance matrix.

[0017] In some possible implementation manners, the first fault information includes a fault position, a fault type and a transition resistance value, and the fault equivalent impedance is calculated based on the first fault information and the first system information, including:

[0018] The nodes in the first circuit are prioritized according to the fault position in the first fault information, to obtain a node sequence of the first circuit.

[0019] Impedance conversion is sequentially performed on the nodes of the first circuit from the lowest to the highest priority according to the node sequence of the first circuit, to obtain a first impedance conversion result.

[0020] The equivalent impedance of the negative sequence network on the fault point side and the equivalent impedance of the zero sequence network on the fault point side are calculated based on the first impedance conversion result.

[0021] The equivalent impedance of the negative sequence network on the fault point side, the equivalent impedance of the zero sequence network on the fault point side and the transition resistance value are combined according to a preset rule according to the fault type in the first fault information, to obtain the fault equivalent impedance.

[0022] In some possible implementation manners, the equivalent impedance of the negative sequence network on the fault point side is determined in the following manner:

[0023] If the first circuit includes a new energy source adopting a negative sequence suppression control strategy, in a case that the new energy source is regarded as an open circuit in the negative sequence network, the equivalent impedance of the negative sequence network on the side of the fault point and the equivalent impedance of the zero sequence network on the side of the fault point are calculated based on the first impedance conversion result.

[0024] In some possible implementation manners, the correcting the first node admittance matrix based on the fault equivalent impedance and the first fault information to obtain a target node admittance matrix includes:

[0025] The fault point in the first circuit is taken as a new node, and self-admittances of the new node and mutual admittances between the new node and adjacent nodes are calculated based on the fault equivalent impedance and the first fault information;

[0026] A fault compensation matrix is constructed according to the self-admittances of the new node and the mutual admittances between the new node and adjacent nodes.

[0027] The self-admittances and mutual admittances of nodes in the first node admittance matrix are corrected according to a network topology including the new node;

[0028] The corrected first node admittance matrix and the fault compensation matrix are added to obtain a target node admittance matrix.

[0029] In some possible implementation manners, the first system information includes power supply parameters, line parameters, load equivalent impedance and node association relationship.

[0030] In some possible implementation manners, the line parameters include line length, unit positive sequence impedance, unit negative sequence impedance and unit zero sequence impedance.

[0031] In a second aspect, the present application provides a kind of admittance matrix generation device, the device includes:

[0032] The acquisition module is used to obtain the first system information in the first circuit when the operating state of the first circuit is normal, calculate the self-admittances of each node in the first circuit and the mutual admittances between nodes based on the first system information, and obtain a first node admittance matrix;When the operating state of the first circuit is abnormal, determine the fault point of the first circuit;The first fault information corresponding to the fault point of the first circuit is obtained.

[0033] The calculation module is used to calculate the fault equivalent impedance of the negative sequence network and the zero sequence network to the positive sequence network based on the first fault information and the first system information.

[0034] The correction module is used to correct the first node admittance matrix based on the fault equivalent impedance and the first fault information, and obtain a target node admittance matrix.

[0035] In a third aspect, the present application provides a computing device, comprising a memory and a processor;

[0036] One or more computer programs are stored in the memory, and the one or more computer programs comprise instructions; when the instructions are executed by the processor, the computing device performs the method according to any one of the first aspect.

[0037] In a fourth aspect, the present application provides a computer readable storage medium for storing a computer program, the computer program being used to perform the method according to any one of the first aspect.

[0038] In a fifth aspect, the present application provides a computer program product, comprising one or more computer instructions, when the computer instructions are executed by a computer, the computer performs the method according to any one of the first aspect.

[0039] From the above technical solutions, the present application has at least the following beneficial effects:

[0040] In the present application, when the operating state of the first circuit is normal, the first system information in the first circuit is obtained, the self-admittances of each node in the first circuit and the mutual admittances between the nodes are calculated based on the first system information, and the first node admittance matrix is obtained; when the operating state of the first circuit is abnormal, the fault point of the first circuit is determined; the first fault information corresponding to the fault point of the first circuit is obtained; the fault equivalent impedance of the negative sequence network and the zero sequence network to the positive sequence network is calculated based on the first fault information and the first system information; the first node admittance matrix is modified based on the fault equivalent impedance and the first fault information, and the target node admittance matrix is obtained. In the prior art, for short-circuit current calculation of a power grid with a high proportion of new energy access, network topology is usually analyzed manually and an admittance matrix is manually constructed, especially when dealing with asymmetric faults, the positive sequence, negative sequence and zero sequence networks need to be processed respectively, which is a tedious and inefficient process and is difficult to automate. It can be seen that, by identifying the topology and generating the node admittance matrix in the normal state, the present application uses the calculated fault equivalent impedance to unify the influence of the sequence network of the asymmetric fault to the positive sequence network for modification, and obtains the target node admittance matrix, thereby realizing accurate generation of the admittance matrix and improving the efficiency and accuracy of short-circuit current calculation of the new energy power grid.

[0041] It should be understood that the description of technical features, technical solutions, advantages or similar language in this application does not imply that all features and advantages can be achieved in any single embodiment. On the contrary, it can be understood that the description of features or advantages means that the specific technical features, technical solutions or advantages are included in at least one embodiment. Therefore, the description of technical features, technical solutions or advantages in this specification does not necessarily refer to the same embodiment. Further, the technical features, technical solutions and advantages described in the embodiments can be combined in any appropriate manner. Those skilled in the art will understand that the embodiments can be implemented without one or more specific technical features, technical solutions or advantages of the specific embodiments. In other embodiments, additional technical features and advantages can be identified in specific embodiments that do not embody all embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0042] Figure 1 A schematic diagram of a power system structure is provided for embodiments of the present application;

[0043] Figure 2 A flowchart of a method for generating an admittance matrix is provided for embodiments of the present application;

[0044] Figure 3 A local schematic diagram of a power system when a fault occurs is provided for embodiments of the present application;

[0045] Figure 4 A schematic diagram of a power system with a fault point is provided for embodiments of the present application;

[0046] Figure 5 A schematic diagram of an admittance matrix generation device is provided for embodiments of the present application;

[0047] Figure 6 A schematic diagram of a computing device is provided for embodiments of the present application. DETAILED DESCRIPTION

[0048] The terms "first", "second", and "third" and the like in the specification and the drawings of the present application are used to distinguish different objects, and are not used to limit a specific order.

[0049] In the embodiments of the present application, the words "exemplary" or "for example" are used to mean serving as an example, instance, or illustration. Any embodiment or design presented as "exemplary" or "for example" in the embodiments of the present application should not be construed as being superior or more advantageous than other embodiments or design solutions. Rather, the use of "exemplary" or "for example" is intended to present concepts in a concrete manner. In the embodiments of the present application, the words "one example" and "another example" are used to introduce an example that is not necessarily an alternative to another example introduced previously. Any embodiment or design presented as "one example" or "another example" in the embodiments of the present application does not necessarily preclude the incorporation of some or all characteristics or components from other examples.

[0050] For the sake of clear and concise description of the following embodiments, a brief introduction of the related art is first given:

[0051] In the short-circuit current calculation of the power system, the construction of the node admittance matrix mainly relies on manual analysis of the network topology and element parameters, and is completed by manually calculating the self-admittance and mutual admittance of each node. For a complex power grid with new energy access, the traditional method needs to manually identify the equivalent models of different power supply types such as synchronous machines and new energy inverters and their access positions, which is tedious and prone to errors.

[0052] When the system is in an asymmetric fault, the existing method usually needs to establish the positive sequence, negative sequence and zero sequence networks respectively and solve them, and the calculation process is complex, it is difficult to realize the fast and automatic modification of the admittance matrix under fault conditions, and it cannot meet the demand of fast and accurate calculation of short-circuit current for high proportion of new energy power grid.

[0053] Therefore, the embodiment of the present application provides an admittance matrix generation method, in which, when the operating state of the first circuit is normal, the first system information in the first circuit is obtained, the self-admittance of each node in the first circuit and the mutual admittance between nodes are calculated based on the first system information, and the first node admittance matrix is obtained; when the operating state of the first circuit is abnormal, the fault point of the first circuit is determined; the first fault information corresponding to the fault point of the first circuit is obtained; the fault equivalent impedance of equivalent the negative sequence network and the zero sequence network to the positive sequence network is calculated based on the first fault information and the first system information; the first node admittance matrix is modified based on the fault equivalent impedance and the first fault information, and the target node admittance matrix is obtained. As can be seen, the present application identifies the topology and generates the node admittance matrix under the normal state, and then uses the calculated fault equivalent impedance to uniformly convert the influence of the sequence network of the asymmetric fault to the positive sequence network for modification, so as to obtain the target node admittance matrix, realize the accurate generation of the admittance matrix, and improve the efficiency and accuracy of the short-circuit current calculation of the new energy power grid.

[0054] In order to make the technical solutions of the present application clearer and easier to understand, the application scenarios of the technical solutions of the present application will be introduced below in combination with the drawings. As shown in the figure, the figure is a schematic diagram of a power system structure provided by the embodiment of the present application, which shows a typical application scenario suitable for the implementation of the technical solutions of the present application. Figure 1 As shown in the figure, the figure is a schematic diagram of a power system structure provided by the embodiment of the present application, which shows a typical application scenario suitable for the implementation of the technical solutions of the present application.

[0055] In this application scenario, the power system contains various types of power supply elements, transmission lines and loads, and is connected by electrical nodes to form a power supply network. Specifically, the system includes three power sources, two synchronous power sources and one new energy power source (for example, a photovoltaic power generation unit). The parameters of each power source are provided by the input information, wherein the equivalent impedances of the two synchronous power sources are defined as Z sa and Z sb ; the parameters of the new energy power source include its rated capacity and low voltage ride through control parameters.

[0056] The system also includes two transmission lines. Based on the input line length and unit impedance parameters, the total impedance of each line section is automatically calculated. The load is measured at equivalent impedance. Z LoadI express.

[0057] The system has three nodes: N1, N2, and N3. Nodes N1 and N3 are connected to the synchronous power source, while node N2 is connected to the renewable energy source. Nodes N1 and N2 are connected by a line impedance Z. LI The connection between nodes N1 and N3 is achieved through the line impedance Z. LII Connections. The relationships between nodes and the system topology are automatically identified from the input information.

[0058] Taking this typical application scenario as an example, the subsequent method description will explain in detail the generation and correction process of the node admittance matrix based on the system parameters and topology in this scenario, so as to clearly and completely illustrate the technical solution of this application.

[0059] To make the technical solution of this application clearer and easier to understand, the following describes a method for generating an admittance matrix provided by an embodiment of this application, in conjunction with the above application scenarios. Figure 2 As shown in the figure, this is a flowchart of an admittance matrix generation method provided in an embodiment of this application.

[0060] This method is applied to processing equipment, which can be a server in a power system dispatch center, a monitoring computer in a substation, or an embedded processor integrated into a relay protection device, or other devices with computing capabilities. The admittance matrix generation method includes:

[0061] S201. When the first circuit is in normal operating condition, the processing device acquires the first system information in the first circuit, calculates the self-admittance of each node in the first circuit and the mutual admittance between nodes based on the first system information, and obtains the first node admittance matrix.

[0062] The first circuit is Figure 1 The schematic diagram of the power system structure in the figure is the power system to be analyzed in this application.

[0063] The first system information refers to the data describing the relationship between power system component parameters and topology, including power source parameters, line parameters, load equivalent impedance, and node relationships. It is the fundamental input for constructing the admittance matrix. A node is an electrical connection point in the power system, such as a power source connection point, line branch point, or load connection point; it is the basic unit for admittance matrix modeling. For a given node, its self-admittance is equal to the sum of the admittances of all branches directly connected to that node, reflecting the node's own current conduction capability, denoted as . , i is the node number. For two associated nodes, the mutual admittance is equal to the inverse of the sum of the admittances of all branches directly connecting the two nodes, reflecting the current coupling relationship between the two nodes, denoted as , (i, j) is the node number, i≠j. The first node admittance matrix refers to an N×N order matrix (N is the number of nodes) with node as row and column dimensions, self-admittance and mutual admittance as elements under normal operating conditions, denoted as , which is used to describe the electrical characteristics of the network under normal conditions.

[0064] When the operating state of the first circuit is normal, the processing device first acquires the first system information through the power grid monitoring system or the preset parameter library.

[0065] The first system information is important data describing the parameter and topological association of the power system element, including power supply parameters, line parameters, load equivalent impedance and node association relationship;

[0066] Among them, the power supply parameters cover traditional synchronous power supply and new energy power supply. Synchronous power supply needs to collect voltage levels such as 10kV and 35kV; equivalent impedance, reflecting the internal impedance characteristics of the generator, denoted as 、 New energy power supply (photovoltaic, wind power, etc.) needs to collect rated capacity (such as 500kW, 1MW) and low voltage ride through control parameters (including voltage drop threshold value, such as 90% of rated voltage, and reactive power compensation coefficient, used to adjust the reactive power output during fault).

[0067] The line parameters include line length, unit positive sequence impedance, unit negative sequence impedance and unit zero sequence impedance; the unit positive sequence, negative sequence and zero sequence impedance of the line will change due to the influence of environmental temperature, so the parameters need to be corrected in combination with real-time temperature during actual collection. Real-time line temperature can be obtained through line temperature measuring device, or reasonable estimation can be made according to environmental temperature, and then the line parameters under the reference temperature of 25℃ are adjusted according to the conductor temperature coefficient (different material conductors have different temperature coefficients, such as copper conductor and aluminum conductor each have corresponding standard value), the corrected parameters are used as a part of the first system information, which can further improve the accuracy of subsequent impedance calculation.

[0068] The load equivalent impedance refers to the equivalent of the user side distributed load as a concentrated impedance, and the equivalent impedance value (denoted as ) is collected, reflecting the power consumption characteristics and current consumption capacity of the load.

[0069] The node association relationship includes node quantity and association information, and the node quantity (such as 3 nodes, 5 nodes) and the connection relationship between nodes (such as node 1 and node 2 are connected through a line, and node 3 and node 1 are associated through a branch) are automatically identified through a power grid topology diagram, wherein the power supply access point, the line branch point and the load connection point are defined as nodes, so as to ensure that the topology identification is not missed.

[0070] For a power converter such as a photovoltaic inverter and a wind power converter, in addition to the rated capacity and the low voltage ride through control parameters mentioned above, the negative sequence current suppression coefficient and the zero sequence current flow capacity related information also need to be collected. The negative sequence current suppression coefficient is used to determine the degree of blocking of the negative sequence current by the power supply, and the value range is usually between 0 and 1, 0 represents no negative sequence current suppression, and 1 represents complete negative sequence current blocking. The zero sequence current flow capacity needs to record whether the power supply is equipped with a grounding transformer, the neutral point grounding mode and the like, such as a certain photovoltaic power station realizing zero sequence current flow through a neutral point of a box transformer via a specific resistance grounding resistor. These information needs to be included in the first system information, which provides a basis for subsequent negative sequence and zero sequence network equivalent impedance calculation.

[0071] Based on the first system information, the processing device calculates the self-impedance of each node in the first circuit and the mutual impedance between nodes to obtain a first node impedance matrix. Specifically, it includes:

[0072] According to the number of nodes of the first circuit, a zero matrix of corresponding dimension is initialized; the self-impedance of each node in the first circuit is calculated; the mutual impedance between the associated nodes in the first circuit is calculated; the self-impedance of each node in the first circuit and the mutual impedance value between the associated nodes in the first circuit are filled in the corresponding position of the zero matrix to obtain the first node impedance matrix.

[0073] According to the number of nodes N identified in the first system information, an N×N order zero matrix is generated, and the row and column numbers of the matrix correspond to the node numbers respectively. The self-impedance is calculated, and for each node i , all branches (including lines, equivalent impedance of power supply, equivalent impedance of load, etc.) directly connected to the node are traversed, the branch impedance (impedance is the inverse of impedance, i.e. Y =1 / Z ) is calculated, and the sum is obtained to obtain the self-impedance of the node. The mutual impedance is calculated: for each pair of associated nodes i and j , all branches directly connecting the two nodes are traversed, the sum of the branch impedances is calculated, and the negative number is taken to obtain the mutual impedance ; if the two nodes have no direct connection (non-associated nodes), the mutual impedance .

[0074] Figure 1 ​For example, the self-admittance of node N1 is the sum of three admittances: the line admittance between node N1 and node N2, the line admittance between node N1 and node N3, and the admittance of the equivalent impedance of the backside synchronous source of node N1; the self-admittance of node N2 is the sum of two admittances: the line admittance between node N1 and node N2, and the admittance of the equivalent impedance of the backside load of node N2; the self-admittance of node N3 is the sum of two admittances: the line admittance between node N1 and node N3, and the admittance of the equivalent impedance of the backside synchronous source of node N3. The calculation formula is shown in formula (1):

[0075] Formula (1)

[0076] wherein, is the self-admittance of node N1, is the self-admittance of node N2, is the self-admittance of node N3, is the line admittance between node N1 and node N3, is the line admittance between node N1 and node N2, is the admittance of the equivalent impedance of the backside synchronous source of node N1, is the admittance of the equivalent impedance of the backside load of node N2, is the admittance of the equivalent impedance of the backside synchronous source of node N3.

[0077] The mutual admittance between node N1 and node N2 is the opposite number of the line admittance between node N1 and node N2, the mutual admittance between node N1 and node N3 is the opposite number of the line admittance between node N1 and node N3, and the mutual admittance between node N2 and node N3 is Figure 1 It can be identified that the irrelevant information is 0. The calculation formula is shown in formula (2):

[0078] Formula (2)

[0079] wherein, is the mutual admittance between node N1 and node N2, is the mutual admittance between node N2 and node N1, is the mutual admittance between node N2 and node N3, is the mutual admittance between node N3 and node N2, is the mutual admittance between node N1 and node N3, is the mutual admittance between node N1 and node N3, is the line admittance between node N1 and node N3, is the line admittance between node N1 and node N2.

[0080] According to Figure 1The number of nodes identified is 3. First, a 3×3 zero matrix is ​​generated, and the magnitude of the zero matrix is ​​calculated based on the admittance information in formulas (1) and (2) to obtain the admittance matrix of the first node under normal conditions. The calculation formula is shown in formula (3):

[0081] Formula (3)

[0082] S202. When the first circuit is in an abnormal operating state, the processing device determines the fault point of the first circuit and obtains the first fault information corresponding to the fault point of the first circuit.

[0083] A fault point refers to the specific location of a power system when the first circuit is in an abnormal operating state, i.e., when a short-circuit fault occurs. It is typically located on the line between two nodes. Processing equipment, through fault recording data (such as the moment of current change and the location of voltage drop), combined with the line topology, can locate the line segment where the fault point is located, such as the line between node 1 and node 2, and quantify the proportional location of the fault point on the line. Figure 3 As shown in the figure, this is a partial schematic diagram of a power system experiencing a fault according to an embodiment of this application. The fault point is located at the midpoint of the line between node 1 and node 2. The first fault information refers to key data describing the fault characteristics, including the fault location, fault type, and transition resistance value, which is an important basis for fault equivalence calculation and matrix correction.

[0084] Specifically, it is necessary to specify "which two nodes on the line" and "the specific proportion of the line where the fault occurs," denoted as k. For example, at 50% of the total line length, k=0.5. When the first circuit is a 110kV or higher high-voltage transmission line, a traveling wave ranging device can be used to achieve precise quantitative location of the fault point. When a fault occurs, the traveling wave detection devices at both ends of the line record the arrival time of the traveling wave front. Combined with the propagation speed of the traveling wave in a specific line (approximately 3×10^5 km / s), the distance from the fault point to the near end of the line is calculated. This distance is then compared with the total line length to obtain the proportion of the fault location. This location method typically has an error of less than 1% and is suitable for high-voltage line scenarios where high accuracy in fault location is required.

[0085] Based on the electrical characteristics of short-circuit faults, the fault types are divided into the following four categories: the first category is three-phase fault, which refers to the simultaneous short circuit of three-phase conductors. It is a symmetrical fault, and the fault current contains only positive sequence components. The second category is single-phase ground fault, which refers to the short circuit between a single-phase conductor and the ground. It is an asymmetrical fault, and the fault current contains positive sequence, negative sequence, and zero sequence components.

[0086] The third type is a two-phase-to-phase fault, which refers to a short circuit between any two phase conductors, belongs to an asymmetric fault, and the fault current contains positive sequence and negative sequence components; the fourth type is a two-phase-to-ground fault, which refers to a short circuit between any two phase conductors and the ground at the same time, belongs to an asymmetric fault, and the fault current contains positive sequence, negative sequence and zero sequence components.

[0087] The transition resistance value refers to the contact resistance at the fault point, and reflects the metallic degree of the fault (for example, the transition resistance is close to 0 ohm when the metallic short circuit occurs, and the transition resistance can reach several ohms to tens of ohms when the short circuit occurs through air or soil). The transition resistance to the ground is denoted as , and the transition resistance of the phase-to-phase fault is denoted as The transition resistance value can be inversely calculated by the voltage and current data of the fault recording by the processing device, without manual estimation.

[0088] It can be seen in Figure 3 that the fault occurs on the line between node 1 (N1) and node 2 (N2), and is located at the midpoint of the line, that is, the fault position is at k=50% of the line of node N1 and node N2; the fault type is a phase-to-phase fault; and the transition resistance is 1.7 ohm.

[0089] By associating the fault recording data with the topology, the positioning and proportional quantification of the fault point are realized, and the calculation deviation of the equivalent impedance caused by the traditional manual estimation of the fault position is avoided; not only the qualitative information such as the fault type and position is collected, but also the key parameters such as the transition resistance and the proportional position are quantified, so as to ensure the accuracy of the subsequent fault equivalent impedance calculation and matrix correction; relying on the automatic fault information collection mechanism, the information collection and arrangement can be completed within seconds after the fault occurs, so as to meet the timeliness requirements of the power grid fault rapid analysis and the relay protection action.

[0090] In S203, the processing device calculates the fault equivalent impedance of equivalent the negative sequence network and the zero sequence network to the positive sequence network based on the first fault information and the first system information.

[0091] The sequence network refers to a network corresponding to three symmetrical components of positive sequence, negative sequence and zero sequence according to the symmetrical component method, including a positive sequence network (describing the flow-through characteristics of the positive sequence current), a negative sequence network (describing the flow-through characteristics of the negative sequence current) and a zero sequence network (describing the flow-through characteristics of the zero sequence current). The fault equivalent impedance refers to the comprehensive impedance after the impedance characteristics of the negative sequence network and the zero sequence network are equivalent and converted to the positive sequence network, denoted as Z feq , which is used for uniformly processing the influence of the asymmetric fault in the positive sequence network and simplifying the matrix correction process.

[0092] Under the low voltage ride through control strategy of new energy negative sequence suppression, the negative sequence is equivalent to open circuit. If there are multiple new energy power sources (such as multiple nodes connected to photovoltaic or wind power) that enable the negative sequence suppression control strategy in the first circuit, when calculating the equivalent impedance of the negative sequence network, all such new energy power sources in the negative sequence network should be regarded as open circuit, and only the negative sequence impedance of the synchronous power source and the line is retained to participate in the calculation, so as to avoid missing the comprehensive influence of multiple new energy power sources on the negative sequence network, and to ensure that the calculation result of the negative sequence impedance conforms to the actual power grid situation.

[0093] When an asymmetric fault occurs, the negative sequence and zero sequence network is the series-parallel connection relationship of the zero sequence or negative sequence line, the internal impedance of the power source and the transition resistance, and the equivalent impedance of the negative sequence zero sequence network can be calculated. In the positive sequence network, the equivalent impedance of the negative sequence zero sequence network is merged into the positive sequence network at the fault point Z feq The unified processing is specifically as follows:

[0094] According to the fault position in the first fault information, the nodes in the first circuit are prioritized to obtain the node sequence of the first circuit. Specifically, according to the association degree of the fault point and the node, all nodes are sorted from high to low priority to provide a logical order for impedance conversion:

[0095] The first level node is the node directly connected to the fault point (such as the fault point is located on the line of node 1-node 2, and the first level node is node 1 and node 2), which is the main node of the fault current.

[0096] The second level node is the node directly connected to the first level node but not directly associated with the fault point (such as node 3 is connected to node 1 and not connected to the fault point, and node 3 is the second level node).

[0097] The third level node and above are nodes connected to low priority nodes and have a lower degree of association with the fault point, and are sorted in order of distance from the fault point, such as node 4 is connected to the second level node 3, and node 4 is the third level node.

[0098] For example Figure 4 N4 is the fault point, the first level node is N1 and N2, and the second level node is N3. Figure 4 is a schematic diagram of a power system with a fault point provided by an embodiment of the present application.

[0099] Impedance conversion is performed on the nodes of the first circuit from the lowest to the highest priority node to obtain the first impedance conversion result; the third level node is converted to the second level node; the second level node is converted to the first level node. When Figure 4 When the second level node N3 is converted to the first level node N1, the equivalent impedance of the left side of N1 node can be represented as: The impedance reduction can concentrate the dispersed impedance of the complex network into the concentrated impedance on the two sides of the fault point (the side of the primary node), simplify the subsequent sequence network equivalent calculation, and avoid the sharp increase in calculation complexity caused by too many nodes.

[0100] Based on the first impedance reduction result, the equivalent impedance of the negative sequence network at the fault point side and the equivalent impedance of the zero sequence network at the fault point side are calculated;

[0101] If the system contains new energy power sources using negative sequence suppression control strategies, such as the negative sequence current suppression function of photovoltaic inverters, it is equivalent to an open circuit in the negative sequence network. Because the negative sequence suppression control blocks the negative sequence current, the negative sequence path of the new energy power source needs to be excluded when calculating the negative sequence impedance, and only the negative sequence impedance of the line and the synchronous power source is retained.

[0102] The calculation method is shown in formula (4):

[0103]

[0104] Among them, is the left equivalent impedance of the negative sequence network, is the right equivalent impedance of the negative sequence network, is the left equivalent impedance of the zero sequence network, is the right equivalent impedance of the zero sequence network, is the comprehensive equivalent impedance of the primary node on the left side of the fault point in the negative sequence network or the zero sequence network, is the comprehensive equivalent impedance of the primary node on the right side of the fault point in the negative sequence network or the zero sequence network.

[0105] According to the fault type in the first fault information, the equivalent impedance of the negative sequence network at the fault point side, the equivalent impedance of the zero sequence network at the fault point side, and the transition resistance value are combined according to a preset rule to obtain a fault equivalent impedance.

[0106] For the special form of symmetrical fault of three-phase ground fault, since the fault current does not contain negative sequence and zero sequence components, the fault equivalent impedance is only the ground transition resistance; for two-phase ground fault, if the transition resistance contains both inter-phase resistance and ground resistance, the two kinds of resistance need to be included in the corresponding calculation link when calculating the fault equivalent impedance, and combined according to the composite characteristics of the transition resistance in the actual fault to ensure that the equivalent impedance can accurately reflect the fault state.

[0107] Specifically, for symmetrical faults, the negative sequence and zero sequence networks are The fault equivalent impedance is .

[0108] For single-phase ground fault, the positive sequence, negative sequence and zero sequence networks are in series, and the fault equivalent impedance calculation formula is shown in formula (5):

[0109] Equation (5)

[0110] For two-phase phase-to-phase short-circuit fault, the positive sequence network and the negative sequence network are connected in parallel, and the fault equivalent impedance calculation formula is as shown in Equation (6):

[0111] Equation (6)

[0112] For two-phase ground fault, the positive sequence and zero sequence networks are connected in parallel, and the fault equivalent impedance calculation formula is as shown in Equation (7):

[0113] Equation (7)

[0114] wherein, is the fault equivalent impedance when the first circuit is in single-phase ground fault, is the fault equivalent impedance when the first circuit is in two-phase phase-to-phase short-circuit fault, is the fault equivalent impedance when the first circuit is in two-phase ground fault, is the left equivalent impedance of the negative sequence network, is the right equivalent impedance of the negative sequence network, is the left equivalent impedance of the zero sequence network, is the right equivalent impedance of the zero sequence network, is the transition resistance value of single-phase ground fault, is the transition resistance value of phase-to-phase fault.

[0115] The application unifies the influence of the negative sequence network and the zero sequence network to the positive sequence network through the fault equivalent impedance, avoids the complex process of separately solving three sequence networks in the traditional method, greatly improves the calculation efficiency, fully considers the negative sequence suppression strategy of new energy, dynamically adjusts the equivalent model in the negative sequence impedance calculation, solves the fault current calculation deviation problem caused by the traditional method ignoring the characteristics of new energy, and improves the calculation accuracy. Through node priority sorting and step-by-step impedance conversion, centralized processing of dispersed impedance is ensured without omission, and the equivalent impedance calculation result can be directly used for subsequent matrix correction without secondary verification.

[0116] S204, the processing device corrects the first node admittance matrix based on the fault equivalent impedance and the first fault information, and obtains a target node admittance matrix.

[0117] In Figure 4In the process, the processing device takes the fault point in the first circuit as a new node, calculates the self-admittance of the new node and the mutual admittance between the new node and the adjacent node based on the fault equivalent impedance and the first fault information; constructs a fault compensation matrix based on the self-admittance of the new node and the mutual admittance between the new node and the adjacent node; specifically, the fault point node only has mutual admittance with the first-level node, and the rest are 0.

[0118] The self-admittance of a fault node is related to the fault equivalent impedance and the line fault information. For example, the self-impedance of node N4. Represented as: When the fault type is a single-phase ground fault, the formula in this equation... yes When the fault type is a two-phase short-circuit fault, the formula in this equation... yes When the fault type is a two-phase ground fault, the formula in this equation... yes Mutual impedance between nodes N1 and N4 Represented as: Mutual impedance between nodes N2 and N4 Represented as: The fault compensation matrix is ​​constructed based on the self-admittance of the newly added node and the mutual admittance between the newly added node and its neighboring nodes. The calculation formula is shown in formula (8):

[0119] Formula (8)

[0120] in, For the fault compensation matrix, The mutual admittance between node N1 and node N4 The mutual admittance between node N4 and node N1, The mutual admittance between node N2 and node N4. The mutual admittance between node N4 and node N2. Let N4 be the self-admittance.

[0121] The self-admittance and mutual admittance of the nodes in the admittance matrix of the first node are corrected based on the network topology including the newly added node; specifically, the original self-admittance of node N1 is corrected. Partially becomes k And since there is no longer an interconnection between nodes N1 and N2, the corrected matrix will be re-aligned. Assigning values, obtaining fault result 4 4th order matrix The calculation formula is shown in formula (9):

[0122] Formula (9)

[0123] wherein, is the modified first node admittance matrix, is the first node admittance matrix.

[0124] The modified first node admittance matrix is added to the fault compensation matrix based on the fault information to obtain a target node admittance matrix, and the calculation formula is wherein, is the target node admittance matrix. The matrix completely contains the impedance characteristics of the fault point, the network topology change after the fault, and the equivalent influence of the sequence network, and can be directly used as an input model for short-circuit current calculation.

[0125] In some embodiments, after the target node admittance matrix is generated, it is necessary to verify whether the determinant value is not zero to ensure that the matrix has reversibility, and only the reversible matrix can be used for subsequent node voltage solving in short-circuit current calculation. If the absolute value of the determinant value is too small (such as less than 10 -6 ), it is necessary to check the construction logic of the fault compensation matrix to check whether there is a sign error, impedance value input deviation, etc. in the calculation of the mutual admittance of the new node, and to ensure that the matrix meets the mathematical requirements of subsequent calculation.

[0126] When the transition resistance of the fault point approaches infinity, that is, the fault disappears and the system returns to normal operation state, the target node admittance matrix should be basically the same as the first node admittance matrix (after removing the dimension of the new node). By setting the transition resistance to a maximum value (such as 10^6Ω, which is approximately open circuit), the target node admittance matrix can be recalculated, and the deviation of the self-admittance and mutual admittance of the modified original node (such as the nodes N1, N2, N3 already existing in the normal state) from the corresponding parameters of the first node admittance matrix is compared. If the deviation is less than 0.1%, it indicates that the matrix modification logic is consistent and there is no systematic error.

[0127] The present application dynamically adjusts the dimension and element value of the admittance matrix through the new node and the fault compensation matrix, ensures that the matrix always remains consistent with the electrical characteristics of the network after the fault, avoids the problem that the traditional fixed matrix cannot adapt to the fault state, each step of modification is based on the quantitative fault information and equivalent impedance, the modification process can be traced back, which is convenient for subsequent fault analysis and verification, reduces the calculation error caused by the fuzzy modification logic, and the target node admittance matrix can be directly imported into the short-circuit current calculation software without additional format conversion or parameter adjustment, thereby providing efficient support for power grid fault analysis and relay protection setting.

[0128] ​Based on the above, when the operating state of the first circuit is normal, first system information in the first circuit is obtained, self-admittances of each node in the first circuit and mutual admittances between nodes are calculated based on the first system information, and a first node admittance matrix is obtained; when the operating state of the first circuit is abnormal, a fault point of the first circuit is determined; first fault information corresponding to the fault point of the first circuit is obtained; fault equivalent impedance of equivalent of a negative sequence network and a zero sequence network to a positive sequence network is calculated based on the first fault information and the first system information; the first node admittance matrix is corrected based on the fault equivalent impedance and the first fault information, and a target node admittance matrix is obtained. The application identifies topology and generates a node admittance matrix in a normal state, then uses calculated fault equivalent impedance to uniformly convert the influence of sequence networks of asymmetric faults to the positive sequence network for correction, obtains a target node admittance matrix, realizes accurate generation of the admittance matrix, and improves the efficiency and precision of short-circuit current calculation of a new energy power grid.

[0129] The above Figures 1 to 4 The admittance matrix generation method provided by the embodiments of the application is described in detail, and the device and equipment provided by the embodiments of the application will be described below with reference to the drawings.

[0130] The embodiments of the application further provide an admittance matrix generation device, as shown in Figure 5 The device includes an obtaining module 501, a calculation module 502 and a correction module 503.

[0131] The obtaining module 501 is configured to, when the operating state of the first circuit is normal, obtain first system information in the first circuit, calculate self-admittances of each node in the first circuit and mutual admittances between nodes based on the first system information, and obtain a first node admittance matrix; when the operating state of the first circuit is abnormal, determine a fault point of the first circuit; and obtain first fault information corresponding to the fault point of the first circuit.

[0132] The calculation module 502 is configured to calculate fault equivalent impedance of equivalent of a negative sequence network and a zero sequence network to a positive sequence network based on the first fault information and the first system information.

[0133] The correction module 503 is configured to correct the first node admittance matrix based on the fault equivalent impedance and the first fault information, and obtain a target node admittance matrix.

[0134] In some possible implementation manners, the obtaining module 501 is specifically configured to initialize a zero matrix of a corresponding dimension according to the number of nodes of the first circuit.

[0135] The self-admittances of each node in the first circuit are calculated.

[0136] Calculate mutual admittance between associated nodes in the first circuit;

[0137] Fill the calculated self-admittance of each node in the first circuit and the mutual admittance between associated nodes in the first circuit into the corresponding positions of the zero matrix to obtain a first node admittance matrix.

[0138] In some possible implementation manners, the first fault information includes a fault position, a fault type, and a transition resistance value, and the calculation module 502 is specifically configured to prioritize nodes in the first circuit according to the fault position in the first fault information to obtain a node sequence of the first circuit.

[0139] Impedance reduction is performed on the nodes in the node sequence of the first circuit from the lowest priority node to the highest priority node to obtain a first impedance reduction result.

[0140] Based on the first impedance reduction result, the equivalent impedance of the negative sequence network on the fault point side and the equivalent impedance of the zero sequence network on the fault point side are calculated.

[0141] According to the fault type in the first fault information, the equivalent impedance of the negative sequence network on the fault point side, the equivalent impedance of the zero sequence network on the fault point side, and the transition resistance value are combined according to a preset rule to obtain a fault equivalent impedance.

[0142] In some possible implementation manners, the equivalent impedance of the negative sequence network on the fault point side is determined in the following manner:

[0143] If the first circuit includes a new energy source that adopts a negative sequence suppression control strategy, the equivalent impedance of the negative sequence network on the fault point side and the equivalent impedance of the zero sequence network on the fault point side are calculated based on the first impedance reduction result under the condition that the new energy source is regarded as an open circuit in the negative sequence network.

[0144] In some possible implementation manners, the correction module 503 is specifically configured to take the fault point in the first circuit as a new node, calculate the self-admittance of the new node and the mutual admittance between the new node and adjacent nodes based on the fault equivalent impedance and the first fault information.

[0145] A fault compensation matrix is constructed according to the self-admittance of the new node and the mutual admittance between the new node and adjacent nodes.

[0146] The self-admittance and mutual admittance of the nodes in the first node admittance matrix are corrected according to the network topology including the new node.

[0147] The corrected first node admittance matrix and the fault compensation matrix are added to obtain a target node admittance matrix.

[0148] In some possible implementation manners, the first system information comprises a power parameter, a line parameter, a load equivalent impedance and a node association relationship.

[0149] In some possible implementation manners, the line parameter comprises a line length, a unit positive sequence impedance, a unit negative sequence impedance and a unit zero sequence impedance.

[0150] The admittance matrix generation apparatus according to the embodiments of the present application can correspond to performing the method described in the embodiments of the present application, and the above other operations and / or functions of each module / unit of the admittance matrix generation apparatus are respectively for realizing Figure 2 The corresponding flow of each method in the illustrated embodiments, for the sake of brevity, will not be repeated here.

[0151] The embodiments of the present application further provide a computing device. As Figure 6 shown, the figure is a schematic diagram of a computing device provided by the embodiments of the present application, and the computing device 400 comprises a bus 401, a processor 402, a communication interface 403 and a memory 404. The processor 402, the memory 404 and the communication interface 403 communicate through the bus 401.

[0152] The bus 401 can be a peripheral component interconnect (peripheral component interconnect, PCI) bus or an extended industry standard architecture (extended industry standard architecture, EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For the sake of convenience, Figure 6 only one thick line is used in the figure, but it does not mean that there is only one bus or only one type of bus.

[0153] The processor 402 can be any one or more of a central processing unit (central processing unit, CPU), a graphics processing unit (graphics processing unit, GPU), a microprocessor (micro processor, MP) or a digital signal processor (digital signal processor, DSP).

[0154] The communication interface 403 is used for external communication.

[0155] The memory 404 can include volatile memory, such as random access memory (RAM) comprising a number of modules. The memory 404 also can include non-volatile memory, such as read-only memory (ROM), EEPROM, flash memory, or hard disks (HDD) or solid-state drives (SSD).

[0156] The memory 404 stores executable code that the processor 402 executes to perform the aforementioned admittance matrix generation method.

[0157] In particular, in the case of the embodiment shown, and Figure 5 In the case of the embodiment described, and Figure 5 In the case of the embodiment described, and Figure 5 In the case of the embodiment described, and

[0158] The embodiments of the present application also provide a computer readable storage medium. The computer readable storage medium can be any available medium or data storage that can be used to store data and that can be accessed by a computing device. The computer readable storage medium can be a magnetic-based, optical-based, semiconductor-based, or any other available data storage medium. The computer readable storage medium includes instructions that are executable by a computing device to perform the aforementioned admittance matrix generation method.

[0159] The embodiments of the present application also provide a computer program product. The computer program product includes one or more computer instructions. When loaded and executed by a computing device, the computer instructions cause the computing device to perform all or part of the processes or functions described in the embodiments of the present application.

[0160] The computer instructions can be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another computer readable storage medium. For example, the computer instructions can be transmitted from one website, computer, or data center to another website, computer, or data center via wired (such as coaxial cable, optical fiber) or wireless (such as infrared, wireless, microwave, etc.) means.

[0161] When the computer program product is executed by a computer, the computer performs any of the aforementioned admittance matrix generation methods. The computer program product can be a software installation package; when any of the aforementioned admittance matrix generation methods is required, the computer program product can be downloaded and executed on the computer.

[0162] The descriptions of the processes or structures corresponding to the above figures each have their own emphasis. For parts of a process or structure that are not described in detail, please refer to the relevant descriptions of other processes or structures.

[0163] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be covered within the scope of protection of this application.

Claims

1. A method of generating an admittance matrix, characterized by, The method comprises: When the operating state of the first circuit is normal, obtaining first system information in the first circuit, calculating self-admittances of nodes in the first circuit and mutual admittances between the nodes based on the first system information, and obtaining a first node admittance matrix; When the operating state of the first circuit is abnormal, determining a fault point of the first circuit, and obtaining first fault information corresponding to the fault point of the first circuit; Based on the first fault information and the first system information, calculating a fault equivalent impedance for equivalent of a negative sequence network and a zero sequence network to a positive sequence network; Based on the fault equivalent impedance and the first fault information, correcting the first node admittance matrix to obtain a target node admittance matrix; The first fault information comprises a fault position, a fault type and a transition resistance value, and the calculation of the fault equivalent impedance for equivalent of the negative sequence network and the zero sequence network to the positive sequence network based on the first fault information and the first system information comprises: According to the fault position in the first fault information, the nodes in the first circuit are prioritized to obtain a node sequence of the first circuit; According to the node sequence of the first circuit, impedance conversion is sequentially performed on nodes from the lowest to the highest priority to obtain a first impedance conversion result; Based on the first impedance conversion result, the equivalent impedance of the negative sequence network at the fault point side and the equivalent impedance of the zero sequence network at the fault point side are calculated; According to the fault type in the first fault information, the equivalent impedance of the negative sequence network at the fault point side, the equivalent impedance of the zero sequence network at the fault point side and the transition resistance value are combined according to a preset rule to obtain the fault equivalent impedance; Based on the fault equivalent impedance and the first fault information, the first node admittance matrix is corrected to obtain a target node admittance matrix, which comprises: The fault point in the first circuit is taken as a new node, and the self-admittance of the new node and the mutual admittance between the new node and adjacent nodes are calculated based on the fault equivalent impedance and the first fault information; A fault compensation matrix is constructed according to the self-admittance of the new node and the mutual admittance between the new node and adjacent nodes; The self-admittance and mutual admittance of the nodes in the first node admittance matrix are corrected according to the network topology containing the new node; The corrected first node admittance matrix and the fault compensation matrix are added to obtain the target node admittance matrix.

2. The method of claim 1, wherein, The calculation of the self-admittance and mutual admittance between nodes in the first circuit based on the first system information to obtain the first node admittance matrix comprises: A zero matrix of corresponding dimension is initialized according to the number of nodes in the first circuit; The self-admittance of each node in the first circuit is calculated; The mutual admittance between associated nodes in the first circuit is calculated; The calculated self-admittance of each node in the first circuit and the mutual admittance between associated nodes in the first circuit are filled into the corresponding positions of the zero matrix to obtain the first node admittance matrix.

3. The method of claim 1, wherein, The first system information comprises power supply parameters, line parameters, load equivalent impedance and node association relationship.

4. The method of claim 3, wherein, The line parameters comprise line length, unit positive sequence impedance, unit negative sequence impedance and unit zero sequence impedance.

5. The method of claim 1, wherein, The equivalent impedance of the negative sequence network at the fault point side is determined by the following manner: If the first circuit contains a new energy source adopting a negative sequence suppression control strategy, the equivalent impedance of the negative sequence network at the fault point side and the equivalent impedance of the zero sequence network at the fault point side are calculated based on the first impedance conversion result under the condition that the new energy source is regarded as an open circuit in the negative sequence network.

6. An admittance matrix generating device characterized by comprising: The device comprises: The acquisition module is configured to, when the operating state of the first circuit is normal, acquire first system information in the first circuit, calculate self-admittances of nodes in the first circuit and mutual admittances between the nodes based on the first system information, and obtain a first node admittance matrix; when the operating state of the first circuit is abnormal, determine a fault point of the first circuit; and acquire first fault information corresponding to the fault point of the first circuit. The calculation module is configured to calculate fault equivalent impedances of the negative sequence network and the zero sequence network to the positive sequence network based on the first fault information and the first system information; prioritize the nodes in the first circuit according to fault positions in the first fault information, and obtain a node sequence of the first circuit; sequentially perform impedance conversion on nodes with the lowest to highest priority in the node sequence of the first circuit, and obtain a first impedance conversion result; calculate the equivalent impedance of the negative sequence network at the fault point side and the equivalent impedance of the zero sequence network at the fault point side based on the first impedance conversion result; and combine the equivalent impedance of the negative sequence network at the fault point side, the equivalent impedance of the zero sequence network at the fault point side, and a transition resistance value according to a preset rule according to the fault type in the first fault information, and obtain the fault equivalent impedances. The correction module is configured to correct the first node admittance matrix based on the fault equivalent impedances and the first fault information, and obtain a target node admittance matrix; take the fault point in the first circuit as a new node, calculate self-admittances of the new node and mutual admittances between the new node and adjacent nodes based on the fault equivalent impedances and the first fault information; construct a fault compensation matrix according to the self-admittances of the new node and the mutual admittances between the new node and the adjacent nodes; correct self-admittances and mutual admittances of nodes in the first node admittance matrix according to a network topology containing the new node; and add the corrected first node admittance matrix and the fault compensation matrix based on the fault compensation matrix, and obtain the target node admittance matrix.

7. A computing device, comprising: comprises a memory and a processor; The memory stores one or more computer programs comprising instructions, and when the instructions are executed by the processor, the computing device performs the method of any one of claims 1 to 5.

8. A computer-readable storage medium, characterized in that, The computer readable storage medium is used to store a computer program for executing the method of any one of claims 1 to 5.

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