A testbench simulation verification platform and system

Abstract

This invention discloses a testbench simulation verification platform and system, comprising: a stimulus database for collecting and storing simulation source data; upon receiving a parameter configuration instruction from the module under test, determining the stimulus content corresponding to the configuration parameters, and outputting the stimulus content through a parameter interface; the stimulus content being used for simulation testing of the module under test; and a data conversion module for acquiring the output signal of the module under test and converting the output signal into response content in a preset format according to conversion rules. This invention simplifies the simulation process, reduces manual intervention, improves the automation and accuracy of simulation testing, and effectively enhances testing efficiency and reusability.

Description

Technical Field

[0001] This invention relates to the field of FPGA technology, and in particular to a testbench simulation verification platform and system. Background Technology

[0002] With the rapid development of FPGA (Field-Programmable Gate Array) technology, FPGAs are increasingly widely used in communication technology, digital signal processing, embedded systems, and many other fields. To ensure the correctness and stability of FPGA design functions, simulation testing has become an indispensable part of the design process. A testbench, as an important tool for verifying whether the FPGA design functions as expected, typically consists of three parts: stimulus signal input, top-level interface signal instantiation, and output result checking. The rationality of the testbench design directly affects the efficiency and accuracy of simulation testing.

[0003] However, in practical applications, FPGA developers often encounter the following problems when using testbench:

[0004] 1. Repetitive testbench writing: Developers typically need to rewrite the testbench module each time a new simulation task is performed, based on the specific test objectives. This leads to a large amount of repetitive work, increasing development costs and time.

[0005] 2. Lack of versatility: Existing testbench modules are typically customized for specific tasks and modules, lacking compatibility with different test scenarios and configurations. Whenever simulation requirements change, the testbench module often needs to be rewritten or adjusted, reducing its versatility and reusability. Summary of the Invention

[0006] According to one aspect of the present invention, a testbench simulation verification platform is provided, which is compatible with a variety of modules under test and improves the simulation efficiency of FPGA engineering.

[0007] To address the aforementioned technical problems, the first aspect of this invention discloses a testbench simulation verification platform, comprising:

[0008] An excitation database collects and stores simulation source data; upon receiving a parameter configuration instruction from the module under test, it determines the excitation content corresponding to the configuration parameters and outputs the excitation content through a parameter interface; the excitation content is used for simulation testing of the module under test.

[0009] The data conversion module acquires the output signal of the module under test and converts the output signal into a response content in a preset format according to the conversion rules.

[0010] In some implementations, the incentive database includes a data splitting unit, a data configuration unit, and a data generation unit. The data splitting unit is used to split the parameter configuration instructions of the module under test. The data configuration unit is used to determine the configuration parameters of each module under test according to the parameter configuration instructions. The data generation unit is used to automatically generate incentive content that meets the requirements of the module under test according to the user's configuration parameters.

[0011] In some implementations, the excitation content includes data type and data parameters. The data type includes single tone, wide spectrum, and constant. The data parameters include bandwidth, sampling rate, number of antennas, and timing data.

[0012] In some implementations, the data generation unit determines the incentive content through one or more of the following methods:

[0013] Different configuration parameters can be defined as macros or parameters using System Verilog or Verilog, and corresponding stimulus data can be generated based on the configuration.

[0014] In some implementations, the module under test defines the required configuration parameters through the parameter interface, and each stimulus content is set with a corresponding parameter interface.

[0015] In some embodiments, the data conversion module includes a data format conversion unit and a file import / export unit. The data format conversion unit is used to convert the data format of the output signal into response content of a preset data format; the file import / export unit is used to convert the output signal into response content of a preset file format.

[0016] In some implementations, the response content includes a data format and a file format, wherein the data format includes a data base and the file format includes txt and xlsx formats.

[0017] In some implementations, the incentive database and response content are written in Verilog or SystemVerilog.

[0018] Secondly, a testbench simulation verification system is disclosed, the system comprising:

[0019] The testbench simulation verification platform described above;

[0020] The module under test performs simulation testing based on the excitation content and generates an output signal.

[0021] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0022] This invention provides a testbench simulation verification platform and system. The stimulus database can automatically determine and output the corresponding stimulus content based on the parameter configuration instructions of the module under test, ensuring that each simulation task can accurately generate stimulus data that meets the requirements, avoiding the tedious work of repeatedly writing stimulus signals. Simultaneously, the data conversion module converts the output signals of the module under test into standard format response content according to conversion rules, making the test results more standardized, easier to store and analyze. This invention simplifies the simulation process, reduces manual intervention, improves the automation and accuracy of simulation testing, and effectively improves testing efficiency and reusability. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of an existing testbench simulation verification platform provided by the present invention;

[0024] Figure 2 This is a schematic diagram of yet another existing testbench simulation verification platform provided by the present invention;

[0025] Figure 3 This is a schematic diagram of a testbench simulation verification platform provided by the present invention. Detailed Implementation

[0026] To better understand and implement this invention, the technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0027] The terms “comprising” and “having” and any variations thereof in this invention are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device that includes a series of steps or modules is not necessarily limited to those steps or modules that are explicitly listed, but may include other steps or modules that are not explicitly listed or that are inherent to such process, method, product or device.

[0028] like Figure 1 As shown, this is a traditional testbench platform where each module under test corresponds to a set of stimulus and response data. This means that whenever a new module is added, new testbench code needs to be written for it, along with its own independent stimulus and response data files. This repetitive coding approach not only increases development costs but also reduces code reusability and maintainability.

[0029] To further improve work efficiency, there are Figure 2 The testbench platform uses a structure where multiple modules under test correspond to multiple independent testbench modules. While this works fine for a single task, it becomes difficult to manage and modify efficiently in complex systems. For example, when multiple modules under test require the same configuration, developers must manually configure multiple testbench modules repeatedly, leading to inefficiency.

[0030] However, the configuration process for both platforms mentioned above is complex, especially in multi-module, multi-task simulation environments. Developers need to manually configure stimulus sources, response files, and interface parameters for each module under test, which is prone to configuration errors or omissions. The configuration process is cumbersome, and there are no automated tools to reduce the risk of human error. The simulation environment setup cycle is long, and improper manual configuration can easily lead to deviations in test results.

[0031] In view of the above findings, embodiments of the present invention disclose a testbench simulation verification platform that is compatible with a variety of modules under test. During the simulation testing process, there is no need to repeatedly write testbench, thereby improving the simulation efficiency of FPGA projects.

[0032] like Figure 1 As shown, this platform includes an incentive database and a data conversion module. The incentive database collects and stores simulation source data; upon receiving a parameter configuration instruction from the module under test, it determines the incentive content corresponding to the configuration parameters and outputs the incentive content through a parameter interface; the incentive content is used for simulation testing of the module under test; the data conversion module acquires the output signal of the module under test and converts the output signal into response content in a preset format according to conversion rules.

[0033] The stimulus database stores and manages various simulation source data, centrally managing all simulation source data. Based on the test requirements of the module under test (DUT), corresponding stimulus content is generated and stored in the stimulus database. In each simulation test, the testbench does not need to write new stimulus signals for each simulation task; instead, it can reuse existing stimulus content. The stimulus content simulates the interaction between the DUT and the external environment, providing different input signals to verify the performance of the DUT and ensure that the functionality and performance of the DUT meet expectations.

[0034] In this application, the stimulus database includes a data splitting unit, a data configuration unit, and a data generation unit. The data splitting unit is used to split the parameter configuration instructions of the module under test (DUT). The parameter configuration instructions of the DUT typically include multiple specified parameters, such as clock signal, data bit width, and sampling rate. The data splitting unit determines the configuration parameters of each DUT based on the parameter configuration instructions, decomposing the input signal of the DUT into independent, easily manageable small units. The split contents can be processed individually, ensuring that the configuration and adjustment of each input signal are more flexible and accurate.

[0035] The data configuration unit independently configures each of the split configuration parameters, assigning different parameters to different simulation tasks and setting the required operating conditions for each module under test (DUT). For example, parameters such as the operating clock frequency, link data bit width, and data sampling rate can be configured individually to ensure that the excitation signal adapts to the needs of the DUT. The configuration process is flexibly adjusted according to the user's requirements and the simulation environment, ensuring that the DUT can operate normally under different configurations and providing accurate parameters for excitation generation.

[0036] After receiving configuration parameters from the data configuration unit, the data generation unit automatically generates stimulus content that meets the requirements of the module under test (DUT) and constructs corresponding stimulus signals based on these configurations. These stimulus signals will be used as input signals for the DUT and provided to the DUT through the testbench. The stimulus generation process is automated, avoiding the tedious manual settings, improving efficiency, and ensuring the consistency and accuracy of the test.

[0037] The stimulus database outputs stimulus content through a parameter interface. The module under test (DUT) defines the required configuration parameters through this parameter interface, and each stimulus content has a corresponding parameter interface; different stimulus contents correspond to different parameter interfaces. Generally, the parameter interface is defined using Verilog or System Verilog, allowing users to flexibly set different simulation parameters and automatically generate stimulus signals that meet these configuration requirements. Each parameter has a clear definition and type in its corresponding parameter interface. All these parameters are defined through the parameter interface before simulation, ensuring that the simulation tool can recognize and utilize these parameters to generate appropriate stimulus content. Users can quickly and accurately generate stimulus content by setting the corresponding parameter interface according to different simulation task requirements.

[0038] During simulation, the specific requirements of the simulation task are specified by filling in the parameter interface, allowing for rapid configuration of different simulation environments without the need to manually write complex excitation signal code. After filling in the parameter interface, the platform will generate the corresponding excitation content and excitation signals based on the configured parameters. For example, based on the set bandwidth and sampling rate, the platform will automatically calculate the required signal timing, data format, etc., thereby generating excitation content that matches the module under test. Automated generation of excitation signals reduces human intervention and avoids errors and inefficiencies caused by manual coding.

[0039] The configured parameter interface provides the necessary data source for the stimulus database, ensuring that the module under test receives the correct input signals under different simulation tasks. This flexible configuration and automated generation mechanism improves simulation efficiency and reduces the workload of configuring each simulation task. The stimulus database can provide highly customized, compliant stimulus signals for each simulation task.

[0040] The module under test (DUT) is responsible for performing specific functions or tasks, while the data conversion module converts the output of the DUT to a different format, ensuring the standardization of test results and compatibility with subsequent processing. The two work closely together, achieving the verification of the DUT and the effective utilization of the results through precise input and output management.

[0041] The module under test (DUT) is typically written by developers using hardware description languages ​​such as Verilog or System Verilog to implement specific functions or logic, such as signal processing, data computation, or control tasks. In simulation testing, the DUT receives stimulus signals from the platform's stimulus database, performs corresponding tasks based on changes in these stimulus signals, and ultimately generates an output signal.

[0042] The data conversion module processes the output signal, converting it into a preset format response according to conversion rules, ensuring that simulation results can be stored and processed in a consistent and standardized manner. This data conversion module receives the raw output signal generated by the module under test and converts it into the required file format according to simulation needs.

[0043] The data conversion module includes a data format conversion unit and a file import / export unit. The data format conversion unit converts the output signal's data format into a preset response format; the file import / export unit converts the output signal into a preset file format response. This typically involves converting complex binary or digital signals into easily readable or subsequently processed formats, such as text files, CSV files, or binary files. The converted response content can be easily used for result analysis, report generation, or further processing compatible with other systems. The data conversion module ensures the usability of test results and cross-platform compatibility, avoiding problems caused by inconsistent data formats.

[0044] Furthermore, multiple modules under test (DUTs) can be configured to perform multiple simulation tests simultaneously. During simulation, the stimulus database generates independent stimulus signals for each DUT and transmits them to the corresponding module through a parameter interface. Each DUT executes its simulation task based on its own input signal and generates an output signal. This platform can flexibly configure different simulation parameters for multiple DUTs, ensuring that each module can run in an independent and accurate test environment without interfering with each other.

[0045] Based on the same inventive idea, such as Figure 3 As shown, this application provides a testbench simulation verification system, the system comprising:

[0046] The testbench simulation verification platform described above;

[0047] The module under test performs simulation testing based on the excitation content and generates an output signal.

[0048] This invention significantly improves the efficiency and flexibility of simulation testing through the collaborative work of an incentive database and a data conversion module. The incentive database automatically determines and outputs corresponding incentive content based on the parameter configuration instructions of the module under test (DUT), ensuring that each simulation task accurately generates the required incentive data and avoiding the tedious work of repeatedly writing incentive signals. Simultaneously, the data conversion module converts the DUT's output signals into standard format response content according to conversion rules, making the test results more standardized, easier to store, and easier to analyze. This invention simplifies the simulation process, reduces manual intervention, improves the automation and accuracy of simulation testing, and effectively enhances testing efficiency and reusability.

[0049] The system's processing method can be referred to the description of the above method, and will not be repeated here.

[0050] The present invention also provides an apparatus, which may include: a memory storing executable program code;

[0051] A processor coupled to memory;

[0052] A transceiver used to communicate with other devices or communication networks and to receive or send network messages;

[0053] A bus used to connect memory, processor, and transceiver for internal communication.

[0054] The transceiver receives messages transmitted over the network and passes them to the processor via the bus. The processor then calls the executable program code stored in the memory via the bus to process the messages and passes the processing results back to the transceiver via the bus for transmission, thereby implementing the method provided in this application embodiment.

[0055] This application also provides a non-transitory machine-readable storage medium storing an executable program. When the executable program is run by a processor, the processor performs the processing method provided in the above embodiments.

[0056] This invention discloses a computer-readable storage medium storing a computer program for electronic data interchange, wherein the computer program causes a computer to perform the described methods.

[0057] This invention discloses a computer program product including a non-transitory computer-readable storage medium storing a computer program operable to cause a computer to perform the described method.

[0058] The embodiments described above are merely illustrative. The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical modules; that is, they may be located in one place or distributed across multiple network modules. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0059] Through the detailed description of the above embodiments, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, including read-only memory (ROM), random access memory (RAM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), one-time programmable read-only memory (OTPROM), electrically-Erasable Programmable Read-Only Memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, disk storage, magnetic tape storage, or any other computer-readable medium that can be used to carry or store data.

[0060] Finally, it should be noted that the embodiments disclosed in this invention are merely preferred embodiments of this invention and are only used to illustrate the technical solutions of this invention, not to limit it. Although this invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this invention.

Claims

1. A testbench simulation verification platform, characterized in that, include: The stimulus database collects and stores simulation source data; Upon receiving a parameter configuration instruction from the module under test, the excitation content corresponding to the configuration parameters is determined, and the excitation content is output through the parameter interface; the excitation content is used for simulation testing of the module under test. The incentive database includes a data splitting unit, a data configuration unit, and a data generation unit. The data splitting unit is used to split the parameter configuration instructions of the module under test. The data splitting unit determines the configuration parameters of each module under test according to the parameter configuration instructions, and decomposes the input signal of the module under test into independent, easily manageable small units; The data configuration unit configures each split configuration parameter independently, configures different parameters for different simulation tasks, and sets the required working conditions for each module under test; After receiving the configuration parameters from the data configuration unit, the data generation unit automatically generates the excitation content that meets the requirements of the module under test and constructs the corresponding excitation signal based on these configurations. The data conversion module acquires the output signal of the module under test and converts the output signal into a response content in a preset format according to the conversion rules.

2. The testbench simulation verification platform according to claim 1, characterized in that, The excitation content includes data types and data parameters. The data types include single tone, wide spectrum, and constant. The data parameters include bandwidth, sampling rate, number of antennas, and timing data.

3. The testbench simulation verification platform according to claim 1, characterized in that, The data generation unit determines the incentive content through one or more of the following methods: Different configuration parameters can be defined as macros or parameters using System Verilog or Verilog, and corresponding stimulus data can be generated based on the configuration.

4. The testbench simulation verification platform according to claim 3, characterized in that, The module under test defines the required configuration parameters through the parameter interface, and each of the stimulus contents sets a corresponding parameter interface.

5. The testbench simulation verification platform according to claim 4, characterized in that, The data conversion module includes a data format conversion unit and a file import / export unit. The data format conversion unit is used to convert the data format of the output signal into response content in a preset data format. The file import / export unit is used to convert the output signal into response content in a preset file format.

6. The testbench simulation verification platform according to claim 5, characterized in that, The response content includes data format and file format. The data format includes data base, and the file format includes txt and xlsx formats.

7. The testbench simulation verification platform according to claim 3, characterized in that, The incentive database and response content are written in Verilog or System Verilog.

8. A testbench simulation verification system, characterized in that, The system includes: A testbench simulation verification platform as described in any one of claims 1-7; The module under test performs simulation testing based on the excitation content and generates an output signal.

Images