Data transmission completion status notification method, system, device, medium and product

Abstract

The application discloses a data transmission completion state notification method, system, device, medium and product, and particularly relates to the technical field of data transmission, and is applied to the host end of a heterogeneous acceleration system and comprises the following steps: acquiring the load condition of the host end in the heterogeneous acceleration system; determining a target reporting mode of a direct memory access transmission completion state based on the load condition, wherein the target reporting mode is an interrupt reporting mode or a polling reporting mode; and notifying the target reporting mode to the device end of the heterogeneous acceleration system, so that the device end notifies the host end of the direct memory access transmission completion state according to the target reporting mode when the device end completes the direct memory access transmission. The application can solve the problem that the host end cannot be notified in real time when data transmission is completed, thereby improving the real-time performance of data transmission.

Description

Technical Field

[0001] This application relates to the field of data transmission completion status notification technology, and in particular to a data transmission completion status notification method, system, device, medium and product. Background Technology

[0002] In the relevant data transmission completion status notification scheme, for interrupt triggering, the processor on the board configures the minimum time interval and minimum number interval for interrupt triggering based on its own computing load. Since the time interval and minimum number of interrupt reporting are set, the host cannot be notified in real time when data transmission is completed, resulting in poor real-time performance in data transmission. Summary of the Invention

[0003] This application provides a method, system, device, medium, and product for notifying data transmission completion status, to at least solve the problem in related technologies where the inability to notify the host in real time when data transmission is completed, due to the setting of time intervals and minimum numbers for interrupt reporting, results in poor real-time performance in data transmission.

[0004] This application provides a data transmission completion status notification method for the host side of a heterogeneous acceleration system, including:

[0005] Obtain the load status of the host in the heterogeneous acceleration system;

[0006] Based on the load conditions, determine the target reporting method for the completion status of direct memory access transfers;

[0007] The target reporting method is notified to the device side of the heterogeneous acceleration system so that when the device side completes the direct memory access transfer, it notifies the host side of the direct memory access transfer completion status according to the target reporting method, which can be interrupt reporting method or polling reporting method.

[0008] Optionally, based on load conditions, the target reporting method for the direct memory access transfer completion status is determined, including:

[0009] In response to a busy load condition, the interrupt reporting method is determined to be the target reporting method for the direct memory access transfer completion status.

[0010] In response to whether the load is idle or the target data is being transmitted, the polling reporting method is determined to be the target reporting method of direct memory access transmission completion status, and the target data is data whose length is less than a preset length threshold.

[0011] Optionally, obtain the load information of the host side in the heterogeneous acceleration system, including:

[0012] Obtain the first resource usage time of the processor in the host at the first sampling time and the second resource usage time at the second sampling time;

[0013] Based on the first resource occupancy time and the second resource occupancy time, determine the comprehensive occupancy time change value and idle state time change value of the processor from the first sampling time to the second sampling time.

[0014] Based on the changes in overall occupied time and idle time, the resource occupancy weight of the processor in the host is determined;

[0015] The resource usage weight is compared with the target weight, and the load on the host is determined based on the comparison result.

[0016] Optionally, based on the combined changes in occupied time and idle time, the resource usage weight of the processor in the host is determined, including:

[0017] Based on the combined changes in occupied time and idle time, determine the changes in the processor's busy time between the first sampling time and the second sampling time.

[0018] The resource usage weight of the processor in the host is determined by the ratio of the change in busy time to the change in total usage time.

[0019] Optionally, after determining the target reporting method for the direct memory access transfer completion status based on the load conditions, the method provided in this disclosure includes:

[0020] Configure the flag information for the reporting method according to the target reporting method;

[0021] The target reporting method is communicated to the devices in the heterogeneous acceleration system, including:

[0022] The flag information of the identification reporting method is notified to the device side of the heterogeneous acceleration system.

[0023] This application also provides a data transmission completion status notification method, applied to the device side of a heterogeneous acceleration system, including:

[0024] In response to the completion of direct memory access transfer, the target reporting method for reporting the completion status of direct memory access transfer to the host of the heterogeneous acceleration system is obtained. The target reporting method for reporting the completion status of direct memory access transfer to the host of the heterogeneous acceleration system is different depending on the load of the host. The target reporting method is either interrupt reporting or polling reporting.

[0025] The host is notified of the direct memory access transfer completion status based on the target reporting method.

[0026] Optionally, the target reporting method for reporting the direct memory access transfer completion status to the host side of the heterogeneous acceleration system includes:

[0027] Obtain the flag information for the flag reporting method;

[0028] Parse the value of the flag information to obtain the target reporting method for reporting the direct memory access transfer completion status to the host of the heterogeneous acceleration system.

[0029] Optionally, the direct memory access transfer completion status is notified to the host based on the target reporting method, including:

[0030] In response to the target reporting method being interrupt reporting, an interrupt signal is sent to the host. The interrupt signal is used to notify the host of the completion status of the direct memory access transfer and to trigger the host to call the interrupt handling function corresponding to the interrupt signal.

[0031] In response to the target reporting method being polling, status update information is written to the storage area shared by the host and the device, so that the host can detect it through polling. The status update information is used to notify the host of the completion status of direct memory access transmission.

[0032] Optionally, the shared storage area between the host and the device includes multiple storage blocks. Writing status update information to this shared storage area includes:

[0033] Obtain the task identifier for the direct memory access transfer task;

[0034] Based on the task identifier, determine the target memory block corresponding to the direct memory access transfer task from multiple memory blocks;

[0035] Write status update information to the target storage block.

[0036] Optionally, the status update information includes at least a direct memory access transfer completion status identifier and metadata associated with the direct memory access transfer task. Writing the status update information to the target storage block includes:

[0037] Write a direct memory access transfer completion status flag to the flag bits in the target memory block, and write metadata associated with the direct memory access transfer task to the data bits in the target memory block. The direct memory access transfer completion status flag is used to indicate that the direct memory access transfer is complete, and the metadata associated with the direct memory access transfer task includes at least the data transfer length and the data transfer task sequence number.

[0038] This application also provides a data transmission completion status notification system. The system includes a host end and a device end. The host end and the device end are connected by a high-speed bus interconnected via peripheral components. The host end includes an acquisition module and a reporting method determination module. The device end includes a direct storage access control module.

[0039] The acquisition module is configured to acquire the load status of the host in the heterogeneous acceleration system;

[0040] The reporting method determination module is configured to determine the target reporting method based on the load condition for the completion status of direct memory access transfer; and to notify the device side of the heterogeneous acceleration system of the target reporting method so that when the device side completes the direct memory access transfer, it notifies the host side of the completion status of the direct memory access transfer according to the target reporting method. The target reporting method is either interrupt reporting or polling reporting.

[0041] The direct memory access control module is configured to, in response to the completion of a direct memory access transfer, obtain a target reporting method for reporting the completion status of the direct memory access transfer to the host of the heterogeneous acceleration system, and notify the host of the completion status of the direct memory access transfer based on the target reporting method.

[0042] Optionally, the direct memory access control module includes a data transmission module, a transmission status reporting module, and an interrupt generation control module:

[0043] The data transmission module is configured to control the direct memory access transfer device to complete data transmission;

[0044] The transmission status reporting module is configured to, in response to the completion of direct memory access transmission, obtain the target reporting method for reporting the completion status of direct memory access transmission to the host of the heterogeneous acceleration system, and notify the host of the completion status of direct memory access transmission based on the target reporting method.

[0045] The interrupt control module is configured to send an interrupt signal to the host in response to the target reporting mode being interrupt reporting mode. The interrupt signal is used to notify the host of the direct memory access transfer completion status and trigger the host to call the interrupt handling function corresponding to the interrupt signal.

[0046] This application also provides a data transmission completion status notification device, including:

[0047] The acquisition unit is used to acquire the load status of the host in the heterogeneous acceleration system;

[0048] The determination unit is used to determine the target reporting method for the direct memory access transfer completion status based on the load conditions.

[0049] The notification unit is used to notify the device side of the heterogeneous acceleration system of the target reporting method, so that when the device side completes the direct memory access transfer, it notifies the host side of the direct memory access transfer completion status according to the target reporting method, which is either interrupt reporting or polling reporting.

[0050] This application also provides a data transmission completion status notification device, including:

[0051] The acquisition unit is used to acquire the target reporting method for reporting the completion status of direct memory access transfer to the host of the heterogeneous acceleration system in response to the completion of direct memory access transfer. The target reporting method for reporting the completion status of direct memory access transfer to the host of the heterogeneous acceleration system is different depending on the load of the host. The target reporting method is either interrupt reporting or polling reporting.

[0052] The notification unit is used to notify the host of the direct memory access transfer completion status based on the target reporting method.

[0053] This application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for executing the computer program to implement the steps of any one of the methods in the first or second aspect described above.

[0054] This application also provides a computer-readable storage medium storing a computer program, wherein when executed by a processor, the computer program implements the steps of any one of the methods in the first or second aspect described above.

[0055] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any one of the methods in the first or second aspect described above.

[0056] The data transmission completion status notification method, electronic device, medium, and product provided in this application include: acquiring the load status of the host in a heterogeneous acceleration system; determining a target reporting method for the direct memory access transmission completion status based on the load status; and notifying the target reporting method to the device in the heterogeneous acceleration system, so that when the device completes the direct memory access transmission, it notifies the host of the direct memory access transmission completion status according to the target reporting method, which can be an interrupt reporting method or a polling reporting method. This solves the problem of poor real-time performance in data transmission due to the inability to notify the host in real time when data transmission is complete, thus improving the real-time performance of data transmission completion status notification. Attached Figure Description

[0057] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0058] Figure 1 This is a schematic diagram of a data transmission completion status notification method in a related scheme provided in an embodiment of this application;

[0059] Figure 2 A flowchart illustrating a data transmission completion status notification method provided in an embodiment of this application;

[0060] Figure 3 A flowchart illustrating another data transmission completion status notification method provided in an embodiment of this application;

[0061] Figure 4 This is a schematic diagram of a consistent memory structure provided in an embodiment of this application;

[0062] Figure 5 A flowchart illustrating another data transmission completion status notification method provided in an embodiment of this application;

[0063] Figure 6 This is a schematic diagram of the structure of a data transmission completion status notification system provided in an embodiment of this application;

[0064] Figure 7 This is a schematic diagram of the structure of a direct memory access controller provided in an embodiment of this application;

[0065] Figure 8 A schematic diagram of a data transmission completion status notification device provided in an embodiment of this application;

[0066] Figure 9 A schematic diagram of another data transmission completion status notification device provided in an embodiment of this application. Detailed Implementation

[0067] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0068] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0069] To facilitate a better understanding of the technical solutions described in the embodiments of this disclosure by those skilled in the art, the technical terms in the embodiments of this disclosure are explained as follows before introducing the embodiments of this disclosure.

[0070] Central Processing Unit (CPU): Responsible for operating system operation, task scheduling, driver management, and application logic control.

[0071] Double Data Rate (DDR) synchronous dynamic random access memory is a data storage medium shared by the CPU and the device.

[0072] Direct Memory Access (DMA): A hardware data transfer mechanism that allows peripherals to bypass the CPU and directly read and write host memory (such as DDR) for efficient data transfer and reduced CPU load.

[0073] High-speed peripheral bus (Peripheral Component Interconnect Express, PCIe): A high-speed interconnect channel between the host and the device.

[0074] Input / Output Memory Management Unit (IOMMU): A hardware address translation and protection unit located between the CPU and PCIe devices, providing virtual address to physical address mapping for the devices.

[0075] With the development of Artificial Intelligence (AI) technology, the computing power of AI servers built on heterogeneous architectures such as PCIe-based CPU + Graphics Processing Unit (GPU), CPU + General-Purpose Computing on Graphics Processing Units (GPGPU), and CPU + Field-Programmable Gate Array (FPGA) accelerators is gradually improving. In the field of heterogeneous data transmission, DMA, as a hardware mechanism that can efficiently transfer data blocks between memory and peripherals without CPU intervention, is widely used in heterogeneous acceleration, such as data transmission during AI training and data forwarding by smart network interface cards (NICs). DMA interrupts, as the core mechanism for collaboration between PCIe devices and the CPU, enable efficient, reliable, and parallel interaction between the host and heterogeneous devices, and are the cornerstone of high-performance I / O in modern computer systems.

[0076] As a heterogeneous system, the accelerator needs to report a completion message to the host after completing its computation task. The traditional reporting method is interrupt reporting, such as PCIe Message Signaled Interrupts (MSI) interrupts. However, very frequent interrupt reporting can affect system performance; untimely interrupt reporting can affect the system's real-time performance.

[0077] like Figure 1 As shown, Figure 1This diagram illustrates a data transmission completion status notification method provided in an embodiment of this application. Centered on the scheduling control unit 110, it receives instructions through a configuration interface and coordinates the entire system's workflow. The cache configuration unit 120 manages the data buffering strategy, while the data transfer unit 130 is dedicated to actual data transmission and reception via the PCIe link and interfaces with external data interfaces. When data transmission is complete, the command word completion feedback unit 150 reports the status to the scheduling control unit, thereby triggering the interrupt generator 140 to send an interrupt signal externally through the interrupt interface. For interrupt triggering, the CPU on the board can configure the minimum time interval and minimum number interval for interrupt triggering based on its computational load. The minimum time interval for interrupt triggering refers to the time interval between interrupts after each trigger, during which interrupts are recorded until the time interval is met. The minimum number interval for interrupt triggering refers to the accumulation of a sufficient number of interrupts before triggering the next interrupt. The minimum time interval and minimum number can be used to control the frequency of interrupt generation by the DMA controller. While this solution reduces the transmission overhead between the host and PCIe and improves resource utilization, it suffers from poor performance in real-time data transmission because it sets the time interval and minimum number of interrupt reporting intervals. This results in the failure to report in a timely manner when data transmission is completed but before the interrupt time has elapsed, making it unsuitable for current scenarios with high real-time requirements.

[0078] In the relevant data transmission completion status notification scheme, for interrupt triggering, the processor on the board configures the minimum time interval and minimum number interval for interrupt triggering based on its own computing load. Since the time interval and minimum number of interrupt reporting are set, the host cannot be notified in real time when data transmission is completed, resulting in poor real-time performance in data transmission.

[0079] To address the technical issues in related solutions, this method obtains the load information of the host in the heterogeneous acceleration system. Based on the load information, a target reporting method for the completion status of direct memory access (DMI) transfers is determined. This target reporting method is then communicated to the devices in the heterogeneous acceleration system, enabling them to notify the host of the DMI transfer completion status according to the target reporting method, which can be either interrupt-based or polling-based. This solves the problem of poor real-time data transmission performance caused by the inability to notify the host in real time upon data transmission completion, thus improving the real-time performance of DMI completion status notifications.

[0080] The data transmission completion status notification method provided in this disclosure can be applied to scenarios such as smart network cards, AI acceleration, cloud storage, high-performance computing, and edge computing. The execution subject of this method can be a data transmission system including the host and the device.

[0081] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0082] Figure 2 This is a flowchart illustrating a data transmission completion status notification method provided in an embodiment of this disclosure.

[0083] like Figure 2 As shown, the data transmission completion status notification method, applied to the host side of a heterogeneous acceleration system, includes:

[0084] Step 201: Obtain the load status of the host in the heterogeneous acceleration system;

[0085] In some embodiments, a heterogeneous acceleration system is a computing system in which a general-purpose processor and a dedicated hardware accelerator work together. They collaborate via high-speed interconnects, such as PCIe communication, to improve performance. In a heterogeneous acceleration system, the host side typically refers to the general-purpose processor running an operating system, such as a CPU, which is responsible for task scheduling, resource management, driver execution, and application logic control. The device side refers to the acceleration hardware within the heterogeneous system, such as DMA and FPGAs, which are responsible for performing high-throughput or low-latency data transfer or computation tasks.

[0086] In some embodiments, load conditions refer to the current resource usage pressure on the host side, which typically includes: CPU utilization, interrupt handling latency, memory bandwidth usage, system average load, and in this application, mainly refers to the idle or busy level of the CPU.

[0087] In some embodiments, the load on the host side of a heterogeneous acceleration system can be obtained by reading CPU load metrics provided by the operating system kernel, such as idle time in / proc / stat, get_cpu_idle_time(), etc.

[0088] In some embodiments, the load on the host side of the heterogeneous acceleration system can also be obtained by sampling the proportion of idle instructions in the CPU cycle through the performance monitoring unit.

[0089] Step 202: Based on the load situation, determine the target reporting method for the direct memory access transfer completion status. The target reporting method is either interrupt reporting or polling reporting.

[0090] In some embodiments, since the load on the host has dynamic characteristics, it can be divided into two core types: idle state and busy state. Therefore, different transmission completion status reporting methods need to be matched under different load scenarios: when the host is in an idle state, the polling reporting method can reduce the system interrupt handling overhead; while when the host is in a busy state, such as when the CPU resource utilization exceeds the threshold or is processing a critical task, the interrupt reporting method can ensure the real-time response to the transmission completion event, and can achieve a balance between system resource utilization and event response real-time performance.

[0091] In some embodiments, the communication strategy for the device to report the completion of DMA transfer to the host includes two types: interrupt reporting: the device triggers a hardware interrupt, forcing the CPU to respond; polling reporting: the device only updates the status flags in the shared memory, which are checked periodically by the host.

[0092] Step 203: Notify the device side of the heterogeneous acceleration system of the target reporting method so that when the device side completes the direct memory access transfer, it notifies the host side of the direct memory access transfer completion status according to the target reporting method.

[0093] In some embodiments, the target reporting method can be notified to the device of the heterogeneous acceleration system by sending an instruction to the device, or the target reporting method can be notified to the device of the heterogeneous acceleration system by writing the target reporting method into a shared flag.

[0094] By acquiring the load information of the host in the heterogeneous acceleration system, and based on the load, determining the target reporting method for the direct memory access (DMI) transfer completion status, the target reporting method is communicated to the device in the heterogeneous acceleration system. This ensures that when a device completes a DMI transfer, it notifies the host of the DMI transfer completion status according to the target reporting method, which can be either interrupt-based or polling-based. Using interrupts when the host is under high load ensures timely response to critical tasks; switching to polling when the host is idle avoids interrupt storms caused by numerous small packet DMA operations. This addresses the problem of poor real-time data transmission performance caused by the inability to notify the host in real time upon data transmission completion, thus improving the real-time performance of data transmission completion status notifications.

[0095] In some embodiments, the target reporting method for the direct memory access transfer completion status is determined based on the load condition, including:

[0096] In response to a busy load condition, the interrupt reporting method is determined to be the target reporting method for the direct memory access transfer completion status.

[0097] In response to whether the load is idle or the target data is being transmitted, the polling reporting method is determined to be the target reporting method of direct memory access transmission completion status, and the target data is data whose length is less than a preset length threshold.

[0098] In some embodiments, a busy load indicates a heavy workload, while an idle load indicates that the CPU has sufficient computing resources.

[0099] In some embodiments, data with a length lower than a preset length threshold indicates that the DMA data to be transmitted is small packet data. The preset length threshold can be determined based on hardware characteristics, such as cache line size, PCIe TLP payload, or application scenarios, such as network packet settings. Preferably, the preset length threshold is 256 bytes.

[0100] In some embodiments, if a large number of small data packets are transmitted using the interrupt reporting method, a large number of interrupts are also required, which will bring significant system overhead. Specifically, interrupt storms will cause a surge in CPU resource utilization and frequent context switching, thereby reducing the overall data processing throughput. Among these, a large number of small data packets include microservice remote procedure calls (RPC) and database requests.

[0101] In some embodiments, the interrupt reporting method is that after the device completes the DMA transfer, it actively sends a hardware interrupt signal, such as MSI / MSI-X, to the host, forcing the CPU to suspend the current task and immediately execute the interrupt handling function to respond to the completion event, thereby reducing latency and improving timeliness.

[0102] In some embodiments, after the DMA transfer is completed, the device in the polling reporting method only updates the completion status flag in the shared memory. If the completion flag is set, no interrupt is triggered. The host can detect whether the process is complete by periodically or on demand actively reading the flag, which can reduce interrupt overhead and is suitable for batch processing.

[0103] In some embodiments, in response to a busy load condition, the interrupt reporting method is determined to be the target reporting method for the direct memory access transmission completion status; in response to an idle load condition or the transmission of target data, the polling reporting method is determined to be the target reporting method for the direct memory access transmission completion status. The target data is data with a length lower than a preset length threshold. The reporting method on the device side is dynamically determined by the host side based on the real-time load and data characteristics, thereby realizing refined and scenario-based adaptive control of the DMA completion reporting method.

[0104] In some embodiments, obtaining the load status of the host in a heterogeneous acceleration system includes:

[0105] Obtain the first resource usage time of the processor in the host at the first sampling time and the second resource usage time at the second sampling time;

[0106] In some embodiments, the first sampling time and the second sampling time are two consecutive or fixed-time intervals, used to form a sampling window to collect the processor state. The interval can be from 1 millisecond to 100 milliseconds. The first resource occupation time is the cumulative time when the processor is in an idle state and a non-idle state at the first sampling time, and the second resource occupation time is the cumulative time when the processor is in an idle state and a non-idle state at the second sampling time. The first resource occupation time and the second resource occupation time include user mode, kernel mode, interrupt handling, and other times.

[0107] In some embodiments, the first resource usage time of the processor at the first sampling time and the second resource usage time at the second sampling time are obtained by summing the fields such as user, nice, system, idle, and irq from the cpu line in the operating system / proc / stat.

[0108] Based on the first resource occupancy time and the second resource occupancy time, determine the comprehensive occupancy time change value and idle state time change value of the processor from the first sampling time to the second sampling time.

[0109] In some embodiments, the overall occupied time change value is the increment of processor occupied time between the first sampling time and the second sampling time, that is, the increment of the second resource occupied time to the first resource occupied time; the idle state time change value is the increment of processor idle time between the first sampling time and the second sampling time, that is, the increment of the idle field value at the first sampling time to the idle field value at the second sampling time.

[0110] In some embodiments, processor occupancy time includes the occupancy time indicated by the user field, nice field, system field, idle field, iowait field, irq field, softirq field, and steal field.

[0111] Based on the changes in overall occupied time and idle time, the resource occupancy weight of the processor in the host is determined;

[0112] In some embodiments, determining the resource usage weight of the processor in the host based on the combined occupied time change value and the idle state time change value includes:

[0113] Based on the combined changes in occupied time and idle time, determine the changes in the processor's busy time between the first sampling time and the second sampling time.

[0114] The resource usage weight of the processor in the host is determined by the ratio of the change in busy time to the change in total usage time.

[0115] In some embodiments, the difference between the combined occupied time change value and the idle state time change value is determined as the processor's busy state time change value between the first sampling time and the second sampling time.

[0116] In some embodiments, the ratio of the change in busy time to the change in total occupied time is used to measure CPU utilization within the sampling time window.

[0117] In some embodiments, with the total occupied time change value as total_diff and the idle state time change value as idle_diff, the processor's resource occupancy weight is (total_diff-idle_diff) / total_diff×100.0}, where total_diff-idle_diff is the processor's busy state time change value.

[0118] The resource usage weight is compared with the target weight, and the load on the host is determined based on the comparison result.

[0119] In some embodiments, the target weight is a preset baseline value used to determine the processor's load status. The target weight may include a target occupied weight and a target idle weight.

[0120] In some embodiments, when the resource occupancy weight is greater than the target occupancy weight, it indicates that the processor is in a busy state. When the resource occupancy weight is lower than the target occupancy weight, the idle utilization rate (the difference between 1 and the CPU utilization rate) is determined. When the idle utilization rate is greater than the target idle weight, it indicates that the processor is in an idle state.

[0121] For example, if the CPU utilization rate on the host is less than 70%, the host is determined to be in a busy state; if the CPU idle rate is greater than 30%, the host is determined to be in an idle state.

[0122] In some embodiments, compared to simply using instantaneous CPU utilization, the two-time-difference calculation eliminates the absolute time accumulation error and better reflects short-term dynamic load trends.

[0123] In some embodiments, after determining the target reporting method for the direct memory access transfer completion status based on the load condition, the data transfer completion status notification method includes:

[0124] Configure the flag information for the reporting method according to the target reporting method;

[0125] The target reporting method is communicated to the devices in the heterogeneous acceleration system, including:

[0126] The flag information of the identification reporting method is notified to the device side of the heterogeneous acceleration system.

[0127] In some embodiments, the flag information identifying the reporting method is a control signal or data field that can be quickly parsed by the device, used to clearly indicate which reporting method should be used for this DMA task.

[0128] In some embodiments, the flag information identifying the reporting method can be a single flag bit, such as the interrupt enable flag bit on the host side. Specifically, if the target reporting method is interrupt reporting, the interrupt enable flag bit can be set to 1; if the target reporting method is polling reporting, the interrupt enable flag bit can be set to 0. Accordingly, the value of the interrupt enable flag bit is notified to the device side of the heterogeneous acceleration system.

[0129] In some embodiments, the flag information identifying the reporting method can also be an enumeration value, such as uint8_t mode=0x01 indicating polling. Accordingly, the enumeration value is notified to the device side of the heterogeneous acceleration system.

[0130] In some embodiments, the flag information identifying the reporting method can also be a specific position in the control register, such as bit[3]=1 indicating that polling mode is enabled. Accordingly, the value of the specific position in the register is notified to the device side of the heterogeneous acceleration system.

[0131] In some embodiments, the flag information of the identification reporting method can be notified to the device side of the heterogeneous acceleration system through a shared storage area between the device side and the host side.

[0132] In some embodiments, the flag information identifying the reporting method can also be sent to the device side of the heterogeneous acceleration system via an instruction that includes flag information identifying the reporting method.

[0133] Figure 3 This is a flowchart illustrating a data transmission completion status notification method provided in an embodiment of this disclosure.

[0134] like Figure 3 As shown, the data transmission completion status notification method, applied to the device side of a heterogeneous acceleration system, includes:

[0135] Step 301: In response to the completion of direct memory access transfer, obtain the target reporting method for reporting the completion status of direct memory access transfer to the host of the heterogeneous acceleration system. The target reporting method for reporting the completion status of direct memory access transfer to the host of the heterogeneous acceleration system is different depending on the load of the host. The target reporting method is interrupt reporting method or polling reporting method.

[0136] Step 302: Notify the host of the direct memory access transfer completion status based on the target reporting method.

[0137] In some embodiments, Direct Memory Access Transfer Complete means that the device sends a message to the host indicating that the DMA has been successfully completed.

[0138] In some embodiments, after each DMA transfer is completed, the device does not use a fixed reporting method, but first obtains the target reporting method pre-configured by the host, and then executes the notification according to that method.

[0139] In some embodiments, the target reporting method for reporting the direct memory access transfer completion status to the host side of the heterogeneous acceleration system can be obtained by parsing the value of the flag information of the reporting method.

[0140] In some embodiments, by determining a specific reporting method based on the host load to notify the host of the direct memory access transfer completion status, the performance bottleneck of the traditional fixed reporting mode under mixed loads is resolved.

[0141] In some embodiments, obtaining a target reporting method for reporting the direct memory access transfer completion status to the host side of the heterogeneous acceleration system includes:

[0142] Obtain the flag information for the flag reporting method;

[0143] Parse the value of the flag information to obtain the target reporting method for reporting the direct memory access transfer completion status to the host of the heterogeneous acceleration system.

[0144] In some embodiments, after the DMA transfer is completed, the device can obtain the flag information of the reporting method written by the host by reading the interrupt enable flag bit of the host.

[0145] In some embodiments, after the DMA transfer is completed, the device can also obtain the flag information of the flag reporting method written by the host by reading the shared storage area of ​​the device and the host.

[0146] In some embodiments, the target reporting method for reporting the direct memory access transfer completion status to the host side of the heterogeneous acceleration system is obtained based on the value of the flag information.

[0147] In some embodiments, notifying the host of the direct memory access transfer completion status based on the target reporting method includes:

[0148] In response to the target reporting method being interrupt reporting, an interrupt signal is sent to the host. The interrupt signal is used to notify the host of the completion status of the direct memory access transfer and to trigger the host to call the interrupt handling function corresponding to the interrupt signal.

[0149] In response to the target reporting method being polling, status update information is written to the storage area shared by the host and the device, so that the host can detect it through polling. The status update information is used to notify the host of the completion status of direct memory access transmission.

[0150] In some embodiments, the interrupt signal is a hardware electrical signal initiated by the device, such as an MSI or MSI-X interrupt message.

[0151] In some embodiments, the interrupt handler function is a callback function pre-registered with the operating system by the host driver. When an interrupt signal arrives, the CPU suspends the current task and jumps to execute the function to handle DMA completion events, such as releasing the buffer or waking up application threads.

[0152] In some embodiments, the storage area shared by the host and the device is typically a segment of physical memory that can be accessed by both the host CPU and the device DMA engine. This can be achieved through coherent DMA memory, a PCIe BAR-mapped memory-mapped I / O (MMIO) region, or other cache coherent interconnect memory, used to transmit control commands, data descriptors, or status information.

[0153] In some embodiments, host-side polling detection refers to the host periodically or on demand reading state update information from shared storage to avoid interruption overhead.

[0154] In some embodiments, the storage area shared by the host and the device includes multiple storage blocks. Writing status update information to the storage area shared by the host and the device includes:

[0155] Obtain the task identifier for the direct memory access transfer task;

[0156] In some embodiments, a direct memory access transfer task is a complete DMA operation request, including information such as source address, destination address, data length, and task identifier, which is typically submitted by the host driver to the device for execution.

[0157] In some embodiments, the task identifier is a number or index that uniquely identifies a DMA transfer task and is used to associate the task context between the host and the device.

[0158] In some embodiments, each storage block is of fixed size and corresponds one-to-one with a task identifier or descriptor index, used to record the completion status of a specific DMA task.

[0159] Based on the task identifier, determine the target memory block corresponding to the direct memory access transfer task from multiple memory blocks;

[0160] Write status update information to the target storage block.

[0161] In some embodiments, the target storage block is the storage block that uniquely corresponds to the task identifier of the current DMA task among a plurality of storage blocks, and the device writes the completion status of this transmission into the target storage block.

[0162] In some embodiments, by obtaining the task identifier of the direct memory access transfer task, determining the target storage block corresponding to the direct memory access transfer task from multiple storage blocks based on the task identifier, and writing state update information into the target storage block, the mutual overwriting or competition of multiple task states can be avoided, thereby improving reliability.

[0163] In some embodiments, the status update information includes at least a direct memory access transfer completion status identifier and metadata associated with the direct memory access transfer task. Writing the status update information to the target memory block includes:

[0164] Write a direct memory access transfer completion status flag to the flag bits in the target memory block, and write metadata associated with the direct memory access transfer task to the data bits in the target memory block. The direct memory access transfer completion status flag is used to indicate that the direct memory access transfer is complete, and the metadata associated with the direct memory access transfer task includes at least the data transfer length and the data transfer task sequence number.

[0165] In some embodiments, the direct memory access transfer completion status flag refers to the specific value of the write flag, such as 1 or the DONE enumeration, which is used to explicitly indicate that the current DMA transfer has been successfully completed; the data transfer length refers to the number of bytes actually successfully transferred, which may be less than the requested length; and the data transfer task sequence number refers to a globally unique or session-unique task number used to distinguish different tasks.

[0166] In some embodiments, such as Figure 4 As shown, Figure 4 This is a schematic diagram of a consistent memory structure provided in an embodiment of this application, including descriptors (data bits) and completion status (flag bits), with each descriptor corresponding to a direct memory access transfer task.

[0167] In some embodiments, such as Figure 5 As shown, Figure 5The flowchart of a data transmission completion status notification method provided in this application embodiment includes: The host first completes PCIe driver registration, which requires initialization of DMA transmission interrupts such as MSI interrupts; the interrupt handling module is initialized for interrupt callbacks when using interrupt mode; the host continuously checks the CPU's busy state and sets the reporting method for DMA transmission completion based on the busy state. When the CPU is busy, interrupt reporting is used, and the interrupt flag needs to be set; when the CPU is idle, polling is used, and the interrupt flag needs to be reset; after the host configuration is completed, the device starts and executes DMA transmission; the device checks whether the interrupt flag is set; if it is set, an interrupt is reported after transmission completion; if it is not set, the corresponding completion status bit is filled into the consistency memory after data transmission completion.

[0168] In summary, the solution provided in this public disclosure is as follows:

[0169] By acquiring the load information of the host in the heterogeneous acceleration system, and based on the load information, determining the target reporting method for the direct memory access (DMI) transfer completion status, and notifying the device in the heterogeneous acceleration system of the target reporting method, the device will notify the host of the DMI transfer completion status according to the target reporting method when it completes the DMI transfer. The target reporting method can be interrupt reporting or polling reporting. This solves the problem of poor real-time performance in data transmission due to the inability to notify the host in real time when data transmission is completed, thus improving the real-time performance of data transmission completion status notifications.

[0170] In some embodiments, this application also provides a data transmission completion status notification system, the system including a host end and a device end, the host end and the device end are connected by a high-speed bus interconnected by peripheral components, the host end includes an acquisition module and a reporting method determination module, and the device end includes a direct storage access control module;

[0171] The acquisition module is configured to acquire the load status of the host in the heterogeneous acceleration system;

[0172] The reporting method determination module is configured to determine the target reporting method based on the load condition for the completion status of direct memory access transfer; and to notify the device side of the heterogeneous acceleration system of the target reporting method so that when the device side completes the direct memory access transfer, it notifies the host side of the completion status of the direct memory access transfer according to the target reporting method. The target reporting method is either interrupt reporting or polling reporting.

[0173] The direct memory access control module is configured to, in response to the completion of a direct memory access transfer, obtain a target reporting method for reporting the completion status of the direct memory access transfer to the host of the heterogeneous acceleration system, and notify the host of the completion status of the direct memory access transfer based on the target reporting method.

[0174] In some embodiments, the direct memory access control module includes a data transmission module, a transmission status reporting module, and an interrupt generation control module:

[0175] The data transmission module is configured to control the direct memory access transfer device to complete data transmission;

[0176] The transmission status reporting module is configured to, in response to the completion of direct memory access transmission, obtain the target reporting method for reporting the completion status of direct memory access transmission to the host of the heterogeneous acceleration system, and notify the host of the completion status of direct memory access transmission based on the target reporting method.

[0177] The interrupt control module is configured to send an interrupt signal to the host in response to the target reporting mode being interrupt reporting mode. The interrupt signal is used to notify the host of the direct memory access transfer completion status and trigger the host to call the interrupt handling function corresponding to the interrupt signal.

[0178] For example, such as Figure 6 As shown, Figure 6The schematic diagram of a data transmission completion status notification system provided in this application embodiment includes a host end and a device end. The host end is responsible for data transmission control, and the device end is mainly responsible for data transmission. The host end includes an application layer and a kernel layer. The application layer is mainly used for users to execute applications, and the kernel layer is used for interaction with the device. The kernel layer is the focus of this invention and mainly includes the following modules: (1) PCIe driver registration module: This module is mainly used to complete the driver registration and hardware initialization of PCIe devices, such as bar control address allocation, configuration space information access, etc. DMA interrupt registration needs to be completed in this module for subsequent DMA interrupt reporting. (2) Consistent memory module: This module is a consistent memory block applied for by the host kernel layer after driver registration. The host end and the device end can access this memory at the same time. This memory can be divided into N memory blocks. Each memory block is used to store the DMA transmission number and transmission completion flag bit. When the polling mode is used, after each DMA transmission is completed, the device end sets the flag bit corresponding to the DMA transmission. The host end then polls and accesses the memory. When a flag bit is found, it indicates that the DMA transmission corresponding to the label descriptor is completed. (3) Interrupt Enable Flag: This flag is used to set the reporting method for DMA transfer completion. The host-side CPU idle state judgment module judges the busy state of the system based on the system information. When the host-side system is busy, the interrupt enable flag is set, indicating that the DMA transfer adopts the interrupt reporting method; when the host is idle or the data transmission is a large number of small packets, the interrupt enable flag is reset, and the DMA transfer adopts the polling method. (4) Interrupt Handling Module: This module is the callback function for DMA interrupt transfer. When the DMA transfer adopts interrupt reporting, the host receives an interrupt and executes the processing function in this module. (5) CPU Idle State Judgment Module, i.e., the acquisition module in this application: It monitors the idle / busy state of the host system and sets the reporting method of DMA transfer status according to the busy state of the host system. When the host system is busy, the DMA transfer adopts the interrupt reporting method; when the host is idle or the data transmission is a large number of small packets, the DMA transfer adopts the polling method.

[0179] Furthermore, such as Figure 7 As shown, Figure 7This is a schematic diagram of the structure of a direct memory access controller provided in this application embodiment. The device side includes a DMA mover, a DMA controller, an interrupt generator, DDR, etc. The DMA mover is used to perform DMA data move operations; the interrupt generator is used to generate interrupts such as MSI for DMA transfer completion status reporting; DDR is the data storage unit of the device side; the DMA controller is used for DMA transfer control, including DMA transfer information judgment, DMA reporting mode control, etc. The control module is mainly responsible for DMA transfer control and is divided into an interrupt enable flag judgment module, a data transmission module, a transfer status reporting module, and an interrupt generation control module. The functions of each module are as follows: (1) Interrupt enable flag judgment module: judges the mode of DMA transfer completion reporting by reading the interrupt enable flag of the host side. If the interrupt enable flag of the host side is set, the interrupt generation module of the DMA controller is enabled. (2) Data transmission control module: responsible for controlling the DMA mover to complete data transmission. (3) Transfer status reporting module: reports the DMA completion status to the host after the DMA mover completes the transfer according to the transfer mode. When polling mode is used, the transmission status reporting module sets the corresponding flag in the consistency memory module; when interrupt mode is used, the interrupt generation control module is notified to inform the interrupt generator to report the MSI interrupt. (4) Interrupt generation control module: controls the interrupt generator to report the MSI interrupt.

[0180] To implement the data transmission completion status notification method provided in this disclosure, this disclosure also provides a data transmission completion status notification device, such as... Figure 8 As shown. Figure 8 This is a schematic diagram of the structure of the data transmission completion status notification device provided in an embodiment of the present disclosure. The data transmission completion status notification device 800 includes:

[0181] The acquisition unit 801 is used to acquire the load status of the host in the heterogeneous acceleration system;

[0182] The determining unit 802 is used to determine the target reporting method for the direct memory access transfer completion status based on the load conditions.

[0183] The notification unit 803 is used to notify the device side of the heterogeneous acceleration system of the target reporting method, so that when the device side completes the direct memory access transfer, it notifies the host side of the direct memory access transfer completion status according to the target reporting method, which is either interrupt reporting or polling reporting.

[0184] In one embodiment, the determining unit 802 is specifically used for:

[0185] In response to a busy load condition, the interrupt reporting method is determined to be the target reporting method for the direct memory access transfer completion status.

[0186] In response to whether the load is idle or the target data is being transmitted, the polling reporting method is determined to be the target reporting method of direct memory access transmission completion status, and the target data is data whose length is less than a preset length threshold.

[0187] In one embodiment, the acquisition unit 801 is specifically used for:

[0188] Obtain the first resource usage time of the processor in the host at the first sampling time and the second resource usage time at the second sampling time;

[0189] Based on the first resource occupancy time and the second resource occupancy time, determine the comprehensive occupancy time change value and idle state time change value of the processor from the first sampling time to the second sampling time.

[0190] Based on the changes in overall occupied time and idle time, the resource occupancy weight of the processor in the host is determined;

[0191] The resource usage weight is compared with the target weight, and the load on the host is determined based on the comparison result.

[0192] In one embodiment, the acquisition unit 801 is specifically used for:

[0193] Based on the combined changes in occupied time and idle time, determine the changes in the processor's busy time between the first sampling time and the second sampling time.

[0194] The resource usage weight of the processor in the host is determined by the ratio of the change in busy time to the change in total usage time.

[0195] In one embodiment, the data transmission completion status notification device 800 further includes a configuration unit, which is used for:

[0196] Configure the flag information for the reporting method according to the target reporting method;

[0197] In one embodiment, the notification unit 803 is specifically used for:

[0198] The flag information of the identification reporting method is notified to the device side of the heterogeneous acceleration system.

[0199] To implement the data transmission completion status notification method provided in this disclosure, this disclosure also provides a data transmission completion status notification device, such as... Figure 9 As shown. Figure 9 This is a schematic diagram of the structure of the data transmission completion status notification device provided in an embodiment of the present disclosure. The data transmission completion status notification device 900 includes:

[0200] The acquisition unit 901 is used to acquire the target reporting method for reporting the completion status of direct memory access transfer to the host of the heterogeneous acceleration system in response to the completion of direct memory access transfer. The target reporting method for reporting the completion status of direct memory access transfer to the host of the heterogeneous acceleration system is different depending on the load of the host. The target reporting method is either interrupt reporting or polling reporting.

[0201] Notification unit 902 is used to notify the host of the direct memory access transfer completion status based on the target reporting method.

[0202] In one embodiment, the acquisition unit 901 is specifically used for:

[0203] Obtain the flag information for the flag reporting method;

[0204] Parse the value of the flag information to obtain the target reporting method for reporting the direct memory access transfer completion status to the host of the heterogeneous acceleration system.

[0205] In one embodiment, the notification unit 902 is specifically used for:

[0206] In response to the target reporting method being interrupt reporting, an interrupt signal is sent to the host. The interrupt signal is used to notify the host of the completion status of the direct memory access transfer and to trigger the host to call the interrupt handling function corresponding to the interrupt signal.

[0207] In response to the target reporting method being polling, status update information is written to the storage area shared by the host and the device, so that the host can detect it through polling. The status update information is used to notify the host of the completion status of direct memory access transmission.

[0208] In one embodiment, the notification unit 902 is specifically used for:

[0209] Obtain the task identifier for the direct memory access transfer task;

[0210] Based on the task identifier, determine the target memory block corresponding to the direct memory access transfer task from multiple memory blocks;

[0211] Write status update information to the target storage block.

[0212] In one embodiment, the notification unit 902 is specifically used for:

[0213] Write a direct memory access transfer completion status flag to the flag bits in the target memory block, and write metadata associated with the direct memory access transfer task to the data bits in the target memory block. The direct memory access transfer completion status flag is used to indicate that the direct memory access transfer is complete, and the metadata associated with the direct memory access transfer task includes at least the data transfer length and the data transfer task sequence number.

[0214] It should be noted that the foregoing explanation of the method embodiments also applies to the apparatus of this embodiment, and the principle is the same, so it is not limited in this embodiment.

[0215] For a description of the features in the embodiment corresponding to the data transmission completion status notification device, please refer to the relevant description in the embodiment corresponding to the data transmission completion status notification method, which will not be repeated here.

[0216] Embodiments of this application also provide an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to perform the steps in any of the above embodiments of the data transmission completion status notification method.

[0217] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described embodiments of the data transmission completion status notification method when it runs.

[0218] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0219] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above-described data transmission completion status notification methods.

[0220] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above-described data transmission completion status notification method embodiments.

[0221] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0222] The foregoing has provided a detailed description of a data transmission completion status notification method, system, device, medium, and product provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and its core ideas. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A method for notifying data transmission completion status, applied to the host side of a heterogeneous acceleration system, characterized in that, include: Obtain the load status of the host side in the heterogeneous acceleration system; In response to the load condition being busy, the interrupt reporting method is determined to be the target reporting method for the direct memory access transmission completion status. In response to the load status being either idle or target data transmission status, the polling reporting method is determined to be the target reporting method with direct memory access transmission completion status, and the target data is data whose length is less than a preset length threshold. The target reporting method is notified to the device side of the heterogeneous acceleration system so that when the device side completes the direct memory access transfer, it notifies the host side of the direct memory access transfer completion status according to the target reporting method. The target reporting method is either interrupt reporting or polling reporting.

2. The data transmission completion status notification method according to claim 1, characterized in that, The process of obtaining the load status of the host in the heterogeneous acceleration system includes: The first resource occupancy time of the processor in the host terminal at the first sampling time and the second resource occupancy time at the second sampling time are obtained; Based on the first resource occupation time and the second resource occupation time, determine the comprehensive occupation time change value and idle state time change value of the processor between the first sampling time and the second sampling time; Based on the changes in the overall occupied time and the changes in the idle time, the resource occupancy weight of the processor in the host is determined; The resource occupancy weight is compared with the target weight, and the load status of the host is determined based on the comparison result.

3. The data transmission completion status notification method according to claim 2, characterized in that, The step of determining the resource occupancy weight of the processor in the host based on the overall occupancy time change value and the idle state time change value includes: Based on the combined occupied time change value and the idle state time change value, determine the busy state time change value of the processor between the first sampling time and the second sampling time; The resource usage weight of the processor in the host is determined based on the ratio of the change value of the busy state time to the change value of the total occupied time.

4. The data transmission completion status notification method according to claim 1, characterized in that, After determining the target reporting method for the direct memory access transfer completion status based on the load situation, the method includes: Configure flag information to identify the reporting method according to the target reporting method; The step of notifying the device side of the heterogeneous acceleration system of the target reporting method includes: The flag information of the flag reporting method is notified to the device side of the heterogeneous acceleration system.

5. A method for notifying data transmission completion status, applied to the device side of a heterogeneous acceleration system, characterized in that, include: In response to the completion of a direct memory access transfer, a target reporting method is obtained for reporting the completion status of the direct memory access transfer to the host of the heterogeneous acceleration system. If the host is in a busy state, an interrupt reporting method is determined as the target reporting method for the completion status of the direct memory access transfer. If the host is in an idle state or transmitting target data, a polling reporting method is determined as the target reporting method for the completion status of the direct memory access transfer. The target data is data with a length lower than a preset length threshold. The host is notified of the direct memory access transfer completion status based on the target reporting method.

6. The data transmission completion status notification method according to claim 5, characterized in that, The target reporting method for obtaining and reporting the direct memory access transfer completion status to the host side of the heterogeneous acceleration system includes: Obtain the flag information for the flag reporting method; Parse the value of the flag information to obtain the target reporting method for reporting the direct memory access transfer completion status to the host of the heterogeneous acceleration system.

7. The data transmission completion status notification method according to claim 5, characterized in that, The step of notifying the host of the direct memory access transfer completion status based on the target reporting method includes: In response to the target reporting method being interrupt reporting, an interrupt signal is sent to the host. The interrupt signal is used to notify the host of the direct memory access transfer completion status and trigger the host to call the interrupt handling function corresponding to the interrupt signal. In response to the target reporting method being a polling reporting method, status update information is written to the storage area shared by the host and the device, so that the host can detect it through polling. The status update information is used to notify the host of the direct memory access transmission completion status.

8. The data transmission completion status notification method according to claim 7, characterized in that, The shared storage area between the host and the device includes multiple storage blocks. Writing status update information to the shared storage area includes: Obtain the task identifier for the direct memory access transfer task; Based on the task identifier, determine the target storage block corresponding to the direct memory access transfer task from the plurality of storage blocks; Write status update information into the target storage block.

9. The data transmission completion status notification method according to claim 8, characterized in that, The status update information includes at least a direct memory access transfer completion status identifier and metadata associated with the direct memory access transfer task. Writing the status update information to the target storage block includes: Write the direct memory access transfer completion status identifier to the flag bit in the target memory block, and write the metadata associated with the direct memory access transfer task to the data bit of the target memory block. The direct memory access transfer completion status identifier is used to indicate that the direct memory access transfer is completed. The metadata associated with the direct memory access transfer task includes at least the data transfer length and the data transfer task sequence number.

10. A data transmission completion status notification system, characterized in that, The system includes a host terminal and a device terminal. The host terminal and the device terminal are connected via a high-speed bus interconnected by peripheral components. The host terminal includes an acquisition module and a reporting method determination module, and the device terminal includes a direct memory access control module. The acquisition module is configured to acquire the load status of the host in the heterogeneous acceleration system; The reporting method determination module is configured to, in response to a busy load condition, determine an interrupt reporting method as the target reporting method for the direct memory access transmission completion status; in response to an idle load condition or a target data transmission status, determine a polling reporting method as the target reporting method for the direct memory access transmission completion status, wherein the target data is data with a length lower than a preset length threshold; and notify the device end of the heterogeneous acceleration system of the target reporting method so that when the device end completes the direct memory access transmission, it notifies the host end of the direct memory access transmission completion status according to the target reporting method, wherein the target reporting method is either an interrupt reporting method or a polling reporting method. The direct memory access control module is configured to, in response to the completion of a direct memory access transfer, acquire a target reporting method for reporting the completion status of the direct memory access transfer to the host of the heterogeneous acceleration system, and notify the host of the completion status of the direct memory access transfer based on the target reporting method.

11. The data transmission completion status notification system according to claim 10, characterized in that, The direct memory access control module includes a data transmission module, a transmission status reporting module, and an interrupt generation control module. The data transmission module is configured to control the direct memory access transfer device to complete the data transmission; The transmission status reporting module is configured to, in response to the completion of direct memory access transmission, obtain a target reporting method for reporting the completion status of direct memory access transmission to the host of the heterogeneous acceleration system, and notify the host of the completion status of direct memory access transmission based on the target reporting method. The interrupt control module is configured to control the device to send an interrupt signal to the host in response to the target reporting mode being interrupt reporting mode. The interrupt signal is used to notify the host of the direct memory access transfer completion status and trigger the host to call the interrupt handling function corresponding to the interrupt signal.

12. An electronic device, characterized in that, include: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions executable by the at least one processor, which, when executed by the at least one processor, enables the at least one processor to perform the steps of the data transmission completion status notification method according to any one of claims 1-4 or 5-9.

13. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to perform the steps of the data transmission completion status notification method according to any one of claims 1-4 or 5-9.

14. A computer program product, characterized in that, The method includes a computer program that, when executed by a processor, implements the steps of the method for notifying a data transmission completion status according to any one of claims 1-4 or 5-9.

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