Storage chip control method, storage controller and storage system
By controlling the read voltage and refreshing the data of the memory chip, the memory cells affected by read or write interference are identified and eliminated, thus solving the problem of low data stability of the memory chip and achieving higher data stability and lower power consumption.
Patent Information
- Application Number
- CN202410851268.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-27
- Publication Date
- 2025-12-30
AI Technical Summary
The lack of optimization schemes for read and write interference in existing memory chips results in low stability of stored data.
By applying a read voltage to the storage cells, the storage cells affected by read or write interference are identified and the data is refreshed. The system selectively refreshes the data based on the type of interference, thereby reducing power consumption and improving the stability of stored data.
It effectively eliminates the impact of read and write interference on storage cells, improves the stability and accuracy of stored data, and reduces the power consumption of storage chips.
Smart Images
Figure CN121237158A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of storage technology, and in particular to a control method for a storage chip, a storage controller, and a storage system. Background Technology
[0002] With the development of storage technology, the storage performance of storage chips is getting higher and higher, and the stability of data stored by storage chips is becoming more and more important.
[0003] Read interference and write interference are important factors affecting the stability of data stored in memory chips. Read interference refers to the impact of the conduction current inside the memory cell on the storage state of the cell itself when frequent read operations are performed. Write interference refers to the impact of the temperature rise of the memory cell itself on the storage state of itself and surrounding memory cells when frequent write operations are performed. Specifically, read interference mainly causes the memory cell to change from a low-resistance state to a high-resistance state, while write interference mainly causes the memory cell to change from a high-resistance state to a low-resistance state.
[0004] Currently, there are no solutions in memory chips to optimize for read and write interference, resulting in low stability of data stored in memory chips. Summary of the Invention
[0005] This application provides a control method, a memory controller, and a memory system for a memory chip, which can improve the stability of data stored in the memory chip. The corresponding technical solution is as follows:
[0006] In a first aspect, a method for controlling a memory chip is provided, comprising: applying a read voltage to a plurality of first memory cells corresponding to a first address; and refreshing data stored in a plurality of second memory cells in response to a failure rate of the plurality of first memory cells being greater than a first threshold, wherein the first threshold is less than a second threshold for triggering a UCE (Unified Entity Encryption) of the memory chip, the plurality of second memory cells are memory cells affected by read interference or write interference, and the plurality of second memory cells are a plurality of first memory cells, or the second memory cells are a plurality of first memory cells and memory cells adjacent to the plurality of first memory cells.
[0007] In the solution presented in this application, after performing a read operation on multiple first memory cells at a first address, if the failure rate of the read result of the first memory cell is determined to be greater than a first threshold, it is considered that the first memory cell may have been affected by read interference or write interference. Then, the data stored in multiple second memory cells (including the first memory cells) that may be affected by read interference or write interference can be refreshed to restore the threshold voltage of the affected memory cells to a state unaffected by read interference or write interference. Since the first threshold is less than the second threshold that triggers the UCE of the memory chip, the solution presented in this application can eliminate the impact of read interference or write interference on the memory cells before triggering the UCE, thereby improving the stability of the data stored in the memory chip and reducing the probability of triggering the UCE.
[0008] In one possible implementation, in response to a failure rate greater than a first threshold, refreshing the data stored in a plurality of second storage units includes: determining an interference type corresponding to the plurality of first storage units, wherein the interference type is read interference or write interference, in response to the failure rate of the plurality of first storage units being greater than the first threshold; if the interference type is determined to be read interference, then determining the plurality of first storage units as a plurality of second storage units, and refreshing the data stored in the second storage units; if the interference type is determined to be read interference, then determining the plurality of first storage units and the storage units adjacent to the plurality of first storage units as second storage units, and refreshing the data stored in the second storage units.
[0009] In the solution shown in this application, it is possible to distinguish whether the first storage cell is primarily affected by read interference or write interference, and to selectively refresh the storage cell based on the type of interference. When affected by read interference, only the data in the first storage cell is refreshed, reducing the number of storage cells to be refreshed and lowering the power consumption of the storage chip. When affected by write interference, the data in the first storage cell and adjacent storage cells can be refreshed to ensure that all storage cells affected by write interference are refreshed, thereby improving the stability of data storage in the storage chip.
[0010] In one feasible approach, determining the interference type corresponding to multiple first memory cells includes: determining the proportion of the number of failed low-resistivity first memory cells to the total number of failed first memory cells. If the proportion is greater than a third threshold, the interference type is determined to be read interference; if the proportion is less than or equal to the third threshold, the interference type is determined to be write interference.
[0011] In the solution presented in this application, the interference type corresponding to multiple first memory cells can be determined based on the number of failed low-resistivity first memory cells or the proportion of failed high-resistivity first memory cells in the total number of failures. By distinguishing the interference types corresponding to the first memory cells, the range of second memory cells affected by read or write interference can be accurately determined, avoiding missed updates to interfered memory cells or accidental updates to undisturbed memory cells. This reduces the power consumption of the memory chip and improves the stability of data storage.
[0012] In one possible implementation, applying a read voltage to a plurality of first memory cells corresponding to a first address includes: applying multiple levels of read voltage to the plurality of first memory cells corresponding to the first address, wherein the read voltage levels increase sequentially. Refreshing the data stored in a plurality of second memory cells in response to a failure rate greater than a first threshold includes: refreshing the data stored in the plurality of second memory cells in response to a failure rate greater than the first threshold obtained by applying read voltage levels to the plurality of first memory cells.
[0013] In the solution shown in this application, when the failure rate obtained by applying multiple levels of read voltage to the first storage cell is greater than the first threshold, the data stored in the storage cell is refreshed. This can eliminate the impact of read interference or write interference on the first storage cell before the first storage cell fails to read, thereby reducing the number of refreshes on the storage cell while ensuring the stability of the data stored in the storage chip, and thus reducing the power consumption of the storage chip.
[0014] In one possible implementation, after applying multiple levels of read voltage to the multiple first storage cells corresponding to the first address, the method further includes: performing error correction processing on the target read data to obtain error-corrected read data, wherein the target read data is the set of read data with the lowest failure rate among the multiple sets of read data obtained by applying the multiple levels of read voltage. Refreshing the data stored in the multiple second storage cells includes: writing the error-corrected read data into the first storage cell included in the multiple second storage cells.
[0015] In the scheme shown in this application, when refreshing the data of the first storage unit, the target read data with the lowest failure rate can be selected for error correction, and the corrected data can be rewritten into the first storage unit. In this way, error correction of the target read data with the lowest failure rate can improve the accuracy of error correction of the target read data, thereby improving the accuracy of the data stored in the first storage unit after refresh.
[0016] In one possible implementation, the memory cells adjacent to the plurality of first memory cells include third memory cells that are on the same bit line or word line and adjacent to the plurality of first memory cells. The method further includes: determining a fourth memory cell that is on the same bit line or word line and adjacent to the third memory cell as a second memory cell. Thus, expanding the scope of the second memory cells ensures that all memory cells affected by write interference are refreshed, thereby improving the stability of data stored in the memory chip.
[0017] In one feasible approach, experimental data shows that a third threshold between one-half and four-fifths provides a high degree of accuracy in distinguishing between read and write interference.
[0018] In one possible implementation, the aforementioned memory chip is a phase-change memory chip, and the memory cells included in the phase-change memory chip are phase-change memory cells.
[0019] Secondly, a storage controller is provided, which is connected to a storage chip. The storage controller is used for:
[0020] A read voltage is applied to multiple first memory cells corresponding to a first address in the memory chip. In response to the failure rate of the multiple first memory cells being greater than a first threshold, the data stored in multiple second memory cells is refreshed, wherein the first threshold is less than a second threshold that triggers an uncorrectable error (UCE) in the memory chip, the multiple second memory cells are memory cells affected by read interference or write interference, the multiple second memory cells are multiple first memory cells, or the second memory cells are multiple first memory cells and memory cells adjacent to the multiple first memory cells.
[0021] In one possible implementation, the storage controller is configured to: in response to a failure rate greater than a first threshold, determine an interference type corresponding to the plurality of first storage cells, wherein the interference type is read interference or write interference. If the interference type is determined to be read interference, the plurality of first storage cells are designated as plurality of second storage cells, and the data stored in the second storage cells is refreshed. If the interference type is determined to be read interference, the plurality of first storage cells and adjacent storage cells are designated as second storage cells, and the data stored in the second storage cells is refreshed.
[0022] In one possible implementation, the storage controller is configured to: determine, among a plurality of first storage cells, the proportion of the number of failed low-resistivity first storage cells to the total number of failed first storage cells. If the proportion is greater than the third threshold, the interference type is determined to be read interference; if the proportion is less than or equal to the third threshold, the interference type is determined to be write interference.
[0023] In one possible implementation, a storage controller is configured to: apply multiple read voltage levels to multiple first storage cells corresponding to a first address, wherein the read voltage levels increase sequentially. In response to a failure rate greater than a first threshold obtained by applying each read voltage level to the multiple first storage cells, the data stored in the multiple second storage cells is refreshed.
[0024] In one possible implementation, the storage controller is further configured to: perform error correction processing on the target read data to obtain error-corrected read data, wherein the target read data is the set of read data with the lowest corresponding failure rate among multiple sets of read data obtained by applying multiple levels of read voltage; and write the error-corrected read data into a first storage cell included in a plurality of second storage cells.
[0025] In one possible implementation, the memory cell adjacent to the plurality of first memory cells includes a third memory cell that is on the same bit line or word line and adjacent to the plurality of first memory cells. The memory controller is further configured to: determine a fourth memory cell that is on the same bit line or word line and adjacent to the third memory cell as a second memory cell.
[0026] In one feasible approach, the third threshold is between one-half and four-fifths.
[0027] In one feasible approach, the first storage unit is a phase-change storage unit.
[0028] Thirdly, a storage system is provided, comprising a storage controller as described in the second aspect above, and at least one storage chip connected to the storage controller.
[0029] Fourthly, an electronic device is provided, comprising a processor and a storage system as described in the third aspect above, wherein the processor is configured to send read / write instructions to the storage system to enable the storage system to perform read / write operations. Attached Figure Description
[0030] Figure 1 This is a schematic diagram of the structure of a memory chip provided in an embodiment of this application;
[0031] Figure 2 This is a schematic diagram of the structure of a control circuit provided in an embodiment of this application;
[0032] Figure 3 This is a schematic diagram of the structure of a storage system provided in an embodiment of this application;
[0033] Figure 4 This is a threshold voltage distribution diagram of a memory cell provided in an embodiment of this application;
[0034] Figure 5This is a schematic diagram illustrating the impact of write interference and read interference on a storage unit provided in an embodiment of this application;
[0035] Figure 6 This is a flowchart of a control method for a memory chip provided in an embodiment of this application;
[0036] Figure 7 This is a threshold voltage distribution diagram of a memory cell provided in an embodiment of this application;
[0037] Figure 8 This is a flowchart of a control method for a memory chip provided in an embodiment of this application;
[0038] Figure 9 This is a schematic diagram of an electronic device provided in an embodiment of this application. Detailed Implementation
[0039] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.
[0040] The following explains some terms used in the embodiments of this application:
[0041] Resistive memory: It uses changes in resistance to store or retrieve data. For example, a resistive memory can store "0" in high configuration and "1" in low configuration.
[0042] Phase Change Memory (PCM): A novel non-volatile semiconductor memory based on chalcogenide compounds, belonging to the resistive memory category. It utilizes the difference in resistance between the crystalline and amorphous states of the phase change material that makes up the PCM to store "0" and "1". Specifically, when the phase change material is in an amorphous state, it is in a high-resistance state, defined as the RESET(0) state; when the phase change material is in a crystalline state, it is in a low-resistance state, defined as the SET(1) state.
[0043] Ovonic Threshold Switch (OTS): A novel bidirectional gating device based on chalcogenide compounds. When an electrical pulse of arbitrary direction (either positive or negative) below the corresponding threshold voltage is applied to the OTS, the response current is small, exhibiting a high-resistance non-conducting state. When an electrical pulse of arbitrary direction (either positive or negative) above the corresponding threshold voltage is applied to the OTS, the response current is large, exhibiting a low-resistance conducting state.
[0044] 1S1R memory cell: A memory cell consisting of an OTS and a PCM. In one implementation, when the PCM in the 1S1R memory cell is in the RESET(0) state, the 1S1R memory cell stores "0", and at this time, the 1S1R memory cell has a higher threshold voltage Vthr. When the PCM in the 1S1R memory cell is in the SET(1) state, the 1S1R memory cell stores "1", and at this time, the 1S1R memory cell has a lower threshold voltage Vths. Wherein, Vthr is equal to the threshold voltage of the OTS plus the threshold voltage corresponding to the PCM in the RESET(0) state, and Vths is equal to the threshold voltage of the OTS plus the threshold voltage corresponding to the PCM in the SET(1) state.
[0045] Based on the above characteristics, it can be seen that when the 1S1R memory cell stores "0", the 1S1R device cell has a small response current under a specific read voltage Vread (greater than Vths, less than Vthr); when the 1S1R memory cell stores "1", the 1S1R device cell has a larger response current under the specific read voltage Vread. Therefore, data stored in the 1S1R memory cell can be read by applying the read voltage Vread.
[0046] Erasure operation: This is achieved by applying a high-amplitude, narrow-width electrical pulse to the 1S1R memory cell. The amplitude of this electrical pulse is higher than the threshold voltage of the OTS. Under the action of this electrical pulse, the temperature of the PCM in the 1S1R memory cell is rapidly raised above the melting temperature and then quenched. Since the microscopic atoms do not have enough time to crystallize, they remain in a high-resistivity amorphous state, thus achieving the storage of "0".
[0047] Write operation: This is achieved by applying an electrical pulse with a relatively low amplitude but a relatively long duration to the 1S1R memory cell. The amplitude of this electrical pulse is higher than the threshold voltage of the OTS. Under the action of this electrical pulse, the temperature of the PCM in the 1S1R memory cell is raised to above the crystallization temperature but below the melting temperature. The PCM can be transformed into a low-resistance state through a thermal crystallization process, thus achieving the storage of "1".
[0048] Read operation: By applying a fixed read voltage Vread across the 1S1R memory cell, the data stored in the 1S1R memory cell can be read according to the response current of the 1S1R memory cell.
[0049] Word line: The signal line required to select a 1S1R memory cell in a memory array. It works together with the bit line to complete the selection of a 1S1R memory cell.
[0050] Bit lines: Signal lines used to select a specific column in a memory array. Working together with word lines, they enable the selection of a 1S1R memory cell. By applying appropriate electrical pulses to the word lines and bit lines, write, erase, or read operations can be performed on the selected 1S1R memory cell.
[0051] Figure 1 This is a schematic diagram of the structure of a memory chip provided in an embodiment of this application. Figure 1 As shown, the memory chip 100 includes a control circuit 110 and at least one storage bank 120, each bank 120 including multiple storage arrays 121. The multiple storage arrays 121 within the multiple banks 120 can generally be tiled on the same plane or stacked in three-dimensional space. Each storage array 121 includes storage cells arranged in rows and columns. When performing read and write operations on the storage cells of the memory chip 100, one storage cell can be selected within each storage array 121 to perform read and write operations on multiple selected storage cells. This allows for an increase in the storage capacity and performance of the memory chip without increasing its footprint.
[0052] Figure 2 This is a schematic diagram of a control circuit provided in an embodiment of this application. For example... Figure 2 As shown, the control circuit 110 includes a logic control circuit 1101, an address register 1102, a bank selection circuit 1103, a row address multiplexing circuit 1104, a column address multiplexing circuit 1105, and a row decoder 1106, a column decoder 1107, a driving circuit 1108, and a sensing circuit (SA) 1109 corresponding to each memory array, wherein:
[0053] The logic control circuit 1101 can be used to receive read, write, and other operation requests sent from the outside, and control the timing of the read, write, and other operations. For example, it can send the address of the memory cell to be read or written to the address register 1102, and send the operation type to be performed, such as write operation or read operation, to the driver circuit.
[0054] Address register 1102 can receive and store the addresses of memory cells to be read, written, or otherwise executed by the logic control circuit 1101. These addresses include the row address, column address, and bank address of the memory cell.
[0055] The Bank selection circuit 1103 can select the Bank containing the memory cell to be read or written from multiple Banks based on the Bank address corresponding to the memory cell to be read or written.
[0056] The row address multiplexing circuit 1104 can send the row address corresponding to the memory cell to be read, written, or otherwise operated to the row decoder 1106 corresponding to each memory array 121 included in the selected Bank. The column address multiplexing circuit 1105 can send the column address corresponding to the memory cell to be read, written, or otherwise operated to the column decoder 1107 corresponding to each memory array 121 included in the selected Bank.
[0057] For each row decoder 1106 that receives a row address, each row decoder 1106 can decode the row address to select the row containing the memory cell to be read, written, or otherwise operated on. For each column decoder 1107 that receives a row address, each column decoder 1107 can decode the column address to select the column containing the memory cell to be read, written, or otherwise operated on. The memory cell selected by both the row decoder 1106 and the column decoder 1107 is the memory cell to be read, written, or otherwise operated on.
[0058] For each drive circuit 1108 included in the selected Bank, each drive circuit 1108 can apply an operating voltage to the selected memory cell in the corresponding memory array 121 according to the received operation type to complete the corresponding operation.
[0059] For each sensing circuit 1109 included in the selected Bank, each sensing circuit 1109 can determine the data stored in the memory cell by detecting the magnitude of the current or voltage after the drive circuit 1108 completes the application of the read operation voltage to the memory cell.
[0060] Figure 3 This is a schematic diagram of a storage system provided in an embodiment of this application. Figure 3 As shown, the storage system 300 includes a storage controller 200 and one or more other components such as... Figure 1 The memory chip 100 shown is as follows. Wherein:
[0061] The storage controller 200 is a hardware device used to control the storage chip 100 to perform read and write operations. The storage controller 200 can send operation requests corresponding to read, write, or erase operations to the storage chip 100, causing the control circuit 120 in the storage chip 100 to select the storage cell via word lines and bit lines, and apply read, write, or erase voltages to the selected storage cell, thereby executing the read, write, or erase operation. To handle read errors in storage cells, the storage controller 200 also includes an error correction algorithm, such as an Error Correction Code (ECC). This error correction algorithm can verify and correct the read results of the storage chip to avoid or reduce erroneous data reads.
[0062] During write or read operations, 1S1R memory cells may be subject to interference from certain factors, causing changes in the overall physical state of the 1S1R memory cell and consequently altering its voltage (Vth), leading to abnormal read operations. These interference factors include read disturbance, write disturbance, and threshold voltage drift caused by prolonged storage.
[0063] OTS threshold voltage drift: The characteristic of OTS threshold voltage to change due to the influence of voltage applied to OTS and ambient temperature during the time from the last time it was turned on to the current time it was turned on is called OTS threshold voltage drift.
[0064] The OTS (Overcurrent Switch) exhibits significant current conduction capability under applied voltages exceeding its threshold voltage. This is due to the transition of low-energy, non-conductive electrons to a high-energy, non-conductive state under high voltage. When the applied voltage is removed from the OTS, the high-energy non-equilibrium carriers do not instantly return to equilibrium; instead, they gradually return to the low-energy, non-conductive state with a certain probability. Therefore, after each operation on a 1S1R memory cell, the threshold voltage of the OTS in the 1S1R memory cell suddenly decreases and then gradually increases over time. The higher the applied voltage, the greater the drop in the OTS threshold voltage. Furthermore, the higher the ambient temperature of the OTS, the faster its threshold voltage drifts upward. Additionally, when the OTS is left unused for an extended period, its threshold voltage will also drift to a higher level.
[0065] Figure 4 This is a threshold voltage distribution diagram provided in an embodiment of this application. See also... Figure 4 Unlike the threshold voltage drift of OTS, which mainly causes the threshold voltage to increase while maintaining a relatively constant threshold voltage distribution curve, read and write interference are primarily caused by electrical and thermal interference affecting the memory cells. This process impacts both the OTS and PCM as a whole, increasing the threshold voltage and widening the threshold voltage distribution curve, leading to an overlap between the "0" and "1" distribution curves of the memory cells.
[0066] In one example, write interference refers to the interference (mainly thermal interference) that occurs when a memory cell at a certain address is frequently written to, affecting neighboring, next-nearest, and next-nearest neighbor memory cells. This causes the high-resistivity "0" state of neighboring cells to be thermally crystallized into a low-resistivity "1" state. The memory cells that may be affected are also called PVs (potential-victims), and the closer the cells are, the greater the impact. For example... Figure 4As shown, the write interference mainly broadens the curve shape of the threshold voltage of the high-impedance "0" state, so that the threshold voltage of some high-impedance "0" states overlaps with the threshold voltage of the low-impedance "1" state.
[0067] In one example, read interference occurs because frequent reads of a memory cell at a certain address can cause the cumulative effect of factors such as current fluctuations during reads on the memory state (mainly current interference), leading to the misinterpretation of a low-impedance "1" state as a "0" state. For example... Figure 4 As shown, the write interference mainly broadens the curve shape of the threshold voltage of the low-impedance "1" state, so that the threshold voltage of some low-impedance "1" states overlaps with the threshold voltage of the high-impedance "0" state.
[0068] Figure 5 This is a schematic diagram illustrating the effects of write interference and read interference on a storage unit provided in an embodiment of this application. For example... Figure 5 As shown, when frequent write operations are performed on target memory cell a, target memory cell a and multiple memory cells (PVs) adjacent to target memory cell a may be affected by the high temperature of the target memory cell, resulting in changes in the storage state. Specifically, memory cells storing a high-resistance state "0" are disturbed and stored as low-resistance states "1". The multiple memory cells adjacent to target memory cell a may include memory cells b, c, d, e, etc. When frequent read operations are performed on target memory cell n, target memory cell n will be frequently turned on. The conduction current will continuously affect the storage state of target memory cell n, leading to changes in the storage state. Specifically, memory cells storing a low-resistance state "1" are disturbed and stored as high-resistance states "0".
[0069] This application provides a control method for a memory chip. During normal reading of the memory chip, if it is determined that the failure rate of a memory cell at a certain address is greater than a set failure rate threshold, the reason for the high failure rate of the memory cell at that address can be further determined, including whether it is affected by write interference or read interference. Based on the different reasons for the high failure rate of the memory cells and the characteristics of the interference of read and write operations on the memory cells in the memory chip, a refresh operation is performed on the corresponding memory cells to refresh the storage state of the memory cells to the storage state before the interference, thereby improving the stability of the data stored in the memory chip and avoiding uncorrectable errors caused by write or read interference.
[0070] Figure 6 This application provides a flowchart of a control method for a memory chip, which can be executed by the aforementioned memory controller. (See also...) Figure 6 The method includes:
[0071] Step 601: The storage controller applies a read voltage to the plurality of first storage cells corresponding to the first address.
[0072] In implementation, the storage controller can receive read requests sent by the host. Upon receiving a read request, the storage controller can send the first address corresponding to the read request to the control circuit in the storage chip. Then, the control circuit applies read voltages to multiple first storage cells corresponding to the first address to perform read operations on these cells. The process of the control circuit applying read voltages to the multiple first storage cells is described above. Figure 2 The corresponding embodiments will not be repeated here. In this application, the memory chip involved in the embodiments can be a phase-change memory chip, and the included memory units are phase-change memory units, such as 1S1R memory units.
[0073] Step 602: In response to the failure rate of multiple first storage cells being greater than a first threshold, refresh the data stored in multiple second storage cells. Wherein, the first threshold is less than a second threshold that triggers an uncorrectable error (UCE) in the storage chip, the multiple second storage cells are storage cells affected by read interference or write interference, the multiple second storage cells are multiple first storage cells, or the second storage cells are multiple first storage cells plus storage cells adjacent to the multiple first storage cells.
[0074] After performing a read operation on multiple first memory cells, the reading results corresponding to the multiple first memory cells can be obtained through the sensing circuit included in the control circuit, and the reading result of each first memory cell can be stored in the register included in the control circuit. The reading result of a first memory cell is either "1" or "0". In one example, a reading result of "1" indicates that the storage state of the first memory cell is low-impedance, and a reading result of "0" indicates that the storage state of the first memory cell is high-impedance.
[0075] The storage controller can read the read results stored in the registers and then determine the failure rate corresponding to the read results using error correction algorithms, such as Error Correction Code (ECC). The failure rate can be represented by the number of storage cells with failed data in multiple first storage cells. For example, the failure rate can be the number of error bits (FBC) or the proportion of the number of storage cells with failed data in multiple first storage cells.
[0076] The second storage unit (PV) is the storage unit that may be affected by read or write interference. When the failure rate of multiple first storage units exceeds a first threshold, it indicates that these units may be affected by read or write interference, leading to a high failure rate. Therefore, at least multiple first storage units can be identified as second storage units to be refreshed, and the data stored in these units can be refreshed to eliminate the impact of read or write interference on the storage state of the units and ensure the accuracy of the stored data. The first threshold is less than the second threshold that triggers the UCE (Unified Error Correction) of the storage chip. This ensures that after determining that the failure rate of multiple first storage units exceeds the first threshold, the error correction algorithm can correct errors by reading the results from these units, thereby refreshing the data stored in the first storage units. In one example, the first threshold is between 0.5 and 0.99 times the second threshold.
[0077] Because when the first memory cell is subject to write interference, the surrounding memory cells may also be subject to write interference. For example... Figure 5 In the context of frequent write operations on storage unit a, besides storage unit a being affected by write interference, the high temperature generated by storage unit a can also be transferred to storage units b, c, d, and e through some media, making storage units b, c, d, and e potentially affected by write interference. Therefore, when it is determined that the first storage unit may be affected by write interference, even if it cannot be directly determined whether the first storage unit is the one frequently performing write operations, it can be determined that the storage units adjacent to the first storage unit may also be affected by write interference. Therefore, in this embodiment of the application, in order to further eliminate the impact of write interference on the storage state of the storage unit, when it is determined that the first storage unit is affected by write interference, the first storage unit and the storage units adjacent to the first storage unit can be identified as second storage units to be refreshed, and the data stored in multiple second storage units can be refreshed to eliminate the impact of read interference or write interference on the storage state of the storage unit and ensure the accuracy of the data stored in the storage unit.
[0078] In this embodiment, refreshing the data stored in the second storage unit involves correcting the read results corresponding to the second storage unit and then rewriting the corrected data into the second storage unit. Since the data rewritten to the second storage unit is corrected data, the accuracy of the data stored in the second storage unit can be guaranteed. Furthermore, after rewriting data to the second storage unit, the threshold voltage of the second storage unit is refreshed to the threshold voltage before being affected by read interference, write interference, threshold voltage drift, etc., thereby avoiding the problem that the read voltage cannot distinguish the storage state of the storage unit and improving the accuracy of the data stored in the storage unit.
[0079] Figure 7This is a threshold voltage distribution diagram provided in an embodiment of this application. For example... Figure 7 As shown, after multiple second memory cells are subjected to read or write interference, the threshold voltage distribution curves of the first memory cell storing "1" and the second memory cell storing "0" may overlap, causing the read voltage (Vread) to be unable to distinguish the storage state of some second memory cells. (Continue referring to...) Figure 7 After the data stored in the second storage cell is refreshed, the threshold voltage of the second storage cell is also refreshed. The threshold voltage distribution curve of the first storage cell storing "1" and the threshold voltage distribution curve of the second storage cell storing "0" will both become "narrower". The read voltage (Vread) can accurately distinguish the storage state of the second storage cell.
[0080] In one example, after determining that the failure rate of multiple first storage cells is greater than a first threshold, it can be determined whether the interference experienced by the multiple first storage cells is read interference or write interference. Then, based on the type of interference experienced by the first storage cells, the range of storage cells for data refresh can be selected. The method for determining the type of interference experienced by the first storage cells is described below:
[0081] Read interference primarily disrupts the memory cell from a low-resistance state to a high-resistance state, essentially causing memory cells storing "1"s to store "0". Write interference, on the other hand, primarily disrupts the memory cell from a high-resistance state to a low-resistance state, essentially causing memory cells storing "0"s to store "1". Therefore, in this embodiment, the number of failures in both the low-resistance and high-resistance states of the memory cells can be used to determine whether a memory cell is primarily affected by read interference or write interference.
[0082] In implementation, the storage controller uses an error correction algorithm to determine the number of failed first storage cells among multiple first storage cells. It can also determine a first number of first storage cells that failed from storage "1" to storage "0", and a second number of first storage cells that failed from storage "0" to storage "1". The sum of the first and second numbers represents the total number of failed storage cells among the multiple first storage cells.
[0083] In one example, when the first number is greater than the second number, that is, when the first proportion of the first memory cells that failed from storage "1" to storage "0" in the total number of failed first memory cells is greater than 50% (or the second proportion of the first memory cells that failed from storage "0" to storage "1" in the total number of failed first memory cells is less than 50%), it can be determined that the multiple first memory cells corresponding to the first address are mainly affected by read interference. When the first number is less than the second number, that is, when the second proportion of the first memory cells that failed from storage "0" to storage "1" in the total number of failed first memory cells is greater than 50% (or the first proportion of the first memory cells that failed from storage "1" to storage "0" in the total number of failed first memory cells is less than 50%), it can be determined that the multiple first memory cells corresponding to the first address are mainly affected by write interference.
[0084] In another example, a threshold (third threshold) can be set for the aforementioned first or second percentage. Based on the relationship between the first or second percentage and the set third threshold, it can be determined whether the memory cell is primarily affected by read interference or write interference. For example, when the first percentage is greater than the third threshold (i.e., the second percentage is less than the third threshold), it can be determined that multiple first memory cells corresponding to the first address are primarily affected by read interference. When the first percentage is greater than the third threshold (i.e., the second percentage is less than the third threshold), it can be determined that multiple first memory cells corresponding to the first address are primarily affected by write interference. The specific value of the third threshold can be preset by technicians. Experimental data shows that setting the third threshold between one-half and four-fifths yields the highest accuracy in identifying read and write interference.
[0085] In this embodiment, when the interference type affecting multiple first storage units is determined to be read interference, the data stored in the determined first storage units can be refreshed, thereby avoiding the impact of read interference on the storage units. When the interference type affecting multiple first storage units is determined to be write interference, the multiple first storage units and the storage units adjacent to the multiple first storage units can be designated as second storage units, and the data stored in the designated second storage units can be refreshed. This avoids the impact of write interference on the first storage units and the surrounding storage units.
[0086] In one example, when it is determined that the interference type experienced by multiple first memory cells is write interference, the second memory cell to be refreshed may include, in addition to the first memory cells, a third memory cell that is on the same word line and adjacent to the first memory cells, and a third memory cell that is on the same bit line and adjacent to the first memory cells. For example... Figure 5As shown, the first storage cell is 'a', and the third storage cells, which are on the same word line and adjacent to the first storage cell, include storage cells b, c, d, and e. Furthermore, the high temperature of the third storage cell may be transmitted through the word line and bit line to the fourth storage cell adjacent to it, causing the fourth storage cell to also be affected by write interference. Therefore, to ensure the accuracy of the data stored in the storage cells, data refresh can also be performed on the fourth storage cell, which is on the same bit line or word line and adjacent to the third storage cell. For example... Figure 5 As shown, the third storage unit includes storage units b, c, d, and e, and the corresponding fourth storage unit includes storage units f, g, h, i, j, k, l, and m. In implementation, the address correspondence between each first storage unit and the third and fourth storage units can be pre-stored. After determining that the first storage unit has been subjected to a write interference operation, the data stored in the third and fourth storage units can be refreshed according to the address relationship.
[0087] It should be noted that, in this embodiment, when the interference type affecting multiple first storage units is determined to be read interference, it means that the failure of multiple first storage units is mainly due to read interference, but the possibility of the first storage units also being affected by write interference cannot be ruled out. Similarly, when the interference type affecting multiple first storage units is determined to be write interference, it means that the failure of multiple first storage units is mainly due to write interference, but the possibility of the first storage units also being affected by read interference cannot be ruled out. However, regardless of whether the interference type affecting multiple first storage units is read interference or write interference, the second storage unit performing data refresh always includes the first storage units, which can avoid read interference or write interference affecting the first storage units, solve the problem of high failure rate of the first storage units, and improve the accuracy of data stored by the storage chip.
[0088] In one possible implementation, the read voltage applied in step 601 is a multi-level read voltage, with the multi-level read voltage increasing sequentially. In some embodiments, the read voltage applied to the first memory cell includes multiple levels, with the read voltage increasing sequentially across the multiple levels. When a read operation needs to be performed on multiple first memory cells, the lowest level of read voltage can be applied to the multiple first memory cells first. If the failure rate of the obtained read result does not trigger the UCE of the memory chip, the read result is corrected using an error correction algorithm to obtain an accurate read result. If the failure rate of the obtained read result triggers the UCE of the memory chip, the level of read voltage can be increased, applying a higher level of read voltage to the multiple first memory cells to obtain a new read result. Then, it is determined again whether the failure rate corresponding to the read result triggers the UCE of the memory chip, and the same operation is performed until an error-corrected read result is obtained. If applying multiple levels of read voltage to the first memory cells triggers the UCE in all cases, the read operation fails. In this way, by applying different levels of read voltage, the influence of threshold voltage drift on the threshold voltage of the memory cell can be resolved.
[0089] In the embodiments provided in this application, a smaller first threshold is set compared to the second threshold that triggers the UCE of the memory chip. After applying a read voltage to multiple first memory cells, if the failure rate of the obtained read result is greater than the first threshold, a higher read voltage level can be applied to the multiple first memory cells again. If a read result with a failure rate less than the first threshold appears among the applied read voltage levels, an error correction algorithm can be used to correct the read result, resulting in an error-corrected read result. If the failure rate of the read result corresponding to the applied read voltage levels is greater than the first threshold, it indicates that the multiple first memory cells are severely affected by read interference or write interference, which may trigger the UCE of the memory chip. Therefore, step 602 above, which refreshes the data stored in the multiple second memory cells, is executed first to ensure data accuracy. In this way, by verifying the failure rate of the reading results obtained from multiple reading voltage levels, the number of times data refresh operations are performed on the first storage unit can be reduced. It can also ensure that data refresh is performed on the storage unit affected by read and write interference before the first storage unit fails to read (that is, it is severely affected by read and write interference). This can reduce the power consumption of the storage chip and improve the accuracy of the data stored by the storage chip.
[0090] In one example, as described in this application, if the second storage cell needs to be refreshed after applying multiple levels of read voltage, the first storage cell included in the second storage cell can be refreshed by performing error correction processing on the target read data to obtain error-corrected read data, and then writing the error-corrected read data into the first storage cell. The target read data is the set of read data with the lowest failure rate among multiple sets of read data obtained by applying multiple levels of read voltage to multiple first storage cells. By correcting the read data with the lowest failure rate, the accuracy of error correction can be reduced, thereby ensuring the accuracy of the data after the first storage cell is refreshed.
[0091] Figure 8 This is a flowchart of a control method for a memory chip provided in an embodiment of this application, as shown below. Figure 8 As shown, the method includes:
[0092] Step 801: Start the read process.
[0093] The lowest level of read voltage is applied to multiple first memory cells corresponding to the first address to obtain the read result.
[0094] Step 802: Determine whether the FBC corresponding to the read result is greater than the set FBC threshold.
[0095] If the FBC is determined to be greater than the set FBC threshold, proceed to step 803. If the FBC is determined not to be greater than the set FBC threshold, perform normal error correction on the read result and return the corrected read result. The set FBC threshold is less than the FBC threshold that triggers the UCE of the memory chip.
[0096] Step 803: Use different voltage levels to perform read retry and find the lowest FBC.
[0097] Step 804: Determine whether the lowest FBC is greater than the set FBC threshold.
[0098] If it is determined that the FBC is greater than the set FBC threshold, then proceed to step 805. If it is determined that the FBC is not greater than the set FBC threshold, then the read result is corrected normally, and the corrected read result is returned.
[0099] Step 805: Determine whether the failure rate of "0→1" exceeds 50%.
[0100] If the percentage of memory cells that fail in the "0→1" state (i.e., memory cells that fail in the high-impedance state) exceeds 50%, it indicates that the first memory cell is mainly affected by write disturb, and step 806 can be executed. If the percentage of memory cells that fail in the "0→1" state does not exceed 50%, it indicates that the memory cell is mainly affected by read disturb, and step 807 can be executed.
[0101] Step 806: Perform a refresh process on the current storage cell and its neighboring storage cells.
[0102] Step 807: Perform a refresh process on the current storage unit.
[0103] Thus, in this embodiment of the application, the effects of read interference and write interference on the storage unit can be distinguished, and different refresh processes can be performed for read interference and write interference respectively, which can improve the stability of data stored in the storage chip and reduce the power consumption of refresh processing.
[0104] Figure 9 This is a schematic diagram of an electronic device provided in an embodiment of this application. The storage system includes a host, a storage controller, and a storage chip. The host, storage controller, and storage chip are connected via an interface. The storage controller is equipped with an algorithm module, including a Disturbance Resolution module, an ECC module, and a Read Retry module. The Disturbance Resolution module, ECC module, and Read Retry module can be used to implement the control method provided in this embodiment of the application to improve the stability of data stored by the storage chip. Wherein:
[0105] After obtaining the FBC corresponding to the read results of multiple first storage units each time, the ECC module can send the FBC to the Disturb resolution module.
[0106] After receiving the FBC corresponding to the read result, the Disturb resolution module determines whether multiple read retry operations are needed for multiple first memory cells (i.e., performing read operations on the first memory cells using multiple higher read voltage levels). If the Disturb resolution module determines that read retry is needed, it can send a read retry command to the Read retry module.
[0107] After receiving the read retry instruction, the read retry module can sequentially read voltages at multiple higher voltage levels from multiple first memory cells and send the read results obtained each time to the ECC module.
[0108] When the ECC module receives the reading result corresponding to the higher-level reading voltage, it can determine the FBC corresponding to the reading result of the higher-level reading voltage and send the corresponding FBC to the Disturb resolution module.
[0109] The Disturb resolution module determines whether a data refresh is needed based on the FBC corresponding to the reading results of the higher-level reading voltage, and if a data refresh is needed, it determines the type of disturbance.
[0110] When the disturbance type is read disturbance, the Disturb resolution module can obtain the error-corrected data corresponding to multiple first storage units from the ECC module, and write the error-corrected data into multiple first storage units to refresh the data in the first storage units, thus solving the impact of read disturbance on the storage units.
[0111] In the case of read interference, the Disturbance Resolution module can send the addresses of the third and fourth memory units to be read to the Read Retry module. The Read Retry module can then read the results from the third and fourth memory units based on their addresses and provide them to the ECC module for error correction. The Disturbance Resolution module can then obtain the corrected data from multiple first, third, and fourth memory units from the ECC module and write the corrected data into these memory units, thus mitigating the impact of write interference on the memory units.
[0112] In this embodiment, when the failure rate of the memory cell at the first address is determined to be high, the main interference experienced by the memory cell can be distinguished based on the specific failure status of the memory cell. Specifically, if the first number of failed memory cells in the low-resistance state is greater than the second number of failed memory cells in the high-resistance state, it indicates that the memory cell at the first address is mainly affected by read interference. Therefore, a write refresh can be performed on the memory cell at the first address to ensure the stability of the data stored therein. If the second number of failed memory cells in the high-resistance state is greater than the first number of failed memory cells in the low-resistance state, it indicates that the memory cell at the first address is mainly affected by write interference. Since write interference is influenced by surrounding memory cells, a write refresh can be performed on the memory cell at the first address and the memory cells surrounding it to ensure the stability of the data stored therein. Therefore, this application can distinguish between read interference and write interference affecting the memory cell and provides different write refresh methods for each type of interference, thereby improving the stability of data stored in the memory chip.
[0113] Based on the same inventive concept, embodiments of this application also provide a storage controller, which... Figure 3 The storage system shown includes a storage controller. During read operations on the storage chip, this storage controller can implement the storage chip control method provided in the above embodiments. This method determines whether read interference or write interference exists based on the failure rate of multiple first storage cells corresponding to a first address in the storage chip, and performs data refresh on the second storage cells affected by the read interference or write interference to eliminate its impact. The process by which the storage controller implements the storage chip control method can be referred to the above method embodiments, and will not be repeated here.
[0114] Based on the same inventive concept, embodiments of this application also provide a storage system, the storage controller. Figure 3 The storage system shown includes a storage controller and one or more storage chips. During read operations on the storage chips, the storage controller can implement the storage chip control method provided in the above embodiments to determine whether read interference or write interference exists based on the failure rate of multiple first storage cells corresponding to a first address in the storage chip, and perform data refresh on the second storage cells affected by the read interference or write interference to eliminate its effects. The process by which the storage controller implements the storage chip control method can be referred to the above method embodiments, and will not be repeated here.
[0115] In this application, the terms "first," "second," etc., are used to distinguish identical or similar items with substantially the same function. It should be understood that there is no logical or temporal dependency between "first" and "second," nor does it limit the quantity or order of execution. It should also be understood that although the following description uses the terms "first," "second," etc., to describe various elements, these elements should not be limited by the terms. These terms are merely used to distinguish one element from another. In this application, the term "at least one" means one or more, and the term "multiple" means two or more.
[0116] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A control method of a memory chip, characterized by, The method comprises: applying a read voltage to a plurality of first storage units corresponding to a first address; in response to a failure rate of the plurality of first storage units being greater than a first threshold value, refreshing data stored in a plurality of second storage units, wherein the first threshold value is less than a second threshold value triggering uncorrectable error (UCE) of the storage chip, the plurality of second storage units are storage units affected by read interference or write interference, the plurality of second storage units are the plurality of first storage units, or the second storage units are the plurality of first storage units and storage units adjacent to the plurality of first storage units.
2. The method of claim 1, wherein, The response to the plurality of first storage units failure rate greater than a first threshold value, refreshing data stored in a plurality of second storage units, comprising: in response to the plurality of first storage units failure rate greater than a first threshold value, determining the interference type corresponding to the plurality of first storage units, the interference type is read interference or write interference; in the case of determining that the interference type is read interference, determining that the plurality of first storage units are a plurality of second storage units, and refreshing the data stored in the second storage units; in the case of determining that the interference type is read interference, determining that the plurality of first storage units and the storage units adjacent to the plurality of first storage units are second storage units, and refreshing the data stored in the second storage units.
3. The method of claim 2, wherein, The determination of the interference type corresponding to the plurality of first storage units comprises: in the plurality of first storage units, determining the proportion of the number of failed low resistance state first storage units in the total number of failed first storage units; in the case that the proportion is greater than a third threshold value, determining that the interference type is read interference, and in the case that the proportion is less than or equal to the third threshold value, determining that the interference type is write interference.
4. The method according to any one of claims 1 to 3, characterized in that, The application of a read voltage to a plurality of first storage units corresponding to a first address comprises: applying a plurality of gear read voltages to a plurality of first storage units corresponding to a first address, the plurality of gear read voltages increasing in turn; The response to the plurality of first storage units failure rate greater than a first threshold value, refreshing data stored in a plurality of second storage units, comprising: in response to the failure rate obtained by applying each gear read voltage to the plurality of first storage units being greater than the first threshold value, refreshing data stored in a plurality of second storage units.
5. The method of claim 4, wherein, After applying a plurality of gear read voltages to a plurality of first storage units corresponding to a first address, the method further comprises: performing error correction processing on the target read data to obtain error correction processed read data, the target read data being a set of read data corresponding to the lowest failure rate in a plurality of sets of read data obtained by applying a plurality of gear read voltages respectively; The refreshing of the data stored in the plurality of second storage units comprises: writing the error correction processed read data into the first storage units included in the plurality of second storage units.
6. The method of claim 2, wherein, The storage units adjacent to the plurality of first storage units comprise third storage units adjacent to the plurality of first storage units in the same bit line or word line, and the method further comprises: A fourth storage unit adjacent to the third storage unit on the same bit line or the same word line is determined as a second storage unit.
7. The method of claim 3, wherein, The third threshold value is between one-half and four-fifths.
8. The method according to any one of claims 1 to 7, characterized in that, The first storage unit is a phase change storage unit.
9. A storage controller, comprising: The storage controller is connected with the storage chip, and the storage controller is configured to: apply a read voltage to a plurality of first storage units corresponding to a first address in the storage chip; in response to a failure rate of the plurality of first storage units being greater than a first threshold value, refresh data stored in a plurality of second storage units, wherein the first threshold value is less than a second threshold value triggering uncorrectable error (UCE) of the storage chip, the plurality of second storage units are storage units affected by read interference or write interference, the plurality of second storage units are the plurality of first storage units, or the second storage units are the plurality of first storage units and storage units adjacent to the plurality of first storage units.
10. The storage controller of claim 9, wherein, The storage controller is configured to: in response to the failure rate of the plurality of first storage units being greater than the first threshold value, determine a type of interference corresponding to the plurality of first storage units, the type of interference being read interference or write interference; in a case where the type of interference is determined to be read interference, determine the plurality of first storage units as the plurality of second storage units, and refresh data stored in the second storage units; in a case where the type of interference is determined to be read interference, determine the plurality of first storage units and storage units adjacent to the plurality of first storage units as the second storage units, and refresh data stored in the second storage units.
11. The storage controller of claim 10, wherein, The storage controller is configured to: determine, among the plurality of first storage units, a proportion of a number of failed low-resistance first storage units in a total number of failed first storage units; in a case where the proportion is greater than a third threshold value, determine the type of interference to be read interference, and in a case where the proportion is less than or equal to the third threshold value, determine the type of interference to be write interference.
12. The storage controller of any one of claims 9 to 11, wherein, The storage controller is configured to: apply a plurality of levels of read voltage to the plurality of first storage units corresponding to the first address, the plurality of levels of read voltage increasing in turn; in response to a failure rate obtained by applying each level of read voltage to the plurality of first storage units being greater than the first threshold value, refresh data stored in a plurality of second storage units.
13. The storage controller of claim 12, wherein, The storage controller is further configured to: perform error correction processing on target read data to obtain read data after error correction processing, the target read data being a group of read data corresponding to the lowest failure rate among a plurality of groups of read data obtained by applying the plurality of levels of read voltage respectively; write the read data after error correction processing into a first storage unit included in the plurality of second storage units.
14. The storage controller of claim 10, wherein, The storage controller is further configured to: determine a fourth storage unit adjacent to the third storage unit on the same bit line or the same word line as a second storage unit.
15. The storage controller of claim 11, wherein, The third threshold value is between one-half and four-fifths.
16. The storage controller of any one of claims 9 to 15, wherein, The first storage unit is a phase change storage unit. The first storage unit is a phase change storage unit.
17. A storage system, characterized by The storage system comprises the storage controller according to any one of claims 9 to 16, and at least one storage chip connected with the storage controller.
18. An electronic device, comprising: The electronic device comprises a processor and the storage system according to claim 17. The processor is configured to send a read-write instruction to the storage system, so that the storage system implements a read-write operation.