EFuse fuse unit circuit integrated with dynamic current compensation module

Abstract

The invention provides an eFuse fuse unit circuit integrated with a dynamic current compensation module, which belongs to the technical field of semiconductor memorizers, and comprises a digital control module, a bias circuit fuse unit output module, divider resistors R1, R3 and R4 connected with the bias circuit, and a fuse programming module, when a low-level control signal is input to the EN1 end of the fuse programming module, an NMOS tube N13 of the fuse programming module is opened, a resistor R0 of the fuse programming module starts fuse programming through large current, and after the fuse programming is completed, a silicification layer on the resistor R0 is fused to enable the resistor R0 to be converted into a high-resistance state from a low-resistance state, and when the resistance value of the resistor R0 is larger than the resistance values of the divider resistors R1, R3 and R4, the resistor R0 is switched to the high-resistance state from the low-resistance state. At the moment, the output Y is turned from 1 to 0, and the fuse unit output module outputs an output signal to other circuits for control. The circuit has the advantages of low power consumption, high stability and wide-range current regulation capability.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor memory technology, and specifically relates to an eFuse fuse unit circuit with an integrated dynamic current compensation module. Background Technology

[0002] eFuse is a one-time programmable memory that stores data by melting a metal fuse; once data is written, it cannot be modified or erased. This technology is widely used to store sensitive information such as unique identifiers (IDs) and encryption keys to ensure data security and integrity. In modern SoC designs, eFuse is used to prevent hacking and unauthorized access; its built-in precision control and multiple protection features can quickly cut off abnormal currents, offering superior response speed and reliability compared to traditional solutions.

[0003] like Figure 3 As shown, the purpose of traditional fuse circuits is to configure different parameters, such as clock frequency and pin functions, according to the chip's application and function during the manufacturing process. These parameters are usually set through fuses. During use, if the chip's configuration needs to be changed, the fuses must be reset. Furthermore, traditional fuses are independent components within the chip, occupying a large amount of space.

[0004] Compared to traditional fuse circuits, the eFuse fuse unit structure of this invention is a one-time programmable memory that changes the circuit's on / off state by melting the silicide layer on a polycrystalline resistor, transforming it from a low-resistance state to a high-resistance state. Once data is written, it cannot be modified or erased. The eFuse in this invention can be used in various application scenarios, such as chip protection, power management, and circuit calibration. In chip protection, the eFuse can prevent circuit damage from overvoltage or overcurrent, and can also be used for tampering and anti-hacking. In power management, the eFuse can control current and voltage to ensure normal circuit operation. In circuit calibration, the eFuse can calibrate circuit parameters such as clock frequency and current bias. In summary, the advantages of the eFuse are small size, low power consumption, high programmability, high reliability, and resistance to erasure. It can be widely used to store sensitive information such as unique identification codes (IDs) and encryption keys to ensure data security and integrity. In modern SoC design, eFuse is used to prevent hacking and unauthorized access. Its built-in precision control and multiple protection features can quickly cut off abnormal current, and its response speed and reliability are superior to traditional fuse structures.

[0005] Traditional fuses used as the basic circuit protection device have several drawbacks in practical applications. The fusing value is greatly affected by the ambient temperature because the alloy material properties of traditional fuses drift with temperature changes. They may melt falsely at high temperatures, and the response is delayed at low temperatures, making the protection threshold uncontrollable. Furthermore, the fusing accuracy is low, the fixed fusing curve cannot adapt to dynamic loads (such as motor starting surges), and the error range is often ±20%, which is difficult to meet the requirements of precision electronic equipment.

[0006] To address the aforementioned issues, while the low cost and anti-interference characteristics of traditional fuses remain valuable in simple scenarios, the need for intelligent and maintenance-free systems is driving the accelerated replacement of traditional fuses with electronic fuses such as eFuse in order to save chip area. Summary of the Invention

[0007] This invention addresses the problems existing in the prior art by providing an eFuse unit circuit with an integrated dynamic current compensation module. It has higher integration, saves more chip area, reduces the impact of transient current on the system, adapts to complex operating conditions, has higher safety, and allows for programmable current and voltage thresholds. It can dynamically match load changes and adapt to application scenarios such as battery aging and temperature fluctuations.

[0008] To solve the above technical problems, the present invention provides the following technical solution: 1. An eFuse fuse unit circuit with an integrated dynamic current compensation module, characterized in that it includes: a digital control module, and a bias circuit and a fuse unit output module respectively connected to the digital control module, wherein the bias circuit is connected to the fuse unit output module, and further includes voltage divider resistors R1, R3, R4, and a fuse programming module, wherein the voltage divider resistors R1, R3, R4 are connected to the bias circuit, and the fuse programming module is connected to the fuse unit output module;

[0009] The bias circuit structure provides a stable bias current, and the digital control module is used to control the bias circuit to generate the bias current.

[0010] When a low-level control signal is input to the EN1 terminal of the fuse programming module, the NMOS transistor N13 of the fuse programming module is turned on. A large current flows through the resistor R0 of the fuse programming module to begin the fuse programming process. After programming is complete, the silicon layer on resistor R0 is melted, causing R0 to change from a low-resistance state to a high-resistance state. When the resistance of R0 is greater than the resistance values ​​of the voltage divider resistors R1, R3, and R4, programming is complete. At this point, the output Y flips from 1 to 0.

[0011] The fuse unit output module outputs the output signal of the entire fuse unit circuit to other circuit controls.

[0012] Furthermore, the aforementioned digital control module includes: PMOS transistors P1 and P2, NMOS transistors N1 and N2, the gate of NMOS transistor N1 being connected to the gate of PMOS transistor P1, the gate of NMOS transistor N2, and the EN terminal, and receiving the bias circuit switching digital signal; the sources of NMOS transistors N1 and NMOS transistor N2 being grounded, the drain of PMOS transistor P1 being connected to the source of NMOS transistor N2 and the gate of PMOS transistor P2, and the source of PMOS transistor P1 being connected to the power supply; the drain of PMOS transistor P2 being connected to the bias circuit and the output module respectively.

[0013] PMOS transistor P1 and NMOS transistor N2 form an inverter whose output is supplied to the gate of PMOS transistor P2, which is connected to the power supply. In other words, PMOS transistor P2 acts as a pull-up transistor for the bias circuit.

[0014] Furthermore, the aforementioned bias circuit includes: PMOS transistors P3, P4, P5, and P6, and NMOS transistors N3, N4, N5, N6, N7, N8, and N9.

[0015] The gate of PMOS transistor P3 is connected to the gate of PMOS transistor P2 and is also connected to the power supply.

[0016] The source of PMOS transistor P3 is connected to the drain of PMOS transistor P5, the gate of PMOS transistor P3, the gate of PMOS transistor P7, and the gate of PMOS transistor P4, and is connected to the drain of PMOS transistor P2 of the digital control module.

[0017] The source of PMOS transistor P5 is connected to the source of NMOS transistor N3, and the source of PMOS transistor P4 is connected to the drain of NMOS transistor N5, the gate of NMOS transistor N5, the gate of NMOS transistor N4, and the gate of NMOS transistor N6.

[0018] The source of PMOS transistor P6 is connected to the drain of NMOS transistor N6 and the gate of NMOS transistor N8; the source of NMOS transistor N6 is connected to the drain of NMOS transistor N8 and connected to the fuse unit output module; the source of NMOS transistor N8 is grounded; the gate of PMOS transistor P6 is connected to the gate of PMOS transistor P3.

[0019] The source of NMOS transistor N7 is connected to the drain of NMOS transistor N9. The gate of NMOS transistor N7 is connected to the gate of NMOS transistor N4 and the gate of NMOS transistor N6, and is connected to the fuse unit output module. The drain of NMOS transistor N7 and the source of NMOS transistor N9 are grounded.

[0020] The MINUS terminals of resistors R1, R3, and R4 are connected to the drains of PMOS transistors P3, P6, and P4, respectively.

[0021] Furthermore, the aforementioned fuse programming module includes: PMOS transistor P8, NMOS transistors N10, NMOS transistors N11, NMOS transistors N12, and NMOS transistors N13;

[0022] The gate of PMOS transistor P8 is connected to the gate of NMOS transistor N10 and connected to the EN1 terminal to receive the fuse programming digital signal. The source of PMOS transistor P8 is grounded, and the drain of PMOS transistor P8 is connected to the drain of NMOS transistor N10, the drain of NMOS transistor N11, and the gate of NMOS transistor N13.

[0023] The gate of NMOS transistor N11 is connected to the power supply of the gate of NMOS transistor N12; the source of NMOS transistor N11 is connected to the drain of NMOS transistor N12; the source of NMOS transistor N12 and the source of NMOS transistor N13 are grounded.

[0024] The drain of NMOS transistor N13 is connected to one end of resistor R0; the other end of resistor R0 is connected to the fuse unit output module.

[0025] Furthermore, the aforementioned fuse unit output module includes: resistor R2, PMOS transistor P9, PMOS transistor P10, PMOS transistor P11, PMOS transistor P12, PMOS transistor P13, NMOS transistor N14, NMOS transistor N15, NMOS transistor N16, NMOS transistor N17, and NMOS transistor N18;

[0026] The source of PMOS transistor P9 is connected to the power supply, the gate of PMOS transistor P9 is connected to the MINUS terminal of resistor R2, the PLUS terminal of resistor R2 is grounded, and the drain of PMOS transistor P9 is connected to the other end of resistor R0.

[0027] The gate of PMOS transistor P10 is connected to the gate of PMOS transistor P3, the drain of PMOS transistor P2, and the gate of PMOS transistor P6 in the bias circuit. The drain of PMOS transistor P10 is connected to one end of resistor R0 and the drain of NMOS transistor N13. The source of PMOS transistor P10 is connected to the drain of NMOS transistor N14, the gate of PMOS transistor P11, and the gate of NMOS transistor N16.

[0028] The drain of PMOS transistor P13 and the drain of NMOS transistor N17 are connected;

[0029] The gate of NMOS transistor N14 serves as the first connection terminal between the fuse unit output module and the bias circuit, and is connected to the gate of NMOS transistor N7. The source of NMOS transistor N14 is connected to the drain of NMOS transistor N15.

[0030] The gate of NMOS transistor N15 serves as the second connection terminal between the fuse unit output module and the bias circuit, and is connected to the source of PMOS transistor P6. The source of NMOS transistor N15 is grounded.

[0031] The source of PMOS transistor P11 is connected to the power supply, and the drain of PMOS transistor P11 is connected to the drain of NMOS transistor N16, the gate of PMOS transistor P12, and the gate of NMOS transistor N18; the source of NMOS transistor N16 is grounded.

[0032] The source of PMOS transistor P12 is connected to the power supply, the drain of PMOS transistor P12 is connected to the source of PMOS transistor P13, the source of NMOS transistor N17 is connected to the drain of NMOS transistor N18, and the source of NMOS transistor N18 is grounded.

[0033] The gate of PMOS transistor P13 is connected to the FDLP clock control signal, and the gate of NMOS transistor N17 is connected to the FDLN (clock control signal).

[0034] Furthermore, the resistance values ​​of the aforementioned resistors R1, R3, and R4 are 5K ohms.

[0035] Furthermore, the aforementioned resistor R0 is a poly resistor.

[0036] Compared with the prior art, the beneficial technical effects of the present invention using the above technical solution are as follows:

[0037] 1. The eFuse fuse unit structure in this invention has a higher integration density and saves more chip area. Compared with the traditional fuse solution, it can save about 90% of the chip area.

[0038] 2. The programming process of the eFuse fuse unit structure in this invention is intuitive and controllable.

[0039] 3. In this invention, the fuse resistor R0 adopts a poly resistor structure, which has stable impedance in the unprogrammed state, and its resistance value can be adjusted after programming.

[0040] 4. The eFuse fuse unit structure in this invention can still be programmed after the CP test (Chip Probing Test), which optimizes product performance and reduces production costs.

[0041] 5. The present invention has a bias circuit and can control whether it is turned on or off, so compared with the conventional eFuse, the static power consumption of the present invention is basically 0.

[0042] In summary, this invention improves upon the shortcomings of traditional fuse structures, saving chip area, and also optimizes static power consumption compared to conventional eFuse. Attached Figure Description

[0043] Figure 1 The digital control module and bias circuit diagram of the present invention are shown below;

[0044] Figure 2 This is a circuit diagram of the fuse unit output module of the present invention.

[0045] Figure 3 It is a conventional eFuse cell structure. Detailed Implementation

[0046] To better understand the technical content of the present invention, specific embodiments are described below in conjunction with the accompanying drawings.

[0047] In this invention, various aspects of the invention are described with reference to the accompanying drawings, in which numerous illustrative embodiments are shown. Embodiments of the invention are not limited to those depicted in the drawings. It should be understood that the invention is implemented through any of the various concepts and embodiments described above, as well as the concepts and embodiments described in detail below, because the concepts and embodiments disclosed herein are not limited to any particular implementation. Furthermore, some aspects of the invention disclosed may be used alone or in any suitable combination with other aspects of the invention disclosed.

[0048] like Figure 1 and Figure 2 As shown, this embodiment provides an eFuse fuse unit circuit with an integrated dynamic current compensation module, including: a digital control module, and a bias circuit and a fuse unit output module respectively connected to the digital control module. The bias circuit is connected to the fuse unit output module. It also includes voltage divider resistors R1, R3, and R4, and a fuse programming module. The voltage divider resistors R1, R3, and R4 are connected to the bias circuit, and the fuse programming module is connected to the fuse unit output module. In this embodiment, the resistance values ​​of R1, R3, and R4 are 5KΩ or 1KΩ.

[0049] The bias circuit structure provides a stable bias current, and the digital control module is used to control the bias circuit to generate the bias current.

[0050] When a low-level control signal is input to the EN1 terminal of the fuse programming module, the NMOS transistor N13 of the fuse programming module is turned on, and a large current flows through the resistor R0 of the fuse programming module to start the fuse programming. After programming is completed, the silicon layer on the resistor R0 is melted, causing the resistor R0 to change from a low resistance state to a high resistance state. When the resistance value of R0 is greater than the resistance values ​​of the voltage divider resistors R1, R3, and R4, the programming is completed. At this time, the output Y flips from 1 to 0. The fuse unit output module outputs the output signal of the entire fuse unit circuit to other circuits for control. R0 uses a poly resistor as the fuse resistor.

[0051] The digital control module includes: PMOS transistors P1 and P2, NMOS transistors N1 and N2. The gate of NMOS transistor N1 is connected to the gate of PMOS transistor P1, the gate of NMOS transistor N2, and the EN terminal to receive the digital signal from the bias circuit. The sources of NMOS transistors N1 and N2 are grounded. The drain of PMOS transistor P1 is connected to the source of NMOS transistor N2 and the gate of PMOS transistor P2. The source of PMOS transistor P1 is connected to the power supply. The drain of PMOS transistor P2 is connected to the bias circuit and the output module respectively.

[0052] PMOS transistor P1 and NMOS transistor N2 form an inverter whose output is supplied to the gate of PMOS transistor P2, which is connected to the power supply. In other words, PMOS transistor P2 acts as a pull-up transistor for the bias circuit.

[0053] The bias circuit includes: PMOS transistors P3, P4, P5, and P6; and NMOS transistors N3, N4, N5, N6, N7, N8, and N9.

[0054] The gate of PMOS transistor P3 is connected to the gate of PMOS transistor P2 and is also connected to the power supply.

[0055] The source of PMOS transistor P3 is connected to the drain of PMOS transistor P5, the gate of PMOS transistor P3, the gate of PMOS transistor P7, and the gate of PMOS transistor P4, and is connected to the drain of PMOS transistor P2 of the digital control module.

[0056] The source of PMOS transistor P5 is connected to the source of NMOS transistor N3, which is an inverting transistor. The source of PMOS transistor P4 is connected to the drain of NMOS transistor N5, the gate of NMOS transistor N5, the gate of NMOS transistor N4, and the gate of NMOS transistor N6.

[0057] The source of PMOS transistor P6 is connected to the drain of NMOS transistor N6 and the gate of NMOS transistor N8; the source of NMOS transistor N6 is connected to the drain of NMOS transistor N8 and connected to the fuse unit output module; the source of NMOS transistor N8 is grounded; the gate of PMOS transistor P6 is connected to the gate of PMOS transistor P3.

[0058] The source of NMOS transistor N7 is connected to the drain of NMOS transistor N9. The gate of NMOS transistor N7 is connected to the gate of NMOS transistor N4 and the gate of NMOS transistor N6, and is connected to the fuse unit output module. The drain of NMOS transistor N7 and the source of NMOS transistor N9 are grounded.

[0059] The MINUS terminals of resistors R1, R3, and R4 are connected to the drains of PMOS transistors P3, P6, and P4, respectively.

[0060] The fuse programming module includes: PMOS transistor P8, NMOS transistors N10, NMOS transistors N11, NMOS transistors N12, and NMOS transistors N13;

[0061] The gate of PMOS transistor P8 is connected to the gate of NMOS transistor N10 and connected to the EN1 terminal to receive the fuse programming digital signal. The source of PMOS transistor P8 is grounded, and the drain of PMOS transistor P8 is connected to the drain of NMOS transistor N10, the drain of NMOS transistor N11, and the gate of NMOS transistor N13.

[0062] The gate of NMOS transistor N11 is connected to the power supply of the gate of NMOS transistor N12; the source of NMOS transistor N11 is connected to the drain of NMOS transistor N12; the source of NMOS transistor N12 and the source of NMOS transistor N13 are grounded.

[0063] The drain of NMOS transistor N13 is connected to one end of resistor R0; the other end of resistor R0 is connected to the fuse unit output module.

[0064] The fuse unit output module includes: resistor R2, PMOS transistors P9, PMOS transistors P10, PMOS transistors P11, PMOS transistors P12, PMOS transistors P13, NMOS transistors N14, NMOS transistors N15, NMOS transistors N16, NMOS transistors N17, and NMOS transistors N18;

[0065] The source of PMOS transistor P9 is connected to the power supply, the gate of PMOS transistor P9 is connected to the MINUS terminal of resistor R2, the PLUS terminal of resistor R2 is grounded, and the drain of PMOS transistor P9 is connected to the other end of resistor R0.

[0066] The gate of PMOS transistor P10 is connected to the gate of PMOS transistor P3, the drain of PMOS transistor P2, and the gate of PMOS transistor P6 in the bias circuit. The drain of PMOS transistor P10 is connected to one end of resistor R0 and the drain of NMOS transistor N13. The source of PMOS transistor P10 is connected to the drain of NMOS transistor N14, the gate of PMOS transistor P11, and the gate of NMOS transistor N16.

[0067] The drain of PMOS transistor P13 and the drain of NMOS transistor N17 are connected;

[0068] The gate of NMOS transistor N14 serves as the first connection terminal between the fuse unit output module and the bias circuit, and is connected to the gate of NMOS transistor N7. The source of NMOS transistor N14 is connected to the drain of NMOS transistor N15.

[0069] The gate of NMOS transistor N15 serves as the second connection terminal between the fuse unit output module and the bias circuit, and is connected to the source of PMOS transistor P6. The source of NMOS transistor N15 is grounded.

[0070] The source of PMOS transistor P11 is connected to the power supply, and the drain of PMOS transistor P11 is connected to the drain of NMOS transistor N16, the gate of PMOS transistor P12, and the gate of NMOS transistor N18; the source of NMOS transistor N16 is grounded.

[0071] The source of PMOS transistor P12 is connected to the power supply, the drain of PMOS transistor P12 is connected to the source of PMOS transistor P13, the source of NMOS transistor N17 is connected to the drain of NMOS transistor N18, and the source of NMOS transistor N18 is grounded.

[0072] The gate of PMOS transistor P13 is connected to the FDLP clock control signal, and the gate of NMOS transistor N17 is connected to the FDLN (clock control signal).

[0073] In this embodiment, specifically, the substrates of PMOS transistors P2, P3, P4, P5, P6, P7, and P10 are all connected to the power supply, while the substrates of NMOS transistors N3, N4, N5, N6, N7, N8, N9, N14, and N15 are all grounded.

[0074] R0 uses a poly resistor as the fuse to avoid introducing defects to the thin gate oxide layer and its silicide substrate during the formation of metal silicides. Therefore, this invention adopts a polysilicon interconnect structure. During programming, under the influence of a high current density between the two electrodes, the metal atoms will migrate along the direction of electron movement. As the current density continues to increase, electromigration also increases. If electromigration is intense, atomic accumulation will occur at the anode of the polysilicon fuse chain, forming "hills." At this time, the cathode will form voids due to the shortage of atoms, ultimately leading to a circuit break and completing the programming. This phenomenon is called electromigration (EM). Electromigration is the essence of fuse failure. The current relationship for an example of electromigration is:

[0075]

[0076] After programming, the fuse resistance value increases several times compared to its initial value of approximately 20 to 150 ohms.

[0077] Because resistors R1, R3, and R4 in the bias current module have equal values, corresponding to the three bias currents respectively, and to ensure more stable bias current, the NMOS transistor N3 in the main bias circuit is made into an inverting ratio transistor. When the resistance of R0 is less than the resistances of R1, R3, and R4, since the currents of N14 and N15 are constant, the current flowing through PMOS transistor P10 is greater than the currents of N14 and N15, so the output terminal will not flip. When the resistance of R0 is greater than the resistances of R1, R3, and R4, since the currents of N14 and N15 are constant, the current flowing through PMOS transistor P10 is less than the currents of N14 and N15, so the output terminal will flip immediately. Furthermore, because the bias circuit uses a Cascode structure, its stability is stronger and its response speed is faster. Therefore, when the resistance of R0 is greater than 5KΩ (R1=R3=R4=5KΩ), the output terminal will flip immediately.

[0078] In summary, this example provides an eFuse unit circuit with an integrated dynamic current compensation module, which features low power consumption, high stability, adaptability to complex operating conditions, higher safety, programmable current and voltage thresholds, dynamic matching of load changes, and adaptability to application scenarios such as battery aging and temperature fluctuations.

[0079] While the present invention has been described above with reference to preferred embodiments, it is not intended to limit the invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the claims.

Claims

1. An eFuse fuse cell circuit integrated with a dynamic current compensation module, characterized by, The application relates to a fuse unit circuit, which comprises a digital control module, a bias circuit and a fuse unit output module connected with the digital control module respectively, a voltage dividing resistor R1, R3 and R4 connected with the bias circuit, and a fuse burning module connected with the fuse unit output module. The bias circuit structure provides stable bias current, and the digital control module is used for controlling the bias circuit to generate bias current. When a low-level control signal is input at the EN1 end, the NMOS tube N13 of the fuse burning module is opened, the resistance R0 of the fuse burning module passes through a large current to start fuse burning, and when the silicon layer on the resistance R0 is fused and broken after the fuse burning is completed, the resistance R0 is converted from a low resistance into a high resistance state, and the resistance value of the resistance R0 is greater than that of the voltage dividing resistor R1, R3 and R4, the fuse burning is completed, and the output Y is inverted from 1 to 0. The fuse unit output module outputs the output signal of the whole fuse unit circuit to other circuit control. The digital control module comprises PMOS tubes P1 and P2, NMOS tubes N1 and N2, the gate of the NMOS tube N1 is connected with the gate of the PMOS tube P1, the gate of the NMOS tube N2 and the EN end, and receives a bias circuit switching digital signal; the sources of the NMOS tubes N1 and N2 are grounded, the drain of the PMOS tube P1 is connected with the source of the NMOS tube N2 and the gate of the PMOS tube P2, and the source of the PMOS tube P1 is connected with a power supply; the drain of the PMOS tube P2 is connected with the bias circuit and the output module respectively.

2. The eFuse fuse cell circuit of claim 1 integrated with a dynamic current compensation module, wherein, The PMOS tube P1 and the NMOS tube N2 constitute an inverter, and the gate of the PMOS tube P2 connected with the inverter is connected with the power supply, that is, the PMOS tube P2 is used as an upper pull tube of the bias circuit. The bias circuit comprises PMOS tubes P3, P4, P5 and P6, and NMOS tubes N3, N4, N5, N6, N7, N8 and N9, the gate of the PMOS tube P3 is connected with the gate of the PMOS tube P2 and connected with the power supply, 3. The eFuse fuse cell circuit of claim 2 integrated with a dynamic current compensation module, wherein, the source of the PMOS tube P3 is connected with the drain of the PMOS tube P5, the gate of the PMOS tube P3, the gate of the PMOS tube P7, the gate of the PMOS tube P4 and the drain of the PMOS tube P2 of the digital control module; the source of the PMOS tube P5 is connected with the source of the NMOS tube N3, the source of the PMOS tube P4 is connected with the drain of the NMOS tube N5, the gate of the NMOS tube N5, the gate of the NMOS tube N4 and the gate of the NMOS tube N6; the source of the PMOS tube P6 is connected with the drain of the NMOS tube N6 and the gate of the NMOS tube N8, the source of the NMOS tube N6 is connected with the drain of the NMOS tube N8 and connected with the fuse unit output module, the source of the NMOS tube N8 is grounded, and the gate of the PMOS tube P6 is connected with the gate of the PMOS tube P3. ​ The source of the NMOS tube N7 is connected with the drain of the NMOS tube N9, the gate of the NMOS tube N7 is connected with the gate of the NMOS tube N4 and the gate of the NMOS tube N6, and is connected with the fuse unit output module; the drain of the NMOS tube N7 and the source of the NMOS tube N9 are grounded; The MINUS ends of the resistors R1, R3 and R4 correspond to the drains of the PMOS tubes P3, P6 and P4 respectively.

4. The eFuse fuse cell circuit of claim 3 integrated with a dynamic current compensation module, wherein, The fuse burning module comprises a PMOS tube P8, NMOS tubes N10, N11, N12 and N13. The gate of the PMOS tube P8 is connected with the gate of the NMOS tube N10 and receives a fuse burning digital signal through the EN1 end, the source of the PMOS tube P8 is grounded, and the drain of the PMOS tube P8 is connected with the drains of the NMOS tubes N10, N11 and the gate of the NMOS tube N13; The gate of the NMOS tube N11 is connected with the gate of the NMOS tube N12 and is connected with the power supply, the source of the NMOS tube N11 is connected with the drain of the NMOS tube N12, and the source of the NMOS tube N12 and the source of the NMOS tube N13 are grounded; The drain of the NMOS tube N13 is connected with one end of the resistor R0, and the other end of the resistor R0 is connected with the fuse unit output module.

5. The eFuse fuse cell circuit of claim 4 integrated with a dynamic current compensation module, wherein, The fuse unit output module comprises resistors R2, PMOS tubes P9, P10, P11, P12, P13, NMOS tubes N14, N15, N16 and N17. The source of the PMOS tube P9 is connected with the power supply, the gate of the PMOS tube P9 is connected with the MINUS end of the resistor R2, the PLUS end of the resistor R2 is grounded, and the drain of the PMOS tube P9 is connected with the other end of the resistor R0; The gate of the PMOS tube P10 is connected with the gate of the PMOS tube P3, the drain of the PMOS tube P2 and the gate of the PMOS tube P6 of the bias circuit, the drain of the PMOS tube P10 is connected with one end of the resistor R0 and the drain of the NMOS tube N13, and the source of the PMOS tube P10 is connected with the drain of the NMOS tube N14, the gate of the PMOS tube P11, the gate of the NMOS tube N16, the drain of the PMOS tube P13 and the drain of the NMOS tube N17; The gate of the NMOS tube N14 is connected with the gate of the NMOS tube N7 as the first connection end of the fuse unit output module and the bias circuit, and the source of the NMOS tube N14 is connected with the drain of the NMOS tube N15, The gate of the NMOS tube N15 is connected with the source of the PMOS tube P6 as the second connection end of the fuse unit output module and the bias circuit, and the source of the NMOS tube N15 is grounded; The source of the PMOS tube P11 is connected with the power supply, the drain of the PMOS tube P11 is connected with the drain of the NMOS tube N16, the gate of the PMOS tube P12 and the gate of the NMOS tube N18, and the source of the NMOS tube N16 is grounded. The source of the PMOS transistor P12 is connected to a power supply, the drain of the PMOS transistor P12 is connected to the source of the PMOS transistor P13, the source of the NMOS transistor N17 is connected to the drain of the NMOS transistor N18, and the source of the NMOS transistor N18 is connected to a ground; The gate of the PMOS transistor P13 is connected to an FDLP clock control signal, and the gate of the NMOS transistor N17 is connected to an FDLN (clock control signal).

6. The eFuse fuse cell circuit of claim 1, wherein: The resistance values of the resistors R1, R3 and R4 are 5K ohms.

7. The eFuse fuse cell circuit of claim 1, wherein: The resistor R0 is a poly resistor.

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