Semiconductor memory device and stacked memory device

Abstract

The invention provides a semiconductor memory device and a stacked memory device. The semiconductor memory device includes a physical region, a direct access region, and a power manager. And the direct access area is directly in interface communication with an external test device. The power manager generates an internal power supply voltage based on one of a first power supply voltage, a second power supply voltage, and a power supply voltage, and supplies the internal power supply voltage to the direct access region. The power manager provides the second supply voltage to the physical region. The direct access area includes a test interface circuit, and in a direct access mode, the test interface circuit generates an internal clock signal based on an external clock signal, generates an internal test control signal by latching a test control signal received from the external test device based on the internal clock signal, and transmits the internal test control signal to the external test device. And providing the internal test control signal to the physical region.

Description

Technical Field

[0001] This disclosure provides a semiconductor memory device including a direct-access region that individually receives an operating voltage. This disclosure also provides semiconductor memory devices and stacked memory devices capable of performing tests in direct-access mode. The test operations can verify that each semiconductor chip in a stacked semiconductor device or wide input / output (I / O) structure is operating correctly. Background Technology

[0002] With advancements in semiconductor technology, integrated semiconductor devices, such as packaged components, have become more integrated and offer higher performance and quality. For this purpose, three-dimensional structures with multiple semiconductor chips stacked vertically and wide I / O structures are emerging.

[0003] Among these emerging technologies, the aim is to ensure that each semiconductor chip in a stacked semiconductor device or wide I / O structure operates properly. Summary of the Invention

[0004] In some implementations, stacked storage devices can adjust the timing of transmitting test control signals to the physical area.

[0005] In a first general aspect, a semiconductor memory device includes: a physical region, a direct access region, and a power manager. The physical region interfaces with an external memory controller. The direct access region interfaces directly with an external test device. The power manager generates an internal power supply voltage based on one of a first power supply voltage, a second power supply voltage, and a dedicated power supply voltage, and supplies the internal power supply voltage to the direct access region, wherein the first and second power supply voltages are provided externally, and the dedicated power supply voltage is received via a dedicated power pad. The power manager provides the second power supply voltage to the physical region. The direct access region includes test interface circuitry, and in direct access mode, the test interface circuitry generates an internal clock signal based on an external clock signal received from the external test device, generates an internal test control signal by latching a test control signal received from the external test device based on the internal clock signal, and provides the internal test control signal to the physical region.

[0006] In a second general aspect, a semiconductor memory device includes: a physical region and a direct access region. The physical region interfaces with an external memory controller. The direct access region interfaces directly with an external test device. The direct access region includes test interface circuitry, and in direct access mode, the test interface circuitry generates an internal clock signal based on an external clock signal received from the external test device, generates a first internal test control signal by latching a test control signal received from the external test device at a first timing point of the internal clock signal, generates a second internal test control signal by latching the first internal test control signal at a second timing point of the internal clock signal, and provides the physical region with one of the first internal test control signal and the second internal test control signal as an internal test control signal. The internal clock signal has different duty cycles at the first timing point and the second timing point.

[0007] In a third general aspect, a stacked memory device includes: a buffer die and a plurality of core dies. The buffer die includes interface circuitry and test interface circuitry. The interface circuitry communicates with an external host device in normal mode, and the test interface circuitry directly interfaces with an external test device in direct access mode. The plurality of core dies are stacked on the buffer die and connected to the buffer die via a plurality of through-silicon vias (TSVs). The buffer die includes a physical region, a direct access region, and a TSV region. The interface circuitry is disposed in the physical region, the test interface circuitry is disposed in the direct access region, and the TSVs are formed in the TSV region. In direct access mode, the test interface circuitry generates an internal clock signal based on an external clock signal received from the external test device, generates a first internal test control signal by latching a test control signal received from the external test device at a first timing point of the internal clock signal, generates a second internal test control signal by latching the first internal test control signal at a second timing point of the internal clock signal, and provides one of the first internal test control signal and the second internal test control signal to the physical region as an internal test control signal. The internal clock signal has different duty cycles at the first timing point and the second timing point.

[0008] Therefore, when testing semiconductor memory devices in direct access mode, the test interface circuit is less sensitive to power supply voltage, and test performance can be improved by separating the power supply areas of the memory region and peripheral circuitry region from the power supply area of ​​the test interface circuit (e.g., the direct access region), and by performing tests for various timing margins by adjusting the timing of the internal test control signal transmitted to the physical region, which is generated by latching the test control signal at different timing points of the internal clock signal. Attached Figure Description

[0009] Figure 1 This is a block diagram illustrating an example of a semiconductor system.

[0010] Figure 2 It shows Figure 1 A block diagram of an example of a semiconductor memory device.

[0011] Figure 3 It shows Figure 2 The arrangement of peripheral circuits in semiconductor memory devices.

[0012] Figure 4 It shows Figure 2 A circuit diagram of an example power manager in the example.

[0013] Figure 5 It shows Figure 4 The circuit diagram of the comparator in the power manager.

[0014] Figure 6 It shows Figure 2 A circuit diagram of an example power manager in the example.

[0015] Figure 7 It shows Figure 2 A circuit diagram of an example power manager in the example.

[0016] Figure 8 It is used for explanation Figure 7 A diagram illustrating an example of how the power manager operates.

[0017] Figure 9 It shows Figure 2 A block diagram of an example test interface circuit in a semiconductor memory device 200.

[0018] Figure 10 It shows Figure 9 A block diagram of an example of an internal clock generator in the test interface circuit.

[0019] Figure 11 It shows Figure 10 An example of the clock signal from the internal clock generator.

[0020] Figure 12 It shows Figure 9 A block diagram of an example of the first input circuit in the test interface circuit.

[0021] Figure 13 It shows Figure 9 A block diagram of an example of the first input circuit in the test interface circuit.

[0022] Figure 14 It shows Figure 12 and Figure 13 Timing diagram of example operation of the first input circuit.

[0023] Figure 15 It shows Figure 2 Semiconductor memory devices.

[0024] Figure 16 It shows Figure 15 A block diagram of an example of the input control circuit.

[0025] Figure 17 This is a diagram showing an example of a semiconductor package.

[0026] Figure 18 It shows Figure 17 A block diagram of an example of a stacked storage device.

[0027] Figure 19 It shows Figure 18 A block diagram of an example of the first core die in a stacked storage device.

[0028] Figure 20 It shows Figure 19 An example of the first memory bank array in the first core die.

[0029] Figure 21 It shows Figure 17 A block diagram of an example of a buffer die.

[0030] Figure 22 It shows Figure 18 An example of a buffer bare die.

[0031] Figure 23 This is a block diagram illustrating an example of a semiconductor system.

[0032] Figure 24 This is a flowchart illustrating an example of a method for testing semiconductor memory devices.

[0033] Throughout this application, the same reference numerals may refer to the same elements. Detailed Implementation

[0034] Figure 1This is a block diagram illustrating an example of a semiconductor system.

[0035] refer to Figure 1 The semiconductor system 100 includes a memory controller 110, a semiconductor memory device 200, an internal layer 1501, and a packaging substrate 160.

[0036] The semiconductor system 100 can be implemented in the form of a multi-chip package, a system-on-a-chip (SoC) or a system-in-package, or in the form of a stacked package that includes multiple packages.

[0037] The semiconductor memory device 200 and the memory controller 110 can be mounted onto the built-in layer 150 via microbumps 102. The built-in layer 150 can be mounted onto the package substrate 160 via bumps 104.

[0038] The storage controller 110 can typically be included in various processors such as central processing unit (CPU), graphics processing unit (GPU), and application processor (AP).

[0039] The storage controller 110 may include a physical region PHY 112, the semiconductor storage device 200 may include a physical region 210 and a direct access region DA 220, and the direct access region 220 may include a test interface circuit TIC 300.

[0040] Physical region 210 of semiconductor memory device 200 can be connected to physical region 112 of memory controller 110 via built-in layer 150. Interface circuitry for communication between semiconductor memory device 200 and memory controller 110 can be provided in each of physical regions 112 and 210. Each of physical regions 112 and 210 can be referred to as a physical layer.

[0041] Figure 2 It shows Figure 1 A block diagram of an example of a semiconductor memory device.

[0042] refer to Figure 2 The semiconductor storage device 200 may include a storage region MR, a peripheral circuit region PCR, a direct access region 220, and a power manager 400.

[0043] The storage region MR may include multiple storage cell arrays 250a, 250b, 250c and 250d, and each of the multiple storage cell arrays 250a, 250b, 250c and 250d may store data.

[0044] Peripheral circuit region PCR may include multiple peripheral circuits ( Figure 2The “PERI circuit” in the circuit includes 260a, 260b, 260c and 260d, and each of the multiple peripheral circuits 260a, 260b, 260c and 260d can control the corresponding memory cell array in the multiple memory cell arrays 250a, 250b, 250c and 250d.

[0045] Physical region 210 may include multiple channel interface circuits CH0_IF, CH1_IF, CH2_IF, and CH3_IF, and each of these circuits can interface with a corresponding memory cell array in multiple memory cell arrays 250a, 250b, 250c, and 250d through a corresponding peripheral circuit in multiple peripheral circuits 260a, 260b, 260c, and 260d. Multiple PHY bumps PB for interfacing with memory controller 110 may be formed on physical region 210.

[0046] The direct access area 220 may include a DA bump area 223, a DA probe area 221, and a test interface circuit 300.

[0047] In the DA bump region 223, multiple DA bumps (DABs) can be formed for interfacing with external test equipment via the built-in layer 150 to test the semiconductor memory device 200. In the DA probe region 221, multiple DA pads (DAPs) can be formed for interfacing with external test equipment to test the semiconductor memory device 200 without passing through the built-in layer 150. The PHY bumps (PB) and DA bumps (DABs) can be formed from microbumps, and the DA pads (DAPs) can be formed from pads larger than microbumps. For example, compared to the PHY bumps (PB) and DA bumps (DABs), the DA pads (DAPs) can be larger in physical size but fewer in number. Figure 2 In this configuration, the DA detection region 221 is formed below the physical region 210, and the DA bump region 223 is formed on one side of the physical region 210. However, the DA bump region 223 and the DA detection region 221 can be configured differently.

[0048] Test operations can be performed to test the semiconductor memory device 200 by entering direct access mode. In direct access mode, test data can be applied through the DA bumps (DAB) or DA pads (DAP) of the direct access area 220. The applied test data can be transmitted to physical area 210 and can be provided to each of the multiple memory cell arrays 250a, 250b, 250c, and 250d via interface circuitry in physical area 210.

[0049] In direct access mode, the test interface circuit 300 can receive external clock signals and test control signals from an external test device. It can generate an internal clock signal based on the external clock signal, generate a first internal test control signal by latching the test control signal at a first timing point of the internal clock signal, and generate a second internal test control signal by latching the first internal test control signal at a second timing point of the internal clock signal. It can also provide the physical area 210 with one of the first or second internal test control signals as the internal test control signal. The internal clock signal can have different duty cycles at the first and second timing points, and its frequency can be twice the frequency of the external clock signal.

[0050] Therefore, in direct access mode, the semiconductor memory device 200 can perform high-speed testing while adjusting the timing of transmitting the internal clock signal to the physical region 210.

[0051] The power manager 400 can receive a first power supply voltage VDD1 through the first power pad PPD1, and a second power supply voltage VDD2 through the second power pad PPD2. It can generate an internal power supply voltage VINT_DA based on one of the first power supply voltage VDD1 and the second power supply voltage VDD2, and can supply the internal power supply voltage VINT_DA to the direct access area 220.

[0052] A first power supply voltage VDD1 and a second power supply voltage VDD2 can be supplied to the storage region MR, and multiple storage cell arrays 250a, 250b, 250c, and 250d can operate based on the first power supply voltage VDD1 and the second power supply voltage VDD2. The second power supply voltage VDD2 can be supplied to the peripheral circuit region PCR and the physical region 210, and the peripheral circuit region PCR and the physical region 210 can operate based on the second power supply voltage VDD2.

[0053] The voltage level of the first power supply voltage VDD1 can be greater than the voltage level of the second power supply voltage VDD2.

[0054] In some implementations, the power manager 400 can receive a dedicated power supply voltage VDD2_DA through a dedicated power pad PPD3, generate an internal power supply voltage VINT_DA by power gating the dedicated power supply voltage VDD2_DA, and provide the internal power supply voltage VINT_DA to the direct access area 220.

[0055] In some implementations, the semiconductor memory device 200 may be a low latency width (LLW) I / O memory device.

[0056] Figure 3 It shows Figure 2 The arrangement of peripheral circuits in semiconductor memory devices.

[0057] refer to Figure 3 The peripheral circuit 260a includes a row decoder 261, a column decoder 262, and a data I / O circuit 263. Figure 2 The memory cell array 250a can be positioned between the row decoder 261 and the column decoder 262. The peripheral circuitry 260a may further include a clock buffer, I / O gate circuitry, memory bank control logic, and a sense amplifier, all associated with accessing the memory cell array 250a.

[0058] Figure 4 It shows Figure 2 A circuit diagram of an example power manager in the example.

[0059] refer to Figure 4 The power manager 400a includes a comparator 410 and a power transistor 420.

[0060] Power transistor 420 can be coupled between a first supply voltage VDD1 and an output node NO, and can generate an internal supply voltage VINT_DA at the output node NO by adjusting the first supply voltage VDD1 based on an adjustment voltage VR. Power transistor 420 may include a p-channel metal-oxide-semiconductor (PMOS) transistor having a source coupled to the first supply voltage VDD1, a gate receiving the adjustment voltage VR, and a drain coupled to the output node NO and providing the internal supply voltage VINT_DA.

[0061] Comparator 410 can generate an regulated voltage VR by comparing a reference voltage VREF and an internal power supply voltage VINT_DA, and can apply the regulated voltage VR to the gate of power transistor 420. Comparator 410 may have a negative input terminal for receiving the regulated voltage VR, a positive input terminal for receiving the internal power supply voltage VINT_DA, and an output terminal for providing the regulated voltage VR.

[0062] Comparator 410 and power transistor 420 can form a low dropout (LDO) regulator.

[0063] Figure 5 It shows Figure 4 Example circuit diagram of the comparator in the power manager.

[0064] refer to Figure 5 The power manager 400a includes a comparator 410 and a power transistor 420. The comparator 410 includes PMOS transistors 411, 412 and 417, n-channel metal-oxide-semiconductor (NMOS) transistors 413, 414 and 416, and a current source 415.

[0065] PMOS transistor 411 can be coupled between the first power supply voltage VDD1 and the first node N11 and has a gate coupled to the second node N12. PMOS transistor 412 can be coupled between the first power supply voltage VDD1 and the second node N12 and has a gate coupled to the second node N12. Therefore, PMOS transistors 411 and 412 can operate as current mirrors. PMOS transistor 411 can be connected in parallel with PMOS transistor 417 between the first power supply voltage VDD1 and the first node N11, and PMOS transistor 417 can have a gate that receives the mode signal DA_EN. The mode signal DA_EN can specify one of a direct access mode and a normal mode; the direct access mode can be specified when the mode signal DA_EN is at a logic high level, and the normal mode can be specified when the mode signal DA_EN is at a logic low level.

[0066] NMOS transistor 413 can be coupled between the first node N11 and the third node N13 and can have a gate that receives a reference voltage VREF. NMOS transistor 414 can be coupled between the second node N12 and the third node N13 and can have a gate coupled to the output node NO and receiving an internal power supply voltage VINT_DA.

[0067] Current source 415 can be coupled between third node N13 and fourth node N14 and can provide current flowing into ground voltage VSS when NMOS transistor 416 is turned on. NMOS transistor 416 can be coupled between fourth node N14 and ground voltage VSS and can have a gate that receives mode signal DA_EN. NMOS transistor 416 can be selectively turned on based on mode signal DA_EN. When mode signal DA_EN specifies direct access mode, NMOS transistor 416 is turned on, and current supplied from current source 415 can flow into ground voltage VSS.

[0068] The first node N11 can be coupled to the gate of the power transistor 420. When the mode signal DA_EN specifies the normal mode, the PMOS transistor 417 is turned on, the first node N11 is precharged based on the first supply voltage VDD1, and the power transistor 420 is turned off based on the voltage level of the first node N11.

[0069] When the mode signal DA_EN specifies the direct access mode, PMOS transistor 417 is turned off, and due to the voltage difference between the reference voltage VREF and the internal supply voltage VINT_DA, a difference exists between the current supplied from the first node N11 and the second node N12 to the third node N13, and the voltage level of the regulating voltage VR can be determined based on the current difference. Power transistor 420 can generate the internal supply voltage VINT_DA at the output node NO by regulating the first supply voltage VDD1 based on the regulating voltage VR.

[0070] Figure 6 It shows Figure 2 A circuit diagram of an example power manager in the example.

[0071] refer to Figure 6 The power manager 400b includes a power transistor 430.

[0072] The power transistor 430 may include a PMOS transistor having a source coupled to a dedicated power supply voltage VDD2_DA, a gate for receiving a power gating control signal PGCS, and a drain for providing an internal power supply voltage VINT_DA.

[0073] The power transistor 430 can generate an internal power supply voltage VINT_DA by power gating the dedicated power supply voltage VDD2_DA in response to a low-level activated power gating control signal PGCS in direct access mode, and can cut off the dedicated power supply voltage VDD2_DA in normal mode.

[0074] Figure 7 It shows Figure 2 A circuit diagram of an example power manager in the example.

[0075] refer to Figure 7 The power manager 400c includes a voltage detector 441, an oscillator 443, and a charge pump 445.

[0076] Voltage detector 441 can receive mode signal DA_EN and can generate decision signal DET by comparing internal power supply voltage VINT_DA with reference voltage VREF in direct access mode (e.g., when mode signal DA_EN specifies direct access mode).

[0077] Oscillator 443 can generate a pumped clock signal CLK_P by performing an oscillation operation based on the decision signal DET.

[0078] The charge pump 445 can generate the internal power supply voltage VINT_DA by performing pumping operations based on the pumping clock signal CLK_P and the second power supply voltage VDD2.

[0079] Figure 8 It is used for explanation Figure 7 A diagram illustrating an example of the operation of the power manager 400c.

[0080] refer to Figure 7 and Figure 8 When the mode signal DA_EN specifies the direct access mode (e.g., when the mode signal DA_EN has a logic high level), the voltage detector 441 can be enabled and can generate a decision signal DET by comparing the internal power supply voltage VINT_DA and the reference voltage VREF. For example, as Figure 8 As shown, the determination signal DET can maintain a high level in the section where the internal power supply voltage VINT_DA is lower than the reference voltage VREF, while it can maintain a low level in other sections.

[0081] The decision signal DET generated by voltage detector 441 is provided to oscillator 443, and oscillator 443 generates a pump clock signal CLK_P by performing an oscillation operation when the decision signal DET is high. As a result, Figure 8 As shown, in the pump clock signal CLK_P, there is a pulse-like signal in the section where the mode signal DA_EN is high and the charge pump 445 generates the internal power supply voltage VINT_DA, while there is no pulse-like signal in other sections.

[0082] In some implementations, charge pump 445 may include multiple charge pump circuits and control circuitry. Each of the multiple charge pump circuits may be enabled or disabled by the control circuitry and may perform pumping operations based on a pumping clock signal CLK_P and a second supply voltage VDD2.

[0083] Because the charge pump 445 generates the internal power supply voltage VINT_DA in direct access mode but not in normal mode, the voltage level of the internal power supply voltage VINT_DA is floated in normal mode.

[0084] exist Figures 4 to 8 In this system, the level of the internal power supply voltage VINT_DA can be adjusted by an external test device or storage controller 110 using the test mode register group (TMRS), fuse settings, or mode register.

[0085] The voltage level of the internal power supply voltage VINT_DA can be less than the first power supply voltage VDD1 and greater than the second power supply voltage VDD2.

[0086] As referenced above Figures 4 to 8As mentioned, when testing the semiconductor memory device 200 in direct access mode, the test interface circuit 300 is not very sensitive to the power supply voltage. Test performance can be improved by separating the power supply regions of the memory region MR and the peripheral circuit region PCR from the power supply region of the test interface circuit 300 (e.g., direct access region 220).

[0087] Figure 9 It shows Figure 2 A block diagram of an example test interface circuit in a semiconductor memory device 200.

[0088] refer to Figure 9 The test interface circuit 300 includes buffers 301, 303, and 305, an internal clock generator 310, a first input circuit 330, and a first data input circuit 350. The first input circuit 330 may be referred to as the input circuit.

[0089] Buffer 301 can respond to the activation of the mode signal DA_EN, which specifies the direct access mode, and can provide the internal clock generator 310 with the external clock signal DA_CLK received from the external test device. In direct access mode, the internal clock generator 310 can generate an internal clock signal PCLK based on the external clock signal DA_CLK and can provide the internal clock signal PCLK to the first input circuit 330 and the first data input circuit 350.

[0090] Buffer 303 can respond to the activation of the mode signal DA_EN specifying the direct access mode and can provide the first input circuit 330 with the test control signal DA_CA received from the external test device. In direct access mode, the first input circuit 330 can generate an internal test control signal DA_PCA by delaying the test control signal DA_CA by at least one time based on the internal clock signal PCLK.

[0091] The test control signal DA_CA can include commands and addresses associated with the test.

[0092] Buffer 305 can respond to the activation of the mode signal DA_EN, which specifies the direct access mode, and can provide the first data input circuit 350 with test data DA_DQ received from an external test device. In direct access mode, the first data input circuit 350 can generate internal test data DA_PDQ by latching the test data DA_DQ based on the internal clock signal PCLK.

[0093] The internal test control signal DA_PCA and the internal test data DA_PDQ can be provided Figure 2 Physical region 210 in the middle.

[0094] Figure 10 It shows Figure 9 A block diagram of an example of an internal clock generator in the test interface circuit.

[0095] refer to Figure 10 The internal clock generator 310 includes a phase shifter 311 and an XOR gate 315.

[0096] Phase shifter 311 can generate a first intermediate clock signal ICLK0 and a second intermediate clock signal ICLK90 with a 90-degree phase difference between them by shifting the phase of the external clock signal DA_CLK. XOR gate 315 can generate an internal clock signal PCLK by performing an XOR operation on the first intermediate clock signal ICLK0 and the second intermediate clock signal ICLK90.

[0097] Figure 11 It shows Figure 10 An example of the clock signal from the internal clock generator.

[0098] refer to Figure 10 and Figure 11 Phase shifter 311 can generate a first intermediate clock signal ICLK0 and a second intermediate clock signal ICLK90 with a 90-degree phase difference between them by shifting the phase of the external clock signal DA_CLK. XOR gate 315 can generate an internal clock signal PCLK' by performing an XOR operation on the first intermediate clock signal ICLK0 and the second intermediate clock signal ICLK90. Therefore, the frequency of the internal clock signal PCLK' can be greater than the frequency of the external clock signal DA_CLK.

[0099] exist Figure 11 In this context, the internal clock signal PCLK' can represent an ideal internal clock signal generated by the phase shifter 311 (e.g., an internal clock signal that is not affected by external factors or is not physically affected by the phase shifter 311 and / or the XOR gate 315), and the internal clock signal PCLK can represent an internal clock that is physically affected by the phase shifter 311 and / or the XOR gate 315 or affected by the transmission path of the direct access area 220.

[0100] Because the aforementioned effects may distort the duty cycle of the internal clock signal PCLK, the internal clock signal PCLK may have different duty cycles at the first timing point A0 and the second timing point A1. For example, the duty cycle of the internal clock signal PCLK may be less than 50% at the first timing point A0, and the duty cycle of the internal clock signal PCLK may be greater than 50% at the second timing point A1.

[0101] The test control signal DA_CA received from the external test device has a different margin when it is latched at the first timing point A0 compared to when it is latched at the second timing point A1. The external test device cannot select the first timing point A0 and the second timing point A1, and the semiconductor memory device 200 is tested based on the test control signal applied at each of the first timing point A0 and the second timing point A1.

[0102] Figure 12 It shows Figure 9 A block diagram of an example of the first input circuit in the test interface circuit.

[0103] refer to Figure 12 The first input circuit 330a includes a first D flip-flop 331, a second D flip-flop 333, and a multiplexer 335. Each of the first D flip-flop 331 and the second D flip-flop 333 may include an input terminal D, an output terminal Q, and a clock terminal CK. The first D flip-flop 331 and the second D flip-flop 333 can constitute a shift register.

[0104] The first D flip-flop 331 can output the first internal test control signal DA_CA1 by latching the test control signal DA_CA1 at the first timing point of the internal clock signal PCLK. The first D flip-flop 331 can also output the first internal test control signal DA_CA1 by latching the test control signal DA_CA at the rising edge of the internal clock signal PCLK and at the first timing point.

[0105] The second D flip-flop 333 can output the second internal test control signal DA_CA2 by latching the first internal test control signal DA_CA1 at the second timing point of the internal clock signal PCLK. Alternatively, the second D flip-flop 333 can output the second internal test control signal DA_CA2 by latching the first internal test control signal DA_CA1 at the rising edge of the internal clock signal PCLK and at the second timing point.

[0106] Multiplexer 335 can select one of the first internal test control signal DA_CA1 and the second internal test control signal DA_CA2 based on the selection signal DA_SEL1, and can output the selected one as the internal test control signal DA_PCA. Figure 2 The physical region 210 transmits the internal test control signal DA_PCA.

[0107] The selection signal DA_SEL1 can be set by the storage controller 110 or an external test device using TMRS and can be used to select one of the first internal test control signal DA_CA1 and the second internal test control signal DA_CA2.

[0108] Figure 13 It shows Figure 9 A block diagram of an example of the first input circuit in the test interface circuit.

[0109] refer to Figure 13 The first input circuit 330b includes a first D flip-flop 331, a second D flip-flop 333, a third D flip-flop 334, and a multiplexer 336. Each of the first D flip-flop 331, the second D flip-flop 333, and the third D flip-flop 334 may include an input terminal D, an output terminal Q, and a clock terminal CK. The first D flip-flop 331 and the second D flip-flop 333 can form a shift register.

[0110] The first D flip-flop 331 can output the first internal test control signal DA_CA1 by latching the test control signal DA_CA1 at the first timing point of the internal clock signal PCLK. The first D flip-flop 331 can also output the first internal test control signal DA_CA1 by latching the test control signal DA_CA at the rising edge of the internal clock signal PCLK and at the first timing point.

[0111] The second D flip-flop 333 can output the second internal test control signal DA_CA2 by latching the first internal test control signal DA_CA1 at the second timing point of the internal clock signal PCLK. Alternatively, the second D flip-flop 333 can output the second internal test control signal DA_CA2 by latching the first internal test control signal DA_CA1 at the rising edge of the internal clock signal PCLK and at the second timing point.

[0112] The third D flip-flop 334 can output the third internal test control signal DA_CA3 by latching the second internal test control signal DA_CA2 at the third timing point of the internal clock signal PCLK. Alternatively, the third D flip-flop 334 can output the third internal test control signal DA_CA3 by latching the second internal test control signal DA_CA2 at the rising edge of the internal clock signal PCLK and at the third timing point.

[0113] Multiplexer 336 can select one of the first internal test control signal DA_CA1, the second internal test control signal DA_CA2, and the third internal test control signal DA_CA3 based on the selection signal DA_SEL2, and can output the selected one as the internal test control signal DA_PCA. Figure 2 The physical region 210 transmits the internal test control signal DA_PCA.

[0114] The selection signal DA_SEL2 can be set by the storage controller 110 or an external test device using TMRS and can be used to select one of the first internal test control signal DA_CA1, the second internal test control signal DA_CA2, and the third internal test control signal DA_CA3.

[0115] Figure 14 It shows Figure 12 and Figure 13 Timing diagram of example operation of the first input circuit.

[0116] exist Figure 14 In this context, it is assumed that the first input circuit 330a and the first input circuit 330b operate based on the internal clock signal PCLK instead of the internal clock signal PCLK', and the mode signal DA_EN has a logic high level ("H").

[0117] In the following text, reference will be made to Figures 9 to 14 describe Figure 12 and Figure 13 Example operation of the first input circuits 330a and 330b.

[0118] The external clock signal DA_CLK and the test control signal DA_CA are input from the external test device to the internal clock generator 310 and the first input circuit 330. The test control signal DA_CA may include continuous signals AA, BB, CC, DD, and EE.

[0119] The first D flip-flop 331 can output a first internal test control signal DA_CA1 by latching the test control signal DA_CA at the rising edge of the internal clock signal PCLK and at the first timing point A0. Therefore, the first internal test control signal DA_CA1 can be delayed by half a period 0.5t DA_CLK relative to the test control signal DA_CA.

[0120] The second D flip-flop 333 can output the second internal test control signal DA_CA2 by latching the first internal test control signal DA_CA1 at the rising edge of the internal clock signal PCLK and at the second timing point A1. Therefore, the second internal test control signal DA_CA2 can be delayed relative to the test control signal DA_CA by the period 1tDA_CLK of the external clock signal DA_CLK.

[0121] The third D flip-flop 334 can output the third internal test control signal DA_CA3 by latching the second internal test control signal DA_CA2 at the rising edge of the internal clock signal PCLK and at the third timing point A2. Therefore, the second internal test control signal DA_CA2 can be delayed by one half-cycle 1.5t DA_CLK relative to the test control signal DA_CA.

[0122] Figure 15 It shows Figure 2 Semiconductor memory devices.

[0123] refer to Figure 15 The semiconductor memory device 200 includes a physical region 210, a direct access region 220, and a peripheral circuit region PCR. Figure 15 For simplicity, the storage area MR is not shown in the text.

[0124] Multiple first PHY bumps PB0<0:8> for receiving the normal control signal PHY_CA during normal operation and a second PHY bump PB1 for receiving the normal clock PHY_CLK during normal operation can be disposed on physical region 210. Multiple first DA pads DAP0<0:8> for receiving the test control signal DA_CA and a second DA pad DAP1 for receiving the external clock DA_CLK can be disposed on direct access region 220. Test interface circuitry 300 can be disposed in direct access region 220.

[0125] The test interface circuit 300 may include buffers 301 and 303, an internal clock generator 310, and a first input circuit 330. Buffer 301 can respond to the activation of the mode signal DA_EN specifying the direct access mode and can provide the internal clock generator 310 with an external clock signal DA_CLK received from an external test device. Buffer 303 can respond to the activation of the mode signal DA_EN specifying the direct access mode and can provide the first input circuit 330 with a test control signal DA_CA received from an external test device.

[0126] For reference Figure 9As mentioned, in direct access mode, the internal clock generator 310 can generate an internal clock signal PCLK based on the external clock signal DA_CLK and can provide the internal clock signal PCLK to the first input circuit 330 and the input control circuit 230 in the physical region 210. In direct access mode, the first input circuit 330 can generate an internal test control signal DA_PCA by delaying the test control signal DA_CA by at least one time based on the internal clock signal PCLK and can transmit the internal test control signal DA_PCA to the input control circuit 230 in the physical region 210.

[0127] The physical area 210 may include an interface circuit 211, an input control circuit 230, and an internal signal generator ISG 240.

[0128] The interface circuit 211 may include buffers 213 and 214, a second input circuit 215, and a clock generator 216.

[0129] In normal mode, buffer 213 can receive the clock signal PHY_CLK and provide the clock signal PHY_CLK to clock generator 216. Clock generator 216 can generate a normal clock signal PPCLK based on the clock signal PHY_CLK and provide the normal clock signal PPCLK to the second input circuit 215 and input control circuit 230.

[0130] In normal mode, buffer 214 can receive the normal control signal PHY_CA and provide the normal control signal PHY_CA to the second input circuit 215. The second input circuit 215 can generate an internal normal control signal PHY_PCA based on the normal clock signal PPCLK and can transmit the internal normal control signal PHY_PCA to the input control circuit 230.

[0131] The input control circuit 230 can receive the mode signal DA_EN, the internal clock signal PCLK, the internal test control signal DA_PCA, the normal clock signal PPCLK, and the internal normal control signal PHY_PCA.

[0132] The input control circuit 230 responds to the mode signal DA_EN that specifies the direct access mode. It can select the internal test control signal DA_PCA from the internal test control signal DA_PCA and the internal normal control signal PHY_PCA. It can generate the selected control signal IPCA by latching the internal test control signal DA_PCA based on the internal clock signal PCLK, and can provide the selected control signal IPCA to the internal signal generator 240.

[0133] The input control circuit 230 responds to the mode signal DA_EN of the specified normal mode, and can select the internal normal control signal PHY_PCA from the internal test control signal DA_PCA and the internal normal control signal PHY_PCA. It can generate the selected control signal IPCA by latching the internal normal control signal PHY_PCA based on the normal clock signal PPCLK, and can provide the selected control signal IPCA to the internal signal generator 240.

[0134] The internal signal generator 240 can generate an internal signal ICA based on a selected control signal IPCA and can provide the internal signal ICA to the peripheral circuit region PCR.

[0135] The test interface circuit 300 can generate internal test data by latching test data and can provide the internal test data to the input control circuit 230. The interface circuit 211 can generate internal normal data by latching normal data and can provide the internal normal data to the input control circuit 230. In direct access mode, the input control circuit 230 can provide internal test data to the storage region MR via the peripheral circuit region PCR, while in normal mode, the input control circuit 230 can provide internal normal data to the storage region MR via the peripheral circuit region PCR.

[0136] In normal mode, the normal control signal PHY_CA and the clock signal PHY_CLK can be obtained from... Figure 1 The storage controller 110 is provided in the middle.

[0137] Figure 16 It shows Figure 15 A block diagram of an example of the input control circuit.

[0138] refer to Figure 16 The input control circuit 230 includes a first multiplexer 231, a second multiplexer 233, and a latch 235.

[0139] The first multiplexer 231 can receive a mode signal DA_EN, an internal test control signal DA_PCA, and an internal normal control signal PHY_PCA. It can select the internal test control signal DA_PCA as the first selected control signal IPCA' in response to the mode signal DA_EN specifying the direct access mode. It can also select the internal normal control signal PHY_PCA as the first selected control signal IPCA' in response to the mode signal DA_EN specifying the normal mode. It can also provide the first selected control signal IPCA' to the latch 235.

[0140] The second multiplexer 233 can receive a mode signal DA_EN, an internal clock signal PCLK, and a normal clock signal PPCLK. It can select the internal clock signal PCLK as the selected clock signal IPCLK in response to the mode signal DA_EN specifying the direct access mode, and can select the normal clock signal PPCLK as the selected clock signal IPCLK in response to the mode signal DA_EN specifying the normal mode. It can also provide the selected clock signal IPCLK to the latch 235.

[0141] Latch 235 can generate a selected control signal IPCA by latching a first selected clock signal IPCA' on the rising edge of the selected clock signal IPCLK, and can provide the selected control signal IPCA to the internal signal generator 240.

[0142] Figure 17 This is a diagram showing an example of a semiconductor package.

[0143] refer to Figure 17 The semiconductor package 500 includes a stacked memory device 600, a system-on-a-chip (SoC) 510, an embedded layer 550, and a package substrate 560. The stacked memory device 600 may include a buffer die 800 and core dies 600a, 600b, 600c, and 600d.

[0144] Each of the core dies 600a, 600b, 600c, and 600d may include a memory cell array. The buffer die 800 may include a physical region 810 and a direct access region DA 820. Physical region 810 may be electrically connected to physical region 530 of the system-on-chip 510. Through physical region 810, the stacked memory device 600 can receive signals from or send signals to the system-on-chip 510. The direct access region DA 820 may include a test interface circuit TIC 900.

[0145] Direct access area 820 provides an access path for testing stacked memory devices 600 without going through system-on-chip 510. Direct access area 820 may include conductive means (e.g., ports or pins) capable of direct communication with external test equipment. Test signals and data received through direct access area 820 can be transmitted to dies 600a, 600b, 600c, and 600d via TSV. Data read from dies 600a, 600b, 600c, and 600d can be transmitted to the test equipment via TSV and direct access area 820 for testing dies 600a, 600b, 600c, and 600d. Thus, direct access testing can be performed on dies 600a, 600b, 600c, and 600d.

[0146] The buffer die 800 and core dies 600a, 600b, 600c, and 600d can be electrically connected via TSV 601 and bump 602. The buffer die 800 can receive signals from the system-on-chip 510, which are provided to each channel via bump 602 assigned to each channel. For example, bump 602 can be a microbump.

[0147] The system-on-chip 510 can run applications supported by the semiconductor package 500 by using the stacked memory device 600. For example, the system-on-chip 510 may include at least one of a central processing unit (CPU), application processor (AP), graphics processing unit (GPU), neural processing unit (NPU), tensor processing unit (TPU), vision processing unit (VPU), image signal processor (ISP), or digital signal processor (DSP), and can perform specialized computing.

[0148] The system-on-chip 510 may include a physical region 530 and a memory controller 520. The physical region 530 (e.g., a physical layer) may include input / output circuitry for exchanging signals with physical region 810 of the stacked memory device 600. The system-on-chip 510 can provide various signals to physical region 810 through physical region 530. Signals provided to physical region 810 can be transmitted to core dies 600a, 600b, 600c, and 600d via interface circuitry of physical region 810 and TSV 601.

[0149] The storage controller 520 can control the overall operation of the stacked storage device 600. The storage controller 520 can provide signals for controlling the stacked storage device 600 through the physical area 530.

[0150] The built-in layer 550 can connect the stacked memory device 600 and the system-on-chip 510. The built-in layer 550 can connect the physical region 810 of the stacked memory device 600 and the physical region 530 of the system-on-chip 510, and can provide a physical path formed by using conductive material. In this way, the stacked memory device 600 and the system-on-chip 510 can be stacked on the built-in layer 550 and can exchange signals with each other.

[0151] Bump 503 may be attached to the upper surface of package substrate 560, and solder ball 504 may be attached to the lower surface of package substrate 560. For example, bump 503 may be a flip chip bump. An internal layer 550 may be stacked on package substrate 560 via bump 503. Semiconductor package 500 may exchange signals with any other external package or semiconductor device via solder ball 504. For example, package substrate 560 may be a printed circuit board (PCB).

[0152] Figure 18It shows Figure 17 A block diagram of an example of a stacked storage device.

[0153] refer to Figure 18 The stacked memory device 600 includes a buffer die 800 and multiple core dies 600a, 600b, 600c, and 600d. For example, the buffer die 800 may also be referred to as an "interface die," "base die," "logic die," or "master die," and each of the core dies 600a, 600b, 600c, and 600d may also be referred to as a "memory die" or a "slave die." Figure 18 In the example shown, the stacked storage device 600 includes four core dies 600a, 600b, 600c, and 600d, but the number of core dies can vary. For example, the stacked storage device 600 may include 8, 12, or 16 core dies.

[0154] The buffer die 800 and core dies 600a, 600b, 600c, and 600d can be stacked and electrically connected using through-silicon vias (TSVs). Thus, the stacked memory device 600 can have a three-dimensional memory structure in which multiple dies 600a, 600b, 600c, and 600d are stacked. For example, the stacked memory device 600 can be implemented according to HBM or Hybrid Memory Cube (HMC) standards.

[0155] The stacked storage device 600 can support multiple channels (or repositories) that are functionally independent of each other. For example, such as Figure 17 As shown, the stacked storage device 600 can support eight channels CH0 to CH7. With each of channels CH0 to CH7 supporting 128 DQ inputs / outputs (I / Os), the stacked storage device 600 can support 1024 DQ I / Os. However, the implementation is not limited to this. For example, the stacked storage device 600 can support 1024 or more DQ I / Os and can support eight or more channels (e.g., 16 channels). With the stacked storage device 600 supporting 16 channels, each channel can support 64 DQ I / Os.

[0156] Each of the 600a, 600b, 600c, and 600d dies can support at least one channel. For example, as... Figure 18As shown, dies 600a, 600b, 600c, and 600d can support channel pairs CH0 and CH2, CH1 and CH3, CH4 and CH6, and CH5 and CH7, respectively. In this case, dies 600a, 600b, 600c, and 600d can support different channels. However, the implementation is not limited to this. For example, at least two of dies 600a, 600b, 600c, and 600d can support the same channel. For example, each of dies 600a, 600b, 600c, and 600d can support a first channel CH0.

[0157] Each channel can form an independent command and data interface. For example, channels can be independently clocked based on independent timing requirements and can be asynchronous. For example, each channel can change its power state or perform a refresh operation based on independent commands.

[0158] Each channel may include multiple memory banks 603. Each memory bank 603 may include memory cells connected to word lines and bit lines, row decoders, column decoders, sense amplifiers, etc. For example, Figure 18 As shown, each of channels CH0 to CH7 can support eight memory banks 401, such as memory banks Bank0, Bank1, Bank2, Bank3, Bank4, Bank5, Bank6, and Bank7. However, the implementation is not limited to this. For example, each of channels CH0 to CH7 can support eight or more memory banks 603. Figure 18 In the example shown, memory cells belonging to one channel are included in a single core die, but memory cells belonging to one channel can be distributed across multiple core dies. For example, if each of core dies 600a, 600b, 600c, and 600d supports a first channel CH0, the memory cells contained in the first channel CH0 can be distributed across core dies 600a, 600b, 600c, and 600d.

[0159] In some implementations, a channel can be divided into two pseudo-channels that operate independently of each other. For example, pseudo-channels can share the command and clock inputs (e.g., clock signals and clock enable signals) of the corresponding channel, but can decode and execute commands independently. For example, if a channel supports 128 DQ I / Os, each pseudo-channel can support 64 DQ I / Os. Alternatively, if a channel supports 64 DQ I / Os, each pseudo-channel can support 32 DQ I / Os.

[0160] Buffer die 800 and core dies 600a, 600b, 600c, and 600d may each include a TSV region 802. A TSV 601 can penetrate core dies 600a, 600b, 600c, and 600d and can also penetrate buffer die 800 (not shown). TSV 601 may be located within TSV region 802. Buffer die 800 can exchange signals and / or data with core dies 600a, 600b, 600c, and 600d via TSVs. Each of core dies 600a, 600b, 600c, and 600d can exchange signals and / or data with buffer die 800 via TSVs, and core dies 600a, 600b, 600c, and 600d can exchange signals and / or data with each other via TSVs. In this case, signals and / or data can be exchanged independently via the corresponding TSV for each channel. For example, when an external host device sends a command and address to the first channel CH0 for the purpose of accessing the memory cell of the first core die 600a, the buffer die 800 can send a control signal to the first core die 600a through the TSV corresponding to the first channel CH0 and can access the memory cell of the first channel CH0.

[0161] The buffer die 800 may include a physical region 810 and a direct access region 820, and the direct access region 820 may include a test interface circuit 900.

[0162] In some implementations, the buffer die 800 may include a channel controller corresponding to a specific channel. The channel controller can manage the memory reference operations of the corresponding channel and determine the timing requirements of the corresponding channel.

[0163] In some implementations, the buffer die 800 may include multiple pins for receiving signals from an external host device.

[0164] Figure 19 It shows Figure 18 A block diagram of an example of the first core die in a stacked storage device.

[0165] refer to Figure 19 The first core die 600a includes control logic circuitry 610, address register 620, memory bank control logic 630, row address multiplexer (RA MUX) 640, column address latch 650, row decoder 660, column decoder 670, memory cell array 710, sense amplifier unit 685, input / output (I / O) gate circuitry 690, refresh counter 645, data I / O buffer 720a, and ECC engine 790.

[0166] The memory cell array 710 may include first to sixteenth memory bank arrays 710a-710p. The row decoder 660 may include first to sixteenth row decoders 660a-660p, respectively coupled to the first to sixteenth memory bank arrays 710a-710p. The column decoder 670 may include first to sixteenth column decoders 670a-670p, respectively coupled to the first to sixteenth memory bank arrays 710a-710p. The sense amplifier unit 685 may include first to sixteenth sense amplifiers 685a-685p, respectively coupled to the first to sixteenth memory bank arrays 710a-710p. The first to sixteenth memory bank arrays 710a-710p, the first to sixteenth row decoders 660a-660p, the first to sixteenth column decoders 670a-670p, and the first to sixteenth sense amplifiers 685a-685p may constitute the first to sixteenth memory banks.

[0167] Each of the first to sixteenth memory bank arrays 710a-710p may include multiple memory cells MC formed at the intersection of multiple word lines WL and multiple bit lines BTL.

[0168] Address register 620 can receive address ADDR, including bank address BANK_ADDR, row address ROW_ADDR, and column address COL_ADDR, from buffer die 800. Address register 620 can provide the received bank address BANK_ADDR to bank control logic 630, the received row address ROW_ADDR to row address multiplexer 640, and the received column address COL_ADDR to column address latch 650.

[0169] The memory bank control logic 630 can generate a memory bank control signal in response to the memory bank address BANK_ADDR. One of the first to sixteenth row decoders 660a-660p corresponding to the memory bank address BANK_ADDR can be activated in response to the memory bank control signal, and one of the first to sixteenth column decoders 670a-670p corresponding to the memory bank address BANK_ADDR can be activated in response to the memory bank control signal.

[0170] The row address multiplexer 640 can receive the row address ROW_ADDR from the address register 620 and the refresh row address REF_ADDR from the refresh counter 645. The row address multiplexer 640 can selectively output either the row address ROW_ADDR or the refresh row address REF_ADDR as the row address RA. The row address RA output from the row address multiplexer 640 can be applied to the first through sixteenth line decoders 660a-660p.

[0171] The refresh counter 645 can sequentially increase or decrease the refresh row address REF_ADDR under the control of the control logic circuit 610.

[0172] One of the sixteenth row decoders 660a-660p, when activated, can decode the row address RA output from the row address multiplexer 640 and can activate the word line corresponding to the row address RA. For example, the activated bank row decoder can apply a word line drive voltage to the word line corresponding to the row address RA.

[0173] Column address latch 650 can receive column address COL_ADDR from address register 620 and can temporarily store the received column address COL_ADDR. In some implementations, in burst mode, column address latch 650 can generate a column address COL_ADDR' incremented from the received column address COL_ADDR. Column address latch 650 can apply the temporarily stored or generated column address COL_ADDR' to the first through sixteenth column decoders 670a-670p.

[0174] One of the first to sixteenth column decoders 670a-670p, when activated, can decode the column address COL_ADDR' output from the column address latch 650 and can control the I / O gate circuit 690 to output data corresponding to the column address COL_ADDR.

[0175] The I / O gating circuit 690 may include a circuit system for gating input / output data. The I / O gating circuit 690 may further include a read data latch for storing data output from the first to sixteenth memory arrays 710a-710p and a write driver for writing data to the first to sixteenth memory arrays 710a-710p.

[0176] A codeword CW read from one of the memory bank arrays 710a-710p (from the first to the sixteenth array) can be read by a read amplifier coupled to the memory bank array from which data is to be read, and can be stored in a read data latch. The codeword CW stored in the read data latch can be provided to the ECC engine 790. The ECC engine 790 can perform ECC decoding on the codeword CW to provide data DQ to the data I / O buffer 720a. The data I / O buffer 720a can send data DQ to the buffer die 800.

[0177] Data DQ to be written to one of the memory bank arrays 710a-710p (from the first to the sixteenth arrays) can be provided from the data I / O buffer 720a to the ECC engine 790. The ECC engine 790 can perform ECC encoding on the data DQ to generate a parity bit, and the ECC engine 790 can provide the data DQ and the parity bit to the I / O gating circuit 690. The I / O gating circuit 690 can write the data DQ and the parity bit to a subpage in a memory bank array via a write driver.

[0178] The ECC engine 790 can perform ECC encoding and ECC decoding on the data DTA based on the second control signal CTL2 from the control logic circuit 610.

[0179] The control logic circuit 610 can control the operation of the first core die 600a. The control logic circuit 610 may include a command decoder 611a that decodes the command CMD received from the buffer die 800, and may include a mode register 612 that sets the operating mode of the first core die 600a.

[0180] By decoding the command CMD, the control logic circuit 610 can generate a first control signal CTL1 for controlling the I / O gate circuit 690 and a second control signal CTL2 for controlling the ECC engine 790.

[0181] Figure 20 It shows Figure 19 An example of the first memory bank array in the first core die.

[0182] refer to Figure 20 The first memory bank array 710a includes multiple word lines WL0-WLm-1 (m is a natural number greater than 2), multiple bit lines BTL0-BTLn-1 (n is a natural number greater than 2), and multiple memory cells MC disposed at the intersections between the word lines WL0-WLm-1 and the bit lines BTL0-BTLn-1. Each memory cell MC may include a unit transistor coupled to each word line in the word lines WL0-WLm-1 and each bit line in the bit lines BTL0-BTLn-1, and a unit capacitor coupled to that unit transistor. Each memory cell MC may have a DRAM cell structure. Each word line in the word lines WL0-WLm-1 extends in a first direction DR1, and each bit line in the bit lines BTL1-BTLn-1 extends in a second direction DR2 intersecting the first direction DR1.

[0183] Word lines WL0-WLm-1 coupled to multiple memory cells MC can be referred to as rows of the first memory bank array 710a, while bit lines BTL0-BTLn-1 coupled to multiple memory cells MC can be referred to as columns of the first memory bank array 710a.

[0184] Figure 21 It shows Figure 17 A block diagram of an example of a buffer die.

[0185] refer to Figure 21 The buffer die 800 includes a physical area 810, a TSV area 802, a direct access area 820, and a power manager 850.

[0186] Multiple PHY bumps PB and multiple channel interface circuits IF_CH0-IF_CH7 for interface communication with channels CH0 to CH7 of the core dies 600a, 600b, 600c and 600d can be formed on the physical region 810. Multiple TSVs 803 can be formed on the TSV region 802.

[0187] The direct access area 820 may include a DA probe area 821, a DA bump area 823, and a test interface circuit 900.

[0188] In the DA bump region 823, multiple DA bumps (DABs) can be formed for interfacing with an external test device via the built-in layer 550 to test the stacked storage device 600. In the DA probe region 821, multiple DA pads (DAPs) can be formed for interfacing with an external test device to test the stacked storage device 600 without passing through the built-in layer 550. The PHY bumps (PB) and DA bumps (DABs) can be formed from microbumps, and the DA pads (DAPs) can be formed from pads larger than microbumps. For example, compared to the PHY bumps (PB) and DA bumps (DABs), the DA pads (DAPs) can be larger in physical size but fewer in number.

[0189] In direct access mode, test signals can be transmitted to physical region 810 via the DA bump (DAB) or DA pad (DAP) of direct access region 820, and then transmitted to each of the core dies 600a, 600b, 600c, and 600d via the channel interface circuits IF_CH0 to IF_CH7 in physical region 810 through TSV 803 of TSV region 802. In this document, because physical region 810 is physically located away from direct access region 820, a high degree of skewness may occur between test signals. Therefore, it may be necessary to transmit test signals between direct access region 820 and physical region 810 at precise timing. Furthermore, when test signals are applied via DA bump (DAB) or DA pad (DAP), internal test operations are constrained by the operating speed of external test equipment. For example, if the external test equipment is operating at low speed, test operations can be performed by placing a clock multiplier inside buffer die 800a. However, the duty cycle of the complementary clock generated by such a clock multiplier may not be constant, and the crossover point of the complementary clock may not be centered, thus degrading the characteristics of the test operation. For example, when performing high-speed testing on conventional semiconductor memory devices that include direct access regions, the sensitivity to the power supply voltage increases because a separate power supply voltage is not applied to the direct access regions, and the test performance degrades due to differences in the margin of the test control signal caused by the inconsistent duty cycle of the internal clock signal generated based on the external clock signal.

[0190] To address these issues, the direct access area 820 includes a test interface circuit 900.

[0191] In direct access mode, the test interface circuit 900 can receive external clock signals and test control signals from an external test device. It can generate an internal clock signal based on the external clock signal, generate a first internal test control signal by latching the test control signal at a first timing point of the internal clock signal, and generate a second internal test control signal by latching the first internal test control signal at a second timing point of the internal clock signal. It can also provide one of the first and second internal test control signals as the internal test control signal to the physical area 810. The internal clock signal can have different duty cycles at the first and second timing points. The frequency of the internal clock signal can be twice the frequency of the external clock signal.

[0192] Therefore, in direct access mode, the stacked storage device 600 can perform high-speed tests while adjusting the timing of transmitting the internal clock signal to the physical area 810.

[0193] The power manager 850 can receive a first power supply voltage VDD1 through the first power pad PPD1, and a second power supply voltage VDD2 through the second power pad PPD2. It can generate an internal power supply voltage VINT_DA based on one of the first power supply voltage VDD1 and the second power supply voltage VDD2, and can supply the internal power supply voltage VINT_DA to the direct access area 820.

[0194] The first power supply voltage VDD1 and the second power supply voltage VDD2 can be supplied to the memory cell array in each of the core dies 600a, 600b, 600c and 600d, and the second power supply voltage VDD2 can be supplied to the peripheral circuits and physical region 810 in each of the core dies 600a, 600b, 600c and 600d.

[0195] The voltage level of the first power supply voltage VDD1 can be greater than the voltage level of the second power supply voltage VDD2.

[0196] In some implementations, the power manager 850 can receive a dedicated power supply voltage VDD2_DA through a dedicated power pad PPD3, generate an internal power supply voltage VINT_DA by power gating the dedicated power supply voltage VDD2_DA, and provide the internal power supply voltage VINT_DA to the direct access area 820.

[0197] Power Manager 850 can adopt Figure 4 Power Manager 400 Figure 6 Power Manager 400b and Figure 7 One of the power managers in the 400c.

[0198] Figure 22 It shows Figure 18 An example of a buffer bare die.

[0199] refer to Figure 22 The buffer die 800 includes a physical area 810, a direct access area 820, and a TSV area 802.

[0200] On the physical region 810, a plurality of first PHY bumps PB0<0:8> for receiving normal control signals PHY_CA during normal operation and a second PHY bump PB1 for receiving normal clock PHY_CA during normal operation can be configured.

[0201] On the direct access area 820, multiple first DA pads DAP0<0:8> for receiving the test control signal DA_CA and a second DA pad DAP1 for receiving the external clock DA_CLK can be configured. The test interface circuit 900 can be configured in the direct access area 820.

[0202] The test interface circuit 900 may include buffers 901 and 903, an internal clock generator 910, and a first input circuit 930. Buffer 901 can respond to the activation of the mode signal DA_EN specifying the direct access mode and can provide the internal clock generator 910 with an external clock signal DA_CLK received from an external test device. Buffer 903 can respond to the activation of the mode signal DA_EN specifying the direct access mode and can provide the first input circuit 930 with a test control signal DA_CA received from an external test device.

[0203] The first input circuit 930 can adopt... Figure 9 The first input circuit 330 and the internal clock generator 910 can be used Figure 9 The internal clock generator 310 in the middle.

[0204] Therefore, in direct access mode, the internal clock generator 910 can generate an internal clock signal PCLK based on the external clock signal DA_CLK and provide the internal clock signal PCLK to the first input circuit 930 and the input control circuit 830 in the physical region 810. In direct access mode, the first input circuit 930 can generate an internal test control signal DA_PCA by delaying the test control signal DA_CA by at least one time based on the internal clock signal PCLK and can transmit the internal test control signal DA_PCA to the input control circuit 830 in the physical region 810.

[0205] The physical region 810 may include an interface circuit 811, an input control circuit 830, and an internal signal generator ISG 840. Each of the interface circuit 811, the input control circuit 830, and the internal signal generator 840 may employ... Figure 15 The interface circuit 211, input control circuit 230, and internal signal generator 240 are included.

[0206] The interface circuit 811 may include buffers 813 and 814, a second input circuit 815, and a clock generator 816.

[0207] In normal mode, buffer 813 can receive clock signal PHY_CLK and provide clock signal PHY_CLK to clock generator 816. Clock generator 816 can generate normal clock signal PPCLK based on clock signal PHY_CLK and provide normal clock signal PPCLK to second input circuit 815 and input control circuit 830.

[0208] In normal mode, buffer 814 can receive the normal control signal PHY_CA and provide the normal control signal PHY_CA to the second input circuit 815. The second input circuit 815 can generate an internal normal control signal PHY_PCA based on the normal clock signal PPCLK and can transmit the internal normal control signal PHY_PCA to the input control circuit 830.

[0209] The input control circuit 830 can receive the mode signal DA_EN, the internal clock signal PCLK, the internal test control signal DA_PCA, the normal clock signal PPCLK, and the internal normal control signal PHY_PCA.

[0210] The input control circuit 830 responds to the mode signal DA_EN that specifies the direct access mode. It can select the internal test control signal DA_PCA from the internal test control signal DA_PCA and the internal normal control signal PHY_PCA. It can generate the selected control signal IPCA by latching the internal test control signal DA_PCA based on the internal clock signal PCLK, and can provide the selected control signal IPCA to the internal signal generator 840.

[0211] The input control circuit 830 responds to the mode signal DA_EN of the specified normal mode, and can select the internal normal control signal PHY_PCA from the internal test control signal DA_PCA and the internal normal control signal PHY_PCA. It can generate the selected control signal IPCA by latching the internal normal control signal PHY_PCA based on the normal clock signal PPCLK, and can provide the selected control signal IPCA to the internal signal generator 840.

[0212] The internal signal generator 840 can generate an internal signal ICA based on a selected control signal IPCA and can provide the internal signal ICA to the TSV 803.

[0213] Test interface circuit 900 can generate internal test data by latching test data and can provide the internal test data to input control circuit 830. Interface circuit 811 can generate internal normal data by latching normal data and can provide the internal normal data to input control circuit 830. In direct access mode, input control circuit 830 can provide internal test data to core dies 600a, 600b, 600c, and 600d through TSV 803, while in normal mode, input control circuit 830 can provide internal normal data to core dies 600a, 600b, 600c, and 600d through TSV 803.

[0214] The first input circuit 930 can adopt... Figure 12 The first input circuit 330a or Figure 13 The first input circuit 330b in the middle.

[0215] Therefore, in direct access mode, the first input circuit 930 can generate a first internal test control signal and a second internal test control signal by latching the test control signal DA_CA at least twice based on the internal clock signal PCLK, and can provide one of the first internal test control signal and the second internal test control signal as an internal test control signal to the physical region 810 based on a selection signal. Therefore, in direct access mode, the first input circuit 930 can perform tests for various timing margins by adjusting the timing point at which the internal test control signal is transmitted to the physical region 810.

[0216] Figure 23 This is a block diagram illustrating an example of a semiconductor system.

[0217] refer to Figure 23 The semiconductor system 1000 includes a memory controller 1010, a test apparatus ATE 1020, and a semiconductor memory device 1030.

[0218] The test apparatus 1020 can provide an external clock signal DA_CLK and a test control signal DA_CA to the semiconductor memory device 1030 during test operations.

[0219] The storage controller 1010 can provide the clock signal PHY_CLK and the normal control signal PHY_CA to the semiconductor storage device 1030 during normal operation.

[0220] The semiconductor memory device 1030 can perform test operations based on an external clock signal DA_CLK and a test control signal DA_CA, and perform normal operations based on a clock signal PHY_CLK and a normal control signal PHY_CA. The semiconductor memory device 1030 may include... Figure 2 Semiconductor memory device 200 or Figure 18 600 stacked storage devices.

[0221] The semiconductor storage device 1030 may include a physical area 1040 that interfaces with the storage controller 1010 and a direct access area 1050 that interfaces directly with the test apparatus 1020.

[0222] Semiconductor memory device 1030 can receive external clock signal DA_CLK and test control signal DA_CA from test device 1020 via direct access area 1050, and can receive clock signal PHY_CLK and normal control signal PHY_CA from memory controller 1010 via physical area 1040.

[0223] The direct access area 1050 may include test interface circuitry 1100. The physical area 1040 may include input control circuitry 1110 and the semiconductor storage device 1030 may further include internal circuitry 1120.

[0224] In direct access mode, the test interface circuit can receive an external clock signal DA_CLK and a test control signal DA_CA from the test device 1020. It can generate an internal clock signal PCLK based on the external clock signal DA_CLK. A first internal test control signal can be generated by latching the test control signal DA_CA at a first timing point of the internal clock signal PCLK. A second internal test control signal can be generated by latching the first internal test control signal at a second timing point of the internal clock signal PCLK. One of the first and second internal test control signals can be provided to the input control circuit 1110 in the physical area 1040 as the internal test control signal DA_PCA. The internal clock signal PCLK can have different duty cycles at the first and second timing points. The frequency of the internal clock signal can be twice the frequency of the external clock signal.

[0225] Therefore, in direct access mode, the semiconductor memory device 1030 can perform high-speed testing while adjusting the timing of transmitting the internal clock signal to the physical region 1040.

[0226] The input control circuit 1110 responds to the mode signal DA_EN that specifies the direct access mode. It can select the internal test control signal DA_PCA from the internal test control signal DA_PCA and the internal normal control signal PHY_PCA. It can generate the selected control signal IPCA by latching the internal test control signal DA_PCA based on the internal clock signal PCLK, and can provide the selected control signal IPCA to the internal circuit 1120.

[0227] The input control circuit 1110 responds to the mode signal DA_EN of the specified normal mode, and can select the internal normal control signal PHY_PCA from the internal test control signal DA_PCA and the internal normal control signal PHY_PCA. It can generate the selected control signal IPCA by latching the internal normal control signal PHY_PCA based on the normal clock signal, and can provide the selected control signal IPCA to the internal circuit 1120.

[0228] Figure 24 This is a flowchart illustrating an example of a method for testing semiconductor memory devices.

[0229] refer to Figure 1 , Figure 2 , Figures 9 to 16 and Figure 24The test interface circuit 300, located in the direct access area 220 of the semiconductor memory device 200, receives the external clock signal DA_CLK and the test control signal DA_CA from the external test device in direct access mode (operation S110).

[0230] The test interface circuit 300 generates an internal clock signal PCLK based on the external clock signal DA_CLK (operation S120). The test interface circuit 300 generates a first internal test control signal DA_CA1 by latching the test control signal DA_CA at a first timing point of the internal clock signal PCLK (operation S130). The test interface circuit 300 generates a second internal test control signal DA_CA2 by latching the first internal test control signal DA_CA1 at a second timing point of the internal clock signal PCLK (operation S140).

[0231] The test interface circuit 300 performs a first test based on the first internal test control signal DA_CA1 by transmitting it to the physical area 210 (operation S150). The test interface circuit 300 performs a second test based on the second internal test control signal DA_CA2 by transmitting it to the physical area 210 (operation S160).

[0232] The external testing device determines whether the semiconductor memory device 200 passes or fails based on the results of the first test and the second test (operation S170).

[0233] An external testing device determines that the test is passed when the semiconductor memory device 200 passes both the first test and the second test, and determines that the test fails when the semiconductor memory device 200 passes only one of the first test and the second test.

[0234] The examples described above are applicable to systems using semiconductor memory devices and stacked memory devices. While this disclosure contains numerous specific implementation details, these should not be construed as limiting the scope of any claims. Certain features described in the context of individual embodiments of this disclosure may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually in multiple embodiments or in any suitable sub-combination. Furthermore, although features may be described above as operating in certain combinations, in some cases, one or more features from a combination may be removed from the combination, and the combination may involve sub-combinations or variations thereof.

[0235] Although this disclosure has been shown and described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that many modifications in form and detail may be made therein without substantially departing from the spirit and scope of this disclosure as set forth by the appended claims.

Claims

1. A semiconductor memory device comprising: a physical region configured to interface with an external memory controller; a direct access region configured to interface with an external test apparatus; and a power manager configured to generate an internal supply voltage based on at least one of a first supply voltage, a second supply voltage, or a supply voltage, the first supply voltage and the second supply voltage being provided from outside the semiconductor memory device, and the supply voltage being received through a power pad, and to provide the internal supply voltage to the direct access region, wherein the power manager is further configured to provide the second supply voltage to the physical region, wherein the direct access region includes a test interface circuit, and wherein the test interface circuit is configured to generate an internal clock signal based on an external clock signal received from the external test apparatus, to generate an internal test control signal by latching a test control signal received from the external test apparatus based on the internal clock signal, and to provide the internal test control signal to the physical region.

2. The semiconductor memory device of claim 1, further comprising: a memory region including a plurality of memory cell arrays; and a peripheral circuit region including a plurality of peripheral circuits configured to control the plurality of memory cell arrays, respectively, wherein the memory region is configured to operate based on the first supply voltage and the second supply voltage, and wherein the peripheral circuit region is configured to operate based on the second supply voltage. the physical region includes a plurality of channel interface circuits, and 3. The semiconductor memory device according to claim 2, wherein, wherein each of the plurality of channel interface circuits is configured to interface with a respective memory cell array of the plurality of memory cell arrays through a respective peripheral circuit of the plurality of peripheral circuits. the power manager includes:

4. The semiconductor memory device according to claim 1, wherein, a comparator configured to generate a regulation voltage by comparing a reference voltage and the internal supply voltage; and a power transistor coupled between the first supply voltage and an output node, the power transistor configured to generate the internal supply voltage by regulating the first supply voltage based on the regulation voltage. the power transistor includes:

5. The semiconductor memory device according to claim 4, wherein, a source coupled to the first supply voltage; a gate configured to receive the regulation voltage; and a drain coupled to the output node and configured to provide the internal supply voltage. the power manager includes:

6. The semiconductor memory device according to claim 1, wherein, a voltage detector configured to generate a decision signal in a direct access mode by comparing the internal supply voltage with a reference voltage; an oscillator configured to generate a pumped clock signal by performing an oscillation operation based on the decision signal; and a power transistor coupled between the first supply voltage and an output node, the power transistor configured to generate the internal supply voltage by regulating the first supply voltage based on the regulation voltage. a charge pump configured to generate the internal supply voltage by performing a pumping operation based on the pumping clock signal and the second supply voltage, and wherein the voltage detector is further configured to be enabled based on the direct access mode being activated.

7. The semiconductor memory device according to claim 1, wherein, the power manager comprises a power transistor, wherein in the direct access mode, the power transistor is configured to generate the internal supply voltage by power gating the supply voltage, and wherein in the normal mode, the power transistor is configured to cut off the supply voltage.

8. The semiconductor memory device according to claim 1, wherein, the test interface circuit is further configured to: generate a first internal test control signal by latching the test control signal at a first timing point of the internal clock signal; generate a second internal test control signal by latching the first internal test control signal at a second timing point of the internal clock signal; and provide at least one of the first internal test control signal or the second internal test control signal to the physical region as the internal test control signal, and wherein the internal clock signal has different duty cycles at the first timing point and the second timing point.

9. A semiconductor memory device, the semiconductor memory device comprising: a physical region configured to interface with an external memory controller; and a direct access region configured to directly interface with an external test apparatus, wherein the direct access region comprises a test interface circuit, and wherein the test interface circuit is configured to: generate an internal clock signal based on an external clock signal received from the external test apparatus; generate a first internal test control signal by latching a test control signal received from the external test apparatus at a first timing point of the internal clock signal; generate a second internal test control signal by latching the first internal test control signal at a second timing point of the internal clock signal; and provide at least one of the first internal test control signal and the second internal test control signal to the physical region as an internal test control signal, wherein the internal clock signal has different duty cycles at the first timing point and the second timing point.

10. The semiconductor memory device according to claim 9, wherein, the test interface circuit comprises: an internal clock generator configured to generate the internal clock signal based on the external clock signal in a direct access mode; and an input circuit configured to generate the internal test control signal by delaying the test control signal at least once based on the internal clock signal in the direct access mode.

11. The semiconductor memory device according to claim 10, wherein, the internal clock generator comprises: a phase shifter configured to generate a first intermediate clock signal and a second intermediate clock signal that are 90 degrees out of phase with respect to each other by shifting a phase of the external clock signal; and an XOR gate configured to generate the internal clock signal by performing an XOR operation on the first intermediate clock signal and the second intermediate clock signal, and wherein a frequency of the internal clock signal is twice a frequency of the external clock signal.

12. The semiconductor memory device according to claim 10, wherein, The input circuit includes: a first D flip-flop configured to output the first internal test control signal by latching the test control signal at the first timing point of the internal clock signal; a second D flip-flop configured to output the second internal test control signal by latching the second internal test control signal at the second timing point of the internal clock signal; and a multiplexer configured to output the first internal test control signal or the second internal test control signal as the internal test control signal based on a selection signal.

13. The semiconductor memory device of claim 12, wherein: a first duty cycle of the internal clock signal at the first timing point is less than 50%; and a second duty cycle of the internal clock signal at the second timing point is greater than 50%.

14. The semiconductor memory device according to claim 12, wherein, the first D flip-flop is further configured to generate the first internal test control signal by delaying the test control signal by a half cycle of the external clock signal based on the internal clock signal, and wherein the second D flip-flop is further configured to generate the second internal test control signal by delaying the test control signal by a cycle of the external clock signal based on the internal clock signal.

15. The semiconductor memory device according to claim 14, wherein, the semiconductor memory device is configured to select the first timing point or the second timing point by setting the selection signal by a test mode register set.

16. The semiconductor memory device according to claim 10, wherein, The physical region includes: an interface circuit configured to generate an internal normal control signal based on a normal signal received from the external storage controller and to generate a normal clock signal based on a clock signal received from the external storage controller in a normal mode; an input control circuit configured to select the internal clock signal or the normal clock signal as a selected clock signal based on a selection signal specifying one of the direct access mode or the normal mode, wherein the input control circuit is further configured to provide the internal test control signal or the internal normal control signal as a selected control signal based on the selected clock signal; and an internal signal generator configured to generate an internal signal based on the selected control signal and to provide the internal signal to a peripheral circuit region.

17. The semiconductor memory device of claim 9, further comprising: a power manager configured to generate an internal supply voltage based on a supply voltage and to supply the internal supply voltage to the direct access region, the supply voltage being received from outside through a power pad, and wherein the power manager includes a power switch, wherein in a direct access mode, the power switch is configured to generate the internal supply voltage by power-gating the supply voltage, and wherein in a normal mode, the power switch is configured to generate the internal supply voltage by passing the supply voltage without power-gating. wherein, in a normal mode, the power switch is configured to cut off the supply voltage.

18. A stacked memory device, comprising: a buffer die including an interface circuit and a test interface circuit, wherein the interface circuit is configured to communicate with an external host device in a normal mode, and wherein the test interface circuit is configured to interface directly with an external test device in a direct access mode; and a plurality of core dies stacked on the buffer die and connected to the buffer die through a plurality of through-silicon vias, wherein the buffer die includes a physical region, a direct access region, and a through-silicon via region, wherein the interface circuit is disposed in the physical region, the test interface circuit is disposed in the direct access region, and the through-silicon vias are formed in the through-silicon via region, wherein the test interface circuit is configured to, in the direct access mode: generate an internal clock signal based on an external clock signal received from the external test device; generate a first internal test control signal by latching a test control signal received from the external test device at a first timing point of the internal clock signal; generate a second internal test control signal by latching the first internal test control signal at a second timing point of the internal clock signal; and provide at least one of the first internal test control signal or the second internal test control signal as an internal test control signal to the physical region, wherein the internal clock signal has different duty cycles at the first timing point and the second timing point.

19. The stacked memory device of claim 18, wherein, the test interface circuit includes: an internal clock generator configured to, in the direct access mode, generate the internal clock signal based on the external clock signal; and an input circuit configured to, in the direct access mode, generate the internal test control signal by delaying the test control signal at least once based on the internal clock signal.

20. The stacked memory device of claim 18, wherein, the buffer die further includes a power manager configured to generate an internal supply voltage based on at least one of a first supply voltage, a second supply voltage, or a supply voltage, and configured to provide the internal supply voltage to the direct access region, wherein the first supply voltage is provided to the core dies, the second supply voltage is provided to the physical region, and the supply voltage is received from outside the stacked memory device through a power pad.

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