Test structure and test method for positioning plasma damage source
By designing a test structure that includes a MOS transistor, gate leads, and an antenna, the gate current is monitored to locate the source of damage to the gate dielectric layer in the plasma etching process. This solves the problem of difficulty in monitoring and locating plasma damage in the prior art and improves the accuracy and reliability of the etching process.
Patent Information
- Application Number
- CN202410867366.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-28
- Publication Date
- 2025-12-30
AI Technical Summary
Existing technologies struggle to effectively monitor and locate the sources of damage to the gate dielectric layer during plasma etching processes, especially damage caused by non-uniform plasma radiation in the metal interconnect layer.
A test structure is designed, including a first MOS transistor, a first gate lead, a first antenna, and a monitoring gate pad. These components form a plasma charge accumulation path, and the gate current is tested using the monitoring gate pad to monitor plasma damage to the gate dielectric layer. Simultaneously, a test reference structure is set up to compare current ratios and quickly locate the source of damage.
It enables the monitoring and localization of damage to the gate dielectric layer in plasma etching processes, and can quickly locate the layer with plasma damage sources among all metal layers, thereby improving the reliability and accuracy of the etching process.
Smart Images
Figure CN121237779A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor integrated circuit manufacturing, and particularly to a test structure for locating the source of plasma damage; this invention also relates to a test method for locating the source of plasma damage. Background Technology
[0002] Plasma etching, with its advantages of good directionality, low temperature requirements, and simple process, is widely used in integrated circuit manufacturing, such as through-hole etching, barrier layer etching, and photoresist ashing in metal interconnect processes. As circuit dimensions continue to shrink, the length and density of interconnects within chips are constantly increasing, and the number of metal wiring layers is also rapidly increasing. Because the uniformity of plasma is difficult to guarantee, the charge generated by non-uniformity travels along the metal interconnects to the gate, leading to charge accumulation and damage to the gate dielectric. Inappropriate wiring density and non-uniform plasma radiation will both exacerbate plasma damage to the gate dielectric. Therefore, designing a test structure capable of layer-by-layer monitoring and locating the source of plasma damage in metal interconnect layers becomes essential.
[0003] like Figure 1 The diagram shows a device structure when damage to the gate dielectric layer occurs during a conventional plasma etching process. A gate structure is formed on a semiconductor substrate, comprising a gate dielectric layer 102 and a gate conductive material layer 103 stacked sequentially. An interlayer film 101 covers the gate structure.
[0004] A metal layer 104 is formed on the top surface of the interlayer membrane 101.
[0005] In existing methods, the step of patterning and etching the metal layer 104 includes:
[0006] Photoresist 105 is coated, and the photoresist 105 is exposed and developed to form a pattern of photoresist 105.
[0007] Then, plasma etching is performed using the pattern of photoresist 105 as a mask. As the etching proceeds, the pattern of photoresist 105 will gradually transfer to the metal layer 104. Figure 1 The structure during the plasma etching process is shown. It can be seen that stripe 104a is the pattern formed after etching the top part of the metal layer 104; with further etching, the bottom part of the metal layer 104 will also be gradually etched away and etched through.
[0008] Figure 1The image also shows positive charges 106a and negative charges 106b focused by the plasma. As can be seen from arrow 107, the area traversed by arrow 107 is a conductor, thus forming a charge movement path. Charged charges can easily transfer along the corresponding path to the gate dielectric layer 102, thereby damaging the gate dielectric layer 102. Summary of the Invention
[0009] The technical problem to be solved by this invention is to provide a test structure for locating the source of plasma damage, which can monitor whether patterned etching of a selected metal layer will form the source of plasma damage in the corresponding gate dielectric layer, thereby locating the source of plasma damage. To this end, this invention also provides a test method for locating the source of plasma damage.
[0010] To solve the above-mentioned technical problems, the test structure for locating the source of plasma damage provided by the present invention includes: a test substructure corresponding to the selected metal layer.
[0011] The test substructure includes: a first MOS transistor, a first gate lead, a first antenna, and a monitoring gate pad.
[0012] The first MOS transistor includes a first gate structure, a first source region, and a first drain region. The first gate structure includes a first gate dielectric layer and a first gate conductive material layer.
[0013] The first gate lead is composed of metal wires of the selected metal layer.
[0014] The first antenna is connected to the first grid lead.
[0015] The first gate lead is connected to the first gate conductive material layer.
[0016] Plasma is used in the patterning etching of the selected metal layer. In the patterning etching of the selected metal layer, a first path is formed by the first antenna, the first gate lead and the first gate conductive material layer to accumulate plasma charge on the surface of the first gate dielectric layer. The first path is an amplification path with the first antenna. The first antenna is used to increase the absorption of plasma charge and amplify the damage of plasma charge to the first gate dielectric layer.
[0017] The monitoring gate pad is connected to the first gate lead. The monitoring gate pad is used to test the gate current of the first MOS transistor. The gate current of the first MOS transistor is used to monitor the amount of damage to the first gate dielectric layer caused by the plasma charge of the patterned etching of the selected metal layer.
[0018] A further improvement is that the top of the first gate conductive material layer includes multiple metal layers, each of which is provided with a corresponding test substructure, and each first gate lead corresponds one-to-one with its respective metal layer.
[0019] A further improvement is that, in the test substructure corresponding to the selected metal layer, the first antenna is composed of metal lines of the selected metal layer, or the first antenna is formed by connecting the metal lines of the selected metal layer and the metal lines of multiple layers of the selected metal layer at the bottom of the selected metal layer.
[0020] A further improvement is that, in the test substructure corresponding to the selected metal layer, the metal lines in the first antenna are connected in a serpentine manner.
[0021] A further improvement is the inclusion of a test benchmark structure.
[0022] The test reference structure includes a second MOS transistor, a second gate lead, and a reference gate pad.
[0023] The second MOS transistor includes a second gate structure, a second source region, and a second drain region. The second gate structure includes a second gate dielectric layer and a second gate conductive material layer.
[0024] The second gate lead is formed by connecting metal lines of one or more metal layers, and the second gate lead is connected to the second gate conductive material layer; in the patterned etching of each metal layer corresponding to the second gate lead, a second path is formed by the second gate lead and the first gate conductive material layer to accumulate plasma charge to the surface of the second gate dielectric layer, and the second path is a reference path without an antenna.
[0025] The reference gate pad is connected to the second gate lead. The reference gate pad is used to test the gate current of the second MOS transistor. The gate current of the second MOS transistor is compared with the gate current of the first MOS transistor in the selected metal layer to monitor the damage of the plasma charge from the patterned etching of the selected metal layer to the first gate dielectric layer.
[0026] A further improvement is that the gate currents of the first MOS transistor and the second MOS transistor in the selected metal layer are used to calculate a first ratio. The first ratio is the ratio between the gate currents of the first MOS transistor and the second MOS transistor in the selected metal layer. The first ratio is used to monitor the damage to the first gate dielectric layer caused by the plasma charge of the patterned etching of the selected metal layer. The larger the first ratio, the greater the damage to the first gate dielectric layer caused by the plasma charge of the patterned etching of the selected metal layer.
[0027] A further improvement is that each of the first MOS transistors and the second MOS transistors is formed in an independent active region.
[0028] The active regions of each of the first MOS transistors and the second MOS transistors are arranged in parallel and aligned, and the length edges of the active regions of each of the first MOS transistors and the second MOS transistors are parallel and along the channel width direction.
[0029] The first gate conductive material layer and the second gate conductive material layer are arranged in parallel, and the first gate lead and the second gate lead are arranged in parallel.
[0030] Each of the first grid leads is provided with a first jumper wire, which is located between the connection end of the first antenna and the first grid lead wire and the connection end of the monitoring grid pad and the first grid lead wire.
[0031] The second gate lead is provided with a second jumper, which is located between the connection end of the second gate lead and the second reference gate pad and the connection end of the second gate lead and the second gate conductive material layer.
[0032] A further improvement is that the first source region of each of the first MOS transistors and the second source region of each of the second MOS transistors are connected to the same source pad via source leads composed of metal wires.
[0033] The first drain region of each of the first MOS transistors and the second drain region of each of the second MOS transistors are connected to the same drain pad via drain leads composed of metal wires.
[0034] The substrate electrodes of the first MOS transistor and the second MOS transistor are connected to the same substrate pad via substrate electrode leads composed of metal wires.
[0035] A first protection diode is also provided on the path of each of the first gate leads. The first protection diode is located between the connection end of the monitoring gate pad and the first gate lead and the connection end of the line connecting the first gate lead and the substrate pad.
[0036] A second protection diode is also provided on the path of each of the second gate leads. The second protection diode is located between the connection end of the reference gate pad and the second gate lead and the connection end of the line connecting the second gate lead and the substrate pad.
[0037] A further improvement is that the monitoring grid pad, the source pad, the drain pad, the substrate pad, and the reference grid pad are arranged in the same row.
[0038] To solve the above-mentioned technical problems, the test structure used in the test method for locating the source of plasma damage provided by the present invention includes: a test substructure corresponding to the selected metal layer.
[0039] The test substructure includes: a first MOS transistor, a first gate lead, a first antenna, and a monitoring gate pad;
[0040] The first MOS transistor includes a first gate structure, a first source region, and a first drain region. The first gate structure includes a first gate dielectric layer and a first gate conductive material layer.
[0041] The first gate lead is composed of metal wires of the selected metal layer.
[0042] The first antenna is connected to the first grid lead.
[0043] The first gate lead is connected to the first gate conductive material layer.
[0044] Plasma is used in the patterning etching of the selected metal layer. In the patterning etching of the selected metal layer, a first path is formed by the first antenna, the first gate lead and the first gate conductive material layer to accumulate plasma charge on the surface of the first gate dielectric layer. The first path is an amplification path with the first antenna. The first antenna is used to increase the absorption of plasma charge and amplify the damage of plasma charge to the first gate dielectric layer.
[0045] The monitoring grid pad is connected to the first grid lead.
[0046] The steps of the testing method include:
[0047] The gate current of the first MOS transistor is tested using the monitoring gate pad.
[0048] The damage to the first gate dielectric layer caused by the plasma charge of the patterned etching of the selected metal layer is monitored using the gate current of the first MOS transistor.
[0049] A further improvement is that the top of the first gate conductive material layer includes multiple metal layers, each of which is provided with a corresponding test substructure, and each first gate lead corresponds one-to-one with its respective metal layer.
[0050] A further improvement is that, in the test substructure corresponding to the selected metal layer, the first antenna is composed of metal lines of the selected metal layer, or the first antenna is formed by connecting the metal lines of the selected metal layer and the metal lines of multiple layers of the selected metal layer at the bottom of the selected metal layer.
[0051] A further improvement is that, in the test substructure corresponding to the selected metal layer, the metal lines in the first antenna are connected in a serpentine manner.
[0052] A further improvement is the inclusion of a test benchmark structure.
[0053] The test reference structure includes: a second MOS transistor, a second gate lead, and a reference gate pad.
[0054] The second MOS transistor includes a second gate structure, a second source region, and a second drain region. The second gate structure includes a second gate dielectric layer and a second gate conductive material layer.
[0055] The second gate lead is formed by connecting metal lines of one or more metal layers, and the second gate lead is connected to the second gate conductive material layer; in the patterned etching of each metal layer corresponding to the second gate lead, a second path is formed by the second gate lead and the first gate conductive material layer to accumulate plasma charge to the surface of the second gate dielectric layer, and the second path is a reference path without an antenna.
[0056] The reference grid pad and the second grid lead are connected.
[0057] The steps of the testing method include:
[0058] The gate current of the second MOS transistor is tested using the reference gate pad.
[0059] The damage to the first gate dielectric layer caused by the patterned etching of the selected metal layer is monitored by comparing the gate current of the first MOS transistor and the gate current of the second MOS transistor in the selected metal layer.
[0060] A further improvement is that, in the test method, the step of comparing the gate current of the first MOS transistor and the gate current of the second MOS transistor in the selected metal layer includes:
[0061] A first ratio is calculated between the gate current of the first MOS transistor and the gate current of the second MOS transistor in the selected metal layer. The first ratio is used to monitor the damage to the first gate dielectric layer caused by the plasma charge of the patterned etching of the selected metal layer. The larger the first ratio, the greater the damage to the first gate dielectric layer caused by the plasma charge of the patterned etching of the selected metal layer.
[0062] A further improvement is that each of the first MOS transistors and the second MOS transistors is formed in an independent active region.
[0063] The active regions of each of the first MOS transistors and the second MOS transistors are arranged in parallel and aligned, and the length edges of the active regions of each of the first MOS transistors and the second MOS transistors are parallel and along the channel width direction.
[0064] The first gate conductive material layer and the second gate conductive material layer are arranged in parallel, and the first gate lead and the second gate lead are arranged in parallel.
[0065] Each of the first grid leads is provided with a first jumper wire, which is located between the connection end of the first antenna and the first grid lead wire and the connection end of the monitoring grid pad and the first grid lead wire.
[0066] The second gate lead is provided with a second jumper, which is located between the connection end of the second gate lead and the second reference gate pad and the connection end of the second gate lead and the second gate conductive material layer.
[0067] A further improvement is that the first source region of each of the first MOS transistors and the second source region of each of the second MOS transistors are connected to the same source pad via source leads composed of metal wires.
[0068] The first drain region of each of the first MOS transistors and the second drain region of each of the second MOS transistors are connected to the same drain pad via drain leads composed of metal wires.
[0069] The substrate electrodes of the first MOS transistor and the second MOS transistor are connected to the same substrate pad via substrate electrode leads composed of metal wires.
[0070] A first protection diode is also provided on the path of each of the first gate leads. The first protection diode is located between the connection end of the monitoring gate pad and the first gate lead and the connection end of the line connecting the first gate lead and the substrate pad.
[0071] A second protection diode is also provided on the path of each of the second gate leads. The second protection diode is located between the connection end of the reference gate pad and the second gate lead and the connection end of the line connecting the second gate lead and the substrate pad.
[0072] The monitoring grid pad, the source pad, the drain pad, the substrate pad, and the reference grid pad are arranged in the same row.
[0073] This invention provides a test substructure corresponding to a selected metal layer. The test substructure includes a first antenna positioned within a first path through which plasma charges from the patterned etching of the selected metal layer accumulate on the surface of the first gate dielectric layer. This first path acts as an amplification path, amplifying the damage caused by the plasma charges to the first gate dielectric layer. The amount of damage to the first gate dielectric layer can be obtained by monitoring the gate current of the first MOS transistor being tested on the gate pad. Therefore, by testing the gate current of the first MOS transistor, this invention can determine the amount of damage to the first gate dielectric layer of the first MOS transistor and thus determine whether the patterned etching plasma of the selected metal layer is the source of plasma damage to the gate dielectric layer. Therefore, this invention can monitor whether the patterned etching of the selected metal layer will form the source of corresponding plasma damage to the gate dielectric layer, thereby locating the source of plasma damage.
[0074] This invention can further set up multiple test substructures so that each metal layer has a corresponding test substructure. In this way, it is possible to monitor whether each metal layer is a source of plasma damage. Therefore, this invention can quickly find the metal layers with plasma damage sources among all metal layers.
[0075] The present invention can further set up a test reference structure. In the test reference structure, the second path for the accumulation of plasma charge on the surface of the second gate dielectric layer is a reference path without an antenna and therefore cannot be amplified. By comparing the gate current of the first MOS transistor and the gate current of the second MOS transistor in the test reference structure, the source of plasma damage can be located more quickly. Attached Figure Description
[0076] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:
[0077] Figure 1 This is a schematic diagram of the device structure when the gate dielectric layer is damaged in the existing plasma etching process;
[0078] Figure 2 This is a schematic diagram of the test substructure of the test structure for locating the source of plasma damage in an embodiment of the present invention;
[0079] Figure 3 This is a schematic diagram of the test structure for locating the source of plasma damage according to a preferred embodiment of the present invention;
[0080] Figure 4 This is a schematic diagram of the arrangement of the pads in the test structure for locating the source of plasma damage according to a preferred embodiment of the present invention. Detailed Implementation
[0081] like Figure 2The diagram shown is a schematic diagram of the test substructure 201 of the test structure 301 for locating the source of plasma damage in an embodiment of the present invention. The test structure 301 for locating the source of plasma damage in an embodiment of the present invention includes: a test substructure 201 corresponding to the selected metal layer.
[0082] The test substructure 201 includes: a first MOS transistor 202, a first gate lead 203, a first antenna 204, and a monitoring gate pad 205.
[0083] The first MOS transistor 202 includes a first gate structure, a first source region, and a first drain region. The first gate structure includes a first gate dielectric layer and a first gate conductive material layer 207. In some embodiments, the first gate conductive material layer 207 is a polysilicon gate or a metal gate.
[0084] The first MOS transistor 202 is formed in the corresponding active region 206. The first source region and the first drain region are self-aligned and formed in the active regions 206 on both sides of the first gate conductive material layer 207.
[0085] The first gate lead 203 is composed of metal wires of the selected metal layer.
[0086] The first antenna 204 is connected to the first grid lead 203.
[0087] In this embodiment of the invention, the metal wires in the first antenna 204 are connected in a serpentine manner. In other embodiments, other suitable connection structures can also be used to form the first antenna 204.
[0088] The first gate lead 203 is connected to the first gate conductive material layer 207.
[0089] Plasma is used in the patterning etching of the selected metal layer. In the patterning etching of the selected metal layer, the first antenna 204, the first gate lead 203 and the first gate conductive material layer 207 form a first path for the accumulation of plasma charge on the surface of the first gate dielectric layer. The first path is an amplification path with the first antenna 204. The first antenna 204 is used to increase the absorption of plasma charge and amplify the damage of plasma charge to the first gate dielectric layer.
[0090] The monitoring gate pad 205 is connected to the first gate lead 203. The monitoring gate pad 205 is used to test the gate current of the first MOS transistor 202. The gate current of the first MOS transistor 202 is used to monitor the amount of damage to the first gate dielectric layer caused by the plasma charge of the patterned etching of the selected metal layer.
[0091] The top of the first gate conductive material layer 207 includes multiple metal layers. For example... Figure 3 The diagram shown is a schematic representation of the test structure 301 for locating plasma damage sources according to an embodiment of the present invention. In a preferred embodiment, each metal layer is provided with a corresponding test substructure 201, and each first gate lead 203 corresponds one-to-one with its respective metal layer. In other embodiments, it is also possible to: firstly select the metal layers that are prone to plasma damage; the selected metal layers are only a portion of all the metal layers; provide the corresponding test substructure 201 for each selected metal layer; and not provide the corresponding test substructure 201 for the unselected metal layers.
[0092] Figure 3 The entire test structure 301 of a preferred embodiment of the present invention is shown in the figure. Figure 3 The structure includes n metal layers, each of which is sequentially labeled M1, M2, M3, M4, ..., Mn. Each metal layer is provided with a test substructure 201. Figure 3 In the above, the n monitoring gate pads are arranged in the order of M1, M2, M3, M4...Mn, and are sequentially labeled as 2051, 2052, 2053, 2054...205n. The n first MOS transistors are sequentially labeled as 2021, 2022, 2023, 2024...202n. Figure 2 The corresponding first gate lead 203 in Figure 3 There are n metal wires, which correspond to the metal layers M1, M2, M3, M4...Mn respectively.
[0093] Figure 3 In the dashed box 302, there are n items. Figure 2 The first antenna 204 shown is connected to the first gate lead 203 corresponding to the metal layer. Figure 3The diagram shows n first antennas 204 formed in the same region, indicated by the dashed box 302. However, these n first antennas 204 are not located on the same metal layer. Therefore, in cross-sectional structure, the n first antennas 204 are separate, i.e., independent. Each first antenna 204 is composed of metal lines of the selected metal layer. Similarly, the n first gate leads 203 described above are also independent of each other and correspond one-to-one with their respective metal layers. Only in this way can each test substructure 201 correspond to a metal layer, thereby enabling each test substructure 201 to test whether the plasma etching process of the corresponding metal layer is a source of damage. In other embodiments, the first antennas 204 may not be located in the same region. In this case, in some embodiments, the first antenna 204 is composed of metal lines of the selected metal layer. In other embodiments, the first antenna 204 may be formed by connecting the metal lines of the selected metal layer and the metal lines of multiple layers of the selected metal layer at the bottom. The metal lines of the multiple layers of the metal layer need to be connected through vias 212.
[0094] In a preferred embodiment of the present invention, such as Figure 3 As shown, it also includes a test baseline structure 201'.
[0095] The test reference structure 201' includes a second MOS transistor 202', a second gate lead 203', and a reference gate pad 205'. Figure 2 Compared to the test substructure 201 in the test reference structure 201', there are fewer antennas in the test reference structure 201'.
[0096] The second MOS transistor 202' includes a second gate structure, a second source region and a second drain region. The second gate structure includes a second gate dielectric layer and a second gate conductive material layer 207'.
[0097] The second MOS transistor 202' is formed in the corresponding active region 206. The first source region and the first drain region are self-aligned and formed in the active regions 206 on both sides of the second gate conductive material layer 207'.
[0098] The second gate lead 203' is formed by connecting metal lines of one or more metal layers, and the second gate lead 203' is connected to the second gate conductive material layer 207'. In the patterned etching of each metal layer corresponding to the second gate lead 203', the second gate lead 203' and the first gate conductive material layer 207 form a second path for the accumulation of plasma charge to the surface of the second gate dielectric layer. The second path is a reference path without an antenna.
[0099] The reference gate pad 205' and the second gate lead 203' are connected. The reference gate pad 205' is used to test the gate current of the second MOS transistor 202'. The gate current of the second MOS transistor 202' is compared with the gate current of the first MOS transistor 202 in the selected metal layer to monitor the damage to the first gate dielectric layer caused by the plasma charge of the patterned etching of the selected metal layer. More preferably, the gate current of the first MOS transistor 202 and the gate current of the second MOS transistor 202' in the selected metal layer are used to calculate a first ratio. The first ratio is the ratio between the gate current of the first MOS transistor 202 and the gate current of the second MOS transistor 202' in the selected metal layer. The damage to the first gate dielectric layer caused by the plasma charge of the patterned etching of the selected metal layer is monitored by the first ratio. The larger the first ratio, the greater the damage to the first gate dielectric layer caused by the plasma charge of the patterned etching of the selected metal layer.
[0100] like Figure 3 As shown, each of the first MOS transistors 202, namely the first MOS transistors 2021, 2022, 2023, 2024...202n, and the second MOS transistors 202' are respectively formed in an independent active region 206. The active regions 206 of each of the first MOS transistors 202 and the second MOS transistors 202' are arranged in parallel and aligned, and the length edges of the active regions 206 of each of the first MOS transistors 202 and the second MOS transistors 202' are parallel and along the channel width direction.
[0101] The first gate conductive material layer 207 and the second gate conductive material layer 207' are arranged in parallel, and the first gate lead 203 and the second gate lead 203' are arranged in parallel. Figure 3 It can be seen that the active region 206, each of the first gate conductive material layers 207 and the second gate conductive material layers 207', and each of the first gate leads 203 and the second gate leads 203' are arranged in parallel to form an array structure.
[0102] In some embodiments, such as Figure 3 As shown, each of the first grid leads 203 is provided with a first jumper 304, which is located between the connection end of the first antenna 204 and the first grid lead 203 and the connection end of the monitoring grid pad 205 and the first grid lead 203.
[0103] A second jumper 304' is provided in the second gate lead 203'. The second jumper 304' is located between the connection end of the second gate lead 203' and the second reference gate pad 205' and the connection end of the second gate lead 203' and the second gate conductive material layer 207'.
[0104] In some embodiments, such as Figure 3 As shown, the first source region of each of the first MOS transistors 202 and the second source region of each of the second MOS transistors 202' are connected to the same source pad 209 through source leads composed of metal wires. Figure 3 In this context, the source lead is composed of metal wires in the metal layer M1.
[0105] The first drain region of each of the first MOS transistors 202 and the second drain region of each of the second MOS transistors 202' are connected to the same drain pad 211 via drain leads composed of metal wires. Figure 3 In this context, the source lead is composed of metal wires in metal layer M2.
[0106] The substrate electrodes of the first MOS transistor 202 and the second MOS transistor 202' are all connected to the same substrate pad 212 via substrate electrode leads composed of metal wires. Figure 3 In this context, each of the active regions 206 is isolated on the semiconductor substrate through shallow trench isolation. Figure 3 The diagram also shows another active region 206' adjacent to each of the active regions 206. The other active region 206' is connected to the active region 206. A contact hole or through hole 212 is formed on the top of the other active region 206' and connected to the substrate electrode lead and finally connected to the substrate pad 212. Figure 3 In this context, the substrate electrode leads are composed of metal lines from the metal layer M1.
[0107] In some embodiments, such as Figure 3 As shown, a first protection diode 305 is also provided on the path of each of the first gate leads 203. The first protection diode 305 is located between the connection end of the monitoring gate pad 205 and the first gate lead 203 and the connection end of the line connecting the first gate lead 203 and the substrate pad 212.
[0108] A second protection diode 305' is also provided on the path of each of the second gate leads 203'. The second protection diode 305' is located between the connection end of the reference gate pad 205' and the second gate lead 203' and the connection end of the line connecting the second gate lead 203' and the substrate pad 212.
[0109] like Figure 4The diagram shows the arrangement of the pads in the test structure 301 for locating plasma damage sources according to an embodiment of the present invention; each of the monitoring grid pads 205, the source pads 209, the drain pads 211, the substrate pads 212, and the reference grid pads 205' is arranged in the same row. Figure 4 The document also shows that the first antenna 204 corresponding to each of the test substructures 201 is set in different regions. Figure 4 In the middle, box 401 indicates Figure 3 An array structure formed by arranging the first MOS transistor 202 and the first gate lead 203 corresponding to each of the test substructures 201 and the second MOS transistor 202' and the second gate lead 203' of the test reference structure 201'. Figure 4 As shown, during the test, it is only necessary to apply a suitable electrical signal to the corresponding pad and read the corresponding electrical signal.
[0110] In this embodiment of the invention, a test substructure 201 corresponding to the selected metal layer is provided. The test substructure 201 is provided with a first antenna 204, which is positioned in a first path through which the plasma charge from the patterned etching of the selected metal layer accumulates on the surface of the first gate dielectric layer. This first path can be an amplification path, thus amplifying the damage of the plasma charge to the first gate dielectric layer caused by the test substructure 201. The amount of damage to the first gate dielectric layer can be obtained by monitoring the gate current of the first MOS transistor 202 tested by the gate pad 205. Therefore, by testing the gate current of the first MOS transistor 202, this embodiment of the invention can determine the amount of damage to the first gate dielectric layer of the first MOS transistor 202, and thus determine whether the patterned etching plasma of the selected metal layer is the source of plasma damage to the gate dielectric layer. Therefore, this embodiment of the invention can monitor whether the patterned etching of the selected metal layer will form the source of plasma damage to the corresponding gate dielectric layer, thereby locating the source of plasma damage.
[0111] The embodiments of the present invention can further set up multiple test substructures 201, so that each metal layer has a corresponding test substructure 201. In this way, it is possible to monitor whether each metal layer is a source of plasma damage. Therefore, the embodiments of the present invention can quickly find the metal layers with plasma damage sources among all metal layers.
[0112] In this embodiment of the invention, a test reference structure 201' can be further configured. The second path in the test reference structure 201' where plasma charge accumulates on the surface of the second gate dielectric layer is a reference path without an antenna and therefore cannot be amplified. By comparing the gate current of the first MOS transistor 202 and the gate current of the second MOS transistor 202' in the test reference structure 201', the source of plasma damage can be located more quickly.
[0113] The test structure of this invention consists of several discrete gates that connect the plasma-damaged antenna structure to transistors. The discrete gate leads belong to different metal layers, and the source, drain, and substrate leads of each transistor are shared. The discrete gates are the first gate conductive material layers 207 of each of the first MOS transistors 202, which are separated from each other.
[0114] The test structure 301 used in the test method for locating the source of plasma damage in this embodiment of the invention includes: a test substructure 201 corresponding to the selected metal layer.
[0115] The test substructure 201 includes: a first MOS transistor 202, a first gate lead 203, a first antenna 204, and a monitoring gate pad 205.
[0116] The first MOS transistor 202 includes a first gate structure, a first source region, and a first drain region. The first gate structure includes a first gate dielectric layer and a first gate conductive material layer 207. In some embodiments, the first gate conductive material layer 207 is a polysilicon gate or a metal gate.
[0117] The first MOS transistor 202 is formed in the corresponding active region 206. The first source region and the first drain region are self-aligned and formed in the active regions 206 on both sides of the first gate conductive material layer 207.
[0118] The first gate lead 203 is composed of metal wires of the selected metal layer.
[0119] The first antenna 204 is connected to the first grid lead 203.
[0120] In this embodiment of the invention, the metal wires in the first antenna 204 are connected in a serpentine manner. In other embodiments, other suitable connection structures can also be used to form the first antenna 204.
[0121] The first gate lead 203 is connected to the first gate conductive material layer 207.
[0122] Plasma is used in the patterning etching of the selected metal layer. In the patterning etching of the selected metal layer, the first antenna 204, the first gate lead 203 and the first gate conductive material layer 207 form a first path for the accumulation of plasma charge on the surface of the first gate dielectric layer. The first path is an amplification path with the first antenna 204. The first antenna 204 is used to increase the absorption of plasma charge and amplify the damage of plasma charge to the first gate dielectric layer.
[0123] The monitoring grid pad 205 is connected to the first grid lead 203.
[0124] The steps of the testing method include:
[0125] The gate current of the first MOS transistor 202 is tested using the monitoring gate pad 205.
[0126] The damage to the first gate dielectric layer caused by the plasma charge of the patterned etching of the selected metal layer is monitored using the gate current of the first MOS transistor 202.
[0127] The top of the first gate conductive material layer 207 includes multiple metal layers. In a preferred embodiment of the present invention, each metal layer is provided with a corresponding test substructure 201, and each first gate lead 203 corresponds one-to-one with its respective metal layer. In other embodiments, it is also possible to: firstly select the metal layers that are prone to plasma damage, the selected metal layers are only a portion of all the metal layers, and provide the corresponding test substructure 201 for each selected metal layer, while not providing the corresponding test substructure 201 for the unselected metal layers.
[0128] Figure 3 The entire test structure 301 of a preferred embodiment of the present invention is shown in the figure. Figure 3 The structure includes n metal layers, each of which is sequentially labeled M1, M2, M3, M4, ..., Mn. Each metal layer is provided with a test substructure 201. Figure 3 In the above, the n monitoring gate pads are arranged in the order of M1, M2, M3, M4...Mn, and are sequentially labeled as 2051, 2052, 2053, 2054...205n. The n first MOS transistors are sequentially labeled as 2021, 2022, 2023, 2024...202n. Figure 2 The corresponding first gate lead 203 in Figure 3 There are n metal wires, which correspond to the metal layers M1, M2, M3, M4...Mn respectively.
[0129] Figure 3In the dashed box 302, there are n items. Figure 2 The first antenna 204 shown is connected to the first gate lead 203 corresponding to the metal layer. Figure 3 The diagram shows n first antennas 204 formed in the same region, indicated by the dashed box 302. However, these n first antennas 204 are not located on the same metal layer. Therefore, in cross-sectional structure, the n first antennas 204 are separate, i.e., independent. Each first antenna 204 is composed of metal lines of the selected metal layer. Similarly, the n first gate leads 203 described above are also independent of each other and correspond one-to-one with their respective metal layers. Only in this way can each test substructure 201 correspond to a metal layer, thereby enabling each test substructure 201 to test whether the plasma etching process of the corresponding metal layer is a source of damage. In other embodiments, the first antennas 204 may not be located in the same region. In this case, in some embodiments, the first antenna 204 is composed of metal lines of the selected metal layer. In other embodiments, the first antenna 204 may be formed by connecting the metal lines of the selected metal layer and the metal lines of multiple layers of the selected metal layer at the bottom. The metal lines of the multiple layers of the metal layer need to be connected through vias 212.
[0130] In a preferred embodiment of the present invention, such as Figure 3 As shown, it also includes a test baseline structure 201'.
[0131] The test reference structure 201' includes a second MOS transistor 202', a second gate lead 203', and a reference gate pad 205'. Figure 2 Compared to the test substructure 201 in the test reference structure 201', there are fewer antennas in the test reference structure 201'.
[0132] The second MOS transistor 202' includes a second gate structure, a second source region and a second drain region. The second gate structure includes a second gate dielectric layer and a second gate conductive material layer 207'.
[0133] The second MOS transistor 202' is formed in the corresponding active region 206. The first source region and the first drain region are self-aligned and formed in the active regions 206 on both sides of the second gate conductive material layer 207'.
[0134] The second gate lead 203' is formed by connecting metal lines of one or more metal layers, and the second gate lead 203' is connected to the second gate conductive material layer 207'. In the patterned etching of each metal layer corresponding to the second gate lead 203', the second gate lead 203' and the first gate conductive material layer 207 form a second path for the accumulation of plasma charge to the surface of the second gate dielectric layer. The second path is a reference path without an antenna.
[0135] The reference grid pad 205' and the second grid lead 203' are connected.
[0136] like Figure 3 As shown, each of the first MOS transistors 202, namely the first MOS transistors 2021, 2022, 2023, 2024...202n, and the second MOS transistors 202' are respectively formed in an independent active region 206. The active regions 206 of each of the first MOS transistors 202 and the second MOS transistors 202' are arranged in parallel and aligned, and the length edges of the active regions 206 of each of the first MOS transistors 202 and the second MOS transistors 202' are parallel and along the channel width direction.
[0137] The first gate conductive material layer 207 and the second gate conductive material layer 207' are arranged in parallel, and the first gate lead 203 and the second gate lead 203' are arranged in parallel. Figure 3 It can be seen that the active region 206, each of the first gate conductive material layers 207 and the second gate conductive material layers 207', and each of the first gate leads 203 and the second gate leads 203' are arranged in parallel to form an array structure.
[0138] In some embodiments, such as Figure 3 As shown, each of the first grid leads 203 is provided with a first jumper 304, which is located between the connection end of the first antenna 204 and the first grid lead 203 and the connection end of the monitoring grid pad 205 and the first grid lead 203.
[0139] A second jumper 304' is provided in the second gate lead 203'. The second jumper 304' is located between the connection end of the second gate lead 203' and the second reference gate pad 205' and the connection end of the second gate lead 203' and the second gate conductive material layer 207'.
[0140] In some embodiments, such as Figure 3As shown, the first source region of each of the first MOS transistors 202 and the second source region of each of the second MOS transistors 202' are connected to the same source pad 209 through source leads composed of metal wires. Figure 3 In this context, the source lead is composed of metal wires in the metal layer M1.
[0141] The first drain region of each of the first MOS transistors 202 and the second drain region of each of the second MOS transistors 202' are connected to the same drain pad 211 via drain leads composed of metal wires. Figure 3 In this context, the source lead is composed of metal wires in metal layer M2.
[0142] The substrate electrodes of the first MOS transistor 202 and the second MOS transistor 202' are all connected to the same substrate pad 212 via substrate electrode leads composed of metal wires. Figure 3 In this context, each of the active regions 206 is isolated on the semiconductor substrate through shallow trench isolation. Figure 3 The diagram also shows another active region 206' adjacent to each of the active regions 206. The other active region 206' is connected to the active region 206. A contact hole or through hole 212 is formed on the top of the other active region 206' and connected to the substrate electrode lead and finally connected to the substrate pad 212. Figure 3 In this context, the substrate electrode leads are composed of metal lines from the metal layer M1.
[0143] In some embodiments, such as Figure 3 As shown, a first protection diode 305 is also provided on the path of each of the first gate leads 203. The first protection diode 305 is located between the connection end of the monitoring gate pad 205 and the first gate lead 203 and the connection end of the line connecting the first gate lead 203 and the substrate pad 212.
[0144] A second protection diode 305' is also provided on the path of each of the second gate leads 203'. The second protection diode 305' is located between the connection end of the reference gate pad 205' and the second gate lead 203' and the connection end of the line connecting the second gate lead 203' and the substrate pad 212.
[0145] like Figure 4 The diagram shows the arrangement of the pads in the test structure 301 for locating plasma damage sources according to an embodiment of the present invention; each of the monitoring grid pads 205, the source pads 209, the drain pads 211, the substrate pads 212, and the reference grid pads 205' is arranged in the same row. Figure 4 The document also shows that the first antenna 204 corresponding to each of the test substructures 201 is set in different regions. Figure 4In the middle, box 401 indicates Figure 3 An array structure formed by arranging the first MOS transistor 202 and the first gate lead 203 corresponding to each of the test substructures 201 and the second MOS transistor 202' and the second gate lead 203' of the test reference structure 201'. Figure 4 As shown, during the test, it is only necessary to apply a suitable electrical signal to the corresponding pad and read the corresponding electrical signal.
[0146] In a preferred embodiment of the present invention, the testing method further includes the following steps:
[0147] The gate current of the second MOS transistor 202' is tested using the reference gate pad 205'.
[0148] The damage to the first gate dielectric layer caused by the patterned etching of the selected metal layer is monitored by comparing the gate current of the first MOS transistor 202 and the gate current of the second MOS transistor 202' of the selected metal layer.
[0149] More preferably, in the test method, the step of comparing the gate current of the first MOS transistor 202 and the gate current of the second MOS transistor 202' in the selected metal layer includes:
[0150] A first ratio is calculated between the gate current of the first MOS transistor 202 and the gate current of the second MOS transistor 202' in the selected metal layer. The first ratio is used to monitor the damage of the plasma charge from the patterned etching of the selected metal layer to the first gate dielectric layer. The larger the first ratio, the greater the damage of the plasma charge from the patterned etching of the selected metal layer to the first gate dielectric layer.
[0151] For example, let the gate currents of the first MOS transistors 202 measured on the n monitoring gate pads corresponding to the labels 2051, 2052, 2053, 2054, ..., 205n be I1, I2, ..., In respectively, and let the gate current of the second MOS transistor 202' measured on the reference gate pad 205' be I0. Then the first ratios are I1 / I0, I2 / I0, ..., In / I0 respectively. The first ratio is the plasma damage parameter. The larger the ratio, the more severe the plasma damage.
[0152] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.
Claims
1. A test structure for locating a source of plasma damage, characterized by, The application relates to a test structure for monitoring plasma damage in a selected metal layer during a lithographic etching process. The test structure comprises a first MOS transistor, a first gate lead, a first antenna and a monitoring gate pad. The first MOS transistor comprises a first gate structure, a first source region and a first drain region, and the first gate structure comprises a first gate dielectric layer and a first gate conductive material layer. The first gate lead is composed of metal lines of the selected metal layer. The first antenna is connected to the first gate lead. The first gate lead is connected to the first gate conductive material layer. During the lithographic etching of the selected metal layer, a first path for plasma charges to accumulate on the surface of the first gate dielectric layer is formed by the first antenna, the first gate lead and the first gate conductive material layer, and the first antenna is used to increase the absorption of plasma charges and amplify the damage of plasma charges to the first gate dielectric layer. The monitoring gate pad is connected to the first gate lead, and the monitoring gate pad is used to test the gate current of the first MOS transistor, which is used to monitor the damage of plasma charges in the lithographic etching of the selected metal layer to the first gate dielectric layer. The top of the first gate conductive material layer comprises a plurality of metal layers, and each metal layer is provided with a corresponding test structure.
2. The test structure for locating a source of plasma damage as recited in claim 1, wherein: In the test structure corresponding to the selected metal layer, the first antenna is composed of metal lines of the selected metal layer or the first antenna is formed by connecting metal lines of the selected metal layer and metal lines of a plurality of metal layers at the bottom of the selected metal layer.
3. The test structure for locating a source of plasma damage as recited in claim 2, wherein: In the test structure corresponding to the selected metal layer, each metal line in the first antenna is in a snake-shaped connection structure.
4. The test structure for locating a source of plasma damage as recited in claim 3, wherein: The application further relates to a test reference structure.
5. The test structure for locating a source of plasma damage as recited in claim 2, wherein, The test reference structure comprises a second MOS transistor, a second gate lead and a reference gate pad. The second MOS transistor comprises a second gate structure, a second source region and a second drain region, and the second gate structure comprises a second gate dielectric layer and a second gate conductive material layer. The second gate lead is connected by metal lines of one or more metal layers, and the second gate lead is connected to the second gate conductive material layer. In the lithographic etching of each metal layer corresponding to the second gate lead, a second path for plasma charges to accumulate on the surface of the second gate dielectric layer is formed by the second gate lead and the first gate conductive material layer, and the second path is a reference path without an antenna. The reference gate pad is connected to the second gate lead, and the reference gate pad is used to test the gate current of the second MOS transistor. The gate current of the second MOS transistor is compared with the gate current of the first MOS transistor of the selected metal layer to monitor the damage of plasma charges in the lithographic etching of the selected metal layer to the first gate dielectric layer.
6. The test structure for locating a source of plasma damage as recited in claim 5, wherein: The gate current of the first MOS transistor and the gate current of the second MOS transistor of the selected metal layer are used to calculate a first ratio, the first ratio being a ratio between the gate current of the first MOS transistor and the gate current of the second MOS transistor of the selected metal layer, the first ratio being used to monitor the damage of the first gate dielectric layer caused by the plasma charge of the patterned etching of the selected metal layer, the greater the first ratio, the greater the damage of the first gate dielectric layer caused by the plasma charge of the patterned etching of the selected metal layer.
7. The test structure for locating sources of plasma damage as recited in claim 5, wherein: Each of the first MOS transistor and the second MOS transistor is formed in an independent active region. The active regions of each of the first MOS transistor and the second MOS transistor are arranged in parallel and aligned, and the length edges of the active regions of each of the first MOS transistor and the second MOS transistor are parallel and along the channel width direction. Each of the first gate conductive material layer and the second gate conductive material layer is arranged in parallel, and each of the first gate lead and the second gate lead is arranged in parallel. A first jumper wire is arranged in each of the first gate leads, and the first jumper wire is located between the connection end of the first antenna and the first gate lead and the connection end of the monitoring gate pad and the first gate lead. A second jumper wire is arranged in the second gate lead, and the second jumper wire is located between the connection end of the second gate lead and the second reference gate pad and the connection end of the second gate lead and the second gate conductive material layer.
8. The test structure for locating a source of plasma damage as recited in claim 7, wherein: The first source region of each of the first MOS transistors and the second source region of the second MOS transistor are connected to the same source pad through a source lead composed of a metal wire. The first drain region of each of the first MOS transistors and the second drain region of the second MOS transistor are connected to the same drain pad through a drain lead composed of a metal wire. The substrate electrode of each of the first MOS transistors and the substrate electrode of the second MOS transistor are connected to the same substrate pad through a substrate electrode lead composed of a metal wire. A first protection diode is further arranged on the path of each of the first gate leads, and the first protection diode is located between the connection end of the monitoring gate pad and the first gate lead and the connection end of the connection line of the first gate lead and the substrate pad. A second protection diode is further arranged on the path of each of the second gate leads, and the second protection diode is located between the connection end of the reference gate pad and the second gate lead and the connection end of the connection line of the second gate lead and the substrate pad.
9. The test structure for locating sources of plasma damage as recited in claim 8, wherein: Each of the monitoring gate pad, the source pad, the drain pad, the substrate pad and the reference gate pad is arranged on the same row.
10. A test method for locating a source of plasma damage, characterized by, The test method adopts a test structure including a test substructure corresponding to the selected metal layer. The test substructure includes a first MOS transistor, a first gate lead, a first antenna and a monitoring gate pad. The first MOS transistor includes a first gate structure, a first source region and a first drain region, and the first gate structure includes a first gate dielectric layer and a first gate conductive material layer. The first gate lead is composed of metal lines of the selected metal layer; The first antenna and the first gate lead are connected; The first gate lead and the first gate conductive material layer are connected; In the patterning etching of the selected metal layer, plasma is used, and in the patterning etching of the selected metal layer, a first path for plasma charges to accumulate on the surface of the first gate dielectric layer is formed by the first antenna, the first gate lead, and the first gate conductive material layer, and the first antenna is used to increase the absorption of plasma charges and amplify the damage of plasma charges to the first gate dielectric layer; The monitoring gate liner and the first gate lead are connected; The steps of the test method include: Testing the gate current of the first MOS transistor through the monitoring gate liner; Monitoring the amount of damage of plasma charges of the patterning etching of the selected metal layer to the first gate dielectric layer by using the gate current of the first MOS transistor.
11. The method of claim 10, wherein the step of locating the source of the plasma damage is performed by: determining a location of the source of the plasma damage based on the detected signal. 10 The top of the first gate conductive material layer includes multiple metal layers, and each of the metal layers is provided with a corresponding test substructure, and each of the first gate leads and the corresponding metal layer are one-to-one corresponding.
12. The method of claim 11, wherein the step of locating the source of the plasma damage is performed by: In the test substructure corresponding to the selected metal layer, the first antenna is composed of metal lines of the selected metal layer, or the first antenna is formed by connecting metal lines of the selected metal layer and metal lines of multiple metal layers at the bottom of the selected metal layer. 13. The method of claim 12, wherein the step of locating the source of the plasma damage is performed by: In the test substructure corresponding to the selected metal layer, each metal line in the first antenna is in a serpentine connection structure. 14. The test method for locating the source of plasma damage as described in claim 11, characterized in that, It also includes a test reference structure; The test reference structure includes a second MOS transistor, a second gate lead, and a reference gate liner; The second MOS transistor includes a second gate structure, a second source region, and a second drain region, and the second gate structure includes a second gate dielectric layer and a second gate conductive material layer; The second gate lead is connected by metal lines of one or more metal layers, and the second gate lead and the second gate conductive material layer are connected; in the patterning etching of each of the metal layers corresponding to the second gate lead, a second path for plasma charges to accumulate on the surface of the second gate dielectric layer is formed by the second gate lead and the first gate conductive material layer, and the second path is an antenna-free reference path; The reference gate liner and the second gate lead are connected; The steps of the test method include: Testing the gate current of the second MOS transistor through the reference gate liner; Comparing the gate current of the first MOS transistor and the gate current of the second MOS transistor of the selected metal layer to monitor the amount of damage of plasma charges of the patterning etching of the selected metal layer to the first gate dielectric layer.
15. The method of claim 14, wherein the test method is used to locate a source of plasma damage. In the test method, the step of comparing the gate current of the first MOS transistor and the gate current of the second MOS transistor of the selected metal layer includes: A first ratio between a gate current of the first MOS transistor and a gate current of the second MOS transistor of the selected metal layer is calculated, and the first ratio is used to monitor a damage of the first gate dielectric layer caused by a plasma charge of a patterned etching of the selected metal layer, the greater the first ratio, the greater the damage of the first gate dielectric layer caused by the plasma charge of the patterned etching of the selected metal layer.
16. The method of claim 14, wherein the step of locating the source of the plasma damage is performed by: Each of the first MOS transistor and the second MOS transistor is formed in an independent active region. Active regions of each of the first MOS transistor and the second MOS transistor are arranged in parallel and aligned, and length edges of the active regions of each of the first MOS transistor and the second MOS transistor are parallel and along a channel width direction. Each of the first gate conductive material layer and the second gate conductive material layer is arranged in parallel, and each of the first gate lead and the second gate lead is arranged in parallel. A first jumper wire is arranged in each of the first gate lead, and the first jumper wire is located between a connection end of the first antenna and the first gate lead and a connection end of the monitoring gate pad and the first gate lead. A second jumper wire is arranged in the second gate lead, and the second jumper wire is located between a connection end of the second gate lead and the second reference gate pad and a connection end of the second gate lead and the second gate conductive material layer.
17. The method of claim 16, wherein the test method is used to locate a source of plasma damage. First source regions of each of the first MOS transistor and second source regions of the second MOS transistor are connected to a same source pad through source leads composed of metal wires. First drain regions of each of the first MOS transistor and second drain regions of the second MOS transistor are connected to a same drain pad through drain leads composed of metal wires. Substrate electrodes of each of the first MOS transistor and the second MOS transistor are connected to a same substrate pad through substrate electrode leads composed of metal wires. First protection diodes are arranged on paths of each of the first gate lead, and the first protection diodes are located between the connection end of the monitoring gate pad and the first gate lead and a connection end of a connection line of the first gate lead and the substrate pad. Second protection diodes are arranged on paths of each of the second gate lead, and the second protection diodes are located between the connection end of the reference gate pad and the second gate lead and a connection end of a connection line of the second gate lead and the substrate pad. The monitoring gate pad, the source pad, the drain pad, the substrate pad, and the reference gate pad are arranged on a same row.