Calibration circuit, chip and electronic device

Abstract

The application discloses a calibration circuit, a chip and an electronic device. The calibration circuit comprises a target sub-circuit, and is used for calibrating a target chip comprising a to-be-calibrated pull-up resistor module and a to-be-calibrated pull-down resistor module. The target sub-circuit comprises a comparison module and a pull-up resistor module with adjustable resistance. The target sub-circuit has a first state and a second state. When the target sub-circuit is in the first state, first input ends of the comparison module are electrically connected with the target resistor and the pull-up resistor module respectively. When the target sub-circuit is in the second state, the first input ends of the comparison module are electrically connected with the to-be-calibrated pull-up resistor module and the to-be-calibrated pull-down resistor module respectively. A second input end of the comparison module is used for inputting a reference voltage. In this way, the to-be-calibrated pull-up resistor module and the to-be-calibrated pull-down resistor module in the target chip can be calibrated by the calibration circuit, so as to eliminate the drift generated in the chip as much as possible, reduce the probability of impedance mismatch, and improve the performance of the chip.

Description

Technical Field

[0001] This application relates to the field of artificial intelligence chip technology, and in particular to a calibration circuit, chip, and electronic device. Background Technology

[0002] Chips typically contain a large number of tiny components that work together to support their normal operation. Some of these components usually have equivalent resistance, which is affected by the objective conditions of the component (such as environmental factors and process factors). This equivalent resistance may cause drift that can lead to impedance mismatch, thereby affecting the normal operation of the chip and consequently its performance.

[0003] Therefore, minimizing the impact of the aforementioned drift is crucial for improving chip performance. Summary of the Invention

[0004] To address the aforementioned technical problems, embodiments of this application propose a calibration circuit, chip, and electronic device that can reduce the probability of impedance mismatch and improve chip performance.

[0005] In a first aspect, embodiments of this application provide a calibration circuit, the calibration circuit including a target sub-circuit, the calibration circuit being used to calibrate a target chip including a pull-up resistor module to be calibrated and a pull-down resistor module to be calibrated;

[0006] The target sub-circuit includes a comparison module and an adjustable pull-up resistor module, and the target sub-circuit has a first state and a second state;

[0007] When the target sub-circuit is in the first state, the first input terminal of the comparison module is electrically connected to the target resistor and the pull-up resistor module, respectively;

[0008] When the target sub-circuit is in the second state, the first input terminal of the comparison module is electrically connected to the pull-up resistor module to be calibrated and the pull-down resistor module to be calibrated, respectively.

[0009] The second input terminal of the comparison module is used to connect to a reference voltage.

[0010] Optionally, the comparison module is a voltage comparator, and the first input terminal of the comparison module is one of the non-inverting input terminal and the inverting input terminal of the voltage comparator, and the other is the second input terminal of the comparison module.

[0011] Optionally, the controlled terminal of the pull-up resistor module is used to receive a first pull-up code (PU Code), which is used to adjust the resistance value of the pull-up resistor module.

[0012] The controlled terminal of the pull-up resistor module to be calibrated is used to receive a second PU Code, which is used to adjust the resistance value of the pull-up resistor module to be calibrated.

[0013] The controlled terminal of the pull-down resistor module to be calibrated is used to receive a pull-down code (PD Code), which is used to adjust the resistance value of the pull-down resistor module to be calibrated.

[0014] Optionally, the target sub-circuit further includes:

[0015] The buffer is used when the target sub-circuit is in the second state. The first input terminal of the comparison module is electrically connected to the pull-up resistor module to be calibrated and the pull-down resistor module to be calibrated respectively via the buffer.

[0016] Optionally, the calibration circuit is a ZQ calibration circuit, used to perform ZQ calibration on the target chip.

[0017] Secondly, embodiments of this application provide a chip, the chip including a data transmission terminal and a target sub-circuit in the calibration circuit described in any one of the first aspects above, the data transmission terminal including the pull-up resistor module to be calibrated and the pull-down resistor module to be calibrated.

[0018] Optionally, the target sub-circuit is arranged adjacent to the data transmission terminal, which is the data pin DQ of the chip.

[0019] Optionally, the target sub-circuit further includes:

[0020] The target resistor has an adjustable resistance value, which is determined by test data of an external resistor located outside the chip.

[0021] Optionally, the chip is cut;

[0022] Before the chip is diced, the external resistor is placed on a dicing slot connected to the outside of the chip. The test data is obtained by measuring and calibrating the external resistor placed on the dicing slot during the chip probe CP test phase.

[0023] Optionally, the calibration circuit includes the target resistor and the target sub-circuit, wherein the target resistor is located outside the chip.

[0024] Thirdly, embodiments of this application provide an electronic device including the chip described in any one of the second aspects above.

[0025] In summary, the embodiments of this application have at least the following beneficial effects:

[0026] In this embodiment, the calibration circuit includes a target sub-circuit for calibrating a target chip including a pull-up resistor module and a pull-down resistor module to be calibrated. The target sub-circuit includes a comparator module and an adjustable pull-up resistor module. The target sub-circuit has a first state and a second state. When the target sub-circuit is in the first state, the first input terminal of the comparator module is electrically connected to the target resistor and the pull-up resistor module, respectively. When the target sub-circuit is in the second state, the first input terminal of the comparator module is electrically connected to the pull-up resistor module and the pull-down resistor module to be calibrated, respectively. The second input terminal of the comparator module is used to connect to a reference voltage. Thus, the pull-up resistor module and the pull-down resistor module to be calibrated in the target chip can be calibrated using the calibration circuit with the above architecture to minimize drift in the chip, reduce the probability of impedance mismatch, and improve chip performance. Attached Figure Description

[0027] Figure 1 This is a circuit diagram of the ZQ calibration circuit in the related technology provided in the embodiments of this application;

[0028] Figure 2 This is a circuit diagram of the calibration circuit when the target sub-circuit does not contain a target resistor, as provided in the embodiments of this application.

[0029] Figure 3 This is a circuit diagram of the calibration circuit when the target sub-circuit includes the target resistor, as provided in the embodiments of this application;

[0030] Figure 4 This is a circuit diagram of an embodiment of this application when the target resistor is located off-chip;

[0031] Figure 5 This is a circuit diagram of the target resistor being located on-chip, as provided in an embodiment of this application.

[0032] Figure 6 This is a schematic diagram of the dicing groove provided in an embodiment of this application. Detailed Implementation

[0033] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments / examples are only a part of the embodiments / examples of this application, and not all of the embodiments / examples. Based on the embodiments / examples in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0034] In the description of this application, the terms "first," "second," "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "first," "second," "third," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "multiple" means two or more. In the description of this application, the term "comprising" and its variations are open-ended, meaning "including but not limited to." The term "based on" means "at least partially based on." The term "according to" means "at least partially according to." The term "one embodiment / example" means "at least one embodiment / example"; the term "another embodiment / example" means "at least one additional embodiment / example"; the term "some embodiments / examples" means "at least some embodiments / examples."

[0035] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0036] In the description of this application, it should be noted that, unless otherwise defined, all technical and scientific terms used in this application have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this application is for the purpose of describing specific embodiments only and is not intended to limit the application. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0037] First, the following is an explanation of some terms and concepts involved in the embodiments of this application:

[0038] Pull-Up Code (PU Code) is a set of digital control signals used to configure the equivalent resistance value of the internal pull-up resistor network of a chip (this equivalent resistance value can be called the pull-up resistor). For example, different combinations of PU Codes can be used to control the number of MOSFETs turned on in the pull-up resistor network, thereby adjusting the size of the pull-up resistor to achieve impedance matching of the chip's I / O (Input / Output) ports.

[0039] Pull-Down Code (PD Code) is a digital control signal that complements pull-up code. It can be used to configure the equivalent resistance value of the internal pull-down resistor network (this equivalent resistance value can be called the pull-down resistor). For example, the number of MOSFETs in the pull-down resistor network that are turned on can be controlled by different combinations of PD Code, thereby adjusting the value of the pull-down resistor. In conjunction with pull-up code, it can improve the impedance stability of the chip's I / O ports under different signal states, ensuring signal integrity for high-speed data transmission.

[0040] DQ (Data Queue) is a pin on a chip used to achieve high-speed bidirectional data transmission, and it belongs to the category of I / O interfaces. For example, in scenarios such as DDR (Double Data Rate) memory, DQ is the core channel for data interaction, and its impedance matching is crucial to the data transmission rate and reliability.

[0041] CP (Chip Probe) testing is a wafer-level chip testing process. Before a chip is cut into individual devices, probes can be used to contact chip test points on the wafer to test the chip's electrical parameters, functions, and other properties.

[0042] ZQ calibration is a self-calibration mechanism in DDR memory used to adjust the resistance value of the DQ resistor. It can improve the accuracy of signal drive and termination resistors, thereby improving signal integrity under high-speed transmission.

[0043] In some exemplary scenarios, such as in DDR interface IP cores (Intellectual Property Cores), the CMOS (Complementary Metal-Oxide-Semiconductor) resistance may drift due to PTV (Process, Temperature, Voltage) effects, potentially leading to impedance mismatch. This can cause signal reflection, timing deviations, and affect the normal operation of the chip, thereby impacting its performance. Mismatch can trigger one or more of the following: signal reflection, ringing, and eye diagram closure, resulting in a smaller DVW (Data Valid Window) and an increased BER (Bit Error Rate).

[0044] In related technologies, an external precision resistor can be used as a reference to calibrate the Ron (On-resistance, the impedance of the output driver) and ODT (On-Die Termination, the on-chip terminating resistor) inside the chip, thereby reducing the probability of impedance mismatch and improving chip performance.

[0045] For example, see Figure 1 The pull-up and pull-down resistors to be calibrated in the I / O of the chip to be calibrated are copied into the ZQ calibration circuit. This ZQ calibration circuit also includes a first comparator 101 and a second comparator 102. Two pull-up resistors are copied: a first pull-up resistor 103 and a second pull-up resistor 104. An external reference resistor module 105 and the first pull-up resistor 103 are connected to the non-inverting input of the first comparator 101, and the inverting inputs of both the first comparator 101 and the second comparator 102 are connected to a reference voltage VREF1. Furthermore, the non-inverting input of the second comparator 102 is connected to the second pull-up resistor 104 and the pull-down resistor 106 copied in the ZQ calibration circuit. The pull-up and pull-down resistors can represent the aforementioned CMOS resistors. The 100 in the figure can represent the on-chip portion of the ZQ calibration circuit, which may include components other than the external reference resistor module 105 located off-chip.

[0046] In this circuit architecture, the external reference resistor module 105 and the first pull-up resistor 103 can form a voltage divider circuit. The difference between the voltage formed by this voltage divider circuit and the reference voltage VREF1 can be detected by the first comparator 101. Based on this difference, the PU Code used to set the equivalent resistance value of the first pull-up resistor 103 can be adjusted so that the equivalent resistance value of the first pull-up resistor 103 represented by the adjusted PU Code can match the external reference resistor module 105. The equivalent resistance value of the second pull-up resistor 104 can be set using the adjusted PU Code (for example, the first and second pull-up resistors can share the same PU Code). Using the equivalent resistance value of the second pull-up resistor 104 at this time as a reference, the second pull-up resistor 104 and the pull-down resistor 106 replicated in the ZQ calibration circuit form a voltage divider circuit. Based on the difference between the voltage formed by this voltage divider circuit and the reference voltage VREF1 detected by the second comparator 102, the PD Code used to set the equivalent resistance value of the pull-down resistor 106 replicated in the ZQ calibration circuit is adjusted, thereby obtaining the adjusted PU Code. The ZQ calibration of the IO can be completed by filling the adjusted PU Code and PD Code back into the IO of the chip to be calibrated.

[0047] However, the aforementioned circuit architecture in the related technology requires at least two pull-up resistors and one pull-down resistor to be replicated in the ZQ calibration circuit, along with at least two comparators. Furthermore, the replicated device in the ZQ calibration circuit needs to have a dummy DRV (virtual driver) added around it to simulate the actual situation of the replicated device within the chip (e.g., its actual environment). This results in a relatively complex structure for the ZQ calibration circuit, requiring excessive layout area when integrated into the chip, thus encroaching on the space of other functional modules and affecting chip performance. In addition, since the two pull-up resistors and one pull-down resistor are replicated, some differences are unavoidable compared to the original pull-up and pull-down resistors in the I / O. Therefore, the backfilled PU Code and PD Code will inevitably contain some errors, further impacting chip performance.

[0048] In view of this, the embodiments of this application subsequently provide a technical solution for a calibration circuit, chip, and electronic device, which aims to at least partially solve the problems existing in the above-mentioned related technologies.

[0049] Firstly, see [the following] Figure 2 The diagram shows a schematic of the structure of a calibration circuit provided in an embodiment of this application. The calibration circuit includes a target sub-circuit 200 and is used to calibrate a target chip including a pull-up resistor module 301 to be calibrated and a pull-down resistor module 302 to be calibrated.

[0050] The target sub-circuit 200 includes a comparison module 201 and an adjustable pull-up resistor module 202. The target sub-circuit 200 has a first state and a second state.

[0051] When the target sub-circuit 200 is in the first state, the first input terminal of the comparison module 201 is electrically connected to the target resistor 400 and the pull-up resistor module 202 respectively.

[0052] When the target sub-circuit 200 is in the second state, the first input terminal of the comparison module 201 is electrically connected to the pull-up resistor module 301 to be calibrated and the pull-down resistor module 302 to be calibrated, respectively.

[0053] The second input terminal of the comparison module 201 is used to connect the reference voltage VREF2.

[0054] For example, the following provides a method of using the calibration circuit, which may include S1 to S2, as detailed below.

[0055] S1, the target sub-circuit 200 is adjusted to the first state, so that the first input terminal of the comparison module 201 is electrically connected to the target resistor 400 and the pull-up resistor module 202 respectively, so that the target resistor 400 and the pull-up resistor module 202 can form a first voltage divider circuit, and the comparison module 201 can obtain the adjusted equivalent resistance value of the pull-up resistor module 202 that matches the target resistor 400 by measuring the difference between the voltage formed by the first voltage divider circuit detected by the first input terminal and the reference voltage VREF2 detected by the second input terminal.

[0056] S2, the equivalent resistance of the pull-up resistor module 301 to be calibrated can be adjusted according to the adjusted equivalent resistance value (for example, the equivalent resistance value of the pull-up resistor module 301 to be calibrated can be adjusted to the adjusted equivalent resistance value), and the target sub-circuit 200 can be adjusted to the second state, so that the first input terminal of the comparison module 201 is electrically connected to the pull-up resistor module 301 to be calibrated and the pull-down resistor module 302 to be calibrated respectively, so that the pull-up resistor module 301 to be calibrated and the pull-down resistor module 302 to be calibrated can form a second voltage divider circuit, and the comparison module 201 can obtain the adjusted equivalent resistance value of the pull-down resistor module 302 to be calibrated, which matches the adjusted equivalent resistance value, by comparing the difference between the voltage formed by the second voltage divider circuit detected by the first input terminal and the reference voltage VREF2 detected by the second input terminal.

[0057] Thus, compared to the circuit architecture provided by the aforementioned related technologies, which requires replicating two pull-up resistors and one pull-down resistor, the circuit architecture provided in this embodiment can set up a pull-up resistor module in the calibration circuit. The pull-down resistor and the other pull-up resistor can both be borrowed from the components contained in the target chip to be calibrated. Therefore, this embodiment reduces the number of components in the calibration circuit, reduces the complexity of the circuit architecture, and thus helps to improve chip performance.

[0058] It is understandable that the first state and the second state are different states of the target sub-circuit 200. In different states, the specific devices connected to the first input terminal of the target sub-circuit 200 are different.

[0059] In some examples, the target sub-circuit 200 can be switched between its first and second states by setting a switching element. For example, the target sub-circuit 200 may also include a first switch 203 and a second switch 204. The first input terminal of the comparison module 201 can be connected to the target resistor 400 and the pull-up resistor module 202 via the first switch 203, and the first input terminal of the comparison module 201 can be connected to the pull-up resistor module 301 to be calibrated and the pull-down resistor module 302 to be calibrated via the second switch 204. Thus, when the first switch 203 is turned on and the second switch 204 is turned off, the target sub-circuit 200 is in the first state, and when the first switch 203 is turned off and the second switch 204 is turned on, the target sub-circuit 200 is in the second state.

[0060] In other examples, the target sub-circuit 200 can be switched between its first and second states by controlling the connection between the pull-up resistor module 301 and the pull-down resistor module 302 to be calibrated in the target chip and the first input terminal of the comparator module 201. For example, the target chip may also include a third switch 303, through which both the pull-up resistor module 301 and the pull-down resistor module 302 to be calibrated are connected to the first input terminal of the comparator module 201. Thus, by controlling the opening and closing of the third switch 303, the connection between the pull-up resistor module 301 and the pull-down resistor module 302 to be calibrated and the first input terminal of the comparator module 201 can be controlled. When the first switch 203 is on and the third switch 303 is off, the target sub-circuit 200 is in the first state; when the first switch 203 is off and the third switch 303 is on, the target sub-circuit 200 is in the second state. It is worth noting that, in addition to controlling the state switching of the target sub-circuit 200, the third switch 303 can also be turned off when calibration is not being performed. This prevents the pull-up resistor module 301 and the pull-down resistor module 302 from forming an electrical connection with the calibration circuit, thus ensuring that the normal function of the pull-up resistor module 301 and the pull-down resistor module 302 in the target chip is not affected.

[0061] Therefore, it can be seen that there are various specific implementation schemes for the target sub-circuit 200 to switch between its first state and second state, and this application does not limit it to a single one.

[0062] In some examples, the comparison module 201 may employ a comparator that is common in the relevant technical field, such as a window comparator, a hysteresis comparator, a general differential comparator, etc., and this application does not impose a unique limitation on it.

[0063] In some examples, the reference voltage VREF2 (similar to the reference voltage VREF1 in the related technologies mentioned above) can be a precise and stable voltage reference generated inside the chip where the calibration circuit is located (e.g., the target chip).

[0064] In one optional implementation, the comparison module 201 is a voltage comparator, and the first input terminal of the comparison module 201 is one of the non-inverting input terminal and the inverting input terminal of the voltage comparator, and the other is the second input terminal of the comparison module 201.

[0065] In this embodiment, a voltage comparator is used as the comparison module 201. The voltage comparator can respond accurately to minute voltage differences (such as millivolts). It also has the characteristic of high-speed response. Since the signal transmission rate of the DDR interface is extremely high (such as DDR5 up to 6400MT / s), the calibration operation needs to be completed within nanoseconds. The voltage comparator has an extremely fast response speed (typically a few nanoseconds to tens of nanoseconds), which can detect voltage division changes in a timely manner and output feedback signals, reducing data transmission timing deviations caused by calibration delays.

[0066] In some examples, the first input of the comparison module 201 is the non-inverting input of the voltage comparator, and the second input of the comparison module 201 is the inverting input of the voltage comparator.

[0067] In one optional implementation, the controlled terminal of the pull-up resistor module 202 is used to receive a first pull-up code (PU Code), which is used to adjust the resistance value of the pull-up resistor module 202.

[0068] The controlled terminal of the pull-up resistor module 301 to be calibrated is used to receive a second PU Code, which is used to calibrate the resistance value of the pull-up resistor module 301 to be calibrated.

[0069] The controlled terminal of the pull-down resistor module 302 to be calibrated is used to receive the pull-down code PD Code, which is used to calibrate the resistance value of the pull-down resistor module 302 to be calibrated.

[0070] In this embodiment, the equivalent resistance value of each resistor module can be adjusted by sending PU Code and PD Code to the controlled terminal of each resistor module. In this way, the equivalent resistance value of each resistor module can be adjusted by combining codes, which helps to improve the efficiency of calibration.

[0071] In some examples, the second PU Code may be determined based on the first PU Code corresponding to the adjusted equivalent resistance value of the pull-up resistor module 202. For example, the encoding value of the first PU Code corresponding to the adjusted equivalent resistance value of the pull-up resistor module 202 may be used as the encoding value of the second PU Code.

[0072] In some examples, the pull-up resistor module 202 may include multiple sets of MOS transistors connected in parallel. The equivalent resistance value of the pull-up resistor module 202 can be changed by controlling the conduction state of each set of MOS transistors. A first PU Code can be used to control the conduction state of each set of MOS transistors included in the pull-up resistor module 202.

[0073] In some examples, the pull-up resistor module 301 to be calibrated may include multiple sets of MOS transistors connected in parallel. The equivalent resistance of the pull-up resistor module 301 to be calibrated can be changed by controlling the on-state of each set of MOS transistors. The second PU Code can be used to control the on-state of each set of MOS transistors included in the pull-up resistor module 301 to be calibrated.

[0074] In some examples, the pull-down resistor module 302 to be calibrated may include multiple sets of MOS transistors connected in parallel. The equivalent resistance of the pull-down resistor module 302 to be calibrated can be changed by controlling the on-state of each set of MOS transistors. PD Code can be used to control the on-state of each set of MOS transistors included in the pull-down resistor module 302 to be calibrated.

[0075] In an optional implementation, the target sub-circuit 200 further includes:

[0076] When the target sub-circuit 200 is in the second state, the first input terminal of the comparison module 201 is electrically connected to the pull-up resistor module 301 to be calibrated and the pull-down resistor module 302 to be calibrated via the buffer 205.

[0077] In this embodiment, the buffer 205 has the characteristics of high input impedance and low output impedance, which can isolate the impedance influence between the preceding and following circuits. The output impedance of the preceding circuit (such as the first input terminal of the comparator module 201, the target resistor 400, and the pull-up resistor module 202) may be high. Directly connecting it to the following circuit (such as the pull-up resistor module 301 and the pull-down resistor module 302 to be calibrated) may cause signal reflection. The buffer 205 can act as an impedance bridge to match the high impedance of the preceding stage with the low impedance of the following stage, reduce signal reflection, and ensure the accurate transmission of calibration parameters (such as PU code / PD code). In addition, in high-speed data transmission (such as the DDR signal of the DQ pin), the signal is susceptible to electromagnetic interference and noise. At this time, the buffer 205 can shape the signal, filter out high-frequency noise, make the edge of the output signal steeper and the level more stable, and minimize the eye diagram closure and data valid window (DVW) shrinkage caused by noise.

[0078] In some examples, the buffer 205 may be an operational amplifier (e.g., a voltage follower) with its non-inverting input connected to the pull-up resistor module 301 and the pull-down resistor module 302 to be calibrated, respectively, and its output connected to the first input of the comparator module 201 and the inverting input of the operational amplifier, respectively.

[0079] In one optional implementation, the calibration circuit is a ZQ calibration circuit used to perform ZQ calibration on the target chip.

[0080] Secondly, see Figure 2 and Figure 3 This application provides a chip, which includes a data transmission terminal 300 and a target sub-circuit 200 in the calibration circuit described in any one of the first aspects above. The data transmission terminal 300 includes the pull-up resistor module 301 to be calibrated and the pull-down resistor module 302 to be calibrated.

[0081] In this embodiment, the target sub-circuit 200 can be integrated into the chip (therefore, the target sub-circuit 200 can also be called an on-chip sub-circuit). Since the target sub-circuit 200 in the chip provided in this embodiment contains fewer components, fewer dummy DRVs need to be added around the components. Therefore, the layout area occupied by the target sub-circuit 200 within the chip can be reduced, thereby freeing up more space for other functional modules in the chip to improve chip performance. Furthermore, it is easy to understand that since the chip includes a data transmission terminal 300, and the data transmission terminal 300 includes a pull-up resistor module 301 to be calibrated and a pull-down resistor module 302 to be calibrated, the chip here can be understood as the target chip described in the first aspect, including the pull-up resistor module 301 and the pull-down resistor module 302 to be calibrated.

[0082] In one optional implementation, the target sub-circuit 200 is disposed adjacent to the data transmission terminal 300, which is the data pin DQ of the chip.

[0083] In this embodiment, the target sub-circuit 200 and the data transmission terminal 300 are arranged adjacently, which reduces the wiring length between them, thereby reducing parasitic parameters (such as parasitic inductance and capacitance) caused by wiring and thus reducing calibration deviations caused by parasitic parameters. Furthermore, it allows the target sub-circuit 200 and the data transmission terminal 300 to be located in similar physical environments, reducing deviations caused by differences in PTV. Additionally, it shortens the transmission path of the calibration signals (PU code / PD code) to reduce transmission latency. For example, in high-speed interfaces such as DDR5 (clock cycles of only about 0.3ns), reduced transmission latency ensures that the calibration operation is completed within timing constraints, minimizing signal timing deviations in the DQ due to calibration lag.

[0084] In one alternative implementation, see [link to implementation details]. Figure 2 and Figure 4 The calibration circuit includes the target resistor 400 and the target sub-circuit 200, wherein the target resistor 400 is located outside the chip. Figure 4 In the context of chip-on-chip (Inchip), the term refers to the on-chip portion, and the... Figure 4 Only shown in Figure 2 Some components of the target sub-circuit 200.

[0085] In this embodiment, the target resistor 400 can be located outside the chip, making it easy to adjust / replace.

[0086] In one alternative implementation, see [link to implementation details]. Figure 3 and Figure 5The target sub-circuit 200 further includes:

[0087] The target resistor 400 has an adjustable resistance value, determined by test data from an external resistor located outside the chip. Figure 5 In the context of chip-on-chip (Inchip), the term refers to the on-chip portion, and the... Figure 5 Only shown in Figure 3 Some components of the target sub-circuit 200.

[0088] In related technologies, the target resistor 400 can be set on the bump outside the chip. However, this requires reserving a bump on the chip for setting the target resistor 400, and requires a resistor independent of the chip, which increases the packaging and hardware costs. Furthermore, the external target resistor 400 may increase the load on the comparator module 201, reduce the response efficiency, and increase the calibration time.

[0089] In this embodiment, the target sub-circuit 200 also includes a target resistor 400. In other words, the target resistor 400 can also be integrated into the chip. In this case, the target resistor 400 can be called an on-chip resistor. Compared with the related technologies where the target resistor 400 is placed on the outside of the chip in the bump, this embodiment reduces the bump and the external resistor, saving packaging and procurement costs. Moreover, the design of the on-chip resistor helps to reduce the load on the comparison module 201 in the chip, improve response efficiency, and reduce the calibration time.

[0090] In one alternative implementation, the chip is diced;

[0091] Before the chip is cut, see Figure 6 The external resistor 501 is disposed on a dicing slot 500 that is externally connected to the chip. The test data is obtained by measuring and calibrating the external resistor 501 disposed on the dicing slot 500 during the chip probe CP test phase.

[0092] In this embodiment, the dicing groove 500 is a blank area between two adjacent chips on the wafer, through which a dicing tool can pass to divide the wafer into individual chips. Therefore, in this embodiment, the external resistor 501 is set on the dicing groove 500, which is externally connected to the chip, so that the external resistor 501 located on the dicing groove 500 can be cut and taken away together during dicing. In addition, the relevant parameters of the external resistor 501 can be obtained by measuring and calibrating the external resistor 501 during the CP testing phase. Then, the resistance value of the target resistor 400 integrated in the chip is set according to the relevant parameters, so that the resistance value of the target resistor 400 is adapted to the external resistor 501 (for example, the resistance values ​​of the target resistor 400 and the external resistor 501 are equal), so as to achieve a similar effect to the external resistor 501 during calibration.

[0093] In some examples, to make the test data obtained from CP testing more accurate, two CP PADs (Chip Probe Pads) 502 can be set on the dicing slot 500. The two ends of the external resistor 501 are respectively connected to the two chip probe pads 502. During CP testing, the test probe can contact the chip probe pads 502 to achieve measurement and calibration of the external resistor 501.

[0094] Thirdly, embodiments of this application provide an electronic device including the chip described in any one of the second aspects above.

[0095] In some examples, the electronic device can be a terminal device, server device, etc., that includes DDR memory.

[0096] In summary, the embodiments of this application have at least the following beneficial effects:

[0097] In this embodiment, the calibration circuit includes a target sub-circuit for calibrating a target chip including a pull-up resistor module and a pull-down resistor module to be calibrated. The target sub-circuit includes a comparator module and an adjustable pull-up resistor module. The target sub-circuit has a first state and a second state. When the target sub-circuit is in the first state, the first input terminal of the comparator module is electrically connected to the target resistor and the pull-up resistor module, respectively. When the target sub-circuit is in the second state, the first input terminal of the comparator module is electrically connected to the pull-up resistor module and the pull-down resistor module to be calibrated, respectively. The second input terminal of the comparator module is used to connect to a reference voltage. Thus, the pull-up resistor module and the pull-down resistor module to be calibrated in the target chip can be calibrated using the calibration circuit with the above architecture to minimize drift in the chip, reduce the probability of impedance mismatch, and improve chip performance.

[0098] Through the above description of the embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary hardware platforms, or it can be implemented entirely by hardware. Based on this understanding, all or part of the technical solutions of this application that contribute to the background technology can be embodied in the form of a software product. This computer software product can be stored in a storage medium, such as ROM (Read-Only Memory) / RAM (Random Access Memory), magnetic disk, optical disk, etc., including several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in various embodiments or some parts of the embodiments of this application.

[0099] The above description is the preferred embodiment of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this application, and these improvements and modifications are also considered to be within the scope of protection of this application.

Claims

1. A calibration circuit, characterized in that, The calibration circuit includes a target sub-circuit, which is an on-chip sub-circuit integrated into the target chip. The target chip also includes a data transmission terminal, which includes a pull-up resistor module to be calibrated and a pull-down resistor module to be calibrated. The calibration circuit is used to calibrate the pull-up resistor module to be calibrated and the pull-down resistor module to be calibrated in the data transmission terminal. Alternatively, the calibration circuit may not include the pull-up resistor module to be calibrated and the pull-down resistor module to be calibrated. The target sub-circuit includes a comparison module and an adjustable pull-up resistor module, and the target sub-circuit has a first state and a second state; When the target sub-circuit is in the first state, the first input terminal of the comparison module is electrically connected to the target resistor and the pull-up resistor module, respectively; When the target sub-circuit is in the second state, the first input terminal of the comparison module is electrically connected to the pull-up resistor module to be calibrated and the pull-down resistor module to be calibrated, respectively. The second input terminal of the comparison module is used to connect a reference voltage; The target sub-circuit also includes: The buffer is used when the target sub-circuit is in the second state. The first input terminal of the comparison module is electrically connected to the pull-up resistor module to be calibrated and the pull-down resistor module to be calibrated respectively via the buffer.

2. The calibration circuit according to claim 1, characterized in that, The comparison module is a voltage comparator. The first input terminal of the comparison module is one of the non-inverting input terminal and the inverting input terminal of the voltage comparator, and the other is the second input terminal of the comparison module.

3. The calibration circuit according to claim 1, characterized in that, The controlled terminal of the pull-up resistor module is used to receive a first pull-up code (PU Code), which is used to adjust the resistance value of the pull-up resistor module. The controlled terminal of the pull-up resistor module to be calibrated is used to receive a second PU Code, which is used to adjust the resistance value of the pull-up resistor module to be calibrated. The controlled terminal of the pull-down resistor module to be calibrated is used to receive a pull-down code (PD Code), which is used to adjust the resistance value of the pull-down resistor module to be calibrated.

4. The calibration circuit according to any one of claims 1-3, characterized in that, The calibration circuit is a ZQ calibration circuit, used for ZQ calibration.

5. A chip, characterized in that, The chip includes a data transmission terminal and a target sub-circuit in the calibration circuit according to any one of claims 1-4. The data transmission terminal includes the pull-up resistor module to be calibrated and the pull-down resistor module to be calibrated.

6. The chip according to claim 5, characterized in that, The target sub-circuit is arranged adjacent to the data transmission terminal, which is the data pin DQ of the chip.

7. The chip according to any one of claims 5-6, characterized in that, The target sub-circuit also includes: The target resistor has an adjustable resistance value, which is determined by test data of an external resistor located outside the chip.

8. The chip according to claim 7, characterized in that, The chip is cut into pieces; Before the chip is diced, the external resistor is placed on a dicing slot connected to the outside of the chip. The test data is obtained by measuring and calibrating the external resistor placed on the dicing slot during the chip probe CP test phase.

9. The chip according to any one of claims 5-6, characterized in that, The calibration circuit includes the target resistor and the target sub-circuit, with the target resistor located outside the chip.

10. An electronic device, characterized in that, Includes the chip described in any one of claims 5-9.

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