A semiconductor power device, a preparation method thereof and an electronic device

Abstract

The embodiment of the present disclosure provides a semiconductor power device and a preparation method thereof and an electronic device, wherein a single crystal diamond epitaxial layer is epitaxially grown on a SiC substrate, which can reduce the on-resistance of the SiC device, increase the heat dissipation effect of the SiC device, and make the SiC device have good thermal stability, effectively solve the poor heat dissipation problem of the traditional SiC device, and improve the working efficiency of the SiC device, and the preparation process is simple. Moreover, the single crystal diamond epitaxial layer is epitaxially grown on the surface of the iridium film layer, compared with the single crystal diamond epitaxially grown directly on the surface of the SiC substrate, the present disclosure can improve the epitaxial quality of the single crystal diamond epitaxial layer and improve the performance of the device.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor power device and its fabrication method, and electronic equipment. Background Technology

[0002] Diamond, as an ultrawide bandgap semiconductor material, has excellent properties such as ultrawide bandgap, high thermal conductivity, high critical breakdown field strength and high carrier saturation drift velocity. These advantages provide favorable conditions for diamond to be used as a high-performance power device. Power device substrates made of diamond have advantages such as low on-resistance and good high-temperature stability.

[0003] Silicon carbide (SiC), as a wide-bandgap semiconductor material, possesses advantages such as high breakdown voltage and high electron saturation velocity. However, traditional SiC devices rely on their own thermal conductivity for heat dissipation, which is insufficient. Both SiC power devices and GaN power devices based on SiC face the risk of performance degradation or even complete failure at high power outputs due to the "self-heating effect." Therefore, improving the heat dissipation performance of silicon carbide semiconductors to avoid or reduce performance degradation or damage caused by the "self-heating effect" is a problem that needs to be solved. Summary of the Invention

[0004] This disclosure provides a semiconductor power device and its fabrication method, as well as an electronic device, to solve the problems of poor heat dissipation, low diamond substrate utilization, and high cost of traditional SiC power devices.

[0005] This disclosure provides a semiconductor power device, its fabrication method, and an electronic device, the specific solutions of which are as follows:

[0006] In one aspect, embodiments of this disclosure provide a semiconductor power device, including:

[0007] A SiC substrate has a first surface and a second surface disposed opposite to each other, and the first surface has a first conductive channel region and a second conductive channel region disposed at intervals.

[0008] A yttrium-stabilized zirconium oxide layer is located on the second surface of the SiC substrate;

[0009] An iridium film layer is located on the side of the yttrium-stabilized zirconium oxide layer away from the SiC substrate;

[0010] A single-crystal diamond epitaxial layer is located on the side of the iridium metal film away from the SiC substrate;

[0011] The first source electrode is located on the side of the first conductive channel region away from the single-crystal diamond epitaxial layer.

[0012] The first drain is located on the side of the second conductive channel region away from the single-crystal diamond epitaxial layer.

[0013] In some embodiments, in the semiconductor power device provided in the present disclosure, the side of the single-crystal diamond epitaxial layer away from the SiC substrate includes a conductive termination region;

[0014] The semiconductor power device further includes:

[0015] The second source and the second drain are disposed at an interval on the side of the conductive terminal region away from the SiC substrate;

[0016] A gate dielectric layer covers the conductive termination region between the second source and the second drain, and also covers a portion of the second source and a portion of the second drain;

[0017] The gate electrode is located on the side of the gate dielectric layer away from the SiC substrate.

[0018] In some embodiments, in the semiconductor power device provided in the present disclosure, the first source and the second source are electrically connected, and / or the first drain and the second drain are electrically connected.

[0019] On the other hand, embodiments of this disclosure also provide an electronic device, including any of the semiconductor power devices described above in embodiments of this disclosure.

[0020] On the other hand, this disclosure also provides a method for fabricating a semiconductor power device, including:

[0021] A yttrium-stabilized zirconium oxide layer is formed on the second surface of the SiC substrate;

[0022] An iridium film is formed on the side of the yttrium-stabilized zirconium oxide layer away from the SiC substrate;

[0023] A single-crystal diamond epitaxial layer is epitaxially grown on the side of the iridium film away from the SiC substrate;

[0024] Ion implantation is performed on the first surface of the SiC substrate to form a first conductive channel region and a second conductive channel region.

[0025] A first source is formed in the first conductive channel region, and a first drain is formed in the second conductive channel region.

[0026] In some embodiments, the preparation method provided in this disclosure, before ion implantation is performed on the first surface of the SiC substrate to form a first conductive channel region and a second conductive channel region, further includes:

[0027] The SiC substrate is thinned.

[0028] In some embodiments, the preparation method provided in this disclosure, after epitaxially growing a single-crystal diamond epitaxial layer on the side of the iridium film away from the SiC substrate, and before thinning the SiC substrate, further includes:

[0029] A conductive termination region is formed on the side of the single-crystal diamond epitaxial layer away from the SiC substrate;

[0030] A second source and a second drain are formed on both sides within the conductive terminal region;

[0031] A gate dielectric layer is formed on the side of the second source and the second drain away from the SiC substrate. The gate dielectric layer covers the conductive termination region between the second source and the second drain, as well as a portion of the second source and a portion of the second drain.

[0032] A gate is formed on the side of the gate dielectric layer away from the SiC substrate.

[0033] In some embodiments, in the preparation method provided in this disclosure, a conductive termination region is formed on the side of the single-crystal diamond epitaxial layer away from the SiC substrate, specifically including:

[0034] SnO is deposited on the side of the single-crystal diamond epitaxial layer away from the SiC substrate. x Thin film, and the SnO x The thin film is patterned to form SnO. x Reserved area and SnO x SnO removal zone x Mask layer; where x = 1 or 2;

[0035] For the SnO formed x The single-crystal diamond epitaxial layer of the mask layer is subjected to plasma hydrogenation treatment to form a tin-terminated region and a hydrogen-terminated region on the side of the single-crystal diamond epitaxial layer away from the SiC substrate; wherein, the tin-terminated region and the SnO x Corresponding to the retention region, the hydrogen terminal region is related to the SnO. x The removal area corresponds to this;

[0036] Remove SnO by acid washing x Mask layer.

[0037] In some embodiments, the preparation method provided in this disclosure, after forming the second source and the second drain, and before forming the gate dielectric layer, further includes:

[0038] A photoresist layer is formed on the side of the second source and the second drain away from the SiC substrate;

[0039] The photoresist layer is exposed and developed to form a photoresist pattern including a photoresist completely retained area and a photoresist completely removed area; wherein, the photoresist completely retained area corresponds to the tin-terminated area, and the photoresist completely removed area corresponds to the hydrogen-terminated area;

[0040] Using the photoresist pattern as a mask, the hydrogen-terminated region is subjected to oxygen plasma treatment to convert the hydrogen-terminated region into an oxygen-terminated region.

[0041] Remove the photoresist pattern.

[0042] In some embodiments, in the preparation method provided in the present disclosure, a first source is formed in the first conductive channel region and a first drain is formed in the second conductive channel region, specifically including:

[0043] A SiO2 thin film is formed on the first surface of the SiC substrate;

[0044] The SiO2 thin film is patterned to form a SiO2 mask layer including a SiO2 retention region and a SiO2 removal region. The SiO2 removal region corresponds to the first conductive channel region and the second conductive channel region, and the SiO2 retention region corresponds to the region other than the first conductive channel region and the second conductive channel region.

[0045] Metal is deposited in the first conductive channel region, the second conductive channel region, and on the side of the SiO2 mask layer away from the single-crystal diamond epitaxial layer;

[0046] The SiO2 mask layer is removed to form a first source in the first conductive channel region and a first drain in the second conductive channel region.

[0047] The beneficial effects of the embodiments disclosed herein are as follows:

[0048] This disclosure provides a semiconductor power device and its fabrication method, as well as an electronic device. By epitaxially growing a single-crystal diamond epitaxial layer on a SiC substrate, the on-resistance of the SiC device can be reduced, and the heat dissipation effect can be increased, giving the SiC device better thermal stability. This effectively solves the problem of poor heat dissipation in traditional SiC devices, improves the operating efficiency of SiC devices, and the fabrication process is simple. Furthermore, the single-crystal diamond epitaxial layer is epitaxially grown on the surface of a metal iridium film. Compared with directly epitaxially growing single-crystal diamond on the surface of the SiC substrate, this disclosure can improve the epitaxial quality of the single-crystal diamond epitaxial layer and improve the performance of the device. Attached Figure Description

[0049] Figure 1 This is a schematic diagram of a semiconductor power device provided in an embodiment of the present disclosure;

[0050] Figure 2 This is another schematic diagram of the structure of a semiconductor power device provided in an embodiment of the present disclosure;

[0051] Figure 3 This is a schematic flowchart of a method for fabricating a semiconductor power device according to an embodiment of the present disclosure;

[0052] Figure 4 This is a schematic flowchart of another method for fabricating a semiconductor power device according to an embodiment of the present disclosure;

[0053] Figure 5 This is a schematic flowchart of another method for fabricating a semiconductor power device according to an embodiment of the present disclosure;

[0054] Figure 6 A schematic diagram of a semiconductor power device in the fabrication process provided in an embodiment of this disclosure;

[0055] Figure 7 This is yet another structural schematic diagram of a semiconductor power device in the fabrication process provided in this embodiment of the disclosure;

[0056] Figure 8 This is yet another structural schematic diagram of a semiconductor power device in the fabrication process provided in this embodiment of the disclosure;

[0057] Figure 9 This is yet another structural schematic diagram of a semiconductor power device in the fabrication process provided in this embodiment of the disclosure;

[0058] Figure 10 This is yet another structural schematic diagram of a semiconductor power device in the fabrication process provided in this embodiment of the disclosure;

[0059] Figure 11 for Figure 10 A schematic diagram of a single-crystal diamond epitaxial layer with conductive and hydrogen-terminated regions;

[0060] Figure 12 This is yet another structural schematic diagram of a semiconductor power device in the fabrication process provided in this embodiment of the disclosure;

[0061] Figure 13 This is yet another structural schematic diagram of a semiconductor power device in the fabrication process provided in this embodiment of the disclosure;

[0062] Figure 14 This is yet another structural schematic diagram of a semiconductor power device in the fabrication process provided in this embodiment of the disclosure;

[0063] Figure 15 for Figure 14 A cross-sectional view along the AA' direction;

[0064] Figure 16 This is yet another structural schematic diagram of a semiconductor power device in the fabrication process provided in this embodiment of the disclosure;

[0065] Figure 17 This is yet another structural schematic diagram of a semiconductor power device in the fabrication process provided in this embodiment of the disclosure;

[0066] Figure 18 This is another schematic diagram of the semiconductor power device in the fabrication process provided in the embodiments of this disclosure. Detailed Implementation

[0067] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be noted that, for clarity, the thickness of layers, films, panels, regions, etc., is enlarged in the drawings. Exemplary embodiments are described in this disclosure with reference to cross-sectional views as schematic diagrams of idealized embodiments. Thus, deviations from the shape of the figures will be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described in this disclosure should not be construed as limited to the specific shape of the regions shown in this disclosure, but rather include deviations in shape caused, for example, by manufacturing processes. For example, a region illustrated or described as flat may typically have rough and / or non-linear characteristics; a sharp corner illustrated may be rounded, etc. Therefore, the regions shown in the figures are schematic in nature, and their dimensions and shapes are not intended to illustrate the precise shape of the regions or reflect true proportions; their purpose is merely to illustrate the content of this disclosure. And throughout, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted.

[0068] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure and the claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word covers the element or object listed following the word and its equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “inner,” “outer,” “upper,” and “lower” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0069] In the following description, when an element or layer is referred to as "on" or "connected to" another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. When an element or layer is referred to as "located on one side of" another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. However, when an element or layer is referred to as "directly on" or "directly connected to" another element or layer, no intermediate elements or intermediate layers are present. The term "and / or" includes any and all combinations of one or more of the related listed items.

[0070] This disclosure provides a semiconductor power device, such as... Figure 1 As shown, it includes:

[0071] The SiC substrate 1 has a first surface A1 and a second surface A2 disposed opposite to each other. The first surface A1 has a first conductive channel region 11 and a second conductive channel region 12 disposed at intervals. Specifically, the SiC substrate 1 is a P-type 4H-SiC substrate, the first surface A1 is the Si surface, and the second surface A2 is the C surface.

[0072] Yttrium-stabilized zirconium oxide layer 2 is located on the second surface A2 of SiC substrate 1;

[0073] The metallic iridium film 3 is located on the side of the yttrium-stabilized zirconium oxide layer 2 away from the SiC substrate 1;

[0074] The single-crystal diamond epitaxial layer 4 is located on the side of the iridium film layer 3 away from the SiC substrate 1;

[0075] The first source S1 is located on the side of the first conductive channel region 11 away from the single crystal diamond epitaxial layer 4;

[0076] The first drain, D1, is located on the side of the second conductive channel region 12 away from the single-crystal diamond epitaxial layer 4.

[0077] The semiconductor power device provided in this disclosure, by epitaxially growing a single-crystal diamond epitaxial layer on a SiC substrate, can reduce the on-resistance of the SiC device and increase its heat dissipation, thus giving the SiC device better thermal stability. This effectively solves the problem of poor heat dissipation in traditional SiC devices, improves the operating efficiency of the SiC device, and simplifies the fabrication process. Furthermore, the single-crystal diamond epitaxial layer is epitaxially grown on the surface of a metal iridium film. Compared to directly epitaxially growing single-crystal diamond on the surface of the SiC substrate, this disclosure can improve the epitaxial quality of the single-crystal diamond epitaxial layer and enhance the device performance.

[0078] Specifically, the yttrium-stabilized zirconium oxide layer can enhance the adhesion between the metallic iridium film and the SiC substrate.

[0079] In some embodiments, in the semiconductor power devices provided in the present disclosure, such as Figure 2 As shown, the side of the single-crystal diamond epitaxial layer 4 away from the SiC substrate 1 includes a conductive termination region 41;

[0080] The semiconductor power device may also include:

[0081] The second source S2 and the second drain D2 are disposed at intervals on the side of the conductive terminal region 41 away from the SiC substrate 1.

[0082] The gate dielectric layer 5 covers the conductive terminal region 41 between the second source S2 and the second drain D2, and also covers a portion of the second source S2 and a portion of the second drain D2.

[0083] The gate electrode G2 is located on the side of the gate dielectric layer 5 away from the SiC substrate 1.

[0084] Thus, this disclosure Figure 2 In the semiconductor power device shown, the single-crystal diamond epitaxial layer 4 not only solves the heat dissipation problem of SiC devices, but also allows for the fabrication of diamond power devices on the single-crystal diamond epitaxial layer 4, thereby improving the utilization rate of the single-crystal diamond epitaxial layer 4 and reducing costs. Therefore, this disclosure solves the problems of poor heat dissipation, low diamond substrate utilization, and high cost of traditional SiC power devices by fabricating SiC devices and diamond power devices on the first surface A1 of SiC substrate 1 and the single-crystal diamond epitaxial layer 4 grown on SiC substrate 1, respectively.

[0085] In some embodiments, the conductive termination region 41 may be a tin termination region, a hydrogen termination region, or a silicon termination region.

[0086] In some embodiments, in the semiconductor power devices provided in the present disclosure, such as Figure 2 As shown, the first surface A1 of the SiC substrate 1 can also be provided with other functional structures required for SiC devices, which are not limited here.

[0087] In some embodiments, in the semiconductor power devices provided in the present disclosure, such as Figure 2 As shown, the first source S1 and the second source S2 can be electrically connected, and / or the first drain D1 and the second drain D2 can be electrically connected. Specifically, for example, if the first source S1 and the second source S2 are electrically connected, and the first drain D1 and the second drain D2 are electrically connected, the SiC device and the diamond power device can be integrated in parallel, which can achieve higher withstand voltage and larger current, improving the overall performance of the device; for example, if the first source S1 and the second drain D2 are electrically connected, the SiC device and the diamond power device can be integrated in series, which can achieve higher withstand voltage and larger current, improving the overall performance of the device.

[0088] In some embodiments, at least two can also be Figure 2 The structures shown are integrated in series or parallel.

[0089] Based on the same inventive concept, this disclosure provides a method for fabricating the above-mentioned semiconductor power device. Since the principle of this fabrication method in solving the problem is similar to that of the above-mentioned semiconductor power device, the implementation of the fabrication method provided in this disclosure can refer to the implementation of the above-mentioned semiconductor power device provided in this disclosure, and repeated details will not be described again.

[0090] In some embodiments, the method for fabricating a semiconductor power device provided in this disclosure, such as... Figure 3 As shown, the following steps may be included:

[0091] S301, A yttrium-stabilized zirconium oxide layer is formed on the second surface of a SiC substrate;

[0092] S302, An iridium film is formed on the side of the yttrium-stabilized zirconium oxide layer away from the SiC substrate;

[0093] S303. A single-crystal diamond epitaxial layer is epitaxially grown on the side of the iridium metal film away from the SiC substrate.

[0094] S304. Ion implantation is performed on the first surface of the SiC substrate to form a first conductive channel region and a second conductive channel region.

[0095] S305, a first source is formed in the first conductive channel region, and a first drain is formed in the second conductive channel region.

[0096] In some embodiments, in the above-described preparation method provided in this disclosure, before ion implantation is performed on the first surface of the SiC substrate to form the first conductive channel region and the second conductive channel region in step S304, as follows: Figure 4 As shown, it also includes:

[0097] S401. Thinning the SiC substrate. For example, polishing the first surface of the SiC substrate to reduce its thickness can accelerate heat dissipation.

[0098] In some embodiments, in the above-described preparation method provided in this disclosure, after the epitaxial growth of a single-crystal diamond layer on the side of the iridium film away from the SiC substrate in step S303, and before the thinning treatment of the SiC substrate in step S401, such as Figure 5 As shown, it also includes:

[0099] S501. A conductive termination region is formed on the side of the single-crystal diamond epitaxial layer away from the SiC substrate.

[0100] S502, A second source and a second drain are formed on both sides of the conductive terminal region;

[0101] S503, a gate dielectric layer is formed on the side of the second source and the second drain away from the SiC substrate. The gate dielectric layer covers the conductive terminal region between the second source and the second drain, as well as a portion of the second source and a portion of the second drain.

[0102] S504. A gate is formed on the side of the gate dielectric layer away from the SiC substrate.

[0103] In some embodiments, in the preparation method provided in this disclosure, step S501, forming a conductive termination region on the side of the single-crystal diamond epitaxial layer away from the SiC substrate, specifically includes:

[0104] SnO is deposited on the side of the single-crystal diamond epitaxial layer away from the SiC substrate. x Thin film, and SnO x The thin film is patterned to form SnO. x Reserved area and SnO x SnO removal zone x Mask layer; where x = 1 or 2; optionally, SnO x It can be SnO2 or SnO;

[0105] For the formation of SnO x The single-crystal diamond epitaxial layer of the mask layer undergoes plasma hydrogenation treatment to form tin-terminated and hydrogen-terminated regions on the side of the single-crystal diamond epitaxial layer away from the SiC substrate; wherein, the tin-terminated region and SnO xCorresponding to the reserved region, the hydrogen terminal region is SnO x The removal area corresponds to this;

[0106] Removal of SnO by acid washing x Mask layer.

[0107] In some embodiments, in the above-described preparation method provided in this disclosure, after forming the second source and the second drain in step S502 and before forming the gate dielectric layer in step S503, the method further includes:

[0108] A photoresist layer is formed on the side of the second source and the second drain away from the SiC substrate;

[0109] The photoresist layer is exposed and developed to form a photoresist pattern including areas where the photoresist is completely retained and areas where the photoresist is completely removed; wherein, the areas where the photoresist is completely retained correspond to the tin-terminated areas and the areas where the photoresist is completely removed correspond to the hydrogen-terminated areas.

[0110] Using a photoresist pattern as a mask, oxygen plasma treatment is applied to the hydrogen terminal region to convert it into an oxygen terminal region.

[0111] Remove the photoresist pattern.

[0112] In this way, oxygen plasma is used to remove hydrogen terminal regions to form oxygen terminal regions, so that the hydrogen terminal regions can act as insulating regions to prevent device leakage.

[0113] In some embodiments, in the above-described preparation method provided in this disclosure, step S305, which involves forming a first source in the first conductive channel region and a first drain in the second conductive channel region, specifically includes:

[0114] A SiO2 thin film is formed on the first surface of a SiC substrate;

[0115] The SiO2 thin film is patterned to form a SiO2 mask layer including a SiO2 retention region and a SiO2 removal region. The SiO2 removal region corresponds to the first conductive channel region and the second conductive channel region, and the SiO2 retention region corresponds to the region outside the first conductive channel region and the second conductive channel region.

[0116] Metal is deposited in the first conductive channel region, the second conductive channel region, and on the side of the SiO2 mask layer away from the single-crystal diamond epitaxial layer;

[0117] The SiO2 mask layer is removed to form a first source in the first conductive channel region and a first drain in the second conductive channel region.

[0118] To better understand the technical solution of the preparation method provided in the embodiments of this disclosure, Figure 2Taking the semiconductor power device shown as an example, the fabrication process of the semiconductor power device is explained in detail, specifically including the following steps:

[0119] (1) Standard RCA cleaning is performed on the P-type 4H-SiC substrate. The main purpose is to remove dust and various contaminants from the surface of the 4H-SiC substrate and enhance the adhesion of the surface.

[0120] (2) such as Figure 6 As shown, a yttrium-stabilized zirconia layer 2 can be deposited on the second surface (C-plane) of the SiC substrate 1 using magnetron sputtering or electron beam evaporation. An iridium film layer 3 is then formed on the side of the yttrium-stabilized zirconia layer 2 away from the SiC substrate 1. The thicknesses of the yttrium-stabilized zirconia layer 2 and the iridium film layer 3 are 100~300 nm, respectively. Specifically, the magnetron sputtering equipment is evacuated until the pressure value is ≤1×10⁻⁶. -5 mbar, then turn on the magnetron sputtering equipment and heat up to 700℃. In the high-temperature environment, yttrium-stabilized zirconium oxide layer 2 and metallic iridium film layer 3 are sputtered and deposited on the C-side of SiC substrate 1.

[0121] (3) such as Figure 7 As shown, a single-crystal diamond epitaxial layer 4 is epitaxially grown on the side of the iridium film 3 away from the SiC substrate 1 using microwave plasma chemical vapor deposition (PCVDC). Specifically, the epitaxial growth process using PCVDC consists of three stages: First, a heating stage, where the hydrogen flow rate is controlled at 200–1000 sccm and the cavity pressure at 50–200 torr, and the microwave power is set at 10–100 kW. The microwave generator is started, and the cavity pressure and microwave power are gradually increased until the temperature of the heterostructure substrate reaches 600–900 °C. Second, a bias-enhanced nucleation stage, where the temperature is 800–900 °C, and etching is performed on the SiC substrate 1 for 5–20 min under hydrogen / argon conditions. Methane gas is then introduced at a flow rate of 2–50 sccm, and hydrogen gas at a flow rate of 200–1000 sccm for plasma pretreatment for 2–10 min. Turn on the DC bias power supply, set the bias voltage to -250~-350V, and the time to 1~5h for bias-enhanced nucleation. Thirdly, in the diamond growth stage, the power is 10~100kW, the pressure is 50~200 torr, the temperature is 800~1200℃, the hydrogen flow rate is 200~1000sccm, the methane flow rate is 2~50sccm, and the growth time is 0~500h. It's understandable that the growth time is not zero.

[0122] (4) such as Figure 8As shown, SnO2 or SnO thin films are deposited on the side of the single-crystal diamond epitaxial layer 4 away from the SiC substrate using electron beam evaporation, thermal evaporation, magnetron sputtering, atomic layer deposition, or chemical vapor deposition. In this embodiment, SnO2 thin film 6 is deposited as an example. SnO2 thin films 6 with a thickness of 0~600nm can be obtained by electron beam evaporation deposition, such as 100nm, 200nm, 300nm, 400nm, 500nm, 600nm, etc.

[0123] (5) Pattern the SnO2 thin film 6 to form a SnO2 mask layer 6' including a SnO2 retention region 61 and a SnO2 removal region 62. Specifically, the SnO2 mask layer 6' can be formed by photolithography. During photolithography, a photoresist with a thickness of 1~10μm is coated by spin coating. The excess photoresist is removed by exposure and development. Then, the SnO2 thin film 6 is etched using the remaining photoresist as a mask using RIE (Reactive Ion Etching) to obtain a patterned SnO2 mask layer 6'. Specifically, the reactive gas introduced into the reactive ion etching equipment is a gas mixture of HBr / Ar (hydrogen bromide / argon), where the percentage of Ar in the gas mixture can be 0%-100%, the input power can be 400~700W, and the gas pressure can be 4~10mTorr. Subsequently, the excess photoresist is washed away to obtain the desired SnO2 mask layer 6', such as Figure 9 As shown.

[0124] (6) The single-crystal diamond epitaxial layer 4 with SnO2 mask layer 6' formed is subjected to plasma hydrogenation treatment using a microwave plasma chemical vapor deposition system. The plasma hydrogenation treatment temperature is 900-1200℃, for example 1100℃, the hydrogen flow rate is 400-600sccm, for example 500sccm, the gas pressure is 110~130 Torr, for example 120 Torr, and the treatment time is 10~30min. In this way, the strong reduction and thermal environment of hydrogen plasma are used to transform the surface of the single-crystal diamond epitaxial layer 4 away from the SiC substrate 1 into the tin terminal region (i.e. the conductive terminal region 41 described above, which will be referred to as the conductive terminal region 41 hereafter) corresponding to the SnO2 removal region 62 into the hydrogen terminal region 42. That is, the conductive terminal region 41 and the hydrogen terminal region 42 are formed on the side of the single-crystal diamond epitaxial layer 4 away from the SiC substrate 1. Then, the unetched SnO2 mask layer on the surface of the single-crystal diamond epitaxial layer 4 was cleaned with 2 mol / L dilute hydrochloric acid for 20 minutes to obtain a diamond patterned substrate with conductive termination regions 41, as shown below. Figure 10 As shown.

[0125] like Figure 11 As shown, Figure 11 for Figure 10A schematic diagram showing the formation of a conductive terminal region 41 and a hydrogen terminal region 42 in the single-crystal diamond epitaxial layer 4.

[0126] It should be noted that the embodiment of this disclosure takes the conductive terminal region formed in step (5) as a tin terminal region as an example. Of course, it is not limited to this. For example, the conductive terminal region can also be a hydrogen terminal region, a silicon terminal region, etc. The type of conductive terminal region can be selected as needed.

[0127] (7) For example Figure 12 As shown, a second source S2 and a second drain D2 are fabricated on both sides within the conductive terminal region 41. Specifically, a layer of photoresist is first coated on the side of the single-crystal diamond epitaxial layer 4 away from the SiC substrate 1. The photoresist is then exposed and developed to expose the second source S2 and the second drain D2. Next, a layer of metal material (e.g., Ti / Au) is deposited using electron beam evaporation, with a thickness of 0~100nm. Subsequently, the remaining photoresist is washed away, and after annealing for 30 minutes, the second source S2 and the second drain D2 are formed in ohmic contact with the conductive terminal region 41.

[0128] In some embodiments, in the above-described fabrication method provided in this disclosure, since the hydrogen termination region 42 is conductive, it is necessary to convert the hydrogen termination region 42 into an insulating region to prevent leakage current in the formed device. For example, after forming the second source S2 and the second drain D2, the method further includes: forming a photoresist layer on the side of the second source and the second drain away from the SiC substrate; exposing and developing the photoresist layer to form a photoresist pattern including a photoresist-retained region and a photoresist-removed region; wherein the photoresist-retained region corresponds to the conductive termination region, and the photoresist-removed region corresponds to the hydrogen termination region; using the photoresist pattern as a mask, the hydrogen termination region is subjected to oxygen plasma treatment to convert the hydrogen termination region into an oxygen termination region; and the photoresist pattern is removed. This process... Figure 12 The hydrogen terminal region 42 is subjected to oxygen plasma removal to form an oxygen terminal region, so that the hydrogen terminal region 42 can be an insulating region to prevent device leakage.

[0129] Specifically, the oxygen plasma treatment process may include: treating the hydrogen removal terminal zone 42 with ultraviolet / ozone and oxygen plasma, wherein the gas flow rate of oxygen or ozone is 1~100 sccm, the plasma power is 100~300W, and the treatment time is 1~60min.

[0130] (8) such as Figure 13As shown, a gate dielectric layer 5 (material can be SiO2) is formed on the side of the second source S2 and the second drain D2 away from the SiC substrate 1. Specifically, a layer of photoresist is first coated on the surface of the second source S2 and the second drain D2. The photoresist is exposed and developed to expose the middle region of the conductive terminal region 41 and a portion of the second source S2 and the second drain D2. Then, SiO2 is deposited, and the remaining photoresist is washed away. This forms a gate dielectric layer 5 that covers the conductive terminal region 41 between the second source S2 and the second drain D2 and covers a portion of the second source S2 and a portion of the second drain D2. The gate dielectric layer 5 covering a portion of the second source S2 and a portion of the second drain D2 can reduce the electric field and increase the breakdown voltage.

[0131] (9) First, a layer of photoresist is coated on the surface of the gate dielectric layer 5. The photoresist is exposed and developed to expose the middle region of the gate dielectric layer 5. Then, a metal material (e.g., Ti / Au) is deposited on the side of the gate dielectric layer 5 away from the SiC substrate 1 using an electron beam evaporation device. Subsequently, the remaining photoresist is washed away, thus forming the gate G2 covering the middle region of the gate dielectric layer 5 and forming a Schottky contact. In this way, a diamond power device is formed on the side of the single crystal diamond epitaxial layer 4 away from the SiC substrate 1, such as... Figure 14 and Figure 15 As shown, Figure 15 for Figure 14 A cross-sectional view along the AA' direction.

[0132] (10) such as Figure 16 As shown, the first surface A1 (Si surface) of the SiC substrate 1 is polished to reduce the thickness of the SiC substrate 1, which can accelerate heat dissipation. Subsequently, ion implantation is performed on the Si surface of the SiC substrate 1 to form a first conductive channel region 11 and a second conductive channel region 12. Specifically, phosphorus and nitrogen can be used as impurity ions implanted into the Si surface of the SiC substrate 1 to form N-type first conductive channel region 11 and second conductive channel region 12, and aluminum and boron can be used as impurity ions implanted into the Si surface of the SiC substrate 1 to form P-type first conductive channel region 11 and second conductive channel region 12.

[0133] Specifically, the surface of the thinned SiC substrate 1 that is far from the single-crystal diamond epitaxial layer 4 is still referred to as the first surface A1.

[0134] (11) such as Figure 17 As shown, a SiO2 thin film 7 was formed on the first surface A1 of the SiC substrate 1 using plasma chemical vapor deposition. The thickness of the SiO2 thin film 7 was 2 μm. The gases used and their flow rates were 400 sccm of SiH4 and He, 800 sccm of N2O, and 750 sccm of N2. The pressure was 900 mtorr, and the temperature was around 140 °C.

[0135] (12) such as Figure 18 As shown, the SiO2 thin film 7 is patterned to form a SiO2 mask layer 7' including a SiO2 retention region 71 and a SiO2 removal region 72. The SiO2 removal region 72 corresponds to the first conductive channel region 11 and the second conductive channel region 12, and the SiO2 retention region 71 corresponds to the region other than the first conductive channel region 11 and the second conductive channel region 12. Specifically, photoresist is coated on the side of the SiO2 thin film 7 away from the SiC substrate 1, and excess photoresist is removed by exposure and development. Then, the SiO2 thin film 7 is etched to form the SiO2 mask layer 7'.

[0136] (13) Clean the first conductive channel region 11 and the second conductive channel region 12 after photolithography, and deposit metal on the side of the first conductive channel region 11, the second conductive channel region 12 and the SiO2 mask layer 7' away from the single crystal diamond epitaxial layer 4; remove the SiO2 mask layer 7' to form the first source S1 in the first conductive channel region 11 and the first drain D1 in the second conductive channel region 12. Specifically, four metal layers, Ti / Al / Ni / Au or Ti / Al / Mo / Au, are deposited sequentially on the side of the first conductive channel region 11, the second conductive channel region 12 and the SiO2 mask layer 7' away from the single crystal diamond epitaxial layer 4 by electron beam evaporation or sputtering. The thicknesses of the four metal layers are 20nm / 50nm / 30nm / 10nm, respectively, and the SiO2 mask layer 7' is removed. Finally, a rapid thermal annealing process was performed in an inert gas at a temperature of 900°C for 30 seconds to form the first source electrode S1 and the first drain electrode D1, ultimately yielding... Figure 2 The SiC and diamond heterostructures shown are, for example Figure 2 As shown.

[0137] It should be noted that in the above-described fabrication method provided in the embodiments of this disclosure, the patterning processes involved in forming each layer structure may include not only some or all of the processes such as deposition, photoresist coating, masking, exposure, development, etching, and photoresist stripping, but may also include other processes, depending on the pattern to be formed in the actual fabrication process, and are not limited here. For example, a post-baking process may be included after development and before etching. The deposition process may be chemical vapor deposition, plasma-enhanced chemical vapor deposition, or physical vapor deposition, and is not limited here; the mask used in the masking process may be a half-tone mask, a single-slit mask, or a gray-tone mask, and is not limited here; the etching may be dry etching or wet etching, and is not limited here.

[0138] Based on the same inventive concept, this disclosure provides an electronic device including the semiconductor power device described above. Since the principle by which this electronic device solves the problem is similar to that of the semiconductor power device, the implementation of the electronic device provided in this disclosure can refer to the implementation of the semiconductor power device provided in this disclosure, and repeated details will not be described again.

[0139] In some embodiments, the electronic devices provided in this disclosure may include, but are not limited to: radio frequency amplifiers, mixers, radar, satellites, power supplies, automotive electronics, energy-saving lamps, and home appliances.

[0140] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0141] Obviously, those skilled in the art can make various modifications and variations to this disclosure without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include such modifications and variations.

Claims

1. A semiconductor power device, characterized in that, include: A SiC substrate has a first surface and a second surface disposed opposite to each other, and the first surface has a first conductive channel region and a second conductive channel region disposed at intervals. A yttrium-stabilized zirconium oxide layer is located on the second surface of the SiC substrate; An iridium film layer is located on the side of the yttrium-stabilized zirconium oxide layer away from the SiC substrate; A single-crystal diamond epitaxial layer is located on the side of the iridium metal film layer away from the SiC substrate; the side of the single-crystal diamond epitaxial layer away from the SiC substrate includes a conductive termination region; The first source electrode is located on the side of the first conductive channel region away from the single-crystal diamond epitaxial layer. The first drain is located on the side of the second conductive channel region away from the single-crystal diamond epitaxial layer; The second source and the second drain are disposed at an interval on the side of the conductive terminal region away from the SiC substrate; A gate dielectric layer covers the conductive termination region between the second source and the second drain, and also covers a portion of the second source and a portion of the second drain; The gate electrode is located on the side of the gate dielectric layer away from the SiC substrate.

2. The semiconductor power device as described in claim 1, characterized in that, The first source and the second source are electrically connected, and / or the first drain and the second drain are electrically connected.

3. An electronic device, characterized in that, Includes the semiconductor power device as described in claim 1 or 2.

4. A method for fabricating a semiconductor power device, characterized in that, include: A yttrium-stabilized zirconium oxide layer is formed on the second surface of the SiC substrate; An iridium film is formed on the side of the yttrium-stabilized zirconium oxide layer away from the SiC substrate; A single-crystal diamond epitaxial layer is epitaxially grown on the side of the iridium film away from the SiC substrate; A conductive termination region is formed on the side of the single-crystal diamond epitaxial layer away from the SiC substrate; A second source and a second drain are formed on both sides within the conductive terminal region; A gate dielectric layer is formed on the side of the second source and the second drain away from the SiC substrate. The gate dielectric layer covers the conductive termination region between the second source and the second drain, as well as a portion of the second source and a portion of the second drain. A gate is formed on the side of the gate dielectric layer away from the SiC substrate; Ion implantation is performed on the first surface of the SiC substrate to form a first conductive channel region and a second conductive channel region. A first source is formed in the first conductive channel region, and a first drain is formed in the second conductive channel region.

5. The preparation method according to claim 4, characterized in that, Before ion implantation is performed on the first surface of the SiC substrate to form the first conductive channel region and the second conductive channel region, the method further includes: The SiC substrate is thinned.

6. The preparation method according to claim 4, characterized in that, A conductive termination region is formed on the side of the single-crystal diamond epitaxial layer away from the SiC substrate, specifically including: SnO is deposited on the side of the single-crystal diamond epitaxial layer away from the SiC substrate. x Thin film, and the SnO x The thin film is patterned to form SnO. x Reserved area and SnO x SnO removal zone x Mask layer; where x = 1 or 2; For the SnO formed x The single-crystal diamond epitaxial layer of the mask layer is subjected to plasma hydrogenation treatment to form a tin-terminated region and a hydrogen-terminated region on the side of the single-crystal diamond epitaxial layer away from the SiC substrate; wherein, the tin-terminated region and the SnO x Corresponding to the retention region, the hydrogen terminal region is related to the SnO. x The removal area corresponds to this; Remove SnO by acid washing x Mask layer.

7. The preparation method according to claim 6, characterized in that, After forming the second source and the second drain, and before forming the gate dielectric layer, the method further includes: A photoresist layer is formed on the side of the second source and the second drain away from the SiC substrate; The photoresist layer is exposed and developed to form a photoresist pattern including a photoresist completely retained area and a photoresist completely removed area; wherein, the photoresist completely retained area corresponds to the tin-terminated area, and the photoresist completely removed area corresponds to the hydrogen-terminated area; Using the photoresist pattern as a mask, the hydrogen-terminated region is subjected to oxygen plasma treatment to convert the hydrogen-terminated region into an oxygen-terminated region. Remove the photoresist pattern.

8. The preparation method according to claim 4, characterized in that, A first source is formed in the first conductive channel region, and a first drain is formed in the second conductive channel region, specifically including: A SiO2 thin film is formed on the first surface of the SiC substrate; The SiO2 thin film is patterned to form a SiO2 mask layer including a SiO2 retention region and a SiO2 removal region. The SiO2 removal region corresponds to the first conductive channel region and the second conductive channel region, and the SiO2 retention region corresponds to the region other than the first conductive channel region and the second conductive channel region. Metal is deposited in the first conductive channel region, the second conductive channel region, and on the side of the SiO2 mask layer away from the single-crystal diamond epitaxial layer; The SiO2 mask layer is removed to form a first source in the first conductive channel region and a first drain in the second conductive channel region.

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