Integrated circuit device

Abstract

An integrated circuit device includes a hammer-shaped sheet partition wall between a nanosheet stack structure, thereby improving a patterning margin of a gate electrode and preventing or reducing an effective channel width reduction. That is, the integrated circuit device can provide increased stability performance and improved reliability in a nanosheet field effect transistor.

Description

Cross-reference to related applications

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2024-0084824, filed with the Korean Intellectual Property Office on June 27, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present invention relates to integrated circuit devices, and more specifically, to integrated circuit devices including field-effect transistors. Background Technology

[0003] In recent years, with the rapid miniaturization of integrated circuit devices, there is a growing demand not only for ensuring their operating speed but also for guaranteeing their accuracy. Furthermore, as the integration density and size of these integrated circuit devices increase, the likelihood of process defects during the fabrication of nanosheet field-effect transistors (FETs) also increases. Therefore, there is a need to develop integrated circuit devices with novel structures that can eliminate or reduce process defects and improve the performance and reliability of FETs. Summary of the Invention

[0004] The present invention provides an integrated circuit device that can provide increased stability and improved reliability in nanosheet field-effect transistors.

[0005] The purpose of this invention is not limited to the above-described purposes, but those skilled in the art will clearly understand from the following description other purposes not described herein.

[0006] According to some aspects of the present invention, an integrated circuit device is provided, comprising: a substrate layer including a pair of first fin active regions and a single second fin active region, each fin active region extending in a first horizontal direction and projecting in a vertical direction, the pair of first fin active regions and the single second fin active region being spaced apart from each other in a second horizontal direction intersecting the first horizontal direction; a first pad pattern extending between the pair of first fin active regions in the second horizontal direction and contacting opposite sidewalls of the pair of first fin active regions; a second pad pattern extending in the second horizontal direction and contacting one sidewall of the single second fin active region; a first sheet-like partition wall on the first pad pattern and including a body having a first width and a head having a second width greater than the first width; and a second sheet-like partition wall on the second pad pattern and including a... The device comprises: a body having a third width and a head having a fourth width greater than the third width; a pair of first nanosheet stacks, each comprising a plurality of first nanosheets, the pair of first nanosheet stacks being above the pair of first fin active regions and spaced apart from each other in a second horizontal direction, with first sheet-like partition walls between the pair of first nanosheet stacks; a single second nanosheet stack comprising a plurality of second nanosheets, the second nanosheet stack being above the single second fin active region; a plurality of recessed spacers between the plurality of first nanosheets and the first sheet-like partition walls, and between the plurality of second nanosheets and the second sheet-like partition walls; a pair of first gate electrodes surrounding the pair of first nanosheet stacks, with first sheet-like partition walls between the pair of first gate electrodes; and a single second gate electrode surrounding the single second nanosheet stack.

[0007] According to some aspects of the present invention, an integrated circuit device is provided, comprising: a substrate layer including a pair of fin-type active regions, each fin-type active region extending in a first horizontal direction and protruding in a vertical direction, the pair of fin-type active regions being spaced apart from each other in a second horizontal direction intersecting the first horizontal direction; a pad pattern extending between the pair of fin-type active regions in the second horizontal direction and contacting opposing sidewalls of the pair of fin-type active regions; a sheet-like partition wall extending on the pad pattern in the first horizontal direction and including a body having a first width and a head having a second width greater than the first width; a pair of nanosheet stacked structures, each nanosheet stacked structure including a plurality of nanosheets, the pair of nanosheet stacked structures being respectively above the pair of fin-type active regions and spaced apart from each other in the second horizontal direction, the sheet-like partition wall being interposed between the pair of nanosheet stacked structures; a plurality of recessed spacers between the plurality of nanosheets and the sheet-like partition wall; and a pair of gate electrodes surrounding the pair of nanosheet stacked structures and the plurality of recessed spacers, the sheet-like partition wall being interposed between the pair of gate electrodes.

[0008] According to some aspects of the present invention, an integrated circuit device is provided, comprising: a substrate layer including a fin-type active region extending in a first horizontal direction and projecting in a vertical direction; a pad pattern contacting a sidewall of the fin-type active region and extending in a second horizontal direction intersecting the first horizontal direction; a sheet-like partition wall extending on the pad pattern along the first horizontal direction and including a body having a first width and a head having a second width greater than the first width; a nanosheet stack structure above the fin-type active region and including a plurality of nanosheets; a plurality of recessed spacers between the plurality of nanosheets and a sidewall of the sheet-like partition wall; and a first gate electrode and a second gate electrode spaced apart from each other in the second horizontal direction, the sheet-like partition wall being interposed between the first gate electrode and the second gate electrode, the first gate electrode surrounding the nanosheet stack structure while the second gate electrode does not surround the nanosheet stack structure. Attached Figure Description

[0009] The embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 This shows a cross-sectional view of an integrated circuit device according to some example embodiments;

[0011] Figure 2 and Figure 3 This shows a cross-sectional view of an integrated circuit device according to some example embodiments;

[0012] Figures 4 to 32B These are perspective views and cross-sectional views illustrating methods for manufacturing integrated circuit devices in process sequence according to some example embodiments; and

[0013] Figures 33 to 36 This is a cross-sectional view illustrating a method for manufacturing integrated circuit devices in process sequence according to some example embodiments. Detailed Implementation

[0014] In the following text, some exemplary embodiments will be described in detail with reference to the accompanying drawings.

[0015] For reference, integrated circuit devices 10, 20, and 30 according to the present invention may include a gate region (the region along line A-A') and a source / drain region (the region along line B-B'). However, for ease of description, only one of these two regions may be shown and described.

[0016] Figure 1 This is a cross-sectional view of an integrated circuit device 10 according to some example embodiments. Specifically, Figure 1 It is the integrated circuit device 10 and its edge Figure 32A The cross-sectional diagram corresponding to the section intercepted by line A-A'.

[0017] refer to Figure 1 The integrated circuit device 10 according to the present invention may include a field-effect transistor having a plurality of nanosheets NS spaced apart from each other in the vertical direction (Z direction).

[0018] Specifically, the components constituting the integrated circuit device 10 according to the present invention are described below.

[0019] The substrate layer BSUB may include semiconductor materials (e.g., silicon (Si) and germanium (Ge)) or compound semiconductor materials (e.g., silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs) and / or indium phosphide (InP)).

[0020] Trench isolation STIs can be arranged within multiple trenches (TREs) of the substrate layer (BSUB). The trench isolation STIs can define multiple finned active regions (FAs) as described below.

[0021] Multiple fin-type active regions FA may include a pair of first fin-type active regions FA1 and a single second fin-type active region FA2. The pair of first fin-type active regions FA1 extend in a first horizontal direction (X direction), are spaced apart from each other in a second horizontal direction (Y direction) intersecting the first horizontal direction (X direction), and protrude in a vertical direction (Z direction). The single second fin-type active region FA2 extends in the first horizontal direction (X direction) and protrudes in the vertical direction (Z direction).

[0022] The plurality of pad patterns LP may include a first pad pattern LP1 and a second pad pattern LP2, wherein the first pad pattern LP1 extends along a second horizontal direction (Y direction) between a pair of first fin active regions FA1 and contacts the opposite sidewalls of the pair of first fin active regions FA1, and the second pad pattern LP2 extends in the second horizontal direction (Y direction) and contacts one sidewall of a single second fin active region FA2.

[0023] The plurality of sheet-like partition walls SW may include a first sheet-like partition wall SW1 and a second sheet-like partition wall SW2. The first sheet-like partition wall SW1 is located on a first pad pattern LP1 and includes a main body SWB with a first width A1B and a head SWH with a second width A1H greater than the first width A1B. The second sheet-like partition wall SW2 is disposed on a second pad pattern LP2 and includes a main body SWB with a third width A2B and a head SWH with a fourth width A2H greater than the third width A2B.

[0024] In some example embodiments, the main bodies SWB of the plurality of sheet-like partition walls SW may all have a rectangular shape with a longer side in the vertical direction (Z direction), and the heads SWH of the plurality of sheet-like partition walls SW may all have a rectangular shape with a longer side in the second horizontal direction (Y direction). In other words, each of the plurality of sheet-like partition walls SW may have a hammer shape.

[0025] In some example embodiments, the first width A1B of the body SWB of the first sheet-like partition wall SW1 may be smaller than the third width A2B of the body SWB of the second sheet-like partition wall SW2, and the second width A1H of the head SWH of the first sheet-like partition wall SW1 may be smaller than the fourth width A2H of the head SWH of the second sheet-like partition wall SW2. This may be because the nanosheet stacked structure NSS described below is not formed on one side of the second sheet-like partition wall SW2 (the rightmost side in the figure), thus increasing the space available for forming the second sheet-like partition wall SW2.

[0026] In some example embodiments, each of the plurality of pad patterns LP may have a rectangular shape with a longer side in the second horizontal direction (Y direction). The horizontal width of the first pad pattern LP1 in the second horizontal direction (Y direction) may be equal to the second width A1H of the head SWH of the first sheet-like partition wall SW1, and the horizontal width of the second pad pattern LP2 in the second horizontal direction (Y direction) may be equal to the fourth width A2H of the head SWH of the second sheet-like partition wall SW2. This may be due to the characteristics of the manufacturing process described below.

[0027] Multiple nanosheet stacked structures NSS may include a pair of first nanosheet stacked structures NSS1 and a single second nanosheet stacked structure NSS2. Each of the pair of first nanosheet stacked structures NSS1 includes multiple nanosheets NS and is respectively disposed above a pair of first fin active regions FA1 and spaced apart from each other in the second horizontal direction (Y direction). A first sheet-like partition wall SW1 is located between the pair of first nanosheet stacked structures NSS1. The single second nanosheet stacked structure NSS2 includes multiple nanosheets NS and is disposed above the second fin active region FA2.

[0028] Multiple recessed spacers IDT can be arranged between multiple nanosheets NS and the first sheet-like partition wall SW1, and between multiple nanosheets NS and the second sheet-like partition wall SW2.

[0029] The multiple gate electrodes GE may include a pair of first gate electrodes GE11 and GE12, a single second gate electrode GE21, and a single electrode structure GE22. The pair of first gate electrodes GE11 and GE12 are respectively surrounding a pair of first nanosheet stacked structures NSS1. A first sheet-like partition wall SW1 is located between the pair of first gate electrodes GE11 and GE12, and the single second gate electrode GE21 is surrounding a single second nanosheet stacked structure NSS2.

[0030] In some example embodiments, the single electrode structure GE22 may not surround multiple nanosheets NS. That is, unlike the single second gate electrode GE21, the single electrode structure GE22 cannot be used as a gate electrode.

[0031] In some example embodiments, the vertical height of the uppermost surface of each of the plurality of gate electrodes GE may be lower than the vertical height of the uppermost surface of each head SWH of the plurality of sheet separator walls SW, and higher than the vertical height of the lowermost surface of each head SWH of the plurality of sheet separator walls SW.

[0032] The gate capping layer (GCL) can cover multiple gate electrodes (GE) and multiple sheet-like partition walls (SW). Specifically, the gate capping layer (GCL) can cover the upper surface and part of the sidewalls of each head (SWH) of the multiple sheet-like partition walls (SW).

[0033] The gate dielectric film GOX can be conformally arranged between multiple gate electrodes GE and multiple nanosheet stacked structures NSS including multiple nanosheets NS, as well as between multiple gate electrodes GE and multiple fin active regions FA.

[0034] although Figure 1 Not shown in the diagram, but multiple source / drain SDs (see [reference]). Figure 24A It can be connected to multiple nanosheets NS in a multi-nanosheet stacked structure NSS. This will be described in detail below.

[0035] In other words, in the integrated circuit device 10 conceived according to the present invention, multiple nanosheet stacked structures NSS, multiple gate electrodes GE, and multiple source / drain electrodes SD (see...) Figure 24A () can be used to construct multiple multi-gate metal-oxide-semiconductor field-effect transistors (MOSFETs).

[0036] More specifically, the numerical ranges for specific components are as follows. However, the numerical ranges for specific components are merely examples and are not limited to these.

[0037] In some example embodiments, the first width A1B of the body SWB of the first sheet-like partition wall SW1 can be about or exactly 0.5 nm to about or exactly 20 nm. Furthermore, the second width A1H of the head SWH of the first sheet-like partition wall SW1 can be about or exactly 3 nm to about or exactly 30 nm.

[0038] As described above, in the first sheet-like partition wall SW1, the second width A1H can be greater than the first width A1B. Furthermore, in the second sheet-like partition wall SW2, the fourth width A2H can be greater than the third width A2B. Additionally, when comparing the first sheet-like partition wall SW1 and the second sheet-like partition wall SW2, the third width A2B can be greater than the first width A1B, and the fourth width A2H can be greater than the second width A1H.

[0039] In some example embodiments, the vertical height of the uppermost end of the head SWH of the first sheet-like separator SW1 may be higher than the vertical height of the upper surface of the uppermost nanosheet NS (hereinafter referred to as the uppermost nanosheet NS) by a first height B1. For example, the first height B1 defined above may be about or exactly 0.5 nm to about or exactly 40 nm. Additionally, the vertical height of the lowermost end of the head SWH of the first sheet-like separator SW1 may be higher than the vertical height of the upper surface of the uppermost nanosheet NS by a second height B2. For example, the second height B2 may be about or exactly 0.5 nm to about or exactly 20 nm.

[0040] In some example embodiments, the thickness C1 of each recessed spacer IDT in the vertical direction (Z direction) can be about or exactly 0.5 nm to about or exactly 7 nm. Additionally, the width C2 of the recessed spacer IDT in the second horizontal direction (Y direction) can be about or exactly 0.5 nm to about or exactly 10 nm.

[0041] In some example embodiments, the vertical thickness D1 of the pad pattern LP from its lower surface to its upper surface can be about or exactly 0.5 nm to about or exactly 10 nm. Additionally, the width D2 of the pad pattern LP in the second horizontal direction (Y direction) can be about or exactly 3 nm to about or exactly 30 nm.

[0042] In some example embodiments, the first height E1 of the fin-type active region FA (e.g., the vertical length from the lower surface of the fin-type active region FA to the lower surface of the pad pattern LP) can be about or exactly 0.5 nm to about or exactly 100 nm. Furthermore, the second height E2 of the fin-type active region FA (e.g., the vertical length from the lower surface of the pad pattern LP to the upper surface of the fin-type active region FA) can be about or exactly 0.5 nm to about or exactly 100 nm.

[0043] In addition, although Figure 1The illustration shows a structure including a first sheet-like partition wall SW1 adjacent to a structure including a second sheet-like partition wall SW2, but the example embodiment is not limited thereto. That is, the integrated circuit device 10 may include at least one of a structure having a first sheet-like partition wall SW1 and a structure having a second sheet-like partition wall SW2.

[0044] Accordingly, the integrated circuit device 10 according to the present invention can have the following advantages.

[0045] In some exemplary embodiments, in the integrated circuit device 10 conceived according to the present invention, hammer-shaped sheet-like separators SW are formed between multiple nanosheet stacked structures NSS, thus ensuring patterning margin for the gate electrode GE. Accordingly, the difficulty of the manufacturing process can be reduced.

[0046] In some exemplary embodiments, in the integrated circuit device 10 according to the present invention, the end of the gate electrode GE facing the sheet separator SW is closer to the sheet separator SW in the second horizontal direction (Y direction) than the end of the nanosheet NS facing the sheet separator SW. Therefore, the effective channel width can be increased.

[0047] In some exemplary embodiments, in the integrated circuit device 10 conceived according to the present invention, the nanosheet NS serving as the channel region is separated from the sheet-like partition wall SW by a recessed spacer IDT. Accordingly, leakage current due to fixed charge can be prevented or reduced.

[0048] Therefore, in some exemplary embodiments, the integrated circuit device 10 conceived according to the present invention can provide increased stability and improved reliability in nanosheet field-effect transistors.

[0049] Figure 2 and Figure 3 Cross-sectional views of integrated circuit devices 20 and 30 according to some example embodiments are shown.

[0050] Most of the components that make up integrated circuit devices 20 and 30 described below are the same as those mentioned above. Figure 1 The components described are essentially the same or similar. Therefore, for ease of description, the focus of the description is on the differences from the integrated circuit device 10 described above.

[0051] refer to Figure 2 The integrated circuit device 20 according to the present invention includes a field-effect transistor having a plurality of nanosheets NS spaced apart from each other in the vertical direction (Z direction).

[0052] According to some example embodiments, the integrated circuit device 20 may include a gate dielectric film GOX 20 disposed between a plurality of gate electrodes GE and a plurality of nanosheet stacked structures NSS including a plurality of nanosheets NS, and between the plurality of gate electrodes GE and a plurality of fin active regions FA.

[0053] Specifically, the gate dielectric film GOX20 can conformally surround multiple nanosheets NS, multiple recessed spacers IDT and multiple sheet-like partition walls SW, but may not cover (e.g., may expose) the upper surface of the head SWH of the multiple sheet-like partition walls SW.

[0054] This characteristic may be due to the fact that the first gate electrode forming layer GE1 and the second gate electrode forming layer GE2 (see...) Figure 31A In the patterning process of separating the node into multiple gate electrodes GE, the gate dielectric film GOX20 located on the upper surface of the head SWH of multiple sheet-like partition walls SW is removed together.

[0055] refer to Figure 3 The integrated circuit device 30 according to the present invention includes a field-effect transistor having a plurality of nanosheets NS spaced apart from each other in the vertical direction (Z direction).

[0056] In the integrated circuit device 30 according to some example embodiments, the bodies SWB of the plurality of sheet partition walls SW30 may all have a rectangular shape with a longer side in the vertical direction (Z direction), and the heads SWH of the plurality of sheet partition walls SW30 may all have an inverted trapezoidal shape with a horizontal width decreasing downward in the second horizontal direction (Y direction). In other words, each of the plurality of sheet partition walls SW30 may have a nail shape.

[0057] In some example embodiments, the width of the body SWB of the third sheet-like partition wall SW3 can be smaller than the width of the body SWB of the fourth sheet-like partition wall SW4, and the width of the head SWH of the third sheet-like partition wall SW3 can be smaller than the width of the head SWH of the fourth sheet-like partition wall SW4. This may be because the nanosheet stacked structure NSS is not formed on one side of the fourth sheet-like partition wall SW4 (the far right in the figure), thus increasing the space available for forming the fourth sheet-like partition wall SW4.

[0058] In the integrated circuit device 30 according to the present invention, nail-shaped sheet-like partition walls SW30 are formed between multiple nanosheet stacked structures NSS, thus ensuring the patterning margin of the gate electrode GE. Accordingly, the difficulty of the manufacturing process can be reduced.

[0059] Figures 4 to 32BThese are perspective views and cross-sectional views illustrating a method for manufacturing integrated circuit devices in process sequence according to some example embodiments.

[0060] Specifically, Figures 4 to 15 It is the integration of integrated circuit devices and the edge Figure 16A The cross-sectional views corresponding to the sections intercepted by lines A-A' and B-B'. Furthermore, Figure 16B , Figure 17B ,……,as well as Figure 24B They are along Figure 16A , Figure 17A ,……,as well as Figure 24A A cross-sectional view of the integrated circuit device taken by line B-B'. Furthermore, Figure 25B , Figure 26B ,……,as well as Figure 32B They are along Figure 25A , Figure 26A ,……,as well as Figure 32A A cross-sectional view of an integrated circuit device taken by line A-A'.

[0061] refer to Figure 4 Multiple sacrificial layers SL and multiple nanosheets NS are stacked alternately on the substrate layer BSUB.

[0062] Each of the multiple sacrificial layers SL can be arranged between the substrate layer BSUB and the lowest nanosheet NS (hereinafter referred to as the lowest nanosheet NS) among the multiple nanosheets NS, and between two nanosheets NS that are adjacent to each other in the vertical direction (Z direction). Each of the multiple nanosheets NS and the multiple sacrificial layers SL can extend parallel to the upper surface of the substrate layer BSUB.

[0063] In some example embodiments, each of the plurality of nanosheets NS may have substantially the same thickness. In other embodiments, the lowest nanosheet NS among the plurality of nanosheets NS may be thinner than the others.

[0064] The substrate layer BSUB may include semiconductor materials (e.g., silicon (Si) and / or germanium (Ge)) and / or compound semiconductor materials (e.g., silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs) and / or indium phosphide (InP)).

[0065] In some example embodiments, the substrate layer BSUB may include at least one of group III-V materials and group IV materials. Group III-V materials may include binary, ternary, or quaternary compound semiconductor materials comprising at least one group III element and at least one group V element. The substrate layer BSUB may include conductive regions (e.g., impurity-doped wells or impurity-doped structures).

[0066] The multiple nanosheets NS may include materials having the same or similar etching properties as the constituent materials of the substrate layer BSUB. The multiple sacrificial layers SL may include materials that have etching selectivity relative to the multiple nanosheets NS.

[0067] In some example embodiments, each of the plurality of nanosheets NS and the substrate layer BSUB may include a semiconductor material (e.g., silicon (Si) and germanium (Ge)). In some example embodiments, the plurality of sacrificial layers SL may include a compound semiconductor material (e.g., SiGe). In some example embodiments, each of the plurality of nanosheets NS, the substrate layer BSUB, and the plurality of sacrificial layers SL may include a compound semiconductor material (e.g., SiGe), but the germanium (Ge) concentration in the plurality of nanosheets NS and the substrate layer BSUB may differ from the germanium (Ge) concentration in the plurality of sacrificial layers SL.

[0068] refer to Figure 5 A first hard mask pattern HM1 and a second hard mask pattern HM2 are formed on a stacked structure of multiple sacrificial layers SL and multiple nanosheets NS. The multiple nanosheets NS and multiple sacrificial layers SL are patterned using the first hard mask pattern HM1 and the second hard mask pattern HM2 as etch masks. The exposed substrate layer BSUB is also partially removed in the patterning process to form multiple trenches TRE.

[0069] The first hard mask pattern HM1 and the second hard mask pattern HM2 may include a first hard mask pattern HM1 at a lower height and a second hard mask pattern HM2 at an upper height. The first hard mask pattern HM1 and the second hard mask pattern HM2 may extend in a first horizontal direction (X direction) and be spaced apart from each other in a second horizontal direction (Y direction). The first horizontal direction (X direction) may intersect with the second horizontal direction (Y direction).

[0070] Multiple trench TREs can each extend in the first horizontal direction (X direction). Figure 5 Multiple trench TREs with vertical sidewalls are shown. However, in some example embodiments, the multiple trench TREs may each have a tapered shape with a horizontal width that decreases downwards (e.g., toward the substrate layer BSUB).

[0071] The portion of the substrate layer BSUB that protrudes from the bottom surface of the multiple trench TREs can be referred to as the first fin active region FA1 and the second fin active region FA2.

[0072] refer to Figure 6 The first dielectric material layer DL1 can fill multiple trench TREs (see...). Figure 5 All the trenches in the TRE.

[0073] The first dielectric material layer DL1 can be formed to a sufficient thickness to have an upper surface located at the same height as the upper surface of the second hard mask pattern HM2. The first dielectric material layer DL1 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0074] refer to Figure 7 After forming a buffer layer BFL on the first dielectric material layer DL1 and the second hard mask pattern HM2, a third hard mask pattern HM3 can be formed on the buffer layer BFL.

[0075] The buffer layer BFL may comprise the same material as the material constituting the second hard mask pattern HM2. Accordingly, the buffer layer BFL and the second hard mask pattern HM2 may be formed as a single entity.

[0076] The third hard mask pattern HM3 may extend on the buffer layer BFL in a first horizontal direction (X direction) and may be spaced apart from each other in a second horizontal direction (Y direction). The third hard mask pattern HM3 may include a material that has etch selectivity relative to the buffer layer BFL and the first dielectric material layer DL1.

[0077] refer to Figure 8 The buffer layer BFL and the second hard mask pattern HM2 are patterned using a third hard mask pattern HM3 as an etching mask. A plurality of first sheet-like separation trenches SWT1 are formed by performing a first etching process on the first dielectric material layer DL1 exposed in the patterning result.

[0078] The first etching process may include a dry etching process. Due to the characteristics of the dry etching process, the multiple first sheet-like separating trenches SWT1 may each have a tapered shape with a downwardly decreasing horizontal width. Accordingly, the first dielectric material layer DL1 may be partially retained on the sidewalls of the stacked structure of multiple sacrificial layers SL and multiple nanosheets NS.

[0079] refer to Figure 9 By applying multiple first sheet-like dividing grooves SWT1 (see...) Figure 8 A second etching process is performed to form multiple second sheet-like separation trenches SWT2.

[0080] The second etching process may include a wet etching process. Due to the characteristics of the wet etching process, the first dielectric material layer DL1 retained on the sidewalls of the stacked structure of multiple sacrificial layers SL and multiple nanosheets NS can be removed. Therefore, the sidewalls of the stacked structure of multiple sacrificial layers SL and multiple nanosheets NS can be exposed in multiple second sheet-like separating trenches SWT2.

[0081] Accordingly, the second sheet-like separating groove SWT2 located on the left side of the figure can have a first groove width W1, while the second sheet-like separating groove SWT2 located on the right side of the figure can have a second groove width W2. The second groove width W2 can be greater than the first groove width W1.

[0082] This could be because multiple nanosheets NS are not formed on one side of the second sheet-like separating trench SWT2 located on the right side of the figure (the far right side of the figure), thus increasing the space available for forming the second sheet-like separating trench SWT2.

[0083] refer to Figure 10 It can remove the third hard mask pattern HM3 (see Figure 9 ), buffer layer BFL (see Figure 9 ) and the second hard mask pattern HM2 (see Figure 9 ).

[0084] Accordingly, the upper surface of the first hard mask pattern HM1 and the uppermost surface of the first dielectric material layer DL1 can be exposed. In some example embodiments, the upper surface of the first hard mask pattern HM1 and the uppermost surface of the first dielectric material layer DL1 may have the same vertical height.

[0085] Next, multiple second sheet-like separating grooves SWT2 can be added (see...) Figure 9 The inner wall of the sheet-like spacer SWL is conformally formed. The sheet-like spacer SWL can conformally cover portions of multiple first hard mask patterns HM1, multiple nanosheets NS, multiple sacrificial layers SL, first finned active regions FA1 and second finned active regions FA2, and the exposed surface of the first dielectric material layer DL1. Furthermore, the sheet-like spacer SWL may not fill the multiple second sheet-like spacer trenches SWT2 (see...). Figure 9 ).

[0086] In some example embodiments, the sheet spacer liner (SWL) may comprise silicon nitride. The sheet spacer liner (SWL) may be formed by, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD) processes.

[0087] Next, a sheet-like separator liner (SWL) can be formed and multiple second sheet-like separator grooves (SWT2) can be filled (see...). Figure 9 Each of the sheet-like partition walls SW in the first hard mask pattern HM1 and the first dielectric material layer DL1 may have the same vertical height.

[0088] The sheet-like separator wall SW may include a material that is etch-selective relative to the sheet-like separator pad SWL. In some example embodiments, the sheet-like separator wall SW may include a low-k dielectric material. The sheet-like separator wall SW may be formed, for example, by ALD, CVD, or PVD processes.

[0089] refer to Figure 11 The upper portion of the sheet-like separator SWL is partially removed. Accordingly, an upper groove SR can be formed that exposes the sidewalls of the first hard mask pattern HM1 and the sidewalls of the sheet-like separator SW. The upper groove SR can be defined by the remaining sheet-like separator SWL, the first hard mask pattern HM1, and the sidewalls of the sheet-like separator SW.

[0090] When forming the upper groove SR, due to the difference in etching selectivity between the materials forming the first hard mask pattern HM1 and the sheet partition wall SW and the material forming the sheet partition liner SWL, only the upper part of the sheet partition liner SWL can be removed.

[0091] In some example embodiments, the vertical height of the bottom surface of the upper groove SR may be higher than the vertical height of the lower surface of the first hard mask pattern HM1.

[0092] refer to Figure 12 By filling the groove SR (see Figure 11 A head SWH is formed. Correspondingly, a hammer-shaped sheet-like partition wall SW in which the head SWH and the main body SWB are integrated can be formed.

[0093] Accordingly, the sheet-like partition wall SW can be modified to include a main body SWB with a first width and a head SWH with a second width greater than the first width. That is, the sheet-like partition pad SWL can be disposed only on the sidewalls and lower surface of the main body SWB surrounding the sheet-like partition wall SW.

[0094] refer to Figure 13 The first hard mask pattern HM1 can be removed (see...). Figure 12 ).

[0095] Accordingly, the upper surface of the uppermost nanosheet NS, the sidewall of the first dielectric material layer DL1, the upper sidewall of the sheet-like separator SWL, and the sidewall of the head SWH of the sheet-like separator wall SW can be exposed.

[0096] refer to Figure 14 Remove the first dielectric material layer DL1 (see Figure 13 The upper part of the first dielectric material layer DL1 (see above) can be placed therein. Figure 13 The remainder of the structure forms a trench isolation STI.

[0097] In some example embodiments, the vertical height of the upper surface of the trench isolation STI may be lower than the vertical height of the upper surfaces of the first fin active region FA1 and the second fin active region FA2. For example, the first fin active region FA1 and the second fin active region FA2 may correspond to the portion of the substrate layer BSUB defined by the trench isolation STI.

[0098] refer to Figure 15 A second dielectric material layer DL2 is formed, which conformally covers the trench isolation STI, the sidewalls of the first fin active region FA1 and the second fin active region FA2, multiple sacrificial layers SL, multiple nanosheets NS, the sidewalls of the sheet-like separator liner SWL, and the head SWH of the sheet-like separator wall SW.

[0099] The second dielectric layer DL2 may include, for example, the same material as the trench isolation STI. In some example embodiments, the second dielectric layer DL2 may be used as a dummy gate dielectric film.

[0100] Let's refer to each other. Figure 16A and Figure 16B A dummy gate electrode DGE is formed, which covers the second dielectric material layer DL2 and the trench isolation STI.

[0101] In some example embodiments, the dummy gate electrode DGE may include polysilicon. That is, the second dielectric material layer DL2, which serves as the dummy gate dielectric film, can be completely covered by the dummy gate electrode DGE.

[0102] Let's refer to each other. Figure 17A and Figure 17B Remove the dummy gate electrode DGE from the source / drain region (the region of line B-B') of the dummy gate electrode DGE.

[0103] The dummy gate electrode DGE is removed, and the second dielectric layer DL2 and trench isolation STI are exposed in the source / drain region (the region of line B-B'). On the other hand, since the dummy gate electrode DGE is not removed in the gate region (the region of line A-A'), the second dielectric layer DL2 and trench isolation STI are not exposed in the gate region (the region of line A-A').

[0104] Let's refer to each other. Figure 18A and Figure 18B Remove the second dielectric material layer DL2 that is exposed in the source / drain region (the region of line B-B').

[0105] With the removal of the exposed second dielectric material layer DL2, multiple sacrificial layers SL, multiple nanosheets NS, the upper part of the sheet-like separator liner SWL, and the head SWH of the sheet-like separator wall SW are exposed.

[0106] Next, the upper part of the exposed sheet-like separator liner SWL and the head SWH of the sheet-like separator wall SW are removed. Accordingly, the uppermost surfaces of the multiple nanosheets NS, the uppermost surface of the sheet-like separator liner SWL, and the upper surface of the sheet-like separator wall SW can have the same or substantially the same vertical height.

[0107] Let's refer to each other. Figure 19A and Figure 19B A third dielectric material layer DL3 can be formed, which conformally covers the trench isolation STI, multiple sacrificial layers SL, multiple nanosheets NS, sheet-like spacer pads SWL and sheet-like spacer walls SW.

[0108] In some example embodiments, the third dielectric layer DL3 may include silicon nitride, silicon carbide, or silicon carbonitride. This is because the source / drain SD described below (see...) Figure 21A Spacers are formed on the sidewalls of the dielectric material, so the third dielectric material layer DL3 can be formed to a certain thickness.

[0109] Let's refer to each other. Figure 20A and Figure 20B The third dielectric material layer DL3 can be patterned, and a portion of the exposed multiple sacrificial layers SL, multiple exposed nanosheets NS, a portion of the exposed sheet-like separator SWL, a portion of the exposed sheet-like separator wall SW, and a portion of the exposed first fin active region FA1 and second fin active region FA2 can be removed.

[0110] Accordingly, multiple sacrificial layers SL and multiple nanosheets NS can be completely removed in the source / drain region (the region of line B-B'). In addition, the vertical height of the upper surface of the third dielectric material layer DL3, the upper surface of the sheet-like spacer SWL, the upper surface of the sheet-like spacer wall SW, and the upper surface of the first fin-type active region FA1 and the second fin-type active region FA2 can be reduced.

[0111] Let's refer to each other. Figure 21A and Figure 21B A first back electrode forming layer BS1, a second back electrode forming layer BS2, and a source / drain electrode SD can be sequentially formed on each upper surface of the first fin-type active region FA1 and the second fin-type active region FA2.

[0112] Multiple source / drain SDs may include an embedded SiGe structure, which includes multiple epitaxially grown SiGe layers, epitaxially grown silicon (Si) layers, or epitaxially grown SiC layers.

[0113] In some example embodiments, some of the multiple source / drain SDs may contain impurities of a different conductivity type than the others. The multiple nanosheets NS in contact with some of the multiple source / drain SDs may contain impurities of a different conductivity type than those in contact with the other multiple source / drain SDs.

[0114] Accordingly, for example, an n-type metal-oxide-semiconductor (NMOS) transistor can be formed in some of the multiple source / drain SDs, and a p-type metal-oxide-semiconductor (PMOS) transistor can be formed in other of the source / drain SDs.

[0115] The first back electrode forming layer BS1 may include the same material as the plurality of source / drain electrodes SD. For example, the SiGe layer in the first back electrode forming layer BS1 may have the same or substantially the same germanium (Ge) concentration as the SiGe layers in the plurality of source / drain electrodes SD.

[0116] The first back electrode forming layer BS1 may include a material different from that of the second back electrode forming layer BS2. For example, the SiGe layer in the first back electrode forming layer BS1 may have a different germanium (Ge) concentration than the SiGe layer in the second back electrode forming layer BS2.

[0117] Next, a fourth dielectric layer DL4 can be formed, which covers the third dielectric layer DL3, the sheet spacer SWL, the sheet partition wall SW, the first fin active region FA1 and the second fin active region FA2, and the source / drain electrode SD. The fourth dielectric layer DL4 may include, for example, the same material as the sheet spacer SWL.

[0118] Let's refer to each other. Figure 22A and Figure 22B This can form an interlayer dielectric film (ILD) covering the fourth dielectric material layer DL4.

[0119] Interlayer dielectric (ILD) films may include, for example, silicon oxide, or dielectric materials having a dielectric constant lower than that of silicon oxide. In some example embodiments, the ILD film may include a tetraethylsilicate (TEOS) film, and / or an ultra-low K (ULK) film having an ultra-low dielectric constant K of about or exactly 2.2 to about or exactly 2.4. ULK films may include, for example, SiOC films and / or SiCOH films.

[0120] Let's refer to each other. Figure 23A and Figure 23BThe upper part of the interlayer dielectric film (ILD) is partially removed, and the area above the removed ILD can be filled with the same material as the fourth dielectric material layer (DL4).

[0121] Accordingly, the fourth dielectric layer DL4 may have a shape surrounding the interlayer dielectric film ILD. In some example embodiments, the fourth dielectric layer DL4 may comprise silicon nitride. The added fourth dielectric layer DL4 may be integrally formed with the underlying fourth dielectric layer DL4, or an interface may be present between them.

[0122] Let's refer to each other. Figure 24A and Figure 24B The upper part of the fourth dielectric material layer DL4 is partially removed, and the area above the removed fourth dielectric material layer DL4 can be filled with the same material as the third dielectric material layer DL3.

[0123] Accordingly, the third dielectric layer DL3 may have a shape surrounding the fourth dielectric layer DL4. In some example embodiments, the third dielectric layer DL3 may include silicon nitride, silicon carbide, or silicon carbonitride. The added third dielectric layer DL3 may be integrally formed with the underlying third dielectric layer DL3, or an interface may be present between them.

[0124] Let's refer to each other. Figure 25A and Figure 25B Remove the dummy gate electrode DGE from the gate region (the region of line A-A') of the dummy gate electrode DGE.

[0125] The dummy gate electrode DGE is removed, and the second dielectric layer DL2 and trench isolation STI are exposed in the gate region (the region of line A-A'). On the other hand, due to the previously formed interlayer dielectric film ILD, the fourth dielectric layer DL4, and the third dielectric layer DL3, the second dielectric layer DL2 and trench isolation STI are not exposed in the source / drain region (the region of line B-B').

[0126] Let's refer to each other. Figure 26A and Figure 26B Remove the second dielectric material layer DL2 exposed in the gate region (the region of line A-A').

[0127] With the removal of the exposed second dielectric material layer DL2, multiple sacrificial layers SL, multiple nanosheets NS, the sidewalls of the sheet-like spacer SWL, and the head SWH of the sheet-like spacer wall SW are exposed in the gate region (the area of ​​line A-A').

[0128] Let's refer to each other. Figure 27A and Figure 27B Multiple sacrifice layers (SL) can be removed (see Figure 26A ).

[0129] Accordingly, multiple gate spaces GS can be formed between the fin-type active region FA and the lowest nanosheet NS among the multiple nanosheets NS, as well as between two nanosheets NS that are adjacent to each other in the vertical direction (Z direction) among the multiple nanosheets NS.

[0130] Let's refer to each other. Figure 28A and Figure 28B The sheet spacer pad SWL on the sidewall of the body SWB of the sheet spacer wall SW can be partially removed by multiple gate spaces GS (see Figure 27A ).

[0131] Accordingly, the body SWB of the sheet-like spacer wall SW within multiple gate spaces GS can be exposed. However, the sheet-like spacer pad SWL (see Figure 27A The bottom portion that is not removed but retained can form a padding pattern LP.

[0132] Let's refer to each other. Figure 29A and Figure 29B Multiple recessed spacers (IDTs) can be formed between multiple nanosheets (NS) and sheet-like separators (SW).

[0133] Accordingly, multiple recessed spacers IDT are arranged in a second horizontal direction (Y direction) from the sidewall of the main body SWB of the sheet-like partition wall SW to the sidewall of the multiple nanosheets NS facing the main body SWB, and are spaced apart from each other in the vertical direction (Z direction). Therefore, the sheet-like partition wall SW can have a recessed shape or a T-shaped shape.

[0134] Let's refer to each other. Figure 30A and Figure 30B After forming multiple recessed spacers (IDTs), a gate dielectric film (GOX) that conformally covers the exposed surface can be formed.

[0135] The gate dielectric film (GOX) may include silicon oxide, a high-k dielectric film, or a combination thereof. The high-k dielectric film may include a material having a dielectric constant higher than that of silicon oxide. For example, a high-k dielectric film may have a dielectric constant of about or exactly 10 to about or exactly 25. In some example embodiments, the high-k dielectric film may include a metal oxide or a metal nitride. For example, the gate dielectric film (GOX) may include HfO2, Al2O3, HfAlO3, Ta2O3, and / or TiO2.

[0136] Let's refer to each other. Figure 31A and Figure 31B After forming the gate dielectric film GOX, a first gate electrode forming layer GE1 and a second gate electrode forming layer GE2 can be formed to cover the exposed surface.

[0137] The first gate electrode forming layer GE1 and the second gate electrode forming layer GE2 can be formed by a metal gate replacement process. The first and second gate electrode forming layers GE1 and GE2 may include the first gate electrode forming layer GE1 and the second gate electrode forming layer GE2.

[0138] In some example embodiments, the first gate electrode forming layer GE1 and the second gate electrode forming layer GE2 may include a metal-containing layer for controlling the work function and a gap-filling metal-containing layer for filling the upper space of the metal-containing layer for controlling the work function. In some example embodiments, the first gate electrode forming layer GE1 and the second gate electrode forming layer GE2 may have a structure in which a metal nitride layer, a metal layer, a conductive capping layer, and a gap-filling metal layer are stacked sequentially on top of each other. In some example embodiments, the first gate electrode forming layer GE1 and the second gate electrode forming layer GE2 may include different materials.

[0139] Let's refer to each other. Figure 32A and Figure 32B The first gate electrode forming layer GE1 and the second gate electrode forming layer GE2 can be removed (see...). Figure 31A The upper part of the sheet-like partition wall SW is such that the head SWH of the sheet-like partition wall SW is at least partially exposed.

[0140] In some example embodiments, the gate dielectric film GOX may still be retained to surround the head SWH of the sheet-like separator wall SW during the removal process.

[0141] Accordingly, the first gate electrode forms layer GE1 (see...) Figure 31A The first gate electrodes GE11 and GE12 can be separated into a pair of first gate electrodes GE11 and GE12 that do not contact each other and are separated by a sheet-like partition wall SW. That is, the pair of first gate electrodes GE11 and GE12 can be electrically separated from each other.

[0142] In addition, a second gate electrode is formed in layer GE2 (see Figure 31A It can be separated into a single second gate electrode GE21 and a single electrode structure GE22, which are not in contact with each other and are separated by sheet-like partition walls SW.

[0143] In some example embodiments, the single electrode structure GE22 may not surround multiple nanosheets NS. That is, unlike the single second gate electrode GE21, the single electrode structure GE22 may not be used as a gate electrode.

[0144] Return to reference Figure 1 A gate capping layer (GCL) can be formed to cover multiple gate electrodes (GE) and multiple sheet-like partition walls (SW). Specifically, the gate capping layer (GCL) can cover the upper surface and part of the sidewalls of each head (SWH) of the multiple sheet-like partition walls (SW).

[0145] The integrated circuit device 10 according to some example embodiments can be manufactured using the above manufacturing process.

[0146] Figures 33 to 36 This is a cross-sectional view illustrating a method for manufacturing integrated circuit devices in process sequence according to some example embodiments.

[0147] The methods for forming most of the components involved in the manufacturing process described below are the same as those mentioned above. Figures 4 to 32B The methods described are basically the same or similar. Therefore, for ease of description, the focus will be on the differences from the manufacturing methods described above.

[0148] refer to Figure 33 The buffer layer BFL, the fifth hard mask pattern HM5, and the fourth hard mask pattern HM4 are patterned using the third hard mask pattern HM3 as an etching mask. Multiple third sheet-like separation trenches SWT3 are formed by partially performing an etching process on the first dielectric material layer DL1 exposed in the patterning result.

[0149] The etching process can include dry etching or wet etching. The fourth hard mask pattern HM4 and the fifth hard mask pattern HM5 can be partially etched using the etching process to form a cone with a decreasing horizontal width.

[0150] Furthermore, through this etching process, the sidewalls of the stacked structure of multiple sacrificial layers SL and multiple nanosheets NS can be exposed in multiple third sheet-like separating trenches SWT3.

[0151] Accordingly, the lower part of the third sheet-like dividing groove SWT3 located on the left side of the figure may have a first groove width W1, and the lower part of the third sheet-like dividing groove SWT3 located on the right side of the figure may have a second groove width W2. The second groove width W2 may be greater than the first groove width W1.

[0152] This could be because multiple nanosheets NS are not formed on one side of the third sheet-like separating trench SWT3 located on the right side of the figure (the far right side of the figure), thus increasing the space available for forming the third sheet-like separating trench SWT3.

[0153] refer to Figure 34 It can remove the third hard mask pattern HM3 (see Figure 33 ), buffer layer BFL (see Figure 33 ) and the fifth hard mask pattern HM5 (see Figure 33 ).

[0154] Accordingly, the upper surface of the fourth hard mask pattern HM4 and the uppermost surface of the first dielectric material layer DL1 can be exposed. In some example embodiments, the upper surface of the fourth hard mask pattern HM4 and the uppermost surface of the first dielectric material layer DL1 may have the same or substantially the same vertical height.

[0155] Next, multiple third-plate-shaped dividing grooves SWT3 can be added (see...) Figure 33 The inner wall of the structure is conformally formed with a sheet-like spacer SWL. The sheet-like spacer SWL can conformally cover portions of multiple fourth hard mask patterns HM4, multiple nanosheets NS, multiple sacrificial layers SL, the first fin active region FA1 and the second fin active region FA2, and the exposed surface of the first dielectric material layer DL1. Furthermore, the sheet-like spacer SWL may not fill the third sheet-like spacer trench SWT3 (see...). Figure 33 ).

[0156] Next, a sheet-like partition wall SW30 can be formed, which covers the sheet-like partition gasket SWL and fills a plurality of third sheet-like partition grooves SWT3 (see...). Figure 33 Each of the following. Accordingly, the upper surface of the sheet partition wall SW30, the uppermost surface of the sheet partition pad SWL, the upper surface of the fourth hard mask pattern HM4, and the uppermost surface of the first dielectric material layer DL1 may have the same or substantially the same vertical height.

[0157] refer to Figure 35 The upper part of the sheet-like separator liner SWL is partially removed. Accordingly, an upper groove SR can be formed that exposes the sidewalls of the fourth hard mask pattern HM4 and the sidewalls of the sheet-like separator SW30.

[0158] When forming the upper groove SR, due to the difference in etching selectivity between the materials forming the fourth hard mask pattern HM4 and the sheet partition wall SW30 and the material forming the sheet partition liner SWL, only the upper part of the sheet partition liner SWL can be removed.

[0159] In some example embodiments, the vertical height of the bottom surface of the upper groove SR may be higher than the vertical height of the lower surface of the fourth hard mask pattern HM4.

[0160] refer to Figure 36 By filling the groove SR (see Figure 35 A head SWH is formed. Correspondingly, a nail-shaped sheet partition wall SW30 in which the head SWH and the body SWB are integrated can be formed.

[0161] Accordingly, the sheet-like partition wall SW30 can be modified to include a main body SWB with a first width and a head SWH with a second width greater than the first width. That is, the head SWH of the sheet-like partition wall SW30 can have an inverted trapezoidal shape with a horizontal width decreasing downwards.

[0162] Return to reference Figure 3 The integrated circuit device 30 according to some example embodiments can be manufactured using the manufacturing process described above.

[0163] When the terms “approximately” or “substantially” are used in conjunction with numerical values ​​in this specification, it is intended to indicate that the relevant numerical value includes manufacturing or operational tolerances (e.g., ±10%) near said value. Furthermore, when the words “generally” and “substantially” are used in conjunction with geometry, it is intended not to require precision in the geometry, but rather a tolerance for that shape within the scope of this disclosure. Moreover, regardless of whether numerical values ​​or shapes are modified to “approximately” or “substantially”, it will be understood that these values ​​and shapes should be interpreted as including manufacturing or operational tolerances (e.g., ±10%) near said numerical values ​​or shapes.

[0164] Although the inventive concept has been specifically shown and described with reference to exemplary embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An integrated circuit device comprising: a base substrate layer including a pair of first fin-type active regions and a single second fin-type active region, each fin-type active region extending in a first horizontal direction and protruding in a vertical direction, the pair of first fin-type active regions and the single second fin-type active region being spaced apart from each other in a second horizontal direction intersecting the first horizontal direction; a first spacer pattern extending in the second horizontal direction between the pair of first fin-type active regions and in contact with opposite sidewalls of the pair of first fin-type active regions; a second spacer pattern extending in the second horizontal direction and in contact with one sidewall of the single second fin-type active region; a first sheet spacer wall on the first spacer pattern and including a main body having a first width and a head having a second width greater than the first width; a second sheet spacer wall on the second spacer pattern and including a main body having a third width and a head having a fourth width greater than the third width; a pair of first nanosheet stack structures each including a plurality of first nanosheets, the pair of first nanosheet stack structures being respectively over the pair of first fin-type active regions and spaced apart from each other in the second horizontal direction, the first sheet spacer wall being interposed between the pair of first nanosheet stack structures; a single second nanosheet stack structure including a plurality of second nanosheets, the second nanosheet stack structure being over the single second fin-type active region; a plurality of recessed spacers between the plurality of first nanosheets and the first sheet spacer wall and between the plurality of second nanosheets and the second sheet spacer wall; a pair of first gate electrodes respectively surrounding the pair of first nanosheet stack structures, the first sheet spacer wall being interposed between the pair of first gate electrodes; and a single second gate electrode surrounding the single second nanosheet stack structure.

2. The integrated circuit device of claim 1, wherein the first spacer pattern and the second spacer pattern each have a rectangular shape having a longer side in the second horizontal direction, a horizontal width of the first spacer pattern in the second horizontal direction is equal to the second width of the head of the first sheet spacer wall, and a horizontal width of the second spacer pattern in the second horizontal direction is equal to the fourth width of the head of the second sheet spacer wall.

3. The integrated circuit device of claim 1, wherein the first width of the main body of the first sheet spacer wall is less than the third width of the main body of the second sheet spacer wall, and the second width of the head of the first sheet spacer wall is less than the fourth width of the head of the second sheet spacer wall.

4. The integrated circuit device of claim 3, wherein the main body of each of the first sheet spacer wall and the second sheet spacer wall has a rectangular shape having a longer side in the vertical direction, and the head of each of the first sheet spacer wall and the second sheet spacer wall has a rectangular shape having a longer side in the second horizontal direction.

5. The integrated circuit device of claim 1, wherein a head portion of each of the first and second sheet-like partition walls has an inverted-trapezoidal shape with a horizontal width decreasing downward. an uppermost surface of each of the pair of first gate electrodes is lower in vertical height than an uppermost surface of the head portion of the first sheet-like partition wall, and higher in vertical height than a lowermost surface of the head portion of the first sheet-like partition wall.

6. The integrated circuit device of claim 1, wherein, a gate capping layer covering the pair of first gate electrodes and the single second gate electrode, 7. The integrated circuit device of claim 6, further comprising: wherein the gate capping layer covers an upper surface and a portion of a sidewall of the head portion of each of the first and second sheet-like partition walls. a vertical thickness of each of the plurality of first nanosheets and a vertical thickness of each of the plurality of second nanosheets are greater than a vertical thickness of each of the plurality of recessed spacers.

8. The integrated circuit device of claim 1, wherein, a gate dielectric film conformally surrounding the plurality of first nanosheets and the plurality of second nanosheets, the plurality of recessed spacers, and the first and second sheet-like partition walls, 9. The integrated circuit device of claim 8, further comprising: wherein the gate dielectric film covers an upper surface of the head portion of each of the first and second sheet-like partition walls. a gate dielectric film conformally surrounding the plurality of first nanosheets and the plurality of second nanosheets, the plurality of recessed spacers, and the first and second sheet-like partition walls, 10. The integrated circuit device of claim 8, further comprising: wherein an upper surface of the head portion of each of the first and second sheet-like partition walls is exposed through the gate dielectric film.

11. An integrated circuit device, comprising: a base substrate layer including a pair of fin-type active regions each extending in a first horizontal direction and protruding in a vertical direction, the pair of fin-type active regions being spaced apart from each other in a second horizontal direction intersecting the first horizontal direction; a spacer pattern extending along the second horizontal direction between the pair of fin-type active regions and in contact with opposite sidewalls of the pair of fin-type active regions; a sheet-like partition wall extending along the first horizontal direction over the spacer pattern and including a main body having a first width and a head portion having a second width greater than the first width; a pair of nanosheet stack structures each including a plurality of nanosheets, the pair of nanosheet stack structures being respectively over the pair of fin-type active regions and spaced apart from each other in the second horizontal direction, the sheet-like partition wall being interposed between the pair of nanosheet stack structures; a plurality of recessed spacers between the plurality of nanosheets and the sheet-like partition wall; and a pair of gate electrodes surrounding the pair of nanosheet stack structures and the plurality of recessed spacers, the sheet-like partition wall being interposed between the pair of gate electrodes.

12. The integrated circuit device of claim 11, wherein the main body of the sheet-like partition wall has a rectangular shape with longer sides in the vertical direction, ​ ​ The head of the spacer pattern and the head of the sheet-shaped spacer wall each have a rectangular shape having a longer side in the second horizontal direction, and a lower surface of the main body of the sheet-shaped spacer wall is in contact with an upper surface of the spacer pattern.

13. The integrated circuit device of claim 12, wherein a horizontal width of the spacer pattern in the second horizontal direction is equal to the second width of the head of the sheet-shaped spacer wall, and a vertical height of an uppermost surface of each of the pair of fin-shaped active regions is higher than a vertical height of an upper surface of the spacer pattern.

14. The integrated circuit device of claim 11, further comprising: a gate dielectric film conformally surrounding the plurality of nanosheets, the plurality of recessed spacers, and the sheet-shaped spacer wall.

15. The integrated circuit device of claim 14, further comprising: a gate capping layer covering the pair of gate electrodes, wherein a vertical height of a lowermost surface of the gate capping layer is lower than a vertical height of an uppermost surface of the head of the sheet-shaped spacer wall, and higher than a vertical height of a lowermost surface of the head of the sheet-shaped spacer wall, and the gate capping layer and the pair of gate electrodes cover the gate dielectric film.

16. An integrated circuit device, comprising: a base substrate layer including a fin-shaped active region extending in a first horizontal direction and protruding in a vertical direction; a spacer pattern in contact with one sidewall of the fin-shaped active region and extending in a second horizontal direction intersecting the first horizontal direction; a sheet-shaped spacer wall extending along the first horizontal direction over the spacer pattern and including a main body having a first width and a head having a second width greater than the first width; a nanosheet stack structure over the fin-shaped active region and including a plurality of nanosheets; a plurality of recessed spacers between the plurality of nanosheets and one sidewall of the sheet-shaped spacer wall; and a first gate electrode and a second gate electrode spaced apart from each other in the second horizontal direction, the sheet-shaped spacer wall being interposed between the first gate electrode and the second gate electrode, the first gate electrode surrounding the nanosheet stack structure, and the second gate electrode not surrounding the nanosheet stack structure.

17. The integrated circuit device of claim 16, wherein the main body of the sheet-shaped spacer wall has a rectangular shape having a longer side in the vertical direction, the head of the spacer pattern and the head of the sheet-shaped spacer wall each have a rectangular shape having a longer side in the second horizontal direction, and a lowermost surface of the main body of the sheet-shaped spacer wall is in contact with an uppermost surface of the spacer pattern.

18. The integrated circuit device of claim 17, wherein a horizontal width of the spacer pattern in the second horizontal direction is equal to the second width of the head of the sheet-shaped spacer wall, and a vertical height of an uppermost surface of the fin-shaped active region is higher than a vertical height of an upper surface of the spacer pattern.

19. The integrated circuit device of claim 16, further comprising: a gate dielectric film conformally surrounding the plurality of nanosheets, the plurality of recessed spacers, and the sheet-shaped spacer wall, wherein the gate dielectric film between the first gate electrode and the main body of the sheet-shaped spacer wall has a different shape than the gate dielectric film between the second gate electrode and the main body of the sheet-shaped spacer wall.

20. The integrated circuit device of claim 19, wherein The first gate electrode and the second gate electrode have different shapes, but their respective upper surfaces are at the same vertical height, The integrated circuit device further includes: a gate capping layer covering the first gate electrode and the second gate electrode, a lowermost surface of the gate capping layer is at a vertical height lower than that of an uppermost surface of the head of the sheet-like partition wall, and higher than that of a lowermost surface of the head of the sheet-like partition wall, and the gate capping layer and the first gate electrode and the second gate electrode cover the gate dielectric film.

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