Electronic device

Abstract

The invention provides an electronic device. The electronic device comprises a substrate, a first active layer, a second active layer, an insulating layer and a metal wire, the first active layer is disposed on the substrate and includes a first end. The second active layer is arranged on the substrate and comprises a second end, and the second end is adjacent to the first end. The insulating layer is disposed on the first active layer and the second active layer. And the metal wire is arranged on the insulating layer. In a section view, the insulating layer comprises a first opening, a part of the metal wire is arranged in the first opening and overlaps the first end, in a plan view, the first end is provided with an edge, and a part of the edge is arc-shaped and is located between the first opening and the second end.

Description

TECHNICAL FIELD

[0001] The present application relates to an electronic device, and more particularly to a display device with high resolution. BACKGROUND

[0002] As the resolution requirement of display devices is increasing, the layout space of a pixel in a display device is thus reduced. In this case, some processes of the display device can be affected due to the reduction of the layout space of the pixel, and thus the process yield of the display device is affected. Therefore, how to solve the above problems is still an important issue in the art. SUMMARY

[0003] The present application aims to provide an electronic device with high resolution, wherein a mask used in the process of the electronic device can have a specific design to reduce the possibility that some processes are affected due to the reduction of the layout space of the pixel.

[0004] The present application provides an electronic device, which includes a substrate, a first active layer, a second active layer, an insulating layer, and a metal line. The first active layer is disposed on the substrate and includes a first end. The second active layer is disposed on the substrate and includes a second end adjacent to the first end. The insulating layer is disposed on the first active layer and the second active layer. The metal line is disposed on the insulating layer. In a cross-sectional view, the insulating layer includes a first opening, a portion of the metal line is disposed in the first opening and overlaps the first end, and in a top view, the first end has an edge, a portion of the edge is arc-shaped and located between the first opening and the second end. BRIEF DESCRIPTION OF DRAWINGS

[0005] Figure 1 FIG. 1 is a top view of an electronic device according to a first embodiment of the present application.

[0006] Figure 2 FIG. 2 is a cross-sectional view of the electronic device according to the first embodiment of the present application.

[0007] Figure 3 FIG. 3 is a partial enlarged top view of the electronic device according to the first embodiment of the present application.

[0008] Figures 4 to 8 FIG. 4 is a partial enlarged top view of the electronic device according to a different variation of the first embodiment of the present application.

[0009] Figure 9 FIG. 5 is a top view of an electronic device according to a second embodiment of the present application.

[0010] Figure 10 FIG. 6 is a cross-sectional view of the electronic device according to the second embodiment of the present application.

[0011] Figure 11A top view schematic diagram of an electronic device according to a third embodiment of the present application.

[0012] Figure 12 A cross-sectional view schematic diagram of an electronic device according to a third embodiment of the present application.

[0013] Figure 13 A cross-sectional view schematic diagram of an electronic device according to a third embodiment of the present application.

[0014] Reference Signs: 100 - Display device; AL - Active layer; AL1 - First active layer; AL3 - Third active layer; BF - Buffer layer; CE1 - First light conversion element; CE2 - Second light conversion element; CE3 - Third light conversion element; CF - Light conversion layer; CL - Circuit layer; CR - Channel region; DL - Data line; DOE - Drain electrode; DR - Drain region; DR1 - First direction; DR2 - Second direction; DS1, DS2 - Minimum distance; DU - Driving unit; E1 - First end; E2 - Second end; E3 - Third end; ED - Electronic device; EE - End; EG, EG1, EG2, EO, EC - Edge; EL1, EL2, EL3 - Electrode; EP - End portion; GE, GE2 - Gate electrode; GS - Geometric center; IN3, IN4, IN5, IN2, IN1, IN6, IN7, IN8, INL - Insulating layer; L1, L2, L3 - Straight line; L2' - Oblique line; LC - Display medium layer; LS, BM - Light shielding layer; M2, M3, M4, M1, M5 - Conductive layer; ML - Metal line; MP - Main spacer; OC - Protection layer; OP1 - First opening; OPA, OPB, OPC - Opening; OSB - Opposite substrate; P1, P2, P3, P4, P5, P7, P8, P9, P10 - Point; PCL - Patterned conductive layer; PP, PO1, PO2 - Portion; PS - Position; PS1, PS2 - Spacer; SB - Substrate; SL - Scan line; AL2 - Second active layer; SOE - Source electrode; SP - Sub-spacer; SR - Source region; T1, T3, W1, W2, W3, W4, Z1, R1, R2 - Width; T2 - Pitch; V1 - Via hole; Y, X, Z - Direction; Y1, X1, Z2 - Distance; θ1 - Angle. DETAILED DESCRIPTION

[0015] The present application can be understood with reference to the following detailed description and drawings, in which it is noted that for the reader's convenience the drawings of the present application only depict a portion of the device and the specific elements in the drawings are not drawn according to the actual scale. In addition, the number and size of the elements in the drawings are only for illustration and are not intended to limit the scope of the present application.

[0016] Throughout this specification and in the claims, certain terminology will be used for describing particular elements. One of ordinary skill in the art will understand that a given element can be referred to by more than one name, depending on the context in which the given element is used. The present disclosure does not intend to distinguish between such elements that differ only in name, but not in function.

[0017] Throughout this specification and in the claims, the terms "comprises," "comprising," "includes," and "including" are to be construed as open-ended terms (i.e., meaning "includes, but is not limited to,") unless otherwise noted.

[0018] It will be understood that when an element or film layer is referred to as being "on" or "connected to" another element or film layer, it can be directly on or connected to the other element or film layer or intervening elements or film layers can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or film layer, there are no intervening elements or film layers present. When an element or film layer is referred to as being "electrically connected" to another element or film layer, it can be interpreted as being directly electrically connected or indirectly electrically connected. The electrically connected or coupled as described in the present disclosure can refer to direct connection or indirect connection, in the case of direct connection, the end points of two circuit components are directly connected or connected to each other by a conductor segment, and in the case of indirect connection, there are switches, diodes, capacitors, inductors, resistors, other suitable components, or combinations of the above components between the end points of the two circuit components, but not limited thereto.

[0019] Although the terms "first," "second," "third," etc. can be used in this disclosure to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. The terms "first," "second," "third," and so on are interchangeable under appropriate circumstances and embodiments of the application. Therefore, a first element discussed in the specification of the present disclosure can become a second element in the claims.

[0020] In the present disclosure, the measurement of thickness, length and width can be obtained by optical microscopy, and the thickness or width can be measured by cross-sectional images in electron microscopy, but not limited thereto.

[0021] In addition, there can be some error in any two values or directions used for comparison. The term "about" or "substantially" or "generally" is generally interpreted as within 10% of the given value, or within 5%, 3%, 2%, 1%, or 0.5% of the given value.

[0022] Further, the phrase "a given range from a first value to a second value" or "a given range falls within a range from a first value to a second value" means that the given range includes the first value, the second value, and other values therebetween.

[0023] If the first direction is perpendicular to the second direction, the angle between the first direction and the second direction can be between 80 degrees and 100 degrees; if the first direction is parallel to the second direction, the angle between the first direction and the second direction can be between 0 degrees and 10 degrees.

[0024] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an overly idealized or overly formal sense unless expressly so defined herein.

[0025] It is to be understood that the following examples can be substituted, reorganized, mixed, and so on, to complete other examples without departing from the spirit of the present application.

[0026] The electronic device of the present application can include a display device, a sensing device, a backlight device, an antenna device, a tiled device, a virtual reality product, or other suitable electronic device, but is not limited thereto. The electronic device of the present application can be a foldable, flexible, or stretchable electronic device. The display device can include a non-self-emissive display device or a self-emissive display device. The non-self-emissive display device includes, for example, a liquid crystal display device, but is not limited thereto. The self-emissive display device includes, for example, a light emitting diode display device, but is not limited thereto. The display device can be applied, for example, to a notebook computer, a public display, a tiled display, a vehicle display, a touch display, a television, a monitor, a smartphone, a tablet, a light source module, a lighting device, or an electronic device applied to the above products, but is not limited thereto. The sensing device can include a biosensor, a touch sensor, a fingerprint sensor, other suitable sensor, or a combination of the above types of sensors. The antenna device can include, for example, a liquid crystal antenna device, but is not limited thereto. The tiled device can include, for example, a display tiled device or an antenna tiled device, but is not limited thereto. The electronic device can have a rectangular, circular, polygonal, curved edge shape, or other suitable shape. The electronic device can include an electronic unit, wherein the electronic unit can include passive elements and active elements, such as capacitors, resistors, inductors, diodes, transistors, sensors, etc. The diode can include a light emitting diode or a photodiode. The light emitting diode can include, for example, an organic light emitting diode (OLED) or an in-organic light emitting diode, which can include, for example, a mini LED, a micro LED, or a quantum dot LED, but is not limited thereto. The electronic device can have a driving system, a control system, a light source system, or other peripheral systems to support the display device, the antenna device, a wearable device (including, for example, augmented reality or virtual reality), a vehicle-mounted device (including, for example, an automobile windshield), or a tiled device. Hereinafter, the present application will be described with reference to an electronic device including a display device, but the present application is not limited thereto. The electronic device of the present application can be various combinations of the above devices, such as a combination of a display device and other devices, but is not limited thereto.

[0027] Please refer to Figures 1 to 3 and Figure 13 , Figure 1 is a top view schematic diagram of an electronic device of a first embodiment of the present application, Figure 2 is a cross-sectional view schematic diagram of an electronic device of a first embodiment of the present application, Figure 3 is a partial enlarged top view schematic diagram of an electronic device of a first embodiment of the present application, Figure 13This is a cross-sectional schematic diagram of an electronic device according to a third embodiment of the present invention. For the sake of simplicity, the accompanying drawings are... Figures 1 to 3 Only some components or films of the electronic device ED are shown. It should be noted that... Figure 13 The structure of the third embodiment shown can be derived from the electronic device ED of the first embodiment, and can be applied to various embodiments of the present invention, i.e. Figure 1 The cross-sectional structure of the electronic device ED of the first embodiment shown can be referred to Figure 13 The structure shown. The electronic device ED of this embodiment may include a display device 100 (labeled as shown). Figure 13 The display device 100 is used to display images or videos. It may be a high-resolution display device, such as a virtual reality display device, but is not limited thereto. In some embodiments, the electronic device ED may include a combination of the display device 100 and other suitable electronic devices. Detailed structures of the electronic device ED (or display device 100) in this embodiment can be found, for example, in reference to... Figure 13 The structure shown. (As illustrated) Figure 13 As shown, an electronic device ED may include a substrate SB, a circuit layer CL, a light conversion layer CF, and a display medium layer LC. The circuit layer CL may be disposed on the substrate SB, the light conversion layer CF may be disposed on the circuit layer CL, and the display medium layer LC may be disposed on the light conversion layer CF. The structure of each component and film layer of the electronic device ED will be described in detail below.

[0028] The substrate SB can be used to support components and films located thereon. The substrate SB can comprise rigid or flexible materials. Rigid materials include, for example, glass, quartz, sapphire, ceramic, other suitable materials, or combinations thereof. Flexible materials include, for example, polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), other suitable materials, or combinations thereof. It should be noted that in some embodiments, the substrate SB may comprise a multilayer structure, and is not necessarily... Figure 13 The above is the limit.

[0029] The circuit layer CL may include various wires, circuits, and electronic units applicable to electronic devices ED. Electronic units may include any suitable active and / or passive components. The circuit layer CL may include any suitable structure formed by stacking conductive and insulating layers, wherein the conductive layers may be used to form the aforementioned wires, circuits, or electronic units, but are not limited thereto. Figure 1 For example, a partial structure of the circuit layer CL of an electronic device ED is shown. Figure 1As shown, the circuit layer CL may include a plurality of metal lines ML disposed on the substrate SB. The metal lines ML may include scan lines SL and data lines DL. In other words, the circuit layer CL includes a plurality of scan lines SL disposed on the substrate SB. Figure 1 (Only one is shown) and multiple data lines DL. Data lines DL may extend along a first direction DR1, while scan lines SL may extend along a second direction DR2, wherein the first direction DR1 is not parallel to the second direction DR2. For example, the first direction DR1 may be direction Y, and the second direction DR2 may be direction X, i.e., the first direction DR1 is perpendicular to the second direction DR2, but this is not a limitation. In some embodiments, the first direction DR1 is not perpendicular to the second direction DR2. In some embodiments, the first direction DR1 may be an oblique direction that is not parallel to directions X and Y (e.g., the angle between the oblique direction and directions X and Y is not 90 degrees), i.e., the data lines DL may extend in this oblique direction. It should be noted that, although... Figure 1 The scan line SL and data line DL shown are straight lines, but this embodiment is not limited thereto. In some embodiments, the data line DL may include any suitable pattern, such as (but not limited to) a zigzag pattern or an irregular pattern. In this case, the above-mentioned "data line DL extends along the first direction DR1" may refer to the fact that the pattern of the data line DL, even if not completely parallel to the first direction DR1, still tends to extend along the first direction DR1. Similarly, the above-mentioned "scan line SL extends along the second direction DR2" may refer to the fact that the pattern of the scan line SL tends to extend along the second direction DR2.

[0030] In this embodiment, the circuit layer CL may further include a driving unit DU. The driving unit DU may include, for example, a thin-film transistor (TFT) element, but is not limited thereto. Figure 13As shown, the driving unit DU may include an active layer AL, a gate electrode GE, a source electrode SOE, and a drain electrode DOE. Specifically, the circuit layer CL may include an active layer AL, a conductive layer M2, a conductive layer M3, and a conductive layer M4. The active layer AL may include a channel region CR, a source region SR, and a drain region DR, while the conductive layer M2 may form the gate electrode GE of the driving unit DU. The channel region CR may be defined as a portion of the active layer AL overlapping the gate electrode GE. The source region SR and the drain region DR may be defined as portions of the active layer AL located on either side of the channel region CR, respectively. The conductive layer M3 may form the source electrode SOE electrically connected to the source region SR. The conductive layer M4 may form the drain electrode DOE electrically connected to the drain region DR. The active layer AL may include a semiconductor material, which may include, but is not limited to, indium gallium zinc oxide (IGZO), amorphous indium gallium zinc tin oxide (a-IGZO), indium zinc oxide (IZO), amorphous indium-zinc-tin oxide (a-IZTO), zinc tin oxide (AZTO), indium gallium zinc oxide (IGO), or indium gallium zinc tin oxide (IGZTO). Conductive layers M2 and M3 may include any suitable conductive material, such as a metallic material, but are not limited to it. Conductive layer M4 may include any suitable conductive material, such as a metallic material or a transparent conductive material, but is not limited to it. Transparent conductive materials include, but are not limited to, indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), other suitable materials, or combinations thereof. The circuit layer CL may also include an insulating layer IN3 disposed between the active layer AL and the conductive layer M2, an insulating layer IN4 disposed between the conductive layer M2 and the conductive layer M3, and an insulating layer IN5 disposed between the conductive layer M3 and the conductive layer M4. Insulating layers IN3, IN4, and IN5 may comprise any suitable insulating material, such as organic or inorganic insulating materials. For example, insulating layers IN3, IN4, and IN5 may comprise silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiNxOy), polyimide (PI), polyester, other suitable materials, or combinations thereof.The materials for the insulating layers described below can be referenced from those described herein and will not be repeated hereafter. Insulating layer IN3 can be a gate insulating layer disposed between the active layer AL and the gate electrode GE. It should be noted that, although... Figure 13 The illustrated driving unit DU includes a top-gate thin-film transistor, but the invention is not limited thereto. In other embodiments, the driving unit DU may include a bottom-gate thin-film transistor, a dual-gate thin-film transistor, a multi-gate thin-film transistor, a dual-channel thin-film transistor, or other suitable types of thin-film transistors. In some embodiments, the circuit layer CL further includes a conductive layer M1 disposed between the conductive layer M2 and the substrate SB. In some embodiments, the conductive layer M1 may form a light-shielding layer LS, wherein the light-shielding layer LS may correspond to the active layer AL (or at least correspond to the channel region CR of the active layer AL). In some embodiments, the conductive layer M1 may serve as another gate electrode GE2 of the driving unit DU, i.e., the driving unit DU may include a dual-gate thin-film transistor in this case. The conductive layer M1 may include any suitable conductive material, such as a metallic material, but is not limited thereto. In some embodiments, the circuit layer CL further includes an insulating layer IN2 disposed between the conductive layer M1 and the active layer AL.

[0031] It should be noted that, Figure 13 The structure of the circuit layer CL shown is merely exemplary and is not intended to limit this embodiment. In some embodiments, the electronic device ED may further include a buffer layer BF disposed between the substrate SB and the circuit layer CL, and an insulating layer IN1 disposed between the buffer layer BF and the conductive layer M1, but is not limited thereto.

[0032] like Figure 13As shown, the electronic device ED may further include a light conversion layer CF disposed on the circuit layer CL. The light conversion layer CF may be directly disposed on the circuit layer CL, but is not limited thereto. In this case, the manufacturing method of the electronic device ED may include a color filter on array (COA) process. The light conversion layer CF may include any suitable element or film layer capable of changing the wavelength or color of light passing through the light conversion layer CF, such as a color filter, but is not limited thereto. In this embodiment, the light conversion layer CF may include multiple light conversion elements, wherein the multiple light conversion elements can allow light of different wavelengths or colors to pass through. For example, the light conversion layer CF may include a first light conversion element CE1, a second light conversion element CE2, and a third light conversion element CE3, wherein the multiple light conversion elements can respectively allow green light, red light, and blue light to pass through, and can mix to produce white light, but is not limited thereto. In some embodiments, the electronic device ED may further include an insulating layer IN6 disposed on the light conversion layer CF, wherein the insulating layer IN6 may serve as a planarization layer to facilitate the placement of other elements or film layers thereon.

[0033] In this embodiment, as Figure 13As shown, the electronic device ED may further include an electrode EL1, an insulating layer IN7 disposed on the electrode EL1, an electrode EL2 disposed on the insulating layer IN7, an insulating layer IN8 disposed on the electrode EL2, a conductive layer M5 disposed on the insulating layer IN8, and an electrode EL3 disposed on the conductive layer M5. Electrode EL1 may serve as a pixel electrode, extending into a via V1 and electrically connected to the conductive layer M4, thereby electrically connecting to the driving unit DU (or the drain electrode DOE of the driving unit DU). The via V1 may be formed by removing a portion of the light conversion layer CF and the insulating layer IN6. The insulating layer IN7 may fill the via V1 and cover the electrode EL1. The insulating layer IN7 may serve as a planarization layer to facilitate the deposition of other film layers (e.g., electrode EL2) thereon. Electrode EL2 may contact electrode EL1, thereby electrically connecting to electrode EL1. Electrodes EL1, EL2, and EL3 may comprise any suitable conductive material, such as transparent conductive materials, metallic materials, but are not limited thereto. Insulating layers IN6, IN7, and IN8 may comprise any suitable organic or inorganic insulating material. Conductive layer M5 may comprise any suitable conductive material, such as a metallic material, but is not limited thereto. In some embodiments, conductive layer M5 may comprise any suitable low-reflectivity metallic material to reduce glare from metal traces in the electronic device ED as observed by the user, or to reduce color mixing problems between adjacent light conversion elements. In some embodiments, conductive layer M5 may be disposed on electrode EL3, and conductive layer M5 may comprise, for example, molybdenum (Mo), chromium (Cr), tungsten (W), cobalt (Co), nickel (Ni), alloys of the above metals, or oxides of the above metals, but is not limited thereto. In some embodiments, conductive layer M5 may be replaced by a non-conductive material; in other words, conductive layer M5 may be, for example, black photoresist, black printing ink, black resin, organic resin, glass paste, but is not limited thereto.

[0034] In this embodiment, as Figure 13 As shown, the electronic device ED may further include a display medium layer LC located between the substrate SB and the opposing substrate OSB. For example, the display medium layer LC may be disposed between the electrode EL3 and the protective layer OC. In this embodiment, the display medium layer LC may include liquid crystal material, but is not limited thereto. In other words, the electronic device ED of this embodiment may include a liquid crystal display device. In other embodiments, the electronic device ED may include other types of display devices, such as light-emitting diode (LED) display devices, and the display medium layer LC may include LED elements, but is not limited thereto.

[0035] In this embodiment, as Figure 13As shown, the electronic device ED may also include a plurality of spacers PS1 and a plurality of spacers PS2. Spacers PS1 and PS2 may comprise any suitable photoresist material. Spacers PS1 may be disposed on the electrode EL3, but are not limited thereto. In a top view of the electronic device ED, spacers PS1 may cover the channel region CR of the active layer AL, but are not limited thereto. Furthermore, in a top view, spacers (e.g., spacers PS1 and PS2) may overlap the conductive layer M1. Specifically, the orthographic projection of spacer PS1 (or spacer PS2) on the substrate SB may fall completely on the orthographic projection of conductive layer M1 on the substrate SB. Spacers PS2 may be disposed corresponding to spacers PS1. In other words, each spacer PS2 may correspond to one of the spacers PS1. Specifically, the electronic device ED may also include a counter substrate OSB, and a plurality of spacers PS2 may be disposed on the counter substrate OSB. In detail, a light-shielding layer BM can first be formed on the opposing substrate OSB. The light-shielding layer BM can be formed at positions corresponding to spacers PS1 and / or PS2, but is not limited thereto. Then, a protective layer OC can be formed on the opposing substrate OSB to cover the light-shielding layer BM, and a plurality of spacers PS2 can be formed on the protective layer OC. Next, the substrate SB and the opposing substrate OSB can be assembled such that the plurality of spacers PS1 correspond to the plurality of spacers PS2 respectively. In this embodiment, the spacers PS2 may include a main spacer MP and a sub-spacer SP. The main spacer MP is the larger of the spacers PS2, and the sub-spacer SP is the smaller of the spacers PS2, that is, the size of the main spacer MP is larger than the size of the sub-spacer SP. The aforementioned "size of the spacer" may be, for example, the height, thickness, or area of ​​the spacer, but is not limited thereto. For example, in the normal direction (i.e., direction Z) of the electronic device ED, the height or thickness of the main spacer MP may be greater than the height or thickness of the sub-spacer SP. Alternatively, in a top view of the electronic device ED, the area of ​​the main spacer MP adjacent to the opposing substrate OSB may be greater than the area of ​​the sub-spacer SP adjacent to the opposing substrate OSB. The main spacer MP may correspond to a portion of the spacer PS1, and the sub-spacer SP may correspond to another portion of the spacer PS1. The main spacer MP may contact its corresponding spacer PS1, while there may be a gap between the sub-spacer SP and its corresponding spacer PS1, or the sub-spacer SP may not contact its corresponding spacer PS1. The material of the opposing substrate OSB may refer to the material of the substrate SB described above. The light-shielding layer BM may include any suitable light-shielding material; for example, the light-shielding layer BM may include black photoresist, black printing ink, black resin, organic resin, or glass paste.The structure of the light-shielding layer BM can be, for example, a black matrix layer, but is not limited thereto. In a top-view orientation, the light-shielding layer BM can overlap the channel region CR of the active layer AL, thereby shading the channel region CR in the top-view direction. Furthermore, although... Figure 13 The diagram illustrates a structure where the width of the light-shielding layer BM is greater than the width of spacers PS1 and / or PS2, but this embodiment is not limited thereto. In some embodiments, the width of the light-shielding layer BM may be less than the width of spacers PS1 and / or PS2. In some embodiments, the light-shielding layer BM may be disposed on the substrate SB (or on one side of the substrate SB), rather than on the opposing substrate OSB. The material of spacer PS1 may be the same as or different from the material of spacer PS2. The protective layer OC may include any element or film layer that can protect the electronic device ED.

[0036] It should be noted that the structure of the electronic device ED in this embodiment is not based on... Figure 13 The description is limited to what is shown. In some embodiments, the electronic device ED may also include other suitable elements and / or films.

[0037] Return to reference Figure 1 According to this embodiment, the circuit layer CL may include a plurality of driving units DU, wherein each driving unit DU may be electrically connected to a pixel electrode. Figure 1 Not shown, i.e. Figure 13 The electrode EL1 is shown. In this case, the circuit layer CL may include a plurality of active layers AL disposed on the substrate SB. In this embodiment, the plurality of active layers AL in the circuit layer CL may be arranged in an array, but are not limited thereto. For example, as Figure 1 As shown, a plurality of active layers AL may include a first active layer AL1, a second active layer AL2, and a third active layer AL3, wherein the first active layer AL1 and the second active layer AL2 can be considered as side by side along the Y direction, and the first active layer AL1 and the third active layer AL3 can be considered as side by side along the X direction, but are not limited thereto. Different active layers AL may include the same or different materials. For example, the material of the first active layer AL1 may be the same as or different from the material of the second active layer AL2. The data line DL may be formed by a conductive layer M3 (such as...). Figure 2 As shown), a portion of the data line DL can be electrically connected to the source region SR of the active layer AL of the drive unit DU, thereby forming a source electrode SOE electrically connected to the source region SR. For example, in Figure 1In this embodiment, one data line DL can be electrically connected to the source region SR of the first active layer AL1 through an opening OPA, while another data line DL can be electrically connected to the source region SR of the third active layer AL3 through another opening OPA. In the top view direction (i.e., parallel to direction Z) of the electronic device ED, the opening OPA can at least partially overlap the source region SR. Furthermore, in this embodiment, one data line DL can be electrically connected to a plurality of active layers AL arranged along direction Y. For example, one data line DL can be electrically connected to the first active layer AL1 through an opening OPA, while although... Figure 1 Not shown, the data line DL can also be electrically connected to the second active layer AL2 through another opening OPA. For example... Figure 13 As shown, insulating layer IN4 and / or insulating layer IN3 may surround opening OPA, which may be formed by removing portions of insulating layer IN4 and insulating layer IN3, but is not limited thereto. In this case, opening OPA may expose at least a portion of active layer AL. In some embodiments, Figure 13 The insulating layer IN3 shown can be a patterned film layer and is only provided corresponding to the gate electrode GE. In this case, the opening OPA can be formed by removing a portion of the insulating layer IN4. The scan line SL can be formed by the conductive layer M2. Specifically, a portion of the scan line SL overlapping the active layer AL can serve as the gate electrode GE. That is, the gate electrode GE can be electrically connected to the scan line SL. In other words, a portion of the active layer AL corresponding to the scan line SL can be defined as the channel region CR, and the portions located at both ends of the channel region CR can be defined as the source region SR and the drain region DR, respectively. Furthermore, as Figure 13 As shown, the conductive layer M4 can be electrically connected to the drain region DR of the active layer AL through the opening OPB. In this case, the opening OPB can at least partially overlap the drain region DR in the top view of the electronic device ED. Figure 1 The diagram shows the opening OPB, but the conductive layer M4 is not shown. It should be noted that... Figure 1 The example shows a structure including an opening OPA and an opening OPB, but the positional design of the openings OPA and OPB is not based on... Figure 1 The above is for reference only. Details regarding the placement of openings OPA and OPB can be found in [reference needed]. Figure 3 And the following explanation.

[0038] As described above, the electronic device ED may include a high-resolution display device 100. The "high-resolution display device 100" as used in this invention can be defined as follows: [e.g., ...] Figure 1As shown, in a top-down view (or in the Z direction), the data line DL can have a width T1, adjacent data lines DL have a spacing T2, and the active layer AL can have a width T3. Width T1 can be defined as the maximum width of the data line DL measured in a direction perpendicular to its extension direction (i.e., the first direction DR1) (i.e., the second direction DR2). In this case, spacing T2 can be defined as the spacing between adjacent data lines DL on the same side (…). Figure 1 The maximum distance (e.g., the left side, but not limited thereto) in the second direction DR2, and the width T3 of the active layer AL can be defined as the maximum width of the active layer AL in the second direction DR2, but not limited thereto. In other words, the width T1, the spacing T2, and the width T3 can be defined in the same direction (i.e., a direction perpendicular to the extension direction of the data line DL). In this embodiment, the electronic device ED may include a plurality of sub-pixels, the region of which can be defined as the region enclosed by the intersection of two adjacent scan lines SL and two adjacent data lines DL. A sub-pixel may, for example, include a light conversion element (i.e., Figure 13 The first light conversion element CE1, the second light conversion element CE2, and the third light conversion element CE3 shown herein, and the driving unit DU (which may be one or more) for driving the portion of the display medium layer LC corresponding to the light conversion element. In this case, the spacing T2 between the two adjacent data lines DL can also be regarded as the width of a sub-pixel in the direction X. According to the present invention, the ratio of width T1 to spacing T2 can range from 0.01 to 0.125 (i.e., 0.01 ≤ T1 / T2 ≤ 0.125), and the ratio of width T1 to width T3 can range from 0.01 to 0.2 (i.e., 0.01 ≤ T1 / T3 ≤ 0.2). Specifically, in the present invention, when the width T1, spacing T2, and width T3 of the data lines DL in the circuit layer CL satisfy the above relationships, the electronic device ED including the circuit layer CL can be regarded as a display device with high resolution.

[0039] Please refer to Figure 1According to the present invention, the plurality of active layers AL in the circuit layer CL may include a first active layer AL1 and a second active layer AL2, wherein the second active layer AL2 is adjacent to the first active layer AL1, or in other words, the first active layer AL1 and the second active layer AL2 are two adjacent active layers AL. Here, "the first active layer AL1 is adjacent to the second active layer AL2" can mean that the first active layer AL1 and the second active layer AL2 are two active layers AL arranged sequentially along an arrangement direction, where "arrangement direction" can refer to the arrangement direction of the aforementioned plurality of active layers AL, such as direction X or direction Y, or a direction perpendicular to the extension direction of the scan line SL or a direction parallel to the extension direction of the scan line SL. In other words, in this embodiment, two active layers AL arranged sequentially along direction X (or direction Y) can be regarded as two adjacent active layers AL. For example, in Figure 1 In this context, the first active layer AL1 and the second active layer AL2 are two active layers AL arranged sequentially along the Y direction. Therefore, the first active layer AL1 and the second active layer AL2 can be defined as being adjacent to each other, but this is not a limitation. In some embodiments, the third active layer AL3, which is arranged sequentially along the X direction, and the first active layer AL1 can be regarded as two active layers AL that are adjacent to each other. When "one active layer AL is adjacent to another active layer AL" is mentioned below, its definition can be referred to above, so it will not be repeated here.

[0040] According to the present invention, a first active layer AL1 may include a first end E1, and a second active layer AL2 adjacent to the first active layer AL1 may include a second end E2, wherein the second end E2 of the second active layer AL2 is adjacent to the first end E1 of the first active layer AL1. Specifically, in the present invention, an active layer AL may include a channel region CR and ends EE respectively located on both sides of the channel region CR. More specifically, as... Figure 1 As shown, the portion of the active layer AL corresponding to the scan line SL can first be defined as the channel region CR. Then, a portion of the active layer AL on one side of the channel region CR can be considered as one end EE, and the other portion of the active layer AL on the other side of the channel region CR can be considered as the other end EE. In this case, one end EE of the active layer AL can be the source region SR, and the other end EE of the active layer AL can be the drain region DR. After defining the two ends EE of the active layer AL, one end EE of another active layer AL that is closer to the active layer AL and the other end EE of another active layer AL that is closer to the active layer AL can be considered as two adjacent ends EE, namely the first end E1 and the second end E2 mentioned above. One of the first end E1 and the second end E2 can be the source region SR, and the other can be the drain region DR. Figure 1As shown in the example, the end EE of the second active layer AL2, which is closer to the first active layer AL1, can be the first end E1, and the end EE of the second active layer AL2, which is closer to the first active layer AL1, can be the second end E2, wherein the second end is adjacent to the first end E1. In this case, the first end E1 of the first active layer AL1 can be the source region SR of the first active layer AL1, that is, the first end E1 of the first active layer AL1 can be electrically connected to the data line DL, and can at least partially overlap with the data line DL in the top view of the electronic device ED; the second end E2 of the second active layer AL2 can be the drain region DR of the second active layer AL2, that is, the second end E2 of the second active layer AL2 can be electrically connected to the conductive layer M4, and can at least partially overlap with the conductive layer M4 in the top view of the electronic device ED. In addition, in the top view, the second end E2 of the second active layer AL2 can be separated from the metal line ML. Specifically, in the top view of the electronic device ED, the second end E2 of the second active layer AL2 may not overlap with the data line DL and / or the scan line SL. It should be noted that the aforementioned first end E1 and the second end E2 adjacent to the first end E1 can be defined in any two adjacent active layers AL, and are not limited to... Figure 1 The first active layer AL1 and the second active layer AL2 shown are limited to this. Specifically, after defining two adjacent active layers AL in the above manner, a source region SR and a drain region DR that are adjacent to each other in the two active layers AL can be defined as the first end E1 and the second end E2.

[0041] Furthermore, in this embodiment, one end EE of the active layer AL may have an edge EG, wherein the edge EG can be defined as a portion of the edge of the active layer AL corresponding to that end EE. For example, as Figure 1 As shown, the first end E1 of the first active layer AL1 may have an edge EG1 ( Figure 1 (shown in thick lines), and the second end E2 of the second active layer AL2 may have an edge EG2 ( Figure 1 (shown in thick lines).

[0042] Please refer to Figure 3 , Figure 3 for Figure 1The diagram shows an enlarged view of a portion of the PP in the top-view structure. According to the present invention, in the top view, a portion of the first end E1 of the first active layer AL1 (e.g., the end portion of the first end E1) may extend in the direction of extension of the data line DL (i.e., the first direction DR1, for example, direction Y) and exceed the edge EO of the first opening OP1 (or opening OPA) for electrically connecting the data line DL to the source region SR of the first active layer AL1; or, in other words, a portion of the first end E1 may extend in the direction Y and protrude beyond the edge EO of the first opening OP1. Here, "edge EO of the first opening OP1" may refer to the edge of the shape of the bottom or top contour of the first opening OP1 in the top-view direction of the electronic device ED. Furthermore, "a portion of the first end E1 exceeding (or protruding) from the first opening OP1" may refer to the situation where a portion of the first end E1 extends from inside the first opening OP1 to outside the first opening OP1. For example, the first end E1 may extend from the area exposed by the first opening OP1 to the area not exposed by the first opening OP1. When the following text mentions "a portion of the first end E1 extends (or protrudes)," the definition can be referred to here, and therefore will not be repeated. In this case, in top view, the first end E1 of the first active layer AL1 may have an edge EG1, wherein a portion of the edge EG1 may be arc-shaped and located between the first opening OP1 and the second end E2 of the second active layer AL2. Here, "a portion of the edge EG1 is arc-shaped" can mean that this portion of the edge EG1 includes an arc-shaped line segment. According to the present invention, the above-mentioned "edge EG1 is located between the first opening OP1 and the second end E2" can be defined in the following way. First, a virtual straight line (i.e., straight line L1) can be defined, which connects a point P1 on the edge EO of the first opening OP1 and a point P2 on the edge EG2 of the second end E2, wherein the distance between points P1 and P2 is the minimum distance between the edge EO and the edge EG2 (e.g., ...). Figure 3 As shown in the diagram, in this case, the virtual straight line will pass through a point (e.g., point P5) on the edge EG1 of the first end E1, which is contained within the arcuate portion of the edge EG1, but is not limited thereto. It should be noted that in other embodiments, the first end E1 may include a portion of any suitable non-linear shape, and is not limited to the arcuate shape described above.

[0043] In short, according to the present invention, the electronic device ED may include a first active layer AL1 disposed on a substrate SB and a second active layer AL2 adjacent to the first active layer AL1, wherein the first active layer AL1 and the second active layer AL2 respectively include a first end E1 and a second end E2 adjacent to the first end E1. The electronic device ED also includes an insulating layer disposed on the first active layer AL1 and the second active layer AL2, wherein the "insulating layer" herein may include a single-layer structure or a multi-layer structure. For example, the "insulating layer" herein may include... Figure 13The insulating layers IN3 and IN4 shown, but not limited thereto. In some embodiments, the "insulating layer" may only include the insulating layer IN4. The electronic device ED further includes a metal line ML, i.e., a data line DL, disposed on the above-mentioned insulating layer. In a cross-sectional view (such as Figure 13 shown), a part of the metal line ML (i.e., the data line DL) is disposed in the first opening OP1 and overlaps the first end E1. In a top view (such as Figure 3 shown), the first end E1 has an edge EG1, where a part of the edge EG1 is arc-shaped and is located between the first opening OP1 and the second end E2. In other words, the arc-shaped part of the edge EG1, the first opening OP1, and the second end E2 may respectively have a positive projection on the substrate SB, and the positive projection of the arc-shaped part of the edge EG1 may be located between the positive projection of the first opening OP1 and the positive projection of the second end E2. It should be noted that the above features can be applied to the first end E1 and the second end E2 defined by any two adjacent active layers AL.

[0044] As described above, a part of the first end E1 may extend in the extending direction of the data line DL (i.e., the first direction DR1) and protrude beyond the edge EO of the first opening OP1 in a top view. According to the present invention, as Figure 3 shown, in a top view, this part of the first end E1 may protrude beyond the first opening OP1 in the first direction DR1, or rather, beyond the edge EO of the first opening OP1. The part of the first end E1 and the first opening OP1 may have a distance Y1 in the first direction DR1, where the distance Y1 may be less than 2 micrometers (μm) (i.e., Y1 < 2 μm). Specifically, the distance Y1 is greater than 0 and less than 2 μm (i.e., 0 < Y1 < 2 μm), but not limited thereto. In some embodiments, the distance Y1 is greater than 0.5 μm and less than 2 μm (i.e., 0.5 μm < Y1 < 2 μm). In some embodiments, the distance Y1 is greater than 1 μm and less than 2 μm (i.e., 1 μm < Y1 < 2 μm). According to the present invention, the distance Y1 can be defined in the following manner. First, the geometric center GS of the shape of the first opening OP1 in a top view can be confirmed, and a straight line L2 passing through the geometric center GS of the first opening OP1 and extending along the first direction DR1 can be defined. The straight line L2 can pass through a point P3 on the edge EO of the first opening OP1 and a point P4 on the edge EG1 of the first end E1. In this case, the distance Y1 can be the straight-line distance between the point P3 and the point P4. That is, the distance Y1 is the distance measured in the first direction DR1. In other embodiments, the distance Y1 can be defined by other suitable methods and is not limited to the above method. In the present invention, the part of the first end E1 protruding beyond the first opening OP1 can have any suitable shape such that the distance Y1 satisfies the above conditions and is not limited to Figure 3The shape shown is for reference only. Distance Y1 can also be considered as the distance by which the first end E1 protrudes beyond the first opening OP1 in a top view. Distance Y1 can be used to indicate the degree to which the first end E1 protrudes beyond the first opening OP1, wherein as distance Y1 increases, the proportion of the first end E1 that protrudes beyond the first opening OP1 will increase.

[0045] Figure 2 It also shows the characteristics of distance Y1. In detail, Figure 2 It shows Figure 1 The diagram shows a cross-sectional view of the structure along tangent A-A'. For simplicity, the accompanying drawings are provided. Figure 2 Only a portion of the film layers and components of the electronic device ED are shown. Specifically, Figure 2 The cross-sectional structure shown can be a cross-sectional structure of the electronic device ED along the tangent A-A' parallel to the extension direction of the data line DL (i.e., the first direction DR1). For example... Figure 2 As shown, the data line DL can be electrically connected to the source region SR of the first active layer AL1 through the first opening OP1 passing through the insulating layer INL. In some embodiments, the insulating layer INL includes... Figure 13 The insulating layers IN3 and IN4 shown, i.e., insulating layer INL, are composite film layers. In some embodiments, insulating layer INL is... Figure 13 The insulating layer IN4 is shown. (As shown) Figure 2 As shown, the first end E1 of the first active layer AL1 and the first opening OP1 can have a distance Y1 in the first direction DR1, where the range of distance Y1 can be referred to above. It should be noted that, although... Figure 2 The intermediate distance Y1 is the distance between the edge of the bottom contour of the first opening OP1 and the edge EG1 of the first end E1 in the first direction DR1, but the present invention is not limited thereto. In some embodiments, the distance Y1 may be the distance between the edge of the top contour of the first opening OP1 and the edge EG1 of the first end E1 in the first direction DR1.

[0046] According to this embodiment, by making the first end E1 of the first active layer AL1 protrude beyond the first opening OP1 in the extension direction of the data line DL, and making the distance Y1 fall within the aforementioned range, the situation where the data line DL is broken due to the setting range of the first opening OP1 exceeding the active layer AL can be reduced while minimizing the impact on the pixel layout space, thereby improving the process yield of the electronic device ED. Specifically, in general high-resolution display devices, due to the limited pixel layout space, when forming an opening on the insulating layer using a photomask, part of the photomask may fall outside the active layer in the top view direction of the display device. Consequently, during exposure, the insulating layer located below the active layer is also removed, meaning that part of the opening is also formed by removing a portion of the insulating layer below the active layer, thus creating a deep trench. In this case, subsequent placement of data lines in the opening may lead to breakage of the data lines, thereby affecting the process yield of the display device. On the other hand, in this invention, after confirming the position of the photomask used to form the first opening OP1, the first active layer AL1 can be made to protrude beyond the photomask by compensating for it (for example, the first active layer AL1 can protrude beyond the photomask by a distance Y1 in top view, but this is not a limitation), thereby reducing the aforementioned process problems of the opening. In other words, the aforementioned distance Y1 can also be called the compensation distance of the first active layer AL1, used to reduce the situation where a portion of the first opening OP1 falls outside the first active layer AL1, thus causing the data line DL located within the first opening OP1 to break. Furthermore, the compensation direction of the first active layer AL1 can be defined as the first direction DR1, or in other words, the first active layer AL1 can be compensated towards the first direction DR1. Thus, the electronic device ED of this invention can have improved product yield even with high resolution. It should be noted that the aforementioned feature of distance Y1 can be applied to any active layer AL, and is not limited to the first active layer AL1.

[0047] like Figure 3As shown, in some embodiments, in top view, a minimum distance DS1 may exist between the first end E1 of the first active layer AL1 and the second end E2 of the second active layer AL2, wherein the minimum distance DS1 may be greater than or equal to 0.5 μm (i.e., 0.5 μm ≤ DS1). Specifically, the minimum distance DS1 may be greater than or equal to 0.5 μm and less than or equal to 1 millimeter (mm) (i.e., 0.5 μm ≤ DS1 ≤ 1 mm), but is not limited thereto. In some embodiments, the minimum distance DS1 may be greater than or equal to 0.5 μm and less than or equal to 0.5 mm (i.e., 0.5 μm ≤ DS1 ≤ 0.5 mm). In some embodiments, the minimum distance DS1 may be greater than or equal to 0.5 μm and less than or equal to 0.2 mm (i.e., 0.5 μm ≤ DS1 ≤ 0.2 mm). In this embodiment, the minimum distance DS1 can be defined by any point on the edge EG1 of the first end E1 and any point on the edge EG2 of the second end E2. Specifically, after taking any point on the edge EG1 of the first end E1 and any point on the edge EG2 of the second end E2, a straight-line distance can be defined between these two points. Then, by taking multiple points on the edge EG1 of the first end E1 and multiple points on the edge EG2 of the second end E2 to define multiple straight-line distances, the smallest of these multiple straight-line distances can be defined as the aforementioned minimum distance DS1. For example, as... Figure 3 As shown, the distance between point P5 on the edge EG1 of the first end E1 and point P2 on the edge EG2 of the second end E2 can be the smallest of the plurality of distances defined by the plurality of points on the edge EG1 of the first end E1 and the plurality of points on the edge EG2 of the second end E2. Therefore, the distance between point P5 and point P2 can be the aforementioned minimum distance DS1. It should be noted that the feature of the aforementioned minimum distance DS1 can be applied to the first end E1 and the second end E2 defined by any two adjacent active layers AL. In some embodiments, the first active layer AL1 and the second active layer AL2 (or other active layers AL) can be located in the same layer; in other embodiments, the first active layer AL1 and the second active layer AL2 (or other active layers AL) can be located in different layers. It should be noted that regardless of whether the first active layer AL1 and the second active layer AL2 are located in the same layer, the aforementioned minimum distance DS1 can be obtained by measuring the first active layer AL1 and the second active layer AL2 after observing them in a top-down direction.

[0048] In this embodiment, as Figure 3 As shown, the first opening OP1 may be aligned with the edge EG1 of the first end E1 of the first active layer AL1 in the X direction, but is not limited thereto. In some embodiments, the first opening OP1 may be recessed relative to the edge EG1 in the X direction. In some embodiments, the first opening OP1 may extend and protrude (or exceed) the edge EG1 in the X direction (e.g., Figure 6(As shown). Furthermore, in this embodiment, in top view, the second end E2 of the second active layer AL2 may at least partially overlap with the opening OPB, i.e., the opening OPB does not completely overlap the second end E2, but this is not a limitation. In other embodiments (e.g.) Figure 7 or Figure 8 The second end E2 can completely overlap the opening OPB when viewed from above, or in other words, the setting range of the second end E2 covers the setting range of the opening OPB.

[0049] Please refer to Figures 4 to 8 , Figures 4 to 8 This is a partially enlarged top view schematic diagram of an electronic device according to different variations of the first embodiment of the present invention. Specifically, Figures 4 to 8 Different designs of the first end E1, the second end E2, the first opening OP1, and the opening OPB in this embodiment are shown.

[0050] like Figure 4 As shown, in this variation embodiment, the extension direction DR1 of the data line DL can be an oblique direction that is not parallel to directions X and Y. In this case, a portion of the first end E1 of the first active layer AL1 can extend in this oblique direction and beyond the first opening OP1 in a top view. In other words, the compensation direction of the first active layer AL1 can be the oblique first direction DR1. Thus, in a top view, an oblique line L2' can be defined first, passing through the geometric center GS of the first opening OP1 and extending along the first direction DR1. The intersection point (point P3) of the oblique line L2' with the edge EO of the first opening OP1 and the intersection point (point P4) of the oblique line L2' with the edge EG1 of the first end E1 are identified. The distance between points P3 and P4 in the first direction DR1 is the aforementioned distance Y1. The portion of the first end E1 protruding from the first opening OP1 can have any suitable shape such that the distance Y1 satisfies the above conditions. The features of the second end E2 and the opening OPB in this variation embodiment can be referred to above, and will not be repeated here.

[0051] like Figure 5As shown, in this variant embodiment, the first active layer AL1 can compensate in directions other than parallel to the extension direction DR1 of the data line DL. In this case, a distance X1 between the edge EO of the first opening OP1 and the edge EG1 of the first end E1 can be defined in the following way, wherein the distance X1 can be defined in a direction that is not parallel to the first direction DR1. First, a straight line L2 extending along the first direction DR1 through the geometric center GS of the first opening OP1 can be defined. Then, another straight line L3 passing through the geometric center GS of the first opening OP1 and having an angle θ1 between it and the straight line L2 can be defined, wherein the angle θ1 can range from 20 degrees to 80 degrees (i.e., 20°≤θ1≤80°). Specifically, a value of the angle θ1 can be selected from the range of 20 degrees to 80 degrees, and the aforementioned straight line L3 can be defined based on this value. After defining line L3, line L3 may intersect the edge EO of the first opening OP1 at point P7, and line L3 may intersect the edge EG1 of the first end E1 at point P8. The length of the line segment of line L3 between points P7 and P8 can be defined as the aforementioned distance X1. According to this variant embodiment, distance X1 may be less than 1 μm and greater than or equal to 0 μm (i.e., 0 μm ≤ X1 < 1 μm), but is not limited thereto. In some embodiments, distance X1 may be less than 0.9 μm and greater than or equal to 0 μm (i.e., 0 μm ≤ X1 < 0.9 μm). In some embodiments, distance X1 may be less than 0.8 μm and greater than or equal to 0 μm (i.e., 0 μm ≤ X1 < 0.8 μm). If distance X1 is greater than 1 μm, it may limit the layout space of other active layers AL (e.g., the second active layer AL2) adjacent to the first active layer AL1. In other words, the portion of the first end E1 that extends (or protrudes) from the first opening OP1 can have any suitable shape such that distance X1 falls within the aforementioned range. By compensating the first active layer AL1 in directions other than parallel to the first direction DR1, the increased impedance between the data line DL and the first active layer AL1 due to reduced contact area can be reduced. The above definition and range of distance X1 can be applied to other active layers AL. Furthermore, in this variation embodiment, as... Figure 5 As shown, the pattern of the second active layer AL2 adjacent to the first active layer AL1 can be designed to increase the minimum distance DS1 between the first active layer AL1 and the second active layer AL2, for example, to make the minimum distance DS1 at least greater than or equal to 0.5 μm, in cases where the first active layer AL1 is compensated in a direction other than parallel to the first direction DR1. This reduces the possibility of the first active layer AL1 and the second active layer AL2 being connected during the manufacturing process of the electronic device ED, thus affecting the process yield. For example, in this variant embodiment, the position of the pattern of the second terminal E2 adjacent to the first active layer AL1 (e.g., Figure 5The part at the position PS shown is subjected to corner cutting, so that the width of the end portion of the second end E2 adjacent to the end of the first active layer AL1 can be smaller than the width of other portions of the second end E2, but not limited thereto. In other words, by at least removing (or cutting off) the portion of the second end E2 adjacent to the corner of the first active layer AL1, the minimum distance DS1 can be increased, or in other words, space for the first active layer AL1 to extend in other directions can be provided. It should be noted that in another embodiment, the active layer AL can be compensated simultaneously in the Figure 3 and Figure 5 shown compensation methods.

[0052] According to the present invention, the first end E1 of the first active layer AL1 can have a width W1, and the first opening OP1 can have a width W2. The width W1 can be the width of a part of the first end E1 extending along the extension direction of the data line DL (i.e., the first direction DR1). Specifically, in a top view, the width W1 can be defined as the maximum width of the part of the first end E1 extending along the first direction DR1 in the direction X (for example, a direction perpendicular to the first direction DR1), and the width W2 can be defined as the maximum width of the first opening OP1 (for example, the bottom of the first opening OP1) in the direction X. That is, the width W1 and the width W2 can be measured in the same direction (for example, the direction X). According to the present invention, the ratio of the width W1 of the first end E1 to the width W2 of the first opening OP1 can be between 0.5 and 2 (i.e., 0.5 < W1 / W2 < 2), but not limited thereto. In other words, the width W1 can be greater than, equal to, or less than the width W2. For example, as Figure 6 shown, in this variant embodiment, the width W1 of the first end E1 of the first active layer AL1 can be smaller than the width W2 of the first opening OP1. That is, the first opening OP1 can protrude beyond the edge EG1 of the first end E1 in the direction X. In this case, the ratio of the width W1 to the width W2 can be greater than 0.5 and less than 1 (i.e., 0.5 < W1 / W2 < 1). In some embodiments, the width W1 can be the same as the width W2 (as Figure 3 shown), and at this time, the ratio of the width W1 to the width W2 can be 1. In some embodiments, the width W1 can be greater than the width W2, and at this time, the ratio of the width W1 to the width W2 can be greater than 1 and less than 2 (i.e., 1 < W1 / W2 < 2). The relationship between the width of the second end E2 and the width of the opening OPB can refer to the relationship between the width W1 and the width W2 described above, so it will not be elaborated here.

[0053] As Figure 7 shown, in this variant embodiment, the part of the edge EG1 located between the first opening OP1 and the edge EG2 of the second end E2 may not include an arc segment. Specifically, as Figure 7As shown, a virtual straight line (i.e., line L1) passing through point P1 on edge EO and point P2 on edge EG2 can be defined using the method described above. Line L1 will pass through a point on edge EG1 of the first end E1 (e.g., point P5), and this point can be included in the straight line segment of edge EG1. It should be noted that although... Figure 7 As not shown, a portion of the edge EG1 of the first end E1 and a portion of the edge EG2 of the second end E2 may include an arcuate line segment.

[0054] like Figure 8 As shown, in this variant embodiment, the first end E1 of the first active layer AL1 may have an end portion EP, wherein the end portion EP may be, for example, the portion of the first end E1 used to connect the first opening OP1. Specifically, in top view, the first opening OP1 may overlap the end portion EP of the first end E1. The end portion EP of the first end E1 may have a width W3, while other portions of the first end E1 may have a width W4, wherein the width W3 may be greater than the width W4. The width W3 may be defined as the maximum width of the end portion EP in the direction X, while the width W4 may be defined as the maximum width of other portions of the first end E1 in the direction X. In other words, the maximum width (i.e., width W3) of the portion of the first end E1 located at its end (i.e., the end portion EP) in the direction X may be greater than the maximum width (i.e., width W4) of other portions of the first end E1 in the direction X. Through the above design, the size of the portion of the first end E1 that overlaps with the first opening OP1 can be increased, thereby reducing the possibility of the data line DL being disconnected due to the first opening OP1 falling outside the first end E1. In some embodiments, the width W3 of the end portion EP may be greater than the maximum width of the channel region CR of the first active layer AL1 in the X direction.

[0055] Please refer to Figure 9 and Figure 10 , Figure 9 This is a top view schematic diagram of the electronic device according to the second embodiment of the present invention. Figure 10 This is a cross-sectional schematic diagram of an electronic device according to a second embodiment of the present invention. For the sake of simplicity, [the accompanying drawings are omitted]. Figure 10 Only a portion of the film layers and components of the electronic device ED are shown. Specifically, Figure 10The cross-sectional structure shown can be a cross-sectional structure of the electronic device ED along a tangent B-B' parallel to the extension direction of the data line DL (i.e., the first direction DR1). According to this embodiment, in top view, the edge EO of the first opening OP1 may extend beyond (or protrude) the edge EG1 of the first end E1 of the first active layer AL1. For example, the edge EO of the first opening OP1 may extend in the extension direction of the data line DL (i.e., the first direction DR1) and extend beyond the edge EG1 of the first end E1, but is not limited thereto. In this case, in top view, a portion of the first opening OP1 may not overlap with the first end E1, or in other words, the first opening OP1 may not completely overlap with the first end E1.

[0056] Specifically, in the manufacturing process of an electronic device (ED), the photomask used to form the first opening OP1 can extend beyond the first end E1 of the first active layer AL1 (for example, extending beyond the first end E1 in the first direction DR1), so that the formed first opening OP1 extends beyond the first end E1. In this case, as... Figure 10 As shown, when removing a portion of the insulating layer INL located on the first active layer AL1 to form the first opening OP1, a portion of the insulating layer IN2 can also be removed to form the opening OPC. That is, the insulating layer INL surrounds the first opening OP1, and the insulating layer IN2 surrounds the opening OPC. Furthermore, the first opening OP1 can expose a portion of the active layer AL. The characteristics of the insulating layer INL can be found in [reference needed]. Figure 2 As mentioned above, it will not be repeated here. In other words, compared to the structure of the above embodiment, this embodiment, in addition to the first opening OP1, can also form an opening OPC by removing a portion of the insulating layer IN2. In this case, the data line DL can be disposed in the first opening OP1 and the opening OPC, wherein a portion of the data line DL can contact the first active layer AL1, and the other portion of the data line DL can be disposed on the insulating layer IN2, or in other words, extend on the insulating layer IN2.

[0057] According to this embodiment, the first opening OP1 is surrounded by an insulating layer INL, and the first opening OP1 may have a width Z1 in the extension direction of the data line DL (i.e., the first direction DR1, which in this embodiment is, for example, direction Y). The edge EG1 of the first end E1 of the first active layer AL1 and the edge EO of the first opening OP1 may have a distance Z2 in the extension direction of the data line DL, wherein the distance Z2 is greater than or equal to 1 / 4 times the width Z1 and less than or equal to 3 / 4 times the width Z1 (i.e., 1 / 4Z1≤Z2≤3 / 4Z1), but is not limited thereto. In a top view (e.g.) Figure 9 As shown), the width Z1 can be defined as the maximum width of the projection of the bottom contour of the first opening OP1 onto a plane perpendicular to direction Z onto the first direction DR1. In other words, in a cross-section parallel to the extension direction of the data line DL (as shown in the diagram), the width Z1 can be defined as the maximum width of the projection of the bottom contour of the first opening OP1 onto a plane perpendicular to direction Z onto the first direction DR1. Figure 10As shown), the width Z1 can be the maximum distance between one side and the other side of the bottom of the first opening OP1 in the first direction DR1. The distance Z2 can be defined as follows. First, a straight line L2 extending along the first direction DR1 through the geometric center GS of the first opening OP1 can be defined, where the straight line L2 intersects the edge EO of the first opening OP1 at point P3 and the edge EG1 of the first end E1 at point P4, and the distance Z2 can be the straight-line distance between points P3 and P4. Here, the edge EO of the first opening OP1 can be the bottom edge of the first opening OP1. In other words, the edge EO surrounds (or defines) the bottom outline of the first opening OP1. Specifically, in the cross-section, the distance Z2 can be the distance in the Y direction between the edge EG1 of the first end E1 of the first active layer AL1 and the bottom end of the sidewall of the first opening OP1 (i.e., the junction of the insulating layer IN2 and the insulating layer INL). In addition, in the cross-section (as shown) Figure 10 As shown), distance Z2 can be the minimum distance between the edge EG1 of the first end E1 and one side of the bottom of the first opening OP1 (exceeding the side of the first end E1) in the first direction DR1.

[0058] In this scenario, distance Z2 can be considered as the distance by which the first opening OP1 extends beyond the first end E1 of the first active layer AL1 in the first direction DR1. By ensuring that distance Z2 and width Z1 conform to the aforementioned relationship, the likelihood of data line DL breakage can be reduced, thereby improving process yield. Specifically, when distance Z2 is less than 1 / 4 of width Z1, the length of the portion of the data line DL extending on the insulating layer IN2 may be insufficient. In detail, the insulating layer IN2 may form a narrow deep trench structure (i.e., an opening OPC) during the etching step, making it difficult for the data line DL to extend on the insulating layer IN2, thus increasing the risk of breakage. When the distance Z2 is greater than 3 / 4 times the width Z1, the distance between the first opening OP1 and other openings (such as the opening OPB that overlaps with the second active layer AL2) may be too close, thereby increasing the possibility that the first opening OP1 overlaps with the opening OPB. Alternatively, the contact area between the data line DL and the first active layer AL1 may be too small, resulting in poor conductivity. Or, the patterning process of the subsequent conductive layer M4 (details are described below) may be affected, thereby increasing the risk of short circuit.

[0059] It should be noted that the above features can be applied to the opening OPA used for electrically connecting the data line DL to other active layers AL, and are not limited to the first opening OP1 mentioned above.

[0060] Please refer to Figures 11 to 13 , Figure 11 This is a top view schematic diagram of the electronic device according to the third embodiment of the present invention. Figure 12 This is a cross-sectional schematic diagram of an electronic device according to a third embodiment of the present invention. Figure 13This is a cross-sectional schematic diagram of an electronic device according to a third embodiment of the present invention. Specifically, Figure 12 It shows Figure 11 The structure shown is a cross-sectional view along the tangent C-C', while Figure 13 Part of the structure is Figure 11 The diagram shows a cross-sectional view of the structure along the tangent D-D'. For simplicity, the accompanying drawings are provided. Figure 12 Only a portion of the film layers and components of the electronic device ED are shown. According to this embodiment, the electronic device ED may further include a pixel electrode and a patterned conductive layer PCL disposed on insulating layers IN3, IN4, and IN5, wherein the pixel electrode is the aforementioned electrode EL1, and the patterned conductive layer PCL is part of the conductive layer M4. Specifically, in this invention, the conductive layer M4 can be patterned to form a plurality of patterned conductive layers PCL, and a pixel electrode (i.e., electrode EL1) can be electrically connected to an active layer AL (or the drain region DR of the active layer AL) through one of the plurality of patterned conductive layers PCL. For example, a pixel electrode can be electrically connected to the drain region DR of the first active layer AL1 through a patterned conductive layer PCL. The plurality of patterned conductive layers PCL can be electrically isolated from each other, i.e., the plurality of patterned conductive layers PCL can be not electrically connected to each other or not energized by each other. Specifically, in top view, the first active layer AL1 also includes a third terminal E3, wherein the third terminal E3 can be the drain region DR of the first active layer AL1. The third terminal E3 can be separated from the metal line ML. Specifically, in the top view of the electronic device ED, the third terminal E3 of the first active layer AL1 may not overlap with the data line DL and / or the scan line SL. One of the patterned conductive layers PCL can be electrically connected to the third terminal E3 of the first active layer AL1 through the aforementioned opening OPB, wherein the opening OPB can be disposed in the insulating layers IN3, IN4, and IN5 located on the first active layer AL1 (e.g., Figure 13 (as shown), or formed by removing a portion of insulating layers IN3, IN4 and IN5, but not limited thereto.

[0061] According to this embodiment, in a top view (e.g.) Figure 11As shown, there may be a minimum distance DS2 between one of the plurality of patterned conductive layers PCL and the first opening OP1, where the minimum distance DS2 may be greater than 0.1 μm (i.e., 0.1 μm < DS2). Specifically, the minimum distance DS2 may be greater than 0.1 μm and less than 1 mm (i.e., 0.1 μm < DS2 < 1 mm), but not limited thereto. In some embodiments, the minimum distance DS2 may be greater than 0.1 μm and less than 0.8 mm (i.e., 0.1 μm < DS2 < 0.8 mm). In some embodiments, the minimum distance DS2 may be greater than 0.1 μm and less than 0.6 mm (i.e., 0.1 μm < DS2 < 0.6 mm). The above-mentioned "there is a minimum distance DS2 between one of the plurality of patterned conductive layers PCL and the first opening OP1" may mean that there is a minimum distance DS2 between the first opening OP1 and the adjacent patterned conductive layer PCL (such as the patterned conductive layer PCL electrically connected to the first active layer AL1 or the patterned conductive layer PCL electrically connected to the third active layer AL3). The definition method of the minimum distance DS2 may refer to the definition method of the above-mentioned minimum distance DS1. Specifically, after arbitrarily taking a point on the edge EC of the patterned conductive layer PCL adjacent to the first opening OP1 and arbitrarily taking a point on the edge EO of the first opening OP1, a distance can be defined between the two points. After taking a plurality of points on the edge EC and taking a plurality of points on the edge EO to define a plurality of distances, the smallest one of the plurality of distances can be defined as the minimum distance DS2. For example, as Figure 11 shown, the distance between point P9 on the edge EC of the patterned conductive layer PCL adjacent to the first opening OP1 and point P10 on the edge EO of the first opening OP1 may be the smallest one among the plurality of distances defined by the plurality of points on the edge EC and the plurality of points on the edge EO. Therefore, the distance between point P9 and point P10 may be the minimum distance DS2. Refer to Figure 12 , the measuring method of the minimum distance DS2 may be, for example, measuring from the edge EC of the patterned conductive layer PCL to the bottom of the first opening OP1. Therefore, the above-mentioned edge EO of the first opening OP1 may refer to the bottom edge of the first opening OP1, and point P10 may be a point on the bottom edge of the first opening OP1.

[0062] According to this embodiment, the pattern of the patterned conductive layer PCL may have a design that facilitates the minimum distance DS2 between the patterned conductive layer PCL and the first opening OP1 to satisfy the above relationship. Specifically, when designing the pattern of the patterned conductive layer PCL, the part of the pattern of the patterned conductive layer PCL adjacent to the first opening OP1 (or other opening OPA) may also be removed to increase the minimum distance DS2 between the patterned conductive layer PCL and the first opening OP1. For example, in this embodiment, a chamfer design may be performed on the corner part of the pattern of the patterned conductive layer PCL close to the first opening OP1 or other opening OPA to formFigure 11 The pattern shown is illustrated. The pattern of the patterned conductive layer PCL, after the aforementioned chamfering design, may include, for example, a chamfered structure, but is not limited thereto. Specifically, in the process of patterning the conductive layer M4 to form the patterned conductive layer PCL, the pattern of the photomask used to form the patterned conductive layer PCL can be chamfered, cutting off the corner portion of the photomask near the first opening OP1 or other openings OPA to form... Figure 11 The patterned conductive layer PCL is shown. In this case, the width of the portion of the patterned conductive layer PCL located between two adjacent openings OPA can be smaller than the width of the portion of the patterned conductive layer PCL not located between two adjacent openings OPA. Specifically, as shown... Figure 11 As shown, a patterned conductive layer (PCL) may include a portion PO1 overlapping at least one of two openings OPA located on both sides of the patterned conductive layer PCL in the X direction, and a portion PO2 not overlapping the two openings OPA. The portion PO2 may be any portion of the patterned conductive layer PCL other than the portion PO1. The portion PO1 may have a width R1, and the portion PO2 may have a width R2, wherein the width R1 may be smaller than the width R2. The width R1 may be defined as the maximum width of the portion PO1 in the X direction, and the width R2 may be defined as the maximum width of the portion PO2 in the X direction.

[0063] According to this embodiment, through the design of the minimum distance DS2 described above, the area where the patterned conductive layer PCL is disposed does not fall within the first opening OP1. This reduces the possibility that, during the patterning process of the conductive layer M4, insufficient exposure intensity may prevent the effective removal of the conductive layer M4 corresponding to the first opening, thereby causing adjacent patterned conductive layers PCL to connect and short-circuit. The features of the patterned conductive layer PCL in this embodiment can be applied to the above-described special embodiment and variations.

[0064] In summary, this invention provides a high-resolution electronic device comprising an active layer, an opening for electrically connecting a data line to the active layer, and a patterned conductive layer for electrically connecting pixel electrodes to the active layer. In some embodiments, the risk of data line breakage within the opening can be reduced through the positional and / or dimensional design of the active layer and the opening. In some embodiments, the patterning design of the patterned conductive layer can reduce the impact of the opening on the fabrication process of the patterned conductive layer. Thus, the fabrication yield of the electronic device can be improved.

[0065] The above description is merely an embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. An electronic device, characterized by comprising: Comprising: a substrate; a first active layer disposed on the substrate and comprising a first end; a second active layer disposed on the substrate and comprising a second end adjacent to the first end; an insulating layer disposed on the first active layer and the second active layer; and a metal line disposed on the insulating layer, in a cross-sectional view, the insulating layer surrounds a first opening, a portion of the metal line is disposed in the first opening and overlaps the first end, and in a top view, the first end has an edge, a portion of the edge is arc-shaped and is located between the first opening and the second end. In a top view, the metal line and a portion of the first end extend along a first direction. 2.The electronic device of claim 1, wherein, In a top view, the portion of the first end exceeds the first opening toward the first direction, and a distance between the portion of the first end and the first opening in the first direction is less than 2 microns. 3.The electronic device of claim 2, wherein, Further comprising a pixel electrode and a plurality of patterned conductive layers disposed on the insulating layer, one of the plurality of patterned conductive layers has a first minimum distance from the first opening, wherein the pixel electrode is electrically connected to the first active layer through the one of the plurality of patterned conductive layers. 4.The electronic device of claim 1, wherein, The plurality of patterned conductive layers are electrically separated from each other. 5.The electronic device of claim 4, wherein, In a top view, the first active layer further comprises a third end, the third end is separated from the metal line, the insulating layer further comprises a second opening, and the one of the plurality of patterned conductive layers is electrically connected to the third end through the second opening. 6.The electronic device of claim 4, wherein, The first minimum distance is greater than 0.1 microns. 7.The electronic device of claim 4, wherein, The first end and the second end have a second minimum distance, the second minimum distance is greater than or equal to 0.5 microns. 8.The electronic device of claim 1, wherein, In a top view, the second end is separated from the metal line. 9.The electronic device of claim 1, wherein, The first end has a first width, the first opening has a second width, and a ratio of the first width to the second width is between 0.5 and 2. 10.The electronic device of claim 1, wherein, ​

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