High bandwidth memory system and apparatus

Abstract

The present disclosure relates to methods, apparatus, systems, and techniques for high bandwidth memory (HBM). An example semiconductor device includes a first layer, a second layer, a first die between the first layer and the second layer, and a second die stacked together in a first direction. Each of the first die and the second die has a conductive layer. The first die and the second die are bonded through the second layer. The semiconductor device also includes a first contact structure coupled to the conductive layer of the first die and a second contact structure coupled to the conductive layer of the second die. The first contact structure extends in a first direction and contacts the conductive layer of the first die without extending through the second layer.

Description

Technical Field

[0001] This disclosure relates to high-bandwidth memory (HBM) systems and devices, and methods of manufacturing the same. Background Technology

[0002] Semiconductor devices (e.g., memory devices) can have various structures to increase the density of memory cells and lines on a chip. For example, three-dimensional (3D) memory devices are attractive because they can increase array density by stacking more layers within a similar footprint. 3D memory devices typically include a memory array of memory cells and peripheral circuitry to facilitate the operation of the memory array.

[0003] High-bandwidth memory (HBM) uses stacked memory devices to achieve efficient data movement and access. While using less power in a smaller form factor, HBM devices can achieve high bandwidth. HBM devices have been applied in high-performance graphics accelerators, networking devices, high-performance data centers, artificial intelligence (AI) and machine learning (ML) training, and various supercomputers. Summary of the Invention

[0004] This disclosure describes methods, apparatus, systems, and techniques for high-bandwidth memory (HBM).

[0005] One aspect of this disclosure features a semiconductor device comprising a first layer, a second layer, a first die between the first and second layers, and a second die stacked together along a first direction. Each of the first die and the second die has a conductive layer. The first die and the second die are bonded together via the second layer. The semiconductor device further includes a first contact structure coupled to the conductive layer of the first die and a second contact structure coupled to the conductive layer of the second die. The first contact structure extends along the first direction and contacts the conductive layer of the first die without extending through the second layer. The second contact structure extends along the first direction through the second layer without extending through the second die. The second contact structure contacts the conductive layer of the second die without extending through the conductive layer of the first die.

[0006] In some embodiments, the semiconductor device further includes a base die. The base die, the first layer, the first die, the second layer, and the second die are stacked along the first direction. The base die and the first die are bonded together through the first layer.

[0007] In some embodiments, the first end of the conductive layer of the first die and the first end of the conductive layer of the second die are offset along a second direction perpendicular to the first direction.

[0008] In some embodiments, the second contact structure is located along the second direction between a first end of the conductive layer of the first die and a first end of the conductive layer of the second die.

[0009] In some implementations, each of the first contact structure and the second contact structure is a continuous structure.

[0010] In some embodiments, the second layer includes at least one dielectric material and does not include conductive bonding contacts, and the first layer includes conductive bonding contacts and at least one dielectric material that isolates the conductive bonding contacts.

[0011] In some embodiments, the second layer includes a top bonding layer and a bottom bonding layer, each of which includes a dielectric material and does not include conductive bonding contacts. The dielectric material of the top bonding layer of the second layer is bonded to the dielectric material of the bottom bonding layer of the second layer. The first layer includes a top bonding layer and a bottom bonding layer, each of which includes conductive bonding contacts and a dielectric material that isolates the conductive bonding contacts. The dielectric material of the top bonding layer of the first layer is bonded to the dielectric material of the bottom bonding layer of the first layer. The conductive bonding contacts of the top bonding layer of the first layer are bonded to the conductive bonding contacts of the bottom bonding layer of the first layer.

[0012] In some embodiments, the base die includes a first via extending along the first direction and coupled to a conductive bonding contact of the first layer. Each of the first contact structure and the second contact structure is coupled to one of the first vias through one of the conductive bonding contacts of the first layer.

[0013] In some embodiments, the semiconductor device further includes a computing die and an interposer, wherein the base die and the computing die are integrated at different locations on the interposer along a second direction perpendicular to the first direction.

[0014] In some embodiments, the base die includes a first via coupled to the computing die through the interposer, the first via coupled to a first conductive terminal on the surface of the interposer, the computing die coupled to a second conductive terminal on the surface of the interposer, and the first conductive terminal and the second conductive terminal are coupled through conductive lines in the interposer.

[0015] In some embodiments, the semiconductor device further includes a computing die and a third layer between the computing die and the base die. The computing die, the third layer, the base die, the first layer, the first die, the second layer, and the second die are stacked along the first direction. The base die and the computing die are bonded together through the third layer.

[0016] In some embodiments, the third layer includes conductive bonding contacts and at least one dielectric material that isolates the conductive bonding contacts.

[0017] In some embodiments, the third layer includes a top bonding layer and a bottom bonding layer, each including conductive bonding contacts and a dielectric material isolating the conductive bonding contacts. The dielectric material of the top bonding layer of the third layer is bonded to the dielectric material of the bottom bonding layer of the third layer. The conductive bonding contacts of the top bonding layer of the third layer are bonded to the conductive bonding contacts of the bottom bonding layer of the third layer.

[0018] In some embodiments, the base die includes a first via coupled to the computing die. The computing die includes a second via extending along the first direction and coupled to a conductive bonding contact of the third layer. The first via is coupled to the second via through the conductive bonding contact of the third layer.

[0019] In some embodiments, the semiconductor device further includes an interposer layer, wherein the interposer layer, the computing die, the third layer, the base die, the first layer, the first die, the second layer, and the second die are stacked along the first direction.

[0020] In some embodiments, the semiconductor device further includes a third die, which is the furthest from the base die along a first direction among the first die, the second die, and the third die, wherein, along the first direction, the thickness of each of the first die and the second die is less than the thickness of the third die.

[0021] In some embodiments, the thickness of the first die and the thickness of the second die are each in the range of 3 micrometers (μm) and 20 μm.

[0022] In some embodiments, the cross-sectional dimension of the second contact structure in the first die is larger than the cross-sectional dimension of the second contact structure in the second die. The cross-sections of the second contact structures in the first die and the second contact structures in the second die are perpendicular to a first direction.

[0023] In some embodiments, the first contact structure and the second contact structure are formed using the same process.

[0024] In some embodiments, each of the first contact structure and the second contact structure has a critical dimension (CD) in the range of 0.5 μm and 10 μm.

[0025] In some embodiments, at least one of the first die or the second die includes a memory array, the memory array including a memory cell array and peripheral circuitry coupled to the memory array.

[0026] In some embodiments, at least one of the first die or the second die is a dynamic random access memory (DRAM) device.

[0027] In some embodiments, the base die includes control circuitry configured to control the first die and the second die.

[0028] In some embodiments, the stacked structure of the first die and the second die includes a first device region, a second device region, and a connection region between the first device region and the second device region along a second direction perpendicular to the first direction. Each of the first die and the second die includes one or more memory arrays in the first device region and the second device region. The first contact structure and the second contact structure are located in the connection region.

[0029] In some embodiments, the ratio of the cross-sectional dimension of the connecting region to the sum of the first dimension of the cross-section of the first device region and the second dimension of the cross-section of the second device region is between 1 / 6 and 1 / 5. The cross-sections of the connecting region, the first device region, and the second device region are perpendicular to the first direction.

[0030] Another aspect of this disclosure features a semiconductor device comprising a base die, a first layer, a second layer, a first die between the first and second layers, and a second die stacked together along a first direction. Each of the base die, the first die, and the second die has a conductive layer. The first die and the second die are bonded through the second layer. The base die and the first die are bonded through the first layer. The semiconductor device further includes a first contact structure coupled to the conductive layer of the base die and a second contact structure coupled to the conductive layer of the first die. The first contact structure extends along the first direction and contacts the conductive layer of the base die without extending through the first layer. The second contact structure extends along the first direction through the first layer without extending through the second layer. The second contact structure contacts the conductive layer of the first die without extending through the conductive layer of the base die. The semiconductor device further includes a third contact structure coupled to the conductive layer of the second die. The third contact structure extends along the first direction through the first and second layers without extending through the second die. The third contact structure contacts the conductive layer of the second die without extending through the conductive layer of the first die.

[0031] In some embodiments, the first end of the conductive layer of the first die and the first end of the conductive layer of the second die are offset along a second direction perpendicular to the first direction.

[0032] In some embodiments, the third contact structure is located along the second direction between a first end of the conductive layer of the first die and a first end of the conductive layer of the second die.

[0033] In some embodiments, each of the first contact structure, the second contact structure, and the third contact structure is a continuous structure.

[0034] In some embodiments, the second layer includes at least one dielectric material and does not include conductive bonding contacts, and the first layer includes at least one dielectric material and does not include conductive bonding contacts.

[0035] In some embodiments, the second layer includes a top bonding layer and a bottom bonding layer, each of which includes a dielectric material and does not include conductive bonding contacts. The dielectric material of the top bonding layer of the second layer is bonded to the dielectric material of the bottom bonding layer of the second layer. The first layer includes a top bonding layer and a bottom bonding layer, each of which includes a dielectric material and does not include conductive bonding contacts. The dielectric material of the top bonding layer of the first layer is bonded to the dielectric material of the bottom bonding layer of the first layer.

[0036] In some embodiments, the base die includes an interconnect layer extending along a second direction perpendicular to the first direction. Each of the first contact structure, the second contact structure, and the third contact structure is coupled to the interconnect layer.

[0037] In some embodiments, the semiconductor device further includes a computing die and an interposer. The base die and the computing die are integrated at different locations on the interposer along the second direction. The base die and the computing die are coupled through the interconnect layer and the interposer.

[0038] In some embodiments, the interconnect layer is coupled to a first conductive terminal on the surface of the interposer layer. The computing die is coupled to a second conductive terminal on the surface of the interposer layer. The first and second conductive terminals are coupled via conductive lines in the interposer layer.

[0039] In some embodiments, the semiconductor device further includes a computing die and a third layer between the computing die and the base die. The computing die, the third layer, the base die, the first layer, the first die, the second layer, and the second die are stacked along the first direction. The base die and the computing die are bonded together through the third layer.

[0040] In some embodiments, the third layer includes conductive bonding contacts and at least one dielectric material that isolates the conductive bonding contacts.

[0041] In some embodiments, the third layer includes a top bonding layer and a bottom bonding layer, each including conductive bonding contacts and a dielectric material isolating the conductive bonding contacts. The dielectric material of the top bonding layer of the third layer is bonded to the dielectric material of the bottom bonding layer of the third layer. The conductive bonding contacts of the top bonding layer of the third layer are bonded to the conductive bonding contacts of the bottom bonding layer of the third layer.

[0042] In some embodiments, the computing die includes a via extending along the first direction and coupled to the conductive bonding contacts of the third layer. The interconnect layer of the base die is coupled to the via through the conductive bonding contacts of the third layer.

[0043] In some embodiments, the semiconductor device further includes an interposer layer, wherein the interposer layer, the computing die, the base die, the first die, and the second die are stacked along the first direction.

[0044] In some embodiments, the semiconductor device further includes a third die, which, among the first, second, and third dies, is furthest from the base die along the first direction. Along the first direction, the thickness of each of the first and second dies is less than the thickness of the third die.

[0045] In some embodiments, the thickness of the first die and the thickness of the second die are each in the range of 3 μm and 20 μm.

[0046] In some embodiments, the cross-sectional dimension of the second contact structure in the first die is larger than the cross-sectional dimension of the second contact structure in the second die. The cross-sections of the second contact structures in the first die and the second contact structures in the second die are perpendicular to the first direction.

[0047] In some embodiments, the first contact structure and the second contact structure are formed using the same process.

[0048] In some embodiments, each of the first contact structure and the second contact structure has a CD in the range of 0.5 μm and 10 μm.

[0049] In some embodiments, at least one of the first die or the second die includes a memory array, the memory array including a memory cell array and peripheral circuitry coupled to the memory array.

[0050] In some embodiments, at least one of the first die or the second die is a DRAM device.

[0051] In some embodiments, the base die includes control circuitry configured to control the first die and the second die.

[0052] In some embodiments, the stacked structure of the first die and the second die includes a first device region, a second device region, and a connection region between the first device region and the second device region along a second direction perpendicular to the first direction. Each of the first die and the second die includes one or more memory arrays in the first device region and the second device region. The first contact structure and the second contact structure are located in the connection region.

[0053] In some embodiments, the ratio of the cross-sectional dimension of the connecting region to the sum of the first dimension of the cross-section of the first device region and the second dimension of the cross-section of the second device region is between 1 / 6 and 1 / 5. The cross-sections of the connecting region, the first device region, and the second device region are perpendicular to the first direction.

[0054] Another aspect of this disclosure is a method comprising providing a first die and a second die, wherein the first die includes a conductive layer and at least a first bonding layer, and the second die includes a conductive layer and at least a second bonding layer. The method further comprises stacking the second die on the first die along a first direction, and bonding the second bonding layer of the second die to the first bonding layer of the first die. The method further comprises forming a first contact structure and a second contact structure extending along the first direction. The first contact structure contacts the conductive layer of the first die. The second contact structure extends through the first bonding layer of the first die and the second bonding layer of the second die. The second contact structure contacts the conductive layer of the second die but not the conductive layer of the first die.

[0055] In some embodiments, the first bonding layer of the first die and the second bonding layer of the second die each comprise a dielectric material and do not include conductive bonding contacts.

[0056] In some embodiments, stacking the second die on top of the first die along the first direction includes aligning the second die with the first die such that a first end of the conductive layer of the first die and a first end of the conductive layer of the second die are offset along a second direction perpendicular to the first direction.

[0057] In some embodiments, providing a first die includes thinning the first die by thinning a substrate included in the first die.

[0058] In some embodiments, the method further includes stacking the first die on a carrier wafer, wherein the first die is between the carrier wafer and the second die.

[0059] In some embodiments, the first contact structure and the second contact structure are formed using the same process. The process includes forming a first contact hole and a second contact hole, forming an insulating layer in each of the first contact hole and the second contact hole, and forming a conductive structure in the insulating layer of each of the first contact hole and the second contact hole to form the first contact structure and the second contact structure. The first contact structure includes an insulating layer and a conductive structure in the first contact hole, and the second contact structure includes an insulating layer and a conductive structure in the second contact hole.

[0060] In some embodiments, the first contact hole and the second contact hole are formed during the same etching process.

[0061] In some embodiments, the method further includes forming a mask layer on top of the first die and etching the mask layer to form a first opening and a second opening. The first contact hole extends from the first opening to a conductive layer of the first die, and the second contact hole extends from the second opening to a conductive layer of the second die.

[0062] In some embodiments, the method further includes forming a third bonding layer on top of the first die, wherein the third bonding layer includes conductive bonding contacts and a dielectric material that isolates the conductive bonding contacts.

[0063] In some embodiments, the method further includes providing a base die, wherein the base die includes a bottom bonding layer comprising conductive bonding contacts and a dielectric material that isolates the conductive bonding contacts.

[0064] In some embodiments, the method further includes stacking the base die on the first die by bonding the dielectric material of the bottom bonding layer of the base die to the dielectric material of the third bonding layer of the first die and bonding the conductive bonding contacts of the bottom bonding layer of the base die to the conductive bonding contacts of the third bonding layer of the first die.

[0065] Another aspect of this disclosure features a semiconductor device comprising a first layer, a second layer, a first die between the first and second layers, and a second die stacked together along a first direction. Each of the first die and the second die has a conductive layer. The first die and the second die are bonded through the second layer. The semiconductor device further includes a first contact structure coupled to the conductive layer of the first die and a second contact structure coupled to the conductive layer of the second die. The first contact structure extends along the first direction and contacts the conductive layer of the first die without extending through the second layer. The second contact structure extends along the first direction through the conductive layer of the first die and the second layer, and contacts the conductive layer of the second die without extending through the second die.

[0066] In some embodiments, the conductive layer of the first die and the conductive layer of the second die have the same dimensions and are located at the same position along a second direction perpendicular to the first direction.

[0067] In some embodiments, each of the first contact structure and the second contact structure includes a conductive layer extending along the first direction and an insulating layer surrounding the conductive layer.

[0068] In some embodiments, the first layer includes conductive bonding contacts and at least one dielectric material that isolates the conductive bonding contacts, and the second layer includes at least one dielectric material but does not include conductive bonding contacts.

[0069] In some embodiments, the first layer includes a top bonding layer and a bottom bonding layer, each of which includes conductive bonding contacts and a dielectric material isolating the conductive bonding contacts. The dielectric material of the top bonding layer of the first layer is bonded to the dielectric material of the bottom bonding layer of the first layer. The conductive bonding contacts of the top bonding layer of the first layer are bonded to the conductive bonding contacts of the bottom bonding layer of the first layer. The second layer includes a top bonding layer and a bottom bonding layer, each of which includes a dielectric material and does not include conductive bonding contacts. The dielectric material of the top bonding layer of the second layer is bonded to the dielectric material of the bottom bonding layer of the second layer.

[0070] In some embodiments, the semiconductor device further includes a base die bonded to the first die via the first layer, wherein the base die, the first layer, the first die, the second layer, and the second die are stacked along the first direction.

[0071] In some embodiments, the base die includes a first via extending along the first direction and coupled to a conductive bonding contact of the first layer. Each of the first contact structure and the second contact structure is coupled to one of the first vias through one of the conductive bonding contacts of the first layer.

[0072] In some embodiments, the semiconductor device further includes a computing die and an interposer, wherein the base die and the computing die are integrated at different locations on the interposer along a second direction perpendicular to the first direction.

[0073] In some embodiments, the first via is coupled to a first conductive terminal on the surface of the interposer. The computing die is coupled to a second conductive terminal on the surface of the interposer. The first and second conductive terminals are coupled via conductive lines in the interposer.

[0074] In some embodiments, the semiconductor device further includes a computing die bonded to the base die via a third layer, wherein the computing die, the third layer, the base die, the first layer, the first die, the second layer, and the second die are stacked along the first direction.

[0075] In some embodiments, the third layer includes conductive bonding contacts and at least one dielectric material that isolates the conductive bonding contacts.

[0076] In some embodiments, the third layer includes a top bonding layer and a bottom bonding layer, each including conductive bonding contacts and a dielectric material isolating the conductive bonding contacts. The dielectric material of the top bonding layer of the third layer is bonded to the dielectric material of the bottom bonding layer of the third layer. The conductive bonding contacts of the top bonding layer of the third layer are bonded to the conductive bonding contacts of the bottom bonding layer of the third layer.

[0077] In some embodiments, the computing die includes a second via extending along the first direction and coupled to a conductive bonding contact of the third layer. The first via is coupled to the second via through the conductive bonding contact of the third layer.

[0078] In some embodiments, the semiconductor device further includes an interposer layer, wherein the interposer layer, the computing die, the third layer, the base die, the first layer, the first die, the second layer, and the second die are stacked along the first direction.

[0079] In some embodiments, the semiconductor device further includes a third die, which, among the first, second, and third dies, is furthest from the base die along the first direction. Along the first direction, the thickness of each of the first and second dies is less than the thickness of the third die.

[0080] In some embodiments, the thickness of the first die and the thickness of the second die are each in the range of 3 μm and 20 μm.

[0081] In some embodiments, the cross-sectional dimension of the second contact structure in the first die is larger than the cross-sectional dimension of the second contact structure in the second die. The cross-sections of the second contact structures in the first die and the second contact structures in the second die are perpendicular to the first direction.

[0082] In some implementations, each of the first contact structure and the second contact structure is a continuous structure.

[0083] In some embodiments, the first contact structure and the second contact structure are formed using the same process.

[0084] In some embodiments, each of the first contact structure and the second contact structure has a CD in the range of 0.5 μm and 10 μm.

[0085] In some embodiments, at least one of the first die or the second die includes a memory array, the memory array including a memory cell array and peripheral circuitry coupled to the memory array.

[0086] In some embodiments, at least one of the first die or the second die includes a DRAM device.

[0087] In some embodiments, the base die includes control circuitry configured to control the first die and the second die.

[0088] In some embodiments, the stacked structure of the first die and the second die includes a first device region, a second device region, and a connection region between the first device region and the second device region along a second direction perpendicular to the first direction. Each of the first die and the second die includes one or more memory arrays in the first device region and the second device region. The first contact structure and the second contact structure are located in the connection region.

[0089] In some embodiments, the ratio of the cross-sectional dimension of the connecting region to the sum of the first dimension of the cross-section of the first device region and the second dimension of the cross-section of the second device region is between 1 / 6 and 1 / 5. The cross-sections of the connecting region, the first device region, and the second device region are perpendicular to the first direction.

[0090] Another aspect of this disclosure features a semiconductor device comprising a base die, a first layer, a second layer, a first die between the first and second layers, and a second die stacked together along a first direction. Each of the base die, the first die, and the second die has a conductive layer. The base die and the first die are bonded through the first layer. The first die and the second die are bonded through the second layer. The semiconductor device further includes a first contact structure coupled to the conductive layer of the base die and a second contact structure coupled to the conductive layer of the first die. The first contact structure extends along the first direction and contacts the conductive layer of the base die without extending through the first layer. The second contact structure extends along the first direction and contacts the conductive layer of the first die without extending through the second layer. The semiconductor device further includes a third contact structure coupled to the conductive layer of the second die. The third contact structure extends along the first direction through the first layer, the conductive layer of the first die, and the second layer, and contacts the conductive layer of the second die without extending through the second die.

[0091] In some embodiments, the conductive layer of the first die and the conductive layer of the second die have the same dimensions and are located at the same position along a second direction perpendicular to the first direction.

[0092] In some embodiments, each of the first contact structure, the second contact structure, and the third contact structure includes a conductive layer extending along the first direction and an insulating layer surrounding the conductive layer.

[0093] In some embodiments, the first layer includes at least one dielectric material and does not include conductive bonding contacts, and the second layer includes at least one dielectric material and does not include conductive bonding contacts.

[0094] In some embodiments, the first layer includes a top bonding layer and a bottom bonding layer, each of which includes a dielectric material and does not include conductive bonding contacts. The dielectric material of the top bonding layer of the first layer is bonded to the dielectric material of the bottom bonding layer of the first layer. The second layer includes a top bonding layer and a bottom bonding layer, each of which includes a dielectric material and does not include conductive bonding contacts. The dielectric material of the top bonding layer of the second layer is bonded to the dielectric material of the bottom bonding layer of the second layer.

[0095] In some embodiments, the base die includes an interconnect layer extending along a second direction perpendicular to the first direction. Each of the first contact structure, the second contact structure, and the third contact structure is coupled to the interconnect layer.

[0096] In some embodiments, the semiconductor device further includes a computing die and an interposer. The base die and the computing die are integrated at different locations on the interposer along the second direction. The base die and the computing die are coupled through the interconnect layer and the interposer.

[0097] In some embodiments, the interconnect layer is coupled to a first conductive terminal on the surface of the interposer layer. The computing die is coupled to a second conductive terminal on the surface of the interposer layer. The first and second conductive terminals are coupled via conductive lines in the interposer layer.

[0098] In some embodiments, the semiconductor device further includes a computing die bonded to the base die via a third layer, wherein the computing die, the third layer, the base die, the first layer, the first die, the second layer, and the second die are stacked along the first direction.

[0099] In some embodiments, the third layer includes conductive bonding contacts and at least one dielectric material that isolates the conductive bonding contacts.

[0100] In some embodiments, the third layer includes a top bonding layer and a bottom bonding layer, each including conductive bonding contacts and a dielectric material isolating the conductive bonding contacts. The dielectric material of the top bonding layer of the third layer is bonded to the dielectric material of the bottom bonding layer of the third layer. The conductive bonding contacts of the top bonding layer of the third layer are bonded to the conductive bonding contacts of the bottom bonding layer of the third layer.

[0101] In some embodiments, the computing die includes a via extending along the first direction and coupled to the conductive bonding contact of the third layer.

[0102] In some embodiments, the semiconductor device further includes an interposer layer, wherein the interposer layer, the computing die, the third layer, the base die, the first layer, the first die, the second layer, and the second die are stacked along the first direction.

[0103] In some embodiments, the semiconductor device further includes a third die, which, among the first, second, and third dies, is furthest from the base die along the first direction. Along the first direction, the thickness of each of the first and second dies is less than the thickness of the third die.

[0104] In some embodiments, the cross-sectional dimension of the second contact structure in the first die is larger than the cross-sectional dimension of the second contact structure in the second die. The cross-sections of the second contact structures in the first die and the second contact structures in the second die are perpendicular to the first direction.

[0105] In some implementations, each of the first contact structure and the second contact structure is a continuous structure.

[0106] In some embodiments, the first contact structure and the second contact structure are formed using the same process.

[0107] In some embodiments, each of the first contact structure, the second contact structure, and the third contact structure has a CD in the range of 0.5 μm and 10 μm.

[0108] In some embodiments, at least one of the first die or the second die includes a memory array, the memory array including a memory cell array and peripheral circuitry coupled to the memory array.

[0109] In some embodiments, at least one of the first die or the second die includes a DRAM device.

[0110] In some embodiments, the base die includes control circuitry configured to control the first die and the second die.

[0111] In some embodiments, the stacked structure of the first die and the second die includes a first device region, a second device region, and a connection region between the first device region and the second device region along a second direction perpendicular to the first direction. Each of the first die and the second die includes one or more memory arrays in the first device region and the second device region. The first contact structure and the second contact structure are located in the connection region.

[0112] In some embodiments, the ratio of the cross-sectional dimension of the connecting region to the sum of the first dimension of the cross-section of the first device region and the second dimension of the cross-section of the second device region is between 1 / 6 and 1 / 5. The cross-sections of the connecting region, the first device region, and the second device region are perpendicular to the first direction.

[0113] Another aspect of this disclosure features a method comprising providing a first die and a second die, wherein the first die includes a first conductive layer and at least a first bonding layer, and the second die includes a second conductive layer and at least a second bonding layer. The method further comprises stacking the second die on the first die along a first direction and bonding the second bonding layer to the first bonding layer. The method further comprises forming a first contact structure and a second contact structure extending along the first direction. The first contact structure contacts the first conductive layer without extending through the first bonding layer. The second contact structure extends through the first conductive layer, the first bonding layer, and the second bonding layer, and contacts the second conductive layer without extending through the second die.

[0114] In some embodiments, each of the first and second bonding layers comprises a dielectric material and does not include conductive bonding contacts. Bonding the second bonding layer to the first bonding layer includes bonding the dielectric material of the first bonding layer to the dielectric material of the second bonding layer.

[0115] In some embodiments, stacking the second die on the first die along the first direction includes aligning the second die with the first die to place the first conductive layer and the second conductive layer in the same position along a second direction perpendicular to the first direction, wherein the first conductive layer and the second conductive layer have the same dimensions.

[0116] In some embodiments, the method further includes thinning the first die by thinning a substrate included in the first die.

[0117] In some embodiments, the method further includes bonding a carrier wafer to the surface of the first die, wherein the first die is located between the carrier wafer and the second die.

[0118] In some embodiments, forming the first contact structure and the second contact structure includes forming a mask layer on top of the first die, etching the mask layer to form a first opening and a second opening, forming a first contact hole and a second contact hole extending along the first direction, wherein the first contact hole extends from the first opening to the first conductive layer and the second contact hole extends from the second opening to the first conductive layer, filling the first contact hole with a filler material, deepening the second contact hole until the second contact hole extends through the first conductive layer and into the second conductive layer, removing the filler material from the first contact hole, forming an insulating layer in each of the first contact hole and the second contact hole, and forming the first contact structure in the first contact hole and the second contact structure in the second contact hole by depositing conductive material into the first contact hole and the second contact hole.

[0119] In some embodiments, forming the first and second contact holes includes etching the insulating material in the first die using a first etching gas. Deepening the second contact hole includes etching the conductive material of the first conductive layer using a second etching gas different from the first etching gas.

[0120] In some embodiments, the method further includes forming a third bonding layer on the surface of the first die opposite to the first bonding layer, wherein the third bonding layer includes conductive bonding contacts and a dielectric material that isolates the conductive bonding contacts.

[0121] In some embodiments, the method further includes providing a base die, wherein the base die includes a via extending along the first direction and a fourth bonding layer, the fourth bonding layer including conductive bonding contacts coupled to the via and a dielectric material isolating the conductive bonding contacts. The method further includes bonding the fourth bonding layer of the base die to the third bonding layer on the surface of the first die.

[0122] In some embodiments, bonding the fourth bonding layer to the third bonding layer includes bonding the dielectric material of the fourth bonding layer to the dielectric material of the third bonding layer and bonding the conductive bonding contacts of the fourth bonding layer to the conductive bonding contacts of the third bonding layer.

[0123] In some embodiments, the method further includes: stacking a base die on the first die, wherein the base die includes a third conductive layer; and forming a third contact structure coupled to the base die. Forming the first contact structure, the second contact structure, and the third contact structure includes forming a mask layer on top of the base die, etching the mask layer to form a first opening, a second opening, and a third opening, forming a first contact hole, a second contact hole, and a third contact hole extending along a first direction, wherein the first contact hole extends from the first opening to the first conductive layer, the second contact hole extends from the second opening to the first conductive layer, and the third contact hole extends from the third opening to the third conductive layer, filling the first contact hole and the third contact hole with a filler material, deepening the second contact hole until the second contact hole extends through the first conductive layer and into the second conductive layer, removing the filler material from the first contact hole and the third contact hole, forming an insulating layer in each of the first contact hole, the second contact hole, and the third contact hole, and forming the first contact structure in the first contact hole, the second contact structure in the second contact hole, and the third contact structure in the third contact hole by depositing conductive material into the first contact hole, the second contact hole, and the third contact hole.

[0124] Embodiments of this disclosure may provide one or more of the following technical advantages and / or benefits. For example, a semiconductor device may include multiple memory dies stacked in a vertical direction. Note that the terms "multiple dies" and "die" are used interchangeably in this disclosure. Multiple memory dies are bonded together using direct bonding technology. Some memory dies can be thinned, thereby increasing the memory density and capacity of the semiconductor device. One memory die may be thicker than the others, thus allowing a carrier wafer to be replaced to provide support to the other memory dies during the semiconductor device fabrication process. As a result, the carrier wafer can be used less frequently during the fabrication process, thereby effectively improving manufacturing efficiency and reducing manufacturing costs. Memory dies may be coupled to each other and to logic devices via contact structures extending into the stacked memory dies. Self-alignment can be achieved during the semiconductor device fabrication process through direct bonding between memory dies, hybrid bonding between adjacent semiconductor structures (such as between a memory die and a base die or between a base die and a computing die), and the use of contact structures, which effectively improves manufacturing reliability. Additionally, each contact structure may have a continuous structure and a small critical dimension. Therefore, higher interconnect density between different dies in a semiconductor device can be achieved, and the memory bandwidth and data transfer speed of the semiconductor device can be increased.

[0125] This technology can be applied to various types of semiconductor devices, volatile memory devices (e.g., DRAM memory devices), or non-volatile memory (NVM) devices (e.g., NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase-change memory (PCM) (e.g., PCRAM), spin-transfer torque (STT)-magnetoresistive random access memory (MRAM), etc.). It can also be applied to charge-trapping based memory devices (e.g., silicon-oxide-nitride-oxide-silicon (SONOS) memory devices) and floating-gate based memory devices. This technology can be applied to three-dimensional (3D) memory devices. It can be applied to various memory types, such as SLC (single-level cell) devices, MLC (multi-level cell) devices such as two-level cell devices, TLC (three-level cell) devices, QLC (four-level cell) devices, or PLC (five-level cell) devices. Alternatively or concurrently, this technology can be applied to various types of devices and systems, such as secure digital cards (SD cards), embedded multimedia cards (eMMC), solid-state drives (SSDs), embedded systems, etc.

[0126] Details of one or more embodiments of the subject matter of this disclosure are set forth in the accompanying drawings and the following description. Other features, aspects, and advantages of the subject matter will become apparent from the specification, drawings, and claims. Attached Figure Description

[0127] The accompanying drawings, which are incorporated herein and form part of this disclosure, illustrate various aspects of this disclosure and, together with the description, further serve to explain the principles of this disclosure and enable those skilled in the art to make and use this disclosure.

[0128] Figure 1 A block diagram of an example system having one or more semiconductor devices is shown, according to some aspects of this disclosure.

[0129] Figures 2A-2E Example semiconductor devices are shown in accordance with some aspects of this disclosure.

[0130] Figures 3A-3H Example semiconductor devices are shown in accordance with some aspects of this disclosure.

[0131] Figure 4A-4J An example process for manufacturing a semiconductor device according to some aspects of this disclosure is shown.

[0132] Figure 5 A flowchart illustrating an example process for forming a semiconductor device according to some aspects of this disclosure is shown.

[0133] Figure 6A-6GExample semiconductor devices are shown in accordance with some aspects of this disclosure.

[0134] Figure 7A-7N An example process for manufacturing a semiconductor device according to some aspects of this disclosure is shown.

[0135] Figure 8 A flowchart illustrating an example process for forming a semiconductor device according to some aspects of this disclosure is shown.

[0136] The same reference numerals and names in the various figures indicate the same elements. It should also be understood that the various exemplary embodiments shown in the figures are merely illustrative representations and are not necessarily drawn to scale. Detailed Implementation

[0137] Figure 1 A block diagram of an example system 100 having one or more semiconductor devices (e.g., memory devices) according to some aspects of this disclosure is shown. System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Figure 1 As shown, system 100 may include one or more memory devices 102, base devices 104, computing devices 108, and external host devices 112. In some embodiments, each of devices 102, 104, 108, and 112 may be a die or multiple dies stacked together. Each of devices 102, 104, 108, and 112 may be fabricated by depositing multiple layers of various materials and etching them onto a semiconductor wafer in a complex pattern defined by a chip design. After the wafer fabrication process is completed, the wafer, including the various circuits, is diced and sliced ​​into individual slabs, each of which is a die. Each die may include fully functional electronic circuitry, which may be a microprocessor, memory, sensor, or any other suitable type of integrated circuit. In some embodiments, each die is encapsulated in a protective package, thereby providing physical support, protection from environmental factors, and connectivity to external devices or systems (e.g., via pins or solder balls).

[0138] Memory die 102 may include any memory device disclosed herein, such as those based on, etc. Figures 2A-2E , Figures 3A-3D , Figure 4A-4J , Figures 6A-6D and Figure 7A-7MA memory device (e.g., a 3D memory device) of any of the described semiconductor structures. In some embodiments, memory die 102 includes one or more dynamic random access memory (DRAM) devices. In some embodiments, memory die 102 includes one or more NAND flash memory devices. In some embodiments, memory die 102 may include high bandwidth memory (HBM). In some embodiments, memory dies 102 may be stacked together, for example, as described above. Figures 2A-2E , Figures 3A-3D and Figures 6A-6D Further detailed description. In some embodiments, the memory die 102 may include, as described above. Figure 2C and Figures 3A-3D One or more HBM devices described and as per the description Figure 2D and Figures 6A-6D A combination of one or more HBM devices described.

[0139] The base die 104 (also referred to as a logic die or buffer die) may include buffer circuitry and test logic units for the memory device 102. The base die 104 may be configured to provide a physical layer communication protocol (e.g., IEEE-1500) between the memory die 102 and the compute die 108. The base die 104 may be configured to transfer data between the memory die 102 and the compute die 108 based on control commands and addresses from the compute die 108.

[0140] The computing die 108 may be a logic device and may include at least one processor of an electronic device, such as a central processing unit (CPU), graphics processing unit (GPU), application-specific integrated circuit (ASIC), or system-on-a-chip (SoC), such as an application processor (AP). The computing die 108 may be configured to send data to or receive data from the memory die 102. The computing die 108 is coupled to the base die 104 via an interface 106. The interface 106 may include bonding contacts (e.g., as per the context of...). Figure 3A and Figure 6A (as described) or intermediary layer (e.g., as about Figure 3D and Figure 6D The described connection is provided. In some implementations, interface 106 includes a connection provided by any suitable combination of the foregoing techniques.

[0141] System 100 may also include an external host die 112 coupled to computing die 108 via interface 110. For example, external host die 112 may be a computer, and computing die 108 may be the CPU of the computer. In this example, interface 110 includes a connection provided by the motherboard of the computer coupled to the CPU. As another example, external host die 112 is a graphics card, computing die 108 is the GPU of the graphics card, and interface 110 includes a connection provided by the printed circuit board (PCB) of the graphics card coupled to the GPU.

[0142] System 100 may also include a memory controller (also referred to as controller circuitry) coupled to memory die 102. Figure 1 (Not shown in the diagram). In some embodiments, the memory controller is located within the computing die 108. Consistent with embodiments of this disclosure, the memory controller may include conductive interconnects through a cover layer contacting conductive pads in a conductive pad layer, and the memory controller may be coupled to the memory die 102 via at least one of the conductive interconnects. The memory controller is configured to control the memory die 102. For example, the memory controller may be configured to operate a channel structure via word lines. The memory controller may manage data stored in the memory die 102 and communicate with the computing die 108.

[0143] In some implementations, the memory controller is designed / configured to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB), flash drives, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones. In some implementations, the memory controller is designed / configured to operate in high duty cycle environments, such as SSDs or embedded multimedia cards (eMMCs), serving as data storage for mobile devices (such as smartphones, tablets, laptops, etc.) and enterprise storage arrays. The memory controller may be configured to control the operation of memory die 102, such as read, erase, and program (or write) operations. The memory controller may also be configured to manage various functions regarding data stored or to be stored in memory die 102, including (but not limited to) bad block management, garbage collection, logic-to-physical address translation, wear leveling, etc. In some implementations, the memory controller is also configured to process error correction codes (ECC) for data read from or written to memory die 102. In some other implementations, the base die 104, rather than the memory controller, is configured to process ECC. The memory controller may also perform any other suitable function, such as formatting memory die 102.

[0144] The memory controller can communicate with external devices (e.g., computing die 108) according to a specific communication protocol. For example, the memory controller can communicate with external devices through at least one of a variety of interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-Express (PCIe or PCI-e), Advanced Technology Attachment (ATA), Serial-ATA, Parallel-ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, etc.

[0145] The memory controller and one or more memory dies 102 can be integrated into various types of storage devices, for example, included in the same package, such as a Universal Flash Memory (UFS) package or an eMMC package. That is, the system 100 can be implemented and packaged into different types of end electronic products. For example, the memory controller and a single memory die 102 can be integrated into a memory card. Memory cards can include PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, Smart Media (SM) cards, Memory Sticks, Multimedia Cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc.

[0146] Figures 2A-2E Example semiconductor devices 200 and 200d are shown according to some aspects of this disclosure. Semiconductor devices 200 or 200d can be used to form memory devices, such as HBM.

[0147] Note that in Figures 2A-2E The X, Y, and Z axes (also referred to as the X, Y, and Z directions) are included to further illustrate the spatial relationships of various components in a semiconductor device. The substrate of the semiconductor device includes two lateral surfaces extending laterally in the XY plane: a top surface on the front side of the wafer, on which components of the semiconductor device may be formed; and a bottom surface on the back side opposite the front side of the wafer. The Z direction is perpendicular to the X and Y directions. As used herein, when the substrate is positioned in the lowest plane of the semiconductor device in the Z direction (a direction perpendicular to the XY plane, e.g., the thickness direction of the substrate), the Z direction relative to the substrate of the semiconductor device determines whether one component (e.g., a layer or device) of the semiconductor device is “on,” “above,” or “below” another component (e.g., a layer or device). The same concepts used to describe spatial relationships are applied throughout this disclosure.

[0148] like Figure 2AAs shown, semiconductor device 200 includes a stack 202 of memory dies 204a-204d. Each of the memory dies 204a-204d may be a dynamic random access memory (DRAM) device. The memory dies 204a-204d are stacked along a vertical direction (e.g., the Z direction) (e.g., sequentially). The stack 202 includes one or more device regions 206 and one or more connection regions 208. Each of the memory dies 204a-204d may include a memory array and peripheral circuitry in each device region 206. The memory array may include an array of memory cells, and the peripheral circuitry may be coupled to the memory array.

[0149] The semiconductor device 200 also includes contact structures 210 in the connection region 208. Each contact structure 210 may extend into one of the memory dies 204a-204d and may be outwardly coupled to external components outside the stack 202. As described in further detail with reference to some other figures in this disclosure, each contact structure 210 may include a conductive material and may be connected to a conductive layer of one of the memory dies 204a-204d. In some embodiments, adjacent memory dies (e.g., memory dies 204a and 204b) in the memory devices 204a-204d are bonded together by corresponding bonding layers ( Figure 2A (Not shown in the image) bonding. The semiconductor device 200 may also include a base die 212. The stack 202 may be stacked on the base die 212 in a vertical direction. In some embodiments, the memory die 204a and the base die 212 are bonded together by another bonding layer (not shown in the image). Figure 2A (Not shown in the image) Bonding.

[0150] Figure 2B Semiconductor device 200 along some aspects of this disclosure is shown. Figure 2A A cross-sectional view of the cutting line AA'. The semiconductor device 200 includes two device regions 206 arranged in a horizontal direction (e.g., the X direction). The semiconductor device 200 also includes a connection region 208 along the X direction between the two device regions 206. Although Figure 2B An example arrangement of device region(s) 206 and connection region(s) 208 is shown, but any other suitable arrangement is possible. In some embodiments, the semiconductor device 200 may include a device region 206 and a connection region 208 adjacent to each other along the X direction. In some embodiments, such as Figure 2EAs shown, the semiconductor device 200 may include two connection regions 208 arranged along the X direction and a device region 206 between the two connection regions 208 along the X direction. In some embodiments, the semiconductor device 200 may include a first connection region 208, a second connection region 208, and a device region 206 arranged along the X direction. The first connection region 208 may be at the center of the semiconductor device 200, and the second connection region 208 may be on one side of the first connection region 208 (e.g., on the left). The device region 206 may be on the other side of the first connection region 208 (e.g., on the right). In some embodiments, the connection region 208 may not include word lines in the memory dies 204a-204d. In this way, the contact structure 210 in the connection region 208 may bypass the conductive material (e.g., metal) of the word lines in the memory dies 204a-204d and may extend through the dielectric material (e.g., the insulating layer or substrate of the memory device), thereby making the manufacture of the semiconductor device 200 cost-effective. The cross-sections (e.g., in the XY plane) of one or more connection regions 208 and the cross-sections (e.g., in the XY plane) of one or more device regions 206 can have any suitable dimensions. For example, in Figure 2B In this embodiment, the ratio of the cross-sectional dimension of the connection region 208 to the sum of the cross-sectional dimensions of the device regions 206 (on the left and right) can be within any suitable range (e.g., between 1 / 6 and 1 / 5). The cross-sections of the connection region 208 and the two device regions 206 can be in the XY plane. In some embodiments, placing one or more device regions 206 at the center of the semiconductor device 200 and placing one or more connection regions 208 on one or both sides of the device regions 206 in the horizontal direction can make the bonding between the memory dies 204a-204d more stable.

[0151] In some implementations, each connection region 208 may include more than 1,000 contact structures 210. Each contact structure 210 may have a critical dimension (CD) within any suitable range (e.g., between 0.5 micrometers (μm) and 10 μm).

[0152] Figure 2C Semiconductor device 200 along some aspects of this disclosure is shown. Figure 2AA cross-sectional view of the cut line BB'. The memory die 204a includes a substrate 220a extending along the X direction. The substrate 220a can be any suitable semiconductor substrate having any suitable semiconductor material, such as single-crystal, polycrystalline, or single-crystal semiconductor. For example, the substrate 220a can include silicon, silicon germanium (SiGe), germanium (Ge), gallium arsenide (GaAs), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium nitride, silicon carbide, III-V compounds, or any combination thereof. The memory die 204a also includes conductive layers 222a and 224a. Each of the conductive layers 222a and 224a extends from device region 206 to connection region 208 and can be coupled to the memory array of the memory die 204a or peripheral circuitry of the memory array in device region 206. For example, conductive layers 222a and 224a can be coupled to the input / output ports of the memory die 204a. In some embodiments, conductive layers 222a and 224a may be configured to provide one or more of a power supply, clock signal, or data path signal to memory die 204a. Each of memory dies 204b-204d also includes its respective substrates 220b-220d and conductive layers (e.g., 222b and 224b, 222c and 224c, 222d and 224d). The conductive layers in each of memory dies 204b-204d are also coupled to a corresponding memory array or peripheral circuitry of the memory die. Similar to conductive layers 222a and 224a, the conductive layers in each of memory dies 204b-204d may also be configured to provide one or more of a power supply, clock signal, or data path signal to the memory die.

[0153] In some embodiments, some of the memory dies 204a-204d can have a reduced thickness (along the Z direction) by thinning their substrate. For example... Figure 2C As shown, each of substrates 220a-220c is thinned, but substrate 220d is not thinned. Therefore, the thickness of each of memory dies 204a-204c is less than the thickness of memory die 204d. The thickness of each of memory dies 204a-204d can be within any suitable range (e.g., between 3 μm and 20 μm).

[0154] Semiconductor device 200 includes bonding layers 221a-221c. For example... Figure 2CAs shown, each of the bonding layers 221a-221c is between two memory dies 204a-204d. Memory dies 204a and 204b are bonded via bonding layer 221a. Memory dies 204b and 204c are bonded via bonding layer 221b. Memory dies 204c and 204d are bonded via bonding layer 221c. Some other figures in this disclosure (e.g., Figure 3B The detailed structure of bonding layers 221a-221c is described. In some embodiments, the semiconductor device 200 includes a device (not shown) on top of the memory die 204a. The device and the memory die 204a can be bonded together via another bonding layer (not shown) between the device and the memory die 204a.

[0155] Semiconductor device 200 includes contact structures 226a-226d and 228a-228d in connection region 208. Contact structures 226a-226d and 228a-228d can be... Figure 2A-2B An example of contact structure 210 is provided. Contact structure 226a may include an inner layer 230 surrounded by an outer layer 232. That is, the inner layer 230 is on the inner surface of the outer layer 232. The inner layer 230 may include a conductive material (e.g., copper or tungsten), and the outer layer 232 may include an insulating material (e.g., silicon oxide). Similarly, each of contact structures 226b-226d and 228a-228d also includes a conductive inner layer and an insulating outer layer. Contact structures 226a-226d and 228a-228d extend in a vertical direction (e.g., the Z direction).

[0156] In some embodiments, each of the contact structures 226a-226d and 228a-228d is a continuous structure extending along the Z direction. That is, each of the contact structures 226a-226d and 228a-228d includes a continuous inner layer and a continuous outer layer, both extending along the Z direction.

[0157] In some embodiments, each of the contact structures 226a-226d and 228a-228d may have a shape similar to a cylinder or a truncated cone. In some embodiments, the dimension of a first cross-section of the contact structure at a first location along the Z direction is larger than the dimension of a second cross-section of the contact structure at a second location along the Z direction. The first and second cross-sections may be perpendicular to the Z direction. The first location is further away from the thickest memory die among the memory dies 204a-204d than the second location. For example, contact structure 226d may have a cross-section in memory die 204a and another cross-section in memory die 204b. The dimension of the cross-section in memory die 204a may be larger than the dimension of the cross-section in memory die 204b. In some embodiments, contact structures 226a-226d and 228a-228d may be formed by the same process (e.g., as per [reference to...]). Figure 4G-4I (More detailed description)

[0158] Contact structures 226a and 228a extend into the memory die 204a but do not extend through the bonding layer 221a. Contact structures 226a and 228a are connected to the conductive layers 222a and 224a of the memory die 204a, respectively. Contact structures 226b and 228b extend through the memory die 204a (including the substrate 220a) and the bonding layer 221a and enter the memory die 204b, but do not extend through the bonding layer 221b. Contact structures 226b and 228b are connected to the conductive layers 222b and 224b of the memory die 204b, respectively. Contact structure 226b does not extend through the conductive layer 222a, and contact structure 228b does not extend through the conductive layer 224a. Contact structures 226c and 228c extend through memory die 204a (including substrate 220a), bonding layer 221a, memory die 204b (including substrate 220b), and bonding layer 221b and enter memory die 204c, but do not extend through bonding layer 221c. Contact structures 226c and 228c are connected to conductive layers 222c and 224c of memory die 204c, respectively. Contact structure 226c does not extend through conductive layers 222a and 222b, and contact structure 228c does not extend through conductive layers 224a and 224b. Contact structures 226d and 228d extend through memory die 204a (including substrate 220a), bonding layer 221a, memory die 204b (including substrate 220b), bonding layer 221b, memory die 204c (including substrate 220c), and bonding layer 221c and enter memory die 204d. Contact structures 226d and 228d are connected to conductive layers 222d and 224d of memory device 204d, respectively. Contact structure 226d does not extend through conductive layers 222a, 222b, and 222c, and contact structure 228d does not extend through conductive layers 224a, 224b, and 224c.

[0159] In some embodiments, conductive layers 222a-222d may be formed in a stepped structure to allow each of the contact structures 226a-226d to connect to one of the conductive layers 222a-222d without extending through the other conductive layers. In some embodiments, such as Figure 2CAs shown, conductive layers 222a-222d can have various lengths. Conductive layers 222a-222d can extend from substantially the same position in the X direction and extend by different lengths (e.g., to the right) to form a stepped structure. Specifically, contact structure 226b is located along the X direction between end 234a (e.g., on the right) of conductive layer 222a and end 234b (e.g., on the right) of conductive layer 222b. That is, end 234a of conductive layer 222a is located along the X direction between contact structure 226a and contact structure 226b. Thus, contact structure 226b can extend through memory die 204a and around the conductive layer 222a of memory die 204a (e.g., not extending through conductive layer 222a). Similarly, contact structure 226c is positioned along the X direction between end 234b of conductive layer 222b and end 234c of conductive layer 222c (e.g., on the right side), such that contact structure 226c can extend through memory die 204a-204b and around conductive layers 222a-222b (e.g., not extending through conductive layers 222a-222b). Additionally, contact structure 226d is positioned along the X direction between end 234c of conductive layer 222c and end 234d of conductive layer 222d (e.g., on the right side), such that contact structure 226d can extend through memory die 204a-204c and around conductive layers 222a-222c (e.g., not extending through conductive layers 222a-222c).

[0160] In a similar manner, conductive layers 224a-224d can also be formed into a stepped structure to allow each of the contact structures 228a-228d to connect to one of the conductive layers 224a-224d without extending through the other conductive layers. Although Figure 2C An example is shown in which the stepped structure is formed by conductive layers of different lengths, but other suitable ways of arranging the conductive layers are also possible (e.g., as discussed in...). Figure 3A , Figure 3D , Figure 3E , Figure 3G and Figure 3H (More detailed description)

[0161] Figure 2D A cross-sectional view of a semiconductor device 200d along dicing line BB' is shown, representing some aspects of this disclosure. Semiconductor device 200d and... Figure 2C The difference between the semiconductor device 200 and the semiconductor device 200d is that the memory dies 204a-204d of the semiconductor device 200d may include conductive layers of the same length and located at the same position along the X direction. For example... Figure 2DAs shown, memory die 204a includes conductive layers 236a and 238a. Each of conductive layers 236a and 238a extends from device region 206 to connection region 208 and is coupled to the memory array of memory die 204a or peripheral circuitry of the memory array in device region 206. For example, conductive layers 236a and 238a may be coupled to input / output ports of memory die 204a. In some embodiments, conductive layers 236a and 238a may be configured to provide one or more of power, clock, or data path signals to memory die 204a. Each of memory dies 204b-204d also includes their respective conductive layers (e.g., 236b and 238b, 236c and 238c, 236d and 238d). The conductive layers in each of memory dies 204b-204d are also coupled to the corresponding memory array or peripheral circuitry of each memory die. Similar to conductive layers 236a and 238a, the conductive layers in each of memory dies 204b-204d can also be configured to provide one or more of power, clock, or data path signals to the memory die. Conductive layers 236a-236d have the same length and are located at the same position along the X-direction. Similarly, conductive layers 238a-238d also have the same length and are located at the same position along the X-direction. In some embodiments, conductive layers 236a-236d have the same shape, and conductive layers 238a-238d have the same shape. Because the same mask can be used to form the conductive layers in each memory die, manufacturing costs can be reduced.

[0162] Semiconductor device 200d includes contact structures 226a-226d and 228a-228d extending in a vertical direction (e.g., the Z direction). Contact structures 226a and 228a extend into a memory die 204a but not through a bonding layer 221a. Contact structures 226a and 228a are connected to conductive layers 236a and 238a of the memory die 204a, respectively. Contact structures 226b and 228b extend through the memory die 204a (including substrate 220a) and the bonding layer 221a and into the memory die 204b, but not through the bonding layer 221b. Contact structure 226b extends through conductive layer 236a, and contact structure 228b extends through conductive layer 238a. Contact structures 226b and 228b are connected to conductive layers 236b and 238b of the memory die 204b, respectively. Contact structures 226c and 228c extend through memory die 204a (including substrate 220a), bonding layer 221a, memory die 204b (including substrate 220b), and bonding layer 221b and enter memory die 204c, but do not extend through bonding layer 221c. Contact structure 226c extends through conductive layers 236a-236b, and contact structure 228c extends through conductive layers 238a-238b. Contact structures 226c and 228c are respectively connected to conductive layers 236c and 238c of memory die 204c. Contact structures 226d and 228d extend through memory die 204a (including substrate 220a), bonding layer 221a, memory die 204b (including substrate 220b), bonding layer 221b, memory die 204c (including substrate 220c), and bonding layer 221c and enter memory die 204d, but do not extend through memory die 204d. Contact structure 226d extends through conductive layers 236a-236c, and contact structure 228d extends through conductive layers 238a-238c. Contact structures 226d and 228d are respectively connected to conductive layers 236d and 238d of memory die 204d.

[0163] In some embodiments, for each of contact structures 226a-226d and 228a-228d, the outer layer of the contact structure lies between the inner layer of the contact structure and the conductive layer through which the contact structure extends. The outer layer may insulate the inner layer from the conductive layer through which the contact structure extends.

[0164] Although Figures 2A-2ESome of the other figures in this disclosure illustrate examples in which the contact structure is coupled to a stacked memory die, but any other suitable semiconductor device or die may also be stacked and coupled to the contact structure using a similar technique. This technology can be applied to various types of semiconductor devices, volatile memory devices (e.g., DRAM memory devices), or non-volatile memory (NVM) devices (e.g., NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase-change memory (PCM) (e.g., PCRAM, STT-MRAM)), and so on. It can also be applied to charge-trapping based memory devices (e.g., silicon-oxide-nitride-oxide-silicon (SONOS) memory devices) and floating-gate based memory devices. This technology can be applied to three-dimensional (3D) memory devices. It can be applied to various memory types, such as SLC (single-level cell) devices, MLC (multi-level cell) devices such as two-level cell devices, TLC (three-level cell) devices, QLC (four-level cell) devices, or PLC (five-level cell) devices. Alternatively or concurrently, this technology can be applied to various types of devices and systems, such as secure digital cards (SD cards), embedded multimedia cards (eMMC), solid-state drives (SSDs), embedded systems, etc.

[0165] Figure 3A A side view of a semiconductor device 300a according to some aspects of this disclosure is shown. The semiconductor device 300a includes memory dies 302a-308a, a base die 344a, a computing die 346a, and an interposer 348a stacked along a vertical direction (e.g., the Z direction) (e.g., sequentially). The memory dies 302a-308a may be... Figure 1 The memory die 102 and Figure 2A Examples of memory dies 204a-204d (e.g., DRAM). The stack of memory dies 302a-308a includes a device region 301a and a connection region 303a adjacent to each other in a horizontal direction (e.g., the X direction). Memory dies 302a-308a include conductive layers 310a-316a extending respectively in a horizontal direction (e.g., the X direction). Each of conductive layers 310a-316a has one end coupled to a memory array or peripheral circuitry in the corresponding memory die in device region 301a and another end extending away from device region 301a (e.g., ends 318a-324a). Each of conductive layers 310a-316a may be coupled to an input / output port of the corresponding memory die, or may be configured to provide one or more of power, clock, or data path signals to the corresponding memory die.

[0166] like Figure 3AAs shown, the semiconductor device 300a includes contact structures 326a-332a in the connection region 303a. The contact structures 326a-332a can be... Figure 2A-2B An example of contact structure 210. Semiconductor device 300a also includes bonding layers between adjacent memory dies 302a-308a (e.g., bonding layers 334a, 336a, and 338a), a bonding layer 340a between memory die 302a and base die 344a, and a bonding layer 342a between base die 344a and computing die 346a. Each of these bonding layers may include a dielectric material such as silicon oxide.

[0167] Contact structures 326a-332a extend in a vertical direction (e.g., the Z direction) and are coupled to conductive layers 310a-316a, respectively. Contact structure 326a extends into memory die 302a and connects to conductive layer 310a of memory die 302a, but does not extend through bonding layer 334a. Contact structure 328a extends through memory die 302a and bonding layer 334a into memory die 304a, but does not extend through bonding layer 336a. Contact structure 328a is connected to conductive layer 312a of memory die 304a, but does not extend through conductive layer 310a. Contact structure 330a extends through memory dies 302a-304a, bonding layers 334a and 336a into memory die 306a, but does not extend through bonding layer 338a. Contact structure 330a is connected to conductive layer 314a of memory die 306a, but does not extend through conductive layers 310a and 312a. Contact structure 332a extends through memory dies 302a-306a and bonding layers 334a-338a into memory die 308a, but does not extend through memory die 308a. Contact structure 332a is connected to conductive layer 316a of memory die 308a, but does not extend through conductive layers 310a-314a.

[0168] Conductive layers 310a-316a can be formed in a stepped structure to allow each of the contact structures 326a-332a to connect to one of the conductive layers 310a-316a without extending through the other conductive layers. In some embodiments, such as Figure 3AAs shown, conductive layers 310a-316a can have the same length and be offset along the X direction. That is, the ends 318a-324a (e.g., the right-hand ends) of conductive layers 310a-316a can be offset along the X direction. Specifically, contact structure 328a is located along the X direction between end 318a of conductive layer 310a and end 320a of conductive layer 312a. That is, end 318a of conductive layer 310a is located along the X direction between contact structure 326a and contact structure 328a. In this way, contact structure 328a can extend through memory die 302a and bypass conductive layer 310a of memory die 302a. Similarly, contact structure 330a is located along the X direction between end 320a of conductive layer 312a and end 322a of conductive layer 314a, allowing contact structure 330a to extend through memory dies 302a-304a and around conductive layers 310a-312a. Additionally, contact structure 332a is located along the X direction between end 322a of conductive layer 314a and end 324a of conductive layer 316a, allowing contact structure 332a to extend through memory dies 302a-306a and around conductive layers 310a-314a. It should be understood that, as Figure 3A The example stepped structure formed by conductive layers 310a-316a shown is for illustrative purposes and is not intended to be interpreted in a limiting sense. Figure 3H Different structures formed by the conductive layers of the semiconductor device 300h are shown, which may also allow each contact structure of the semiconductor device 300h to be connected to one of the conductive layers of the semiconductor device 300h without extending through other conductive layers.

[0169] In some embodiments, bonding layers 334a, 336a, and 338a may be referred to as direct bonding layers because they are formed by direct dielectric-dielectric bonding. Each of bonding layers 334a, 336a, and 338a may include at least one dielectric material and does not include conductive bonding contacts. In some embodiments, bonding layers 340a and 342a may be referred to as hybrid bonding layers because they can be formed by a mixture of dielectric-dielectric bonding and metal-metal bonding. Each of bonding layers 340a and 342a may include bonding contacts (e.g., conductive bonding contacts) and at least one dielectric material that isolates the bonding contacts. Figure 3A As shown, the bonding layer 340a includes conductive bonding contacts 354a. The conductive bonding contacts 354a can be configured to connect the memory die 302a and the base die 344a. In some embodiments, the memory die 302a may include an interconnect layer in contact with the bonding layer 340a. Figure 3A (Not shown in the image). The interconnect layer of memory die 302a has a connection with... Figure 3FThe interconnect layer 345f described herein has a similar structure. Each of the contact structures 326a-332a can be coupled to the interconnect layer of the memory die 302a. The interconnect layer of the memory die 302a can be coupled to the base die 344a through conductive bonding contacts 354a in the bonding layer 340a. The base die 344a includes a via 350a extending along the Z direction through the base die 344a and connecting to the conductive bonding contacts 354a. Each of the contact structures 326a-332a is coupled to a corresponding via 350a through a corresponding conductive bonding contact 354a. The bonding layer 342a includes conductive bonding contacts 356a. The conductive bonding contacts 356a can be configured to connect the base die 344a and the computing die 346a. The computing die 346a can be... Figure 1 An example of computing die 108. Computing die 346a includes a via 352a extending along the Z-direction through computing die 346a and connected to a conductive bonding contact 356a. Each via 350a is coupled to a corresponding via 352a via a corresponding conductive bonding contact 356a. In some embodiments, vias 350a and 352a may be through-silicon vias (TSVs). See later. Figure 3B and Figure 3C The structures of bonding layers 334a, 336a, 338a, 340a and 342a are described in further detail.

[0170] In some embodiments, the base die 344a includes control circuitry configured to control memory dies 302a-308a. The control circuitry may be coupled to memory dies 302a-308a, for example, via contact structures 326a-332a, the interconnect layer of memory die 302a, and conductive bonding contacts 354a.

[0171] Intermediate layer 348a has surface 358a and surface 360a. Surface 358a can be bonded to computing die 346a. Conductive terminal 362a can be connected to surface 360a. Intermediate layer 348a may include interconnects connecting vias 352a of computing device 346a to conductive terminal 362a. Conductive terminal 362a can be coupled to external devices (e.g., Figure 1 (External host die 112). In some embodiments, the conductive terminal 362a may be a microbump.

[0172] In some implementations, such as Figure 3AAs shown, memory dies 302a-306a can have a reduced thickness (along the Z direction) by thinning their substrate. The topmost memory die 308a (e.g., the one furthest from the base die 344a among memory dies 302a-308a) may not be thinned. Therefore, the thickness of each of memory dies 302a-306a can be less than the thickness of memory die 308a. The thickness of each of memory dies 302a-308a can be within any suitable range (e.g., between 3 μm and 20 μm).

[0173] Figure 3B This disclosure illustrates some aspects of the content. Figure 3A Figure 300b shows an enlarged view of the bonding layer 334a. The bonding layer 334a may include a top bonding layer 333b and a bottom bonding layer 337b bonded at a bonding interface 335b. Each of the top bonding layer 333b and the bottom bonding layer 337b may include a dielectric material (including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof) and may not include conductive bonding contacts. The memory die 304a may be bonded to the top of the memory die 302a face-to-face via the bonding layer 334a. As a result of direct bonding (e.g., dielectric-dielectric bonding), the bonding interface 335b is disposed between the top bonding layer 333b and the bottom bonding layer 337b, where direct bonding forms a bond between the surfaces without the use of an intermediate layer, such as solder or adhesive. In some embodiments, for example, when the dielectric material of the top bonding layer 333b and the dielectric material of the bottom bonding layer 337b are different materials, the bonding interface 335b can be a visible layer of a certain thickness, including the top surface of the bottom bonding layer 337b and the bottom surface of the top bonding layer 333b. In some embodiments, for example, when the dielectric material of the top bonding layer 333b and the dielectric material of the bottom bonding layer 337b are the same material, the bonding interface 335b can be invisible and can form a continuous portion with the top bonding layer 333b and the bottom bonding layer 337b. Figure 3A The bonding layers 336a and 338a can have the same properties as... Figure 3B The structure is similar to that of the bonding layer 334a described in the text.

[0174] Figure 3C This disclosure illustrates some aspects of the content. Figure 3AFigure 300c shows an enlarged view of the bonding layer 340a. The bonding layer 340a may include a top bonding layer 343c and a bottom bonding layer 347c bonded at a bonding interface 345c. The top bonding layer 343c includes conductive bonding contacts 341c and a dielectric material 339c that isolates the conductive bonding contacts 341c. The conductive bonding contacts 341c may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicides, or any combination thereof. The dielectric material 339c may include dielectrics, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. Similarly, the bottom bonding layer 347c includes conductive bonding contacts 349c and a dielectric material 351c that isolates the conductive bonding contacts 349c. The conductive bonding contact 349c may include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicides, or any combination thereof. The dielectric material 351c may include a dielectric, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0175] Conductive bonding contacts 341c and 349c can be Figure 3A An example of conductive bonding contact 354a. Conductive bonding contact 341c contacts conductive bonding contact 349c at bonding interface 345c. Memory die 302a can be bonded to the top of base die 344a face-to-face via bonding layer 340a. As a result of hybrid bonding (e.g., metal-metal / dielectric-dielectric bonding), bonding interface 345c is disposed between top bonding layer 343c and bottom bonding layer 347c. Hybrid bonding forms a bond between surfaces without the use of intermediate layers, such as solder or adhesive, and can simultaneously achieve metal-metal bonding and dielectric-dielectric bonding. In some embodiments, for example, when the dielectric material 339c of the top bonding layer 343c and the dielectric material 351c of the bottom bonding layer 347c are different materials, the bonding interface 345c can be a visible layer of a certain thickness, including the top surface of the bottom bonding layer 347c and the bottom surface of the top bonding layer 343c. In some embodiments, for example, when the dielectric material 339c and the dielectric material 351c are the same material, the bonding interface 345c can be invisible and can form a continuous portion with the top bonding layer 343c and the bottom bonding layer 347c. Figure 3A The bonding layer 342a can have the same as Figure 3C The structure is similar to that of the bonding layer 340a described in the text.

[0176] Figure 3DA side view of a semiconductor device 300d according to some aspects of this disclosure is shown. The semiconductor device 300d includes memory dies 302d-308d, a base die 344d, a computing die 346d, and an interposer 348d. The memory dies 302d-308d and the base die 344d are stacked along the Z direction (e.g., sequentially). The base die 344d and the computing die 346d are integrated along the X direction at different locations on the interposer 348d. The memory dies 302d-308d are similar to... Figure 3A The memory dies are 302a-308a. The memory dies are 302d-308d. Figure 1 The memory die 102 and Figure 2A Examples of memory dies 204a-204d (e.g., DRAM). The stack of memory dies 302d-308d includes a device region 301d and a connection region 303d adjacent to the device region 301d in a horizontal direction (e.g., the X direction). Memory dies 302d-308d include conductive layers 310d-316d extending in a horizontal direction (e.g., the X direction), respectively. Each of conductive layers 310d-316d has one end coupled to a memory array or peripheral circuitry in the corresponding memory die in the device region 301d and another end extending away from the device region 301d (e.g., ends 318d-324d). Each of conductive layers 310d-316d may be coupled to an input / output port of the corresponding memory die, or may be configured to provide one or more of power, clock, or data path signals to the corresponding memory die.

[0177] like Figure 3D As shown, the semiconductor device 300d includes contact structures 326d-332d in the connection region 303d. The contact structures 326d-332d can be... Figure 2A-2B An example of contact structure 210. The semiconductor device 300d also includes bonding layers between adjacent memory dies in memory dies 302d-308d (e.g., bonding layers 334d, 336d, and 338d) and a bonding layer 340d between memory die 302d and base die 344d. Each of these bonding layers may include a dielectric material such as silicon oxide.

[0178] Contact structures 326d-332d extend in a vertical direction (e.g., the Z direction) and are coupled to conductive layers 310d-316d, respectively. Contact structure 326d extends into memory die 302d and connects to conductive layer 310d of memory die 302d, but does not extend through bonding layer 334d. Contact structure 328d extends through memory die 302d and bonding layer 334d into memory die 304d, but does not extend through bonding layer 336d. Contact structure 328d is connected to conductive layer 312d of memory die 304d, but does not extend through conductive layer 310d. Contact structure 330d extends through memory dies 302d-304d and bonding layers 334d and 336d into memory die 306d, but does not extend through bonding layer 338d. Contact structure 330d connects to conductive layer 314d of memory die 306d without extending through conductive layers 310d and 312d. Contact structure 332d extends through memory dies 302d-306d into memory die 308d without extending through memory die 308d. Contact structure 332d connects to conductive layer 316d of memory die 308d without extending through conductive layers 310d-314d.

[0179] Conductive layers 310d-316d can be formed into a stepped structure to allow each of the contact structures 326d-332d to connect to one of the conductive layers 310d-316d without extending through the other conductive layers. In some embodiments, such as Figure 3D As shown, conductive layers 310d-316d can have the same length and be offset along the X direction. That is, the ends 318d-324d of conductive layers 310d-316d (e.g., the right-hand ends) can be offset along the X direction. Specifically, contact structure 328d is located along the X direction between end 318d of conductive layer 310d and end 320d of conductive layer 312d. That is, end 318d of conductive layer 310d is located along the X direction between contact structure 326d and contact structure 328d. In this way, contact structure 328d can extend through memory die 302d and bypass conductive layer 310d of memory die 302d. Similarly, contact structure 330d is located along the X direction between end 320d of conductive layer 312d and end 322d of conductive layer 314d, allowing contact structure 330d to extend through memory die 302d-304d and around conductive layers 310d-312d. Additionally, contact structure 332d is located along the X direction between end 322d of conductive layer 314d and end 324d of conductive layer 316d, allowing contact structure 332d to extend through memory die 302d-306d and around conductive layers 310d-314d.

[0180] In some implementations, bonding layers 334d, 336d, and 338d may be referred to as direct bonding layers, and may have the same characteristics as... Figure 3B The structure is similar to that of bonding layer 334a described herein. Each of bonding layers 334d, 336d, and 338d may include at least one dielectric material and does not include conductive bonding contacts. In some embodiments, bonding layer 340d may be referred to as a hybrid bonding layer and may have a structure similar to... Figure 3C The bonding layer 340a described herein has a similar structure. The bonding layer 340d may include bonding contacts (e.g., such as...). Figure 3D The conductive bonding contact 354d shown is a dielectric material for both the conductive bonding contact 354d and the insulating bonding contact. The conductive bonding contact 354d can be configured to connect the memory die 302d and the base die 344d. In some embodiments, the memory die 302d may include an interconnect layer ( ) in contact with the bonding layer 340d. Figure 3D (Not shown in the image). The interconnect layer of memory die 302d has the same characteristics as... Figure 3F The interconnect layer 345F described herein has a similar structure. Each of the contact structures 326d-332d can be coupled to the interconnect layer of the memory die 302d. The interconnect layer of the memory die 302d can be coupled to the base die 344d through conductive bonding contacts 354d in the bonding layer 340d. The base die 344d includes a via 350d extending along the Z direction through the base die 344d and connecting to the conductive bonding contacts 354d. Each of the contact structures 326d-332d is coupled to a corresponding via 350d through a corresponding conductive bonding contact 354d. In some embodiments, the via 350d may be a TSV.

[0181] In some embodiments, the base die 344d includes control circuitry configured to control memory dies 302d-308d. The control circuitry may be coupled to memory dies 302d-308d, for example, via contact structures 326d-332d, the interconnect layer of memory die 302d, and conductive bonding contacts 354d.

[0182] A base die 344d can be coupled to a computing die 346d via an interposer 348d. The interposer 348d has a surface 358d and a surface 360d. A via 350d in the base die 344d can be connected to a conductive terminal 364d on the surface 358d of the interposer 348d. The computing die 346d can be connected to a conductive terminal 366d on the surface 358d of the interposer 348d. The semiconductor device 300d may include a conductive terminal 362d connected to the surface 360d of the interposer 348d. The conductive terminals 364d, 366d, and 362d can be coupled via conductive lines in the interposer 348d (e.g., as shown in the image). Figure 3DThe conductive line 369d shown is coupled. The conductive terminal 362d can be coupled to an external device (e.g., Figure 1 The external host die 112). In some embodiments, conductive terminals 364d, 366d, and 362d may be microbumps. It should be understood that in practice, the base die 344d, the computing die 346d, and the interposer 348d may be integrated together using any suitable packaging technology, including, for example, chip-on-wafer-on-substrate (CoWoS).

[0183] In some implementations, such as Figure 3D As shown, memory dies 302d-306d can have reduced thickness (along the Z direction) by thinning their substrate. The topmost memory die 308d (e.g., the one furthest from the base die 344d among memory dies 302d-308d) may not be thinned. Therefore, the thickness of each of memory dies 302d-306d can be less than the thickness of memory die 308d. The thickness of each of memory dies 302d-308d can be within any suitable range (e.g., between 3 μm and 20 μm).

[0184] Figure 3E A side view of a semiconductor device 300e according to some aspects of this disclosure is shown. The semiconductor device 300e includes memory dies 302e-308e, a base die 344e, a computing die 346e, and an interposer 348e stacked along a vertical direction (e.g., the Z direction) (e.g., sequentially). The memory dies 302e-308e are similar to... Figure 3A The memory dies are 302a-308a. The memory dies are 302e-308e. Figure 1 The memory die 102 and Figure 2A Examples of memory dies 204a-204d (e.g., DRAM). The stack of memory dies 302e-308e includes a device region 301e and a connection region 303e adjacent to the device region 301e in a horizontal direction (e.g., the X direction). Memory dies 302e-308e include conductive layers 310e-316e extending in a horizontal direction (e.g., the X direction), respectively. Each of the conductive layers 310e-316e has one end coupled to a memory array or peripheral circuitry in the corresponding memory die in the device region 301e and another end extending away from the device region 301e (e.g., ends 318e-324e). Each of the conductive layers 310e-316e may be coupled to an input / output port of the corresponding memory die, or may be configured to provide one or more of power, clock, or data path signals to the corresponding memory die.

[0185] like Figure 3E As shown, the semiconductor device 300e includes contact structures 326e-332e in the connection region 303e. The contact structures 326e-332e can be... Figure 2A-2B An example of contact structure 210. Semiconductor device 300e also includes bonding layers (e.g., bonding layers 334e, 336e, and 338e) between adjacent memory dies 302e-308e and a bonding layer 340e between memory die 302e and base die 344e. Each of these bonding layers may include a dielectric material, silicon oxide. Base die 344e includes a surface 365e and another surface 367e. Surface 365e is bonded to memory die 302e via bonding layer 340e. Base die 344e also includes a conductive layer 368e and a contact structure 370e connected to the conductive layer 368e. Contact structure 370e extends into base die 344e in the Z direction. Conductive layer 368e includes an end 372e coupled to circuitry of base die 344e and another end 374e closer to contact structure 370e. In some implementations, bonding layers 334e, 336e, 338e, and 340e may be referred to as direct bonding layers, and may have the same characteristics as... Figure 3B The structure is similar to that of bonding layer 334A described herein. Each of bonding layers 334e, 336e, 338e, and 340e may include at least one dielectric material and does not include conductive bonding contacts. In some embodiments, bonding layer 342e may be referred to as a hybrid bonding layer and may have a structure similar to... Figure 3C The bonding layer 340a described herein has a similar structure. The bonding layer 342e may include bonding contacts (e.g., such as...). Figure 3E The conductive bonding contact 356e shown and the isolation bonding contact are made of at least one dielectric material.

[0186] Contact structures 370e and 326e-332e extend in a vertical direction (e.g., the Z direction) and are coupled to conductive layers 368e and 310e-316e, respectively. Specifically, contact structure 370e extends into the base die 344e without extending through the bonding layer 340e. Contact structure 326e extends through the bonding layer 340e into the memory die 302e without extending through the bonding layer 334e. Contact structure 326e is connected to the conductive layer 310e of the memory die 302e without extending through the conductive layer 368e. Contact structure 328e extends through the memory die 302e and bonding layers 340e and 334e into the memory die 304e without extending through the bonding layer 336e. Contact structure 328e is connected to the conductive layer 312e of the memory die 304e without extending through the conductive layers 368e and 310e. Contact structure 330e extends through memory dies 302e-304e and bonding layers 340e, 334e, and 336e and enters memory die 306e, but does not extend through bonding layer 338e. Contact structure 330e is connected to conductive layer 314e of memory die 306e, but does not extend through conductive layers 368e, 310e, and 312e. Contact structure 332e extends through memory dies 302e-306e and bonding layers 340e, 334e, 336e, and 338e and enters memory die 308e, but does not extend through memory die 308e. Contact structure 332e is connected to conductive layer 316e of memory die 308e, but does not extend through conductive layers 368e, 310e, 312e, and 314e.

[0187] Conductive layers 368e and 310e-316e can be formed into a stepped structure to allow each of the contact structures 370e and 326e-332e to connect to one of the conductive layers 368e and 310e-316e without extending through the other conductive layers. In some embodiments, such as Figure 3EAs shown, conductive layers 368e and 310e-316e are offset along the X direction. In some embodiments, conductive layers 310e-316e may have the same length. Specifically, the ends 374e and 318e-324e (e.g., the right-hand ends) of conductive layers 368e and 310e-316e may be offset along the X direction. Contact structure 326e is located along the X direction between the end 374e of conductive layer 368e and the end 318e of conductive layer 310e. That is, the end 374e of conductive layer 368e is located along the X direction between contact structure 370e and contact structure 326e. Thus, contact structure 326e can extend through the base die 344e and around the conductive layer 368e of the base die 344e. Contact structure 328e is located along the X direction between the end 318e of conductive layer 310e and the end 320e of conductive layer 312e. That is, the end 318e of the conductive layer 310e is located between the contact structure 326e and the contact structure 328e along the X direction. Thus, the contact structure 328e can extend through the memory die 302e and bypass the conductive layer 310e of the memory die 302e. Similarly, the contact structure 330e is located between the end 320e of the conductive layer 312e and the end 322e of the conductive layer 314e along the X direction, allowing the contact structure 330e to extend through the memory dies 302e-304e and bypass the conductive layers 310e-312e. Furthermore, the contact structure 332e is located between the end 322e of the conductive layer 314e and the end 324e of the conductive layer 316e along the X direction, allowing the contact structure 332e to extend through the memory dies 302e-306e and bypass the conductive layers 310e-314e.

[0188] The base die 344e may include an interconnect layer in contact with the bonding layer 342e. Figure 3E (Not shown in the diagram). Each of the contact structures 326e-332e and 370e can be coupled to the interconnect layer of the base die 344e. See later. Figure 3F A further detailed description of an example of the interconnect layer of the base die 344e is provided. The interconnect layer of the base die 344e can be coupled to the computing die 346e via conductive bonding contacts 356e in the bonding layer 342e. The conductive bonding contacts 356e can be configured to couple the base die 344e and memory dies 302e-308e to the computing die 346e. The computing die 346e can be... Figure 1 An example of computing die 108. Computing die 346e includes a via 352e extending along the Z-direction through computing die 346e and connected to conductive bonding contact 356e. Each of the contact structures 370e and 326e-332e can be coupled to a corresponding one of the vias 352e through the interconnect layer of the base die 344e and the corresponding conductive bonding contact 356e. In some embodiments, via 352e may be a TSV.

[0189] In some embodiments, the base die 344e includes control circuitry configured to control memory dies 302e-308e. The control circuitry may be coupled to memory dies 302e-308e, for example, via contact structures 370e and 326e-332e, the interconnect layer of the base die 344e, and conductive bonding contacts 356e.

[0190] Intermediate layer 348e has surface 358e and surface 360e. Surface 358e can be bonded to computing die 346e. Conductive terminal 362e can be connected to surface 360e. Intermediate layer 348e may include interconnects connecting vias 352e of computing die 346e to conductive terminal 362e. Conductive terminal 362e can be coupled to external devices (e.g., Figure 1 (External host die 112). In some embodiments, the conductive terminal 362e may be a microbump.

[0191] In some implementations, such as Figure 3E As shown, memory dies 302e-306e can have reduced thickness (along the Z direction) by thinning their substrate. The topmost memory die 308e (e.g., the one furthest from the base die 344e among memory dies 302e-308e) may not be thinned. Therefore, the thickness of each of memory dies 302e-306e can be less than the thickness of memory die 308e. The thickness of each of memory dies 302e-308e can be within any suitable range (e.g., between 3 μm and 20 μm).

[0192] Figure 3F This disclosure illustrates some aspects of the content. Figure 3EFigure 300f shows an enlarged view of the interconnect layer 345f in the base die 344e. The interconnect layer 345F is located along the Z-direction between the contact structures 326e-332e and 370e and the bonding layer 342e. The interconnect layer 345f may include interconnects (also referred to herein as “contacts”) including lateral interconnects 347f and vertical interconnect pathways (VIA) contacts (not shown). The contact structures 326e-332e and 370e, as well as the conductive bonding contacts 356e of the bonding layer 342e, may be coupled to the interconnects in the interconnect layer 345f. As used herein, the term “interconnect” may broadly include any suitable type of interconnect, such as mid-stage (MEOL) interconnects and back-end (BEOL) interconnects. The interconnect layer 345f may also include one or more interlayer dielectric (ILD) layers (also referred to as “intermetallic dielectric (IMD) layers”) in which the interconnects 347f and VIA contacts may be formed. That is, interconnect layer 345f may include interconnect lines 347e and VIA contacts in multiple ILD layers. Interconnect lines 347f and VIA contacts in interconnect layer 345f may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicides, or any combination thereof. ILD layers in interconnect layer 345f may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant (low k) dielectrics, or any combination thereof.

[0193] Figure 3G A side view of a semiconductor device 300g according to some aspects of this disclosure is shown. The semiconductor device 300g includes memory dies 302g-308g, a base die 344g, a computing die 346g, and an interposer 348g. The memory dies 302g-308g and the base die 344g are stacked sequentially along the Z-direction. The base die 344g and the computing die 346g are integrated at different locations on the interposer 348g along the X-direction. The memory dies 302g-308g are similar to... Figure 3A The memory dies are 302a-308a. The memory dies are 302g-308g. Figure 1 The memory die 102 and Figure 2AExamples of memory dies 204a-204d (e.g., DRAM). The stack of memory devices 302g-308g includes a device region 301g and a connection region 303g adjacent to the device region 301g in a horizontal direction (e.g., the X direction). Memory dies 302g-308g include conductive layers 310g-316g extending in a horizontal direction (e.g., the X direction), respectively. Each of conductive layers 310g-316g has one end coupled to a memory array or peripheral circuitry in the corresponding memory die in the device region 301g and another end extending away from the device region 301g (e.g., end 318g-324g). Each of conductive layers 310g-316g may be coupled to an input / output port of the corresponding memory die, or may be configured to provide one or more of power, clock, or data path signals to the corresponding memory die.

[0194] like Figure 3G As shown, the semiconductor device 300g includes contact structures 326g-332g in the connection region 303g. The contact structures 326g-332g can be... Figure 2A-2B An example of contact structure 210. The semiconductor device 300g also includes bonding layers (e.g., bonding layers 334g, 336g, and 338g) between adjacent memory dies 302g-308g, and a bonding layer 340g between memory die 302g and base die 344g. Each of these bonding layers may include silicon oxide. Base die 344g includes a surface 365g and another surface 367g. Surface 365g is bonded to memory die 302g via bonding layer 340g. Base die 344g also includes a conductive layer 368g and a contact structure 370g connected to the conductive layer 368g. Contact structure 370g extends into base die 344g in the Z direction. Conductive layer 368g includes an end 372g coupled to circuitry of base die 344g and another end 374g closer to contact structure 370g. In some embodiments, bonding layers 334g, 336g, 338g, and 340g may be referred to as direct bonding layers, and may have the same characteristics as... Figure 3B The structure of bonding layer 334a described herein is similar to that of the structure described herein. Each of bonding layers 334g, 336g, 338g, and 340g may include at least one dielectric material and does not include conductive bonding contacts.

[0195] Contact structures 370g and 326g-332g extend in a vertical direction (e.g., the Z direction) and are coupled to conductive layers 368g and 310g-316g, respectively. Specifically, contact structure 370g extends into the base die 344g without extending through the bonding layer 340g. Contact structure 326g extends through the bonding layer 340g into the memory die 302g without extending through the bonding layer 334g. Contact structure 326g is connected to the conductive layer 310g of the memory die 302g without extending through the conductive layer 368g. Contact structure 328g extends through the memory die 302g and the bonding layers 340g and 334g into the memory die 304g without extending through the bonding layer 336g. Contact structure 328g is connected to the conductive layer 312g of the memory die 304g without extending through the conductive layers 368g and 310g. Contact structure 330g extends through memory dies 302g-304g and bonding layers 340g, 334g, and 336g and enters memory die 306g, but does not extend through bonding layer 338g. Contact structure 330g is connected to conductive layer 314g of memory die 306g, but does not extend through conductive layers 368g, 310g, and 312g. Contact structure 332g extends through memory dies 302g-306g and bonding layers 340g, 334g, 336g, and 338g and enters memory die 308g, but does not extend through memory die 308g. Contact structure 332g is connected to conductive layer 316g of memory die 308g, but does not extend through conductive layers 368g, 310g, 312g, and 314g.

[0196] Conductive layers 368g and 310g-316g can be formed into a stepped structure to allow each of the contact structures 370g and 326g-332g to connect to one of the conductive layers 368g and 310g-316g without extending through the other conductive layers. In some embodiments, such as Figure 3GAs shown, conductive layers 368g and 310g-316g are offset along the X direction. In some embodiments, conductive layers 310g-316g may have the same length. Specifically, the ends 374g and 318g-324g (e.g., the right-hand ends) of conductive layers 368g and 310g-316g may be offset along the X direction. Contact structure 326g is located along the X direction between the end 374g of conductive layer 368g and the end 318g of conductive layer 310g. That is, the end 374g of conductive layer 368g is located along the X direction between contact structure 370g and contact structure 326g. Thus, contact structure 326g can extend through the base die 344g and around the conductive layer 368g of the base die 344g. Contact structure 328g is located along the X direction between the end 318g of conductive layer 310g and the end 320g of conductive layer 312g. That is, the end 318g of the conductive layer 310g is located between the contact structure 326g and the contact structure 328g along the X direction. Thus, the contact structure 328g can extend through the memory die 302g and bypass the conductive layer 310g of the memory die 302g. Similarly, the contact structure 330g is located between the end 320g of the conductive layer 312g and the end 322g of the conductive layer 314g along the X direction, allowing the contact structure 330g to extend through the memory dies 302g-304g and bypass the conductive layers 310g-312g. Furthermore, the contact structure 332g is located between the end 322g of the conductive layer 314g and the end 324g of the conductive layer 316g along the X direction, allowing the contact structure 332g to extend through the memory dies 302g-306g and bypass the conductive layers 310g-314g.

[0197] The base die 344g may include an interconnect layer ( Figure 3G (Not shown in the image). The interconnect layer of the base die 344g has... Figure 3F The structure of interconnect layer 345f described herein is similar to that of the structure described above. Each of contact structures 326g-332g and 370g can be coupled to the interconnect layer of the base die 344g. The base die 344g can be coupled to the computing die 346g via the interconnect layer and the interposer layer 348g. The interposer layer 348g has a surface 358g and a surface 360g. The interconnects in the interconnect layer of the base die 344g can be connected to conductive terminals 364g on the surface 358g of the interposer layer 348g. The computing die 346g can be connected to conductive terminals 366g on the surface 358g of the interposer layer 348g. The semiconductor device 300g may include conductive terminals 362g connected to the surface 360g of the interposer layer 348g. The conductive terminals 364g, 366g, and 362g can be connected via conductive lines in the interposer layer 348g (e.g., as shown in the image). Figure 3G The conductive line 369g shown is coupled. The conductive terminal 362g can be coupled to an external device (e.g., Figure 1 The external host die 112). In some embodiments, conductive terminals 364g, 366g, and 362g may be microbumps. It should be understood that in practice, the base die 344g, computing die 346g, and interposer 348g may be integrated together using any suitable packaging technology, including, for example, chip-on-wafer (CoWoS) on a substrate.

[0198] In some embodiments, the base die 344g includes control circuitry configured to control memory dies 302g-308g. The control circuitry may be coupled to the memory dies 302g-308g, for example, via contact structures 370g and 326g-332g and the interconnect layer of the base die 344g.

[0199] In some implementations, such as Figure 3G As shown, memory dies 302g-306g can have a reduced thickness (along the Z direction) by thinning their substrate. The topmost memory die 308g (e.g., the one furthest from the base die 344g among memory dies 302g-308g) may not be thinned. Therefore, the thickness of each of memory dies 302g-306g can be less than the thickness of memory die 308g. The thickness of each of memory dies 302g-308g can be within any suitable range (e.g., between 3 μm and 20 μm).

[0200] Figure 3H A side view of a semiconductor device 300h according to some aspects of this disclosure is shown. The semiconductor device 300h includes memory dies 302h-308h, a base die 344h, a computing die 346h, and an interposer 348h. The memory dies 302h-308h and the base die 344h are stacked sequentially along the Z-direction. The base die 344h and the computing die 346h are integrated at different locations on the interposer 348h along the X-direction. The memory dies 302h-308h are similar to... Figure 3A The memory dies are 302a-308a. The memory dies are 302h-308h. Figure 1 The memory die 102 and Figure 2AExamples of memory dies 204a-204d (e.g., DRAM). The stack of memory devices 302h-308h includes a device region 301h and a connection region 303h adjacent to the device region 301h in a horizontal direction (e.g., the X direction). Memory dies 302h-308h include conductive layers 310h-316h extending in a horizontal direction (e.g., the X direction), respectively. Each of the conductive layers 310h-316h can be coupled (e.g., through one of its ends) to a memory array or peripheral circuitry in a corresponding memory die in the device region 301h. In some embodiments, each of the conductive layers 310h-316h can be coupled to an input / output port of a corresponding memory die, or can be configured to provide one or more of power, clock, or data path signals to the corresponding memory die.

[0201] like Figure 3H As shown, the semiconductor device 300h includes contact structures 326h-332h in the connection region 303h. The contact structures 326h-332h can be... Figure 2A-2B An example of contact structure 210. The semiconductor device 300h also includes bonding layers (e.g., bonding layers 334h, 336h, and 338h) between adjacent memory dies in memory dies 302h-308h, and a bonding layer 340h between memory die 302h and base die 344h. Each of these bonding layers may include silicon oxide. The base die 344h includes a surface 365h and another surface 367h. Surface 365h is bonded to memory die 302h via bonding layer 340h. The base die 344h also includes a conductive layer 368h and a contact structure 370h connected to the conductive layer 368h. The contact structure 370h extends into the base die 344h in the Z direction. The conductive layer 368h includes an end 372h coupled to circuitry of the base die 344h and another end 374h closer to the contact structure 370h. In some embodiments, bonding layers 334h, 336h, 338h, and 340h may be referred to as direct bonding layers, and may have the same characteristics as... Figure 3B The structure of bonding layer 334A described herein is similar to that of the structure described herein. Each of bonding layers 334h, 336h, 338h and 340h may include at least one dielectric material and does not include conductive bonding contacts.

[0202] Contact structures 370h and 326h-332h extend in a vertical direction (e.g., the Z direction) and are coupled to conductive layers 368h and 310h-316h, respectively. Specifically, contact structure 370h extends into the base die 344h without extending through the bonding layer 340h. Contact structure 326h extends through memory die 302h and bonding layers 340h and 334h into memory die 304h without extending through the bonding layer 336h. Contact structure 326h is connected to conductive layer 312h of memory die 304h without extending through conductive layers 310h, 314h, 316h, and 368h. Contact structure 328h extends through memory dies 302h-306h and bonding layers 340h, 334h, 336h, and 338h and into memory die 308h without extending through the memory die 308h. Contact structure 328h is connected to the conductive layer 316h of memory die 308h, but does not extend through conductive layers 310h, 312h, 314h, and 368h. Contact structure 330h extends through memory dies 302h-304h and bonding layers 340h, 334h, and 336h and enters memory die 306h, but does not extend through bonding layer 338h. Contact structure 330h is connected to the conductive layer 314h of memory die 306h, but does not extend through conductive layers 310h, 312h, 316h, and 368h. Contact structure 332h extends through bonding layer 340h and enters memory die 302h, but does not extend through bonding layer 334h. Contact structure 332h is connected to the conductive layer 310h of memory die 302h, but does not extend through conductive layers 312h, 314h, 316h, and 368h.

[0203] like Figure 3H As shown, although conductive layers 368h and 310h-316h are formed with some other diagrams (e.g., Figure 3A , Figure 3D , Figure 3E and Figure 3G The stepped structures in the () are different structures, but each of the contact structures 370h and 326h-332h can still be connected to one of the conductive layers 368h and 310h-316h without extending through other conductive layers. In some embodiments, such as Figure 3HAs shown, conductive layers 368h and 310h-316h are offset along the X direction. In some embodiments, conductive layers 310h-316h may have the same length and their ends may be offset along the X direction. Specifically, contact structure 326h is located along the X direction between end 374h of conductive layer 368h and end 318h of conductive layer 312h. Contact structure 328h is located along the X direction between end 318h of conductive layer 312h and end 320h of conductive layer 314h. Contact structure 330h is located along the X direction between end 320h of conductive layer 314h and end 322h of conductive layer 310h. End 322h is located along the X direction between contact structure 330h and contact structure 332h.

[0204] The base die 344h may include an interconnect layer ( Figure 3H (Not shown in the image). The interconnect layer of the base die 344h has the same characteristics as... Figure 3F The structure of interconnect layer 345f described herein is similar to that of the structure described above. Each of contact structures 326h-332h and 370h can be coupled to the interconnect layer of the base die 344h. The base die 344h can be coupled to the computing die 346h via the interconnect layer and the interposer layer 348h. The interposer layer 348h has a surface 358h and a surface 360h. Interconnects in the interconnect layer of the base die 344h can be connected to conductive terminals 364h on surface 358h of the interposer layer 348h. The computing die 346h can be connected to conductive terminals 366h on surface 358h of the interposer layer 348h. The semiconductor device 300h may include conductive terminals 362h connected to surface 360h of the interposer layer 348h. Conductive terminals 364h, 366h, and 362h can be connected via conductive lines in the interposer layer 348h (e.g., as shown in the image). Figure 3H The conductive line 369h shown is coupled. The conductive terminal 362h can be coupled to an external device (e.g., Figure 1 The external host die 112). In some embodiments, conductive terminals 364h, 366h, and 362h may be microbumps. It should be understood that in practice, the base die 344h, computing die 346h, and interposer 348h may be integrated together using any suitable packaging technology, including, for example, chip-on-wafer (CoWoS) on a substrate.

[0205] In some embodiments, the base die 344h includes control circuitry configured to control memory dies 302h-308h. The control circuitry may be coupled to the memory dies 302h-308h, for example, via contact structures 370h and 326h-332h and the interconnect layer of the base die 344h.

[0206] In some implementations, such as Figure 3HAs shown, memory dies 302h-306h can have reduced thickness (along the Z direction) by thinning their substrate. The topmost memory die 308h (e.g., the one furthest from the base die 344h among memory dies 302h-308h) may not be thinned. Therefore, the thickness of each of memory dies 302h-306h can be less than the thickness of memory die 308h. The thickness of each of memory dies 302h-308h can be within any suitable range (e.g., between 3 μm and 20 μm).

[0207] Figure 4A-4J Example processes for manufacturing a semiconductor device according to some aspects of this disclosure are illustrated. In some embodiments, the processes described herein can be used to manufacture any suitable semiconductor device, such as semiconductor device 200, 300a, or 300d.

[0208] Figure 4A The process can be illustrated by providing semiconductor structures 400 and 402, both extending in a horizontal direction (e.g., the X direction). Semiconductor structure 400 may be a carrier wafer. Semiconductor structure 402 may include a conductive layer 410 (e.g., Figure 3A Semiconductor devices or semiconductor dies (e.g., conductive layer 310a) of conductive layer 310a Figure 2C Memory die 204a or Figure 3A (Memory die 302a). Semiconductor structure 402 may be stacked on semiconductor structure 400 in a vertical direction (e.g., the Z direction) and bonded to semiconductor structure 400 via bonding layer 401. Any suitable bonding technique (e.g., direct bonding technique) may be used to bond semiconductor structures 400 and 402. For example, a first dielectric layer (e.g., silicon oxide) may be deposited on surface 403 of semiconductor structure 400, and a second dielectric layer (e.g., silicon oxide) may be deposited on surface 405 of semiconductor structure 402. By applying pressure and heat, the first and second dielectric layers may be bonded together to form bonding layer 401 between semiconductor structures 400 and 402. Semiconductor structure 400 may serve as a support for semiconductor structure 402. Semiconductor structures 400 and 402 may have any suitable thickness in the Z direction. In some embodiments, the thickness of semiconductor structure 402 may be in the range of 40 μm and 50 μm.

[0209] like Figure 4BAs shown, semiconductor structure 402 is thinned. Thinning semiconductor structure 402 includes removing the top portion of semiconductor structure 402 (e.g., the portion furthest from semiconductor structure 400 along the Z direction). For example, the thickness of semiconductor structure 402 can be reduced from about 40-50 μm to 3-20 μm by thinning. In some embodiments, semiconductor structure 402 includes a substrate on its bottom and is inverted before being bonded to semiconductor structure 400. That is, after inversion, the substrate of semiconductor structure 402 becomes the top of semiconductor structure 402. Therefore, a portion of the substrate of semiconductor structure 402 is removed by thinning the top portion of semiconductor structure 402. In some embodiments, semiconductor structure 402 can still maintain its shape after thinning without significant distortion or deformation due to the support provided by semiconductor structure 400 (e.g., carrier wafer).

[0210] like Figure 4C As shown, a semiconductor structure 404 is provided. Semiconductor structure 404 (e.g., Figure 3A The memory die 304a) includes a conductive layer 412 (e.g., Figure 3A (Conductive layer 312a). In some embodiments, the semiconductor structure 404 includes a substrate in its top portion, which is similar to that described above. Figure 4B The semiconductor structure 402 is described. A semiconductor structure 404 can be aligned with the semiconductor structure 402 such that the ends 420 of the conductive layer 412 and the ends 418 of the conductive layer 410 are offset along the X direction. By doing so, the conductive layers 412 and 410 can form a stepped structure (e.g., as per [reference to...]). Figure 2C and Figures 3A-3D The stepped structure described allows the contact structure formed in a later step to connect to the conductive layer 412 without extending through the conductive layer 410. A dielectric layer can be deposited on the bottom surface of the semiconductor structure 404, and a dielectric layer can be deposited on the top surface of the semiconductor structure 402. The semiconductor structure 404 can be stacked on and bonded to the semiconductor structure 402 along the Z-direction, similar to... Figure 4A Examples of the bonded semiconductor structure 402 and semiconductor structure 400 are described.

[0211] like Figure 4D As shown, the dielectric layer of semiconductor structure 404 and the dielectric layer of semiconductor structure 402 can form a bonding layer 407. Semiconductor structure 404 is thinned by removing a top portion (e.g., a portion of the substrate of semiconductor structure 404).

[0212] Figure 4E It is shown that a conductive layer 414 is provided (e.g., Figure 3A Semiconductor structure 406 (e.g., conductive layer 314a) Figure 3A The memory die 306a) and including a conductive layer 416 (e.g., Figure 3A Semiconductor structure 408 (e.g., conductive layer 316a) Figure 3A (Memory die 308a). Semiconductor structure 406 is similar to that of the memory die 308a. Figures 4A-4D The described example is aligned with, stacked on, and bonded to semiconductor structure 404. Semiconductor structure 406 may also be thinned. Similarly, semiconductor structure 408 is aligned with, stacked on, and bonded to semiconductor structure 406. In some embodiments, semiconductor structure 408 is not thinned, so that semiconductor structure 408 provides support due to its thickness when the stack of semiconductor structures 404-408 is inverted in a later step. Conductive layers 410-416 may be formed as described above. Figure 2C , Figure 3A and Figure 3D The described stepped structure. In some embodiments, the conductive layers 410-416 can have various lengths. For example, as... Figure 4E As shown, conductive layers 410-416 can extend from substantially the same location (e.g., on the right side) and extend different lengths (e.g., toward the left side) in the X direction. That is, the ends 418-424 of conductive layers 410-416 are offset along the X direction. In some embodiments, semiconductor structures 404-408 are labeled based on the location and length of conductive layers 410-416. Semiconductor structures 404-408 can be stacked in the correct order based on their labels.

[0213] While in this example the semiconductor device may include four semiconductor structures 402-408 stacked together, the techniques disclosed herein can be applied to stacking any suitable number of semiconductor structures (e.g., 2, 5, or 8). The number of semiconductor structures can be determined based on factors including technical constraints, thermal considerations, signal integrity and interference, physical size and application, cost and yield, reliability considerations, etc. In these cases, the last semiconductor structure furthest from semiconductor structure 400 (rather than, as...) Figure 4E The fourth one shown can be thicker than the other semiconductor structures along the Z-direction. For example, the last semiconductor structure is not thinned, but the others are. In this way, when the stacked structure is inverted in a later step, the last semiconductor structure can provide support due to its thickness.

[0214] like Figure 4F As shown, semiconductor structure 400 can be removed using a stripping process. The stack of semiconductor structures 402-408 is then inverted. As the thickest of semiconductor structures 402-408, semiconductor structure 408 now sits at the bottom and supports the other semiconductor structures.

[0215] Figure 4G A mask layer 411 is shown formed on top of a semiconductor structure 402. Openings 413, 415, 417, and 419 are formed in the mask layer 411. In some embodiments, the mask layer 411 comprises a photoresist material, and the openings 413, 415, 417, and 419 can be formed by etching the mask layer 411. The locations of the openings 413, 415, 417, and 419 can be determined such that corresponding contact holes (e.g., extending along the Z-direction) are formed. Figure 4H The contact holes 425, 427, 429 and 431 can extend from one of the openings 413, 415, 417 and 419 to a corresponding one of the conductive layers 410-416, without extending through the other conductive layers 410-416.

[0216] Figure 4H Contact holes 425, 427, 429, and 431 are shown forming extending along the Z-direction into semiconductor structures 402-408. Contact hole 425 extends into semiconductor structure 402 and reaches conductive layer 410. Contact hole 427 extends through semiconductor structure 402 into semiconductor structure 404 and reaches conductive layer 412. Contact hole 429 extends through semiconductor structures 402 and 404 into semiconductor structure 406 and reaches conductive layer 414. Contact hole 431 extends through semiconductor structures 402, 404, and 406 into semiconductor structure 408 and reaches conductive layer 416. In some embodiments, contact holes 425, 427, 429, and 431 can be formed by etching away one or more dielectric materials in semiconductor structures 402-408 from openings 413, 415, 417, and 419. The stepped structure formed by conductive layers 410-416 allows each of contact holes 425, 427, 429, and 431 to connect to one of semiconductor structures 402-408 and bypass other semiconductor structures in semiconductor structures 402-408. Specifically, contact hole 427 is located between end 418 of conductive layer 410 and end 420 of conductive layer 412, contact hole 429 is located between end 420 of conductive layer 412 and end 422 of conductive layer 414, and contact hole 431 is located between end 422 of conductive layer 414 and end 424 of conductive layer 416. After forming contact holes 425, 427, 429, and 431, mask layer 411 can be removed using, for example, chemical mechanical planarization (CMP). In some embodiments, contact holes 425, 427, 429, and 431 are formed during the same etching process.

[0217] Figure 4IContact structures 426, 428, 430, and 432 are shown formed in contact holes 425, 427, 429, and 431, respectively. Each of the contact structures 426, 428, 430, and 432 may include an outer layer (e.g., outer layer 433) and an inner layer (e.g., inner layer 435) on the inner surface of the outer layer 433. The inner layer may include a conductive material (e.g., copper or tungsten) and may be referred to as a conductive structure. The outer layer may include an insulating material (such as a dielectric material like silicon oxide) and may be referred to as an insulating layer. The contact structures 426, 428, 430, and 432 can be formed by first depositing a dielectric material into the contact holes 425, 427, 429, and 431 to form an insulating layer on the inner surface of the contact holes 425, 427, 429, and 431. Subsequently, the bottom of the insulating layer can be etched away to expose the conductive layers 410, 412, 414, and 416 in contact holes 425, 427, 429, and 431, respectively. The inner layers of contact structures 426, 428, 430, and 432 can then be formed by depositing conductive material into the contact holes 425, 427, 429, and 431. In some embodiments, after deposition, CMP can be used to polish away excess material such as metal and dielectric, leaving a flat, metallic surface in the contact holes.

[0218] Figure 4J Semiconductor structure 444 is shown stacked on and bonded to semiconductor structure 402. Semiconductor structure 444 can be a base die (e.g., Figure 2A Basic die 212, Figure 3A Basic die 344a or Figure 3DThe base die 344d). Semiconductor structure 444 includes vias 450 extending along the Z direction. Semiconductor structure 444 can be bonded to semiconductor structure 402 using any suitable bonding technique. In some embodiments, semiconductor structure 444 and semiconductor structure 402 can be bonded via conductive bonding contacts and dielectric materials. Specifically, bonding layer 443 can be formed on the top surface of semiconductor structure 402. Bonding layer 443 may include conductive bonding contacts 442 and a dielectric material isolating the conductive bonding contacts 442. Contact structures 426, 428, 430, and 432 are connected to corresponding bonding contacts in conductive bonding contacts 442. In some embodiments, an interconnect layer is formed in semiconductor structure 402 prior to the formation of bonding layer 443. The interconnect layer can be coupled to contact structures 426, 428, 430, and 432. Bonding layer 445 can be formed on the bottom surface of semiconductor structure 444. Bonding layer 445 may include conductive bonding contacts 446 and a dielectric material isolating the conductive bonding contacts 446. The conductive bonding contacts 446 are connected to vias 450 of the semiconductor structure 444. Conductive bonding contacts 442 and 446 may include the same conductive material, such as a metal (e.g., copper). Bonding layers 443 and 445 may include the same dielectric material (e.g., silicon oxide). The semiconductor structure 444 is stacked on the semiconductor structure 402 such that bonding layer 445 contacts bonding layer 443, and each conductive bonding contact 446 contacts a corresponding conductive bonding contact 442. Bonding layers 445 and 443 are achieved by applying pressure and heat.

[0219] In some implementations, modifications can be made regarding Figure 4A-4J The described process is to form a semiconductor device having a contact structure extending through the semiconductor structure 444 (e.g., as per [reference]). Figure 3E , Figure 3G and Figure 3H The memory die and the stack of base dies described. For example, a mask layer 411 is formed on top of the semiconductor structure 402 (such as...). Figure 4G (As shown) Before this, semiconductor structure 444 can be stacked on semiconductor structure 402 and bonded to semiconductor structure 402 via a dielectric bonding layer. Then, a mask layer 411 can be formed on top of semiconductor structure 444. Therefore, a contact structure extending through semiconductor structure 444 can be formed by etching mask layer 411 to form openings, forming contact holes extending from the openings to conductive layers 410-416, and forming contact structures in the contact holes, similar to the contact structure shown above. Figure 4G-4I The described process.

[0220] In some embodiments, semiconductor structures 402, 404, 406, 408, and 444 can be fabricated individually, such that limitations in fabricating one of them (e.g., thermal budget) do not limit the process for fabricating the others. In some embodiments, semiconductor structures 402, 404, 406, 408, and 444 can be fabricated in parallel.

[0221] In some implementations, each of the semiconductor structures 402, 404, 406, 408, and 444 includes a semiconductor die (e.g., a memory die or a base die). Each semiconductor die may include fully functional electronic circuitry (e.g., a microprocessor, memory, sensor, or any other suitable type of integrated circuit) and may be encapsulated in a protective package.

[0222] In some embodiments, each of semiconductor structures 402, 404, 406, 408, and 444 includes a semiconductor wafer. The semiconductor wafer may include multiple semiconductor devices or dies manufactured by depositing multiple layers of various materials and etching them onto the semiconductor wafer in a complex pattern defined by a chip design. Regarding Figure 4A-4J The described process is performed at the wafer level and applied to multiple semiconductor wafers to form a stack of semiconductor wafers bonded together. After the process is complete, the stack of semiconductor wafers is diced and cut into individual dies. Each individual die (which may also be referred to as a die) includes fully functional electronic circuitry, which may be a microprocessor, HBM, sensor, or any other suitable type of integrated circuit. In some embodiments, each individual die is encapsulated in a protective package, thereby providing physical support, protection from environmental factors, and connectivity to external devices or systems (e.g., via pins or solder balls).

[0223] Figure 5 A flowchart illustrating an example process 500 for forming a semiconductor device according to some aspects of this disclosure is shown. The semiconductor device may be similar in structure to or identical to semiconductor devices 200, 300a, 300d, 300e, 300g, or 300h, or a portion thereof, or intermediate manufacturing processes of such semiconductor devices. Reference may be made to... Figure 4A-4J Describe process 500. Process 500 may include forming Figure 4A-4J The process of manufacturing semiconductor structures. Process 500 includes steps that can be performed in any suitable order and / or any combination.

[0224] At step 502, a first die and a second die are provided. The first die includes a conductive layer and at least a first bonding layer. The second die includes a conductive layer and at least a second bonding layer. The first die may be, for example... Figure 4D The semiconductor structure 402, and the second die can be, for example... Figure 4DThe semiconductor structure 404. In some embodiments, the first bonding layer of the first die and the second bonding layer of the second die each comprise a dielectric material and do not include conductive bonding contacts. In some embodiments, providing the first die includes thinning the first die by thinning the substrate included in the first die (e.g., as per [reference to...]). Figure 4B The thinned semiconductor structure described is 402).

[0225] At step 504, a second die is stacked on top of the first die along a first direction (e.g., the Z direction). In some embodiments, stacking the second die on top of the first die along the first direction includes aligning the second die with the first die so that the first end of the conductive layer of the first die (e.g., ...) is aligned with the first die. Figure 4C The end 418) and the first end of the conductive layer of the second die (e.g., Figure 4C The end portion 420) is offset along a second direction (e.g., the X direction) perpendicular to the first direction.

[0226] At step 506, the second bonding layer of the second die is bonded to the first bonding layer of the first die. For example, the second bonding layer may be a dielectric layer deposited on the bottom surface of the semiconductor structure 404, and the first bonding layer may be a dielectric layer deposited on the top surface of the semiconductor structure 402, as per [reference to...]. Figure 4C As stated above.

[0227] At step 508, a first contact structure and a second contact structure extending along a first direction are formed. The first contact structure (e.g., Figure 4I The contact structure 426 extends into the first die (e.g., semiconductor structure 402) and contacts the conductive layer of the first die (e.g., conductive layer 410). The second contact structure (e.g., Figure 4I The second contact structure (428) extends through the first bonding layer of the first die and the second bonding layer of the second die and enters the second die (e.g., semiconductor structure 404). The second contact structure contacts the conductive layer of the second die (e.g., conductive layer 412) but not the conductive layer of the first die.

[0228] In some embodiments, process 500 further includes stacking the first die on a carrier wafer (e.g., Figures 4A-4E The semiconductor structure 400 is on the substrate. The first die can be stacked on the carrier wafer before the second die is stacked on top of the first die. The first die is between the carrier wafer and the second die.

[0229] In some implementations, the first contact structure and the second contact structure are manufactured using the same process (e.g., as per [reference to...]). Figure 4H and Figure 4I The process includes forming a first contact hole (e.g., ...). Figure 4HThe contact hole 425) and the second contact hole (e.g., Figure 4H Contact hole 427). The first and second contact holes can be formed during the same etching process (e.g., as per [reference to...]). Figure 4H The process also includes forming a corresponding insulating layer in each of the first and second contact holes (e.g., as described above). Figure 4I The outer layer 433). The process also includes forming a conductive structure in the insulating layer of each of the first and second contact holes (e.g., by depositing a conductive material such as copper or tungsten into the first and second contact holes). The first contact structure includes an insulating layer and a conductive structure in the first contact hole, and the second contact structure includes an insulating layer and a conductive structure in the second contact hole.

[0230] In some embodiments, forming the first contact structure and the second contact structure further includes etching the bottom of the insulating layer to expose the conductive layer of the first die and the conductive layer of the second die in the first contact hole and the second contact hole, respectively.

[0231] In some embodiments, process 500 further includes forming a mask layer on top of the first die (e.g., Figure 4G The mask layer 411) and the mask layer is etched to form the first opening (e.g., Figure 4G The opening 413) and the second opening (e.g., Figure 4G (Opening 415). The first contact hole extends from the first opening to the conductive layer of the first die, and the second contact hole extends from the second opening to the conductive layer of the second die.

[0232] In some embodiments, process 500 further includes forming a third bonding layer on top of the first die (e.g., Figure 4J The third bonding layer includes conductive bonding contacts (e.g., bonding layer 443). Figure 4J The conductive bonding contact 442 and the dielectric material that isolates the conductive bonding contact. The first contact structure and the second contact structure can be coupled to the conductive bonding contact.

[0233] In some implementations, process 500 also includes providing a base die (e.g., Figure 4J The semiconductor structure 444). The base die includes a bottom bonding layer (e.g., Figure 4J The bonding layer 445 includes conductive bonding contacts (e.g., ...). Figure 4J The conductive bonding contact 446) and the dielectric material for isolating the conductive bonding contact. (See also: Regarding...) Figure 4JAs described, process 500 may further include stacking a base die on a first die and bonding a bottom bonding layer of the base die to a third bonding layer of the first die. The bottom bonding layer and the third bonding layer may be bonded by bonding a dielectric material of the bottom bonding layer to a dielectric material of the third bonding layer and bonding conductive bonding contacts of the bottom bonding layer to conductive bonding contacts of the third bonding layer.

[0234] Figure 6A A side view of a semiconductor device 600a according to some aspects of this disclosure is shown. The semiconductor device 600a includes memory dies 602a-608a, a base die 644a, a computing die 646a, and an interposer 648a stacked along a vertical direction (e.g., the Z direction) (e.g., sequentially). The memory dies 602a-608a may be... Figure 1 The memory die 102 and Figure 2A Examples of memory dies 204a-204d (e.g., DRAM). The stack of memory dies 602a-608a includes device regions 601a and connection regions 603a adjacent to each other in a horizontal direction (e.g., the X direction). Memory dies 602a-608a include conductive layers 610a-616a extending respectively in a horizontal direction (e.g., the X direction). Each of conductive layers 610a-616a is coupled to a memory array or peripheral circuitry in a corresponding memory die within device region 301a. Each of conductive layers 610a-616a may be coupled to an input / output port of the corresponding memory die, or may be configured to provide one or more of power, clock, or data path signals to the corresponding memory die.

[0235] like Figure 6A As shown, the semiconductor device 600a includes contact structures 626a-632a in the connection region 603a. The contact structures 626a-632a can be... Figure 2A-2B An example of contact structure 210. Semiconductor device 600a also includes bonding layers between adjacent memory dies 602a-608a (e.g., bonding layers 634a, 636a, and 638a), a bonding layer 640a between memory die 602a and base die 644a, and a bonding layer 642a between base die 644a and computing die 646a. Each of these bonding layers may include a dielectric material such as silicon oxide.

[0236] Contact structures 626a-632a extend in a vertical direction (e.g., the Z direction) and are coupled to conductive layers 610a-616a, respectively. Contact structure 626a extends into memory die 602a and contacts conductive layer 610a of memory die 602a, but does not extend through bonding layer 634a. Contact structure 628a extends through conductive layer 610a and bonding layer 634a of memory die 602a. Contact structure 628a further extends into memory die 604a and contacts conductive layer 612a of memory die 604a, but does not extend through bonding layer 636a. Contact structure 630a extends through conductive layer 610a, bonding layer 634a, memory die 604a, conductive layer 612a, and bonding layer 636a of memory die 602a. Contact structure 630a extends further into memory die 606a and contacts conductive layer 614a of memory die 606a, but does not extend through bonding layer 638a. Contact structure 632a extends through conductive layer 610a, bonding layer 634a, memory die 604a, conductive layer 612a, bonding layer 636a, memory die 606a, conductive layer 614a, and bonding layer 638a of memory die 602a. Contact structure 632a further extends into memory die 608a and contacts conductive layer 616a of memory die 608a, but does not extend through memory die 608a.

[0237] In some embodiments, conductive layers 610a-616a may have the same dimensions and may be located at the same position along the X direction. That is, conductive layers 610a-616a may be aligned along the Z direction. Each contact structure in contact structures 626a-632a may include a conductive structure (inner layer) extending along the Z direction and an insulating layer (outer layer) surrounding the conductive structure. The insulating layer may isolate the conductive structure from one or more conductive layers through which the contact structure extends.

[0238] In some embodiments, bonding layers 634a, 636a, and 638a may be referred to as direct bonding layers because they are formed by direct dielectric-dielectric bonding. Each of bonding layers 634a, 636a, and 638a may include at least one dielectric material and does not include conductive bonding contacts. In some embodiments, bonding layers 640a and 642a may be referred to as hybrid bonding layers because they can be formed by a mixture of dielectric-dielectric bonding and metal-metal bonding. Each of bonding layers 640a and 642a may include bonding contacts (e.g., conductive bonding contacts) and at least one dielectric material that isolates the bonding contacts. Figure 6AAs shown, the bonding layer 640a includes conductive bonding contacts 654a. The conductive bonding contacts 654a can be configured to connect the memory die 602a and the base die 644a. In some embodiments, the memory die 602a may include an interconnect layer in contact with the bonding layer 640a. Figure 6A (Not shown in the image). The interconnect layer of memory die 602a has a connection with... Figure 6F The interconnect layer 645F described herein has a similar structure. Each of the contact structures 626a-632a can be coupled to the interconnect layer of the memory die 602a. The interconnect layer of the memory die 602a can be coupled to the base die 644a through conductive bonding contacts 654a in the bonding layer 640a. The base die 644a includes a via 650a extending along the Z direction through the base die 644a and connecting to the conductive bonding contacts 654a. Each of the contact structures 626a-632a is coupled to a corresponding via 350a through a corresponding conductive bonding contact 654a. The bonding layer 642a includes conductive bonding contacts 656a. The conductive bonding contacts 656a can be configured to connect the base die 644a and the computing die 646a. The computing die 646a can be... Figure 1 An example of computing die 108. Computing die 646a includes a via 652a extending along the Z-direction through computing die 646a and connected to a conductive bonding contact 656a. Each via 650a is coupled to a corresponding via 652a via a corresponding conductive bonding contact 656a. In some embodiments, vias 650a and 652a may be through-silicon vias (TSVs). See later. Figure 6B and Figure 6C The structure of bonding layers 634a, 636a, 638a, 640a, and 642a is described in further detail.

[0239] In some embodiments, the base die 644a includes control circuitry configured to control memory dies 602a-608a. The control circuitry may be coupled to memory dies 602a-608a, for example, via contact structures 626a-632a, the interconnect layer of memory die 602a, and conductive bonding contacts 654a.

[0240] Intermediate layer 648a has a surface 658a and a surface 660a. Surface 658a can be bonded to computing die 646a. Conductive terminal 662a can be connected to surface 660a. Intermediate layer 648a may include interconnects connecting vias 652a of computing device 646a to conductive terminal 662a. Conductive terminal 662a can be coupled to external devices (e.g., Figure 1 (External host die 112). In some embodiments, the conductive terminal 662a may be a microbump.

[0241] In some implementations, such as Figure 6A As shown, memory dies 602a-606a can have reduced thickness (along the Z direction) by thinning their substrate. The topmost memory die 608a (e.g., the one furthest from the base die 644a among memory dies 602a-608a) may not be thinned. Therefore, the thickness of each of memory dies 602a-606a can be less than the thickness of memory die 608a. The thickness of each of memory dies 602a-608a can be within any suitable range (e.g., between 3 μm and 20 μm).

[0242] Figure 6B This disclosure illustrates some aspects of the content. Figure 6A Figure 600b shows an enlarged view of the bonding layer 634a. The bonding layer 634a may include a top bonding layer 633b and a bottom bonding layer 637b bonded at a bonding interface 635b. Each of the top bonding layer 633b and the bottom bonding layer 637b may include a dielectric material (including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof) and may not include conductive bonding contacts. A memory die 604a may be bonded to the top of a memory die 602a face-to-face via the bonding layer 634a. As a result of direct bonding (e.g., dielectric-dielectric bonding), the bonding interface 635b is disposed between the top bonding layer 633b and the bottom bonding layer 637b, where direct bonding forms a bond between the surfaces without the use of an intermediate layer, such as solder or adhesive. In some embodiments, for example, when the dielectric material of the top bonding layer 633b and the dielectric material of the bottom bonding layer 637b are different materials, the bonding interface 635b can be a visible layer of a certain thickness, including the top surface of the bottom bonding layer 637b and the bottom surface of the top bonding layer 633b. In some embodiments, for example, when the dielectric material of the top bonding layer 633b and the dielectric material of the bottom bonding layer 637b are the same material, the bonding interface 635b can be invisible and can form a continuous portion with the top bonding layer 633b and the bottom bonding layer 637b. Figure 6A The bonding layers 636a and 638a can have the same characteristics as... Figure 6B The structure of the bonding layer 634a described is similar to that of the structure described above.

[0243] Figure 6C This disclosure illustrates some aspects of the content. Figure 6AFigure 600c shows an enlarged view of the bonding layer 640a. The bonding layer 640a may include a top bonding layer 643c and a bottom bonding layer 647c bonded at a bonding interface 645c. The top bonding layer 643c includes conductive bonding contacts 641c and a dielectric material 639c that isolates the conductive bonding contacts 641c. The conductive bonding contacts 641c may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicides, or any combination thereof. The dielectric material 639c may include dielectrics, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. Similarly, the bottom bonding layer 647c includes conductive bonding contacts 649c and a dielectric material 651c that isolates the conductive bonding contacts 649c. The conductive bonding contact 649c may include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicides, or any combination thereof. The dielectric material 651c may include a dielectric, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0244] Conductive bonding contacts 641c and 649c can be Figure 6A An example of conductive bonding contact 654a. Conductive bonding contact 641c contacts conductive bonding contact 649c at bonding interface 645c. Memory die 602a can be bonded to the top of base die 644a face-to-face via bonding layer 640a. As a result of hybrid bonding (e.g., metal-metal / dielectric-dielectric bonding), bonding interface 645c is disposed between top bonding layer 643c and bottom bonding layer 647c. Hybrid bonding forms a bond between surfaces without the use of intermediate layers, such as solder or adhesive, and can simultaneously achieve metal-metal bonding and dielectric-dielectric bonding. In some embodiments, for example, when the dielectric material 639c of the top bonding layer 643c and the dielectric material 651c of the bottom bonding layer 647c are different materials, the bonding interface 645c can be a visible layer of a certain thickness, including the top surface of the bottom bonding layer 647c and the bottom surface of the top bonding layer 643c. In some embodiments, for example, when the dielectric material 639c and the dielectric material 651c are the same material, the bonding interface 645c can be invisible and can form a continuous portion with the top bonding layer 643c and the bottom bonding layer 647c. Figure 6A The bonding layer 642a can have the same properties as... Figure 6C The structure is similar to that of the bonding layer 640a described in the text.

[0245] Figure 6DA side view of a semiconductor device 600d according to some aspects of this disclosure is shown. The semiconductor device 600d includes memory dies 602d-608d, a base die 644d, a computing die 646d, and an interposer 648d. The memory dies 602d-608d and the base die 644d are stacked along the Z direction (e.g., sequentially). The base die 644d and the computing die 646d are integrated along the X direction at different locations on the interposer 648d. The memory dies 602d-608d are similar to... Figure 6A The memory dies are 602A-608A. The memory dies are 602d-608d. Figure 1 The memory die 102 and Figure 2A Examples of memory dies 204a-204d (e.g., DRAM). The stack of memory dies 602d-608d includes a device region 601d and a connection region 603d adjacent to the device region 601d in a horizontal direction (e.g., the X direction). Memory dies 602d-608d include conductive layers 610d-616d extending in a horizontal direction (e.g., the X direction), respectively. Each of conductive layers 610d-616d is coupled to a memory array or peripheral circuitry in the corresponding memory die in the device region 601d. Each of conductive layers 610d-616d may be coupled to an input / output port of the corresponding memory die, or may be configured to provide one or more of power, clock, or data path signals to the corresponding memory die.

[0246] like Figure 6D As shown, the semiconductor device 600d includes contact structures 626d-632d in the connection region 603d. The contact structures 626d-632d can be... Figure 2A-2B An example of contact structure 210. The semiconductor device 600d also includes bonding layers between adjacent memory dies in memory dies 602d-608d (e.g., bonding layers 634d, 636d, and 638d) and a bonding layer 640d between memory die 602d and base die 644d. Each of these bonding layers may include a dielectric material such as silicon oxide.

[0247] Contact structures 626d-632d extend in a vertical direction (e.g., the Z direction) and are coupled to conductive layers 610d-616d, respectively. Contact structure 626d extends into memory die 602d and contacts conductive layer 610d of memory die 602d, but does not extend through bonding layer 634d. Contact structure 628d extends through conductive layer 610d and bonding layer 634d of memory die 602d. Contact structure 628d further extends into memory die 604d and contacts conductive layer 612d of memory die 604d, but does not extend through bonding layer 636d. Contact structure 630d extends through conductive layer 610d, bonding layer 634d, memory die 604d, conductive layer 612d, and bonding layer 636d of memory die 602d. Contact structure 630d extends further into memory die 606d and contacts conductive layer 614d of memory die 606d, but does not extend through bonding layer 638d. Contact structure 632d extends through conductive layer 610d, bonding layer 634d, memory die 604d, conductive layer 612d, bonding layer 636d, memory die 606d, conductive layer 614d, and bonding layer 638d of memory die 602d. Contact structure 632d extends further into memory die 608d and contacts conductive layer 616d of memory die 608d, but does not extend through memory die 608d.

[0248] In some embodiments, conductive layers 610d-616d may have the same dimensions and may be located at the same position along the X direction. That is, conductive layers 610d-616d may be aligned along the Z direction. Each contact structure in contact structures 626d-632d may include a conductive structure (inner layer) extending along the Z direction and an insulating layer (outer layer) surrounding the conductive structure. The insulating layer may isolate the conductive structure from one or more conductive layers through which the contact structure extends.

[0249] In some implementations, bonding layers 634d, 636d, and 638d may be referred to as direct bonding layers, and may have the same characteristics as... Figure 6B The structure is similar to that of bonding layer 634a described herein. Each of bonding layers 634d, 636d, and 638d may include at least one dielectric material and does not include conductive bonding contacts. In some embodiments, bonding layer 640d may be referred to as a hybrid bonding layer and may have a structure similar to... Figure 6C The bonding layer 640A described herein has a similar structure. The bonding layer 640d may include bonding contacts (e.g., such as...). Figure 6DThe conductive bonding contact 654d shown is a dielectric material for both the conductive bonding contact 654d and the insulating bonding contact. The conductive bonding contact 654d can be configured to connect the memory die 602d and the base die 644d. In some embodiments, the memory die 602d may include an interconnect layer ( ) in contact with the bonding layer 640d. Figure 6D (Not shown in the image). The interconnect layer of memory die 602d has the same characteristics as... Figure 6F The interconnect layer 645f described herein has a similar structure. Each of the contact structures 626d-632d can be coupled to the interconnect layer of the memory die 602d. The interconnect layer of the memory die 602d can be coupled to the base die 644d through conductive bonding contacts 654d in the bonding layer 640d. The base die 644d includes a via 650d extending along the Z direction through the base die 644d and connecting to the conductive bonding contacts 654d. Each of the contact structures 626d-632d is coupled to a corresponding via 650d through the corresponding conductive bonding contact 654d. In some embodiments, the via 650d may be a TSV.

[0250] In some embodiments, the base die 644d includes control circuitry configured to control memory dies 602d-608d. The control circuitry may be coupled to memory dies 602d-608d, for example, via contact structures 626d-632d, the interconnect layer of memory die 602d, and conductive bonding contacts 654d.

[0251] A base die 644d can be coupled to a computing die 646d via an interposer 648d. The interposer 648d has a surface 658d and a surface 660d. A via 650d in the base die 644d can be connected to a conductive terminal 664d on surface 658d of the interposer 648d. The computing die 646d can be connected to a conductive terminal 666d on surface 658d of the interposer 648d. The semiconductor device 600d may include a conductive terminal 662d connected to surface 660d of the interposer 648d. The conductive terminals 664d, 666d, and 662d can be coupled via conductive lines in the interposer 648d (e.g., as shown in the image). Figure 6D The conductive line 669d shown is coupled. The conductive terminal 662d can be coupled to an external device (e.g., Figure 1 The external host die 112). In some embodiments, conductive terminals 664d, 666d, and 662d may be microbumps. It should be understood that in practice, the base die 644d, computing die 646d, and interposer 648d may be integrated together using any suitable packaging technology, including, for example, chip-on-wafer (CoWoS) on a substrate.

[0252] In some implementations, such as Figure 6DAs shown, memory dies 602d-606d can have reduced thickness (along the Z direction) by thinning their substrate. The topmost memory die 608d (e.g., the one furthest from the base die 644d among memory dies 602d-608d) may not be thinned. Therefore, the thickness of each of memory dies 602d-606d can be less than the thickness of memory die 608d. The thickness of each of memory dies 602d-608d can be within any suitable range (e.g., between 3 μm and 20 μm).

[0253] Figure 6E A side view of a semiconductor device 600e according to some aspects of this disclosure is shown. The semiconductor device 600e includes memory dies 602e-608e, a base die 644e, a computing die 646e, and an interposer 648e stacked along a vertical direction (e.g., the Z direction) (e.g., sequentially). The memory dies 602e-608e are similar to... Figure 6A The memory dies are 602a-608a. The memory dies are 602e-608e. Figure 1 The memory die 102 and Figure 2A Examples of memory dies 204a-204d (e.g., DRAM). The stack of memory dies 602e-608e includes a device region 601e and a connection region 603e adjacent to the device region 601e in a horizontal direction (e.g., the X direction). Memory dies 602e-608e include conductive layers 610e-616e extending in a horizontal direction (e.g., the X direction), respectively. Each of conductive layers 610e-616e is coupled to a memory array or peripheral circuitry in the corresponding memory die in the device region 601e. Each of conductive layers 610e-616e may be coupled to an input / output port of the corresponding memory die, or may be configured to provide one or more of power, clock, or data path signals to the corresponding memory die.

[0254] like Figure 6E As shown, the semiconductor device 600e includes contact structures 626e-632e in the connection region 603e. The contact structures 626e-632e can be... Figure 2A-2BAn example of contact structure 210. Semiconductor device 600e also includes bonding layers (e.g., bonding layers 634e, 636e, and 638e) between adjacent memory dies 602e-608e and a bonding layer 640e between memory die 602e and base die 644e. Each of these bonding layers may include a dielectric material, silicon oxide. Base die 644e includes a surface 665e and another surface 667e. Surface 665e is bonded to memory die 602e via bonding layer 640e. Base die 644e also includes a conductive layer 668e and a contact structure 670e connected to the conductive layer 668e. Contact structure 670e extends into base die 644e in the Z direction. Conductive layer 668e may couple between circuitry of base die 644e and contact structure 670e. In some implementations, bonding layers 634e, 636e, 638e, and 640e may be referred to as direct bonding layers, and may have the same characteristics as... Figure 6B The structure is similar to that of bonding layer 634a described herein. Each of bonding layers 634e, 636e, 638e, and 640e may include at least one dielectric material and does not include conductive bonding contacts. In some embodiments, bonding layer 642e may be referred to as a hybrid bonding layer and may have a structure similar to... Figure 6C The bonding layer 640a described herein has a similar structure. The bonding layer 642e may include bonding contacts (e.g., such as...). Figure 6E The conductive bonding contact 656e shown and the isolation bonding contact are made of at least one dielectric material.

[0255] Contact structures 626e-632e and 670e extend in a vertical direction (e.g., the Z direction) and are coupled to conductive layers 610e-616e and 668e, respectively. Contact structure 670e extends into the base die 644e and contacts the conductive layer 668e of the base die 644e, without extending through the bonding layer 640e. Contact structure 626e extends through the bonding layer 640e into the memory die 602e and contacts the conductive layer 610e of the memory die 602e, without extending through the bonding layer 634e. Contact structure 628e extends through the bonding layer 640e, the conductive layer 610e of the memory die 602e, and the bonding layer 634e. Contact structure 628e further extends into the memory die 604e and contacts the conductive layer 612e of the memory die 604e, without extending through the bonding layer 636e. Contact structure 630e extends through bonding layer 640e, conductive layer 610e of memory die 602e, bonding layer 634e, memory die 604e, conductive layer 612e, and bonding layer 636e. Contact structure 630e further extends into memory die 606e and contacts conductive layer 614e of memory die 606e, without extending through bonding layer 638e. Contact structure 632e extends through bonding layer 640e, conductive layer 610e of memory die 602e, bonding layer 634e, memory die 604e, conductive layer 612e, bonding layer 636e, memory die 606e, conductive layer 614e, and bonding layer 638e. Contact structure 632e further extends into memory die 608e and contacts conductive layer 616e of memory die 608e, without extending through memory die 608e. Although Figure 6E An example is shown where contact structures 626e-632e do not extend through conductive layer 668e; however, it should be understood that in some other embodiments, one or more of contact structures 626e-632e may extend through conductive layer 668e.

[0256] In some embodiments, conductive layers 610e-616e may have the same dimensions and may be located at the same position along the X direction. That is, conductive layers 610e-616e may be aligned along the Z direction. Each contact structure in contact structures 626e-632e may include a conductive structure (inner layer) extending along the Z direction and an insulating layer (outer layer) surrounding the conductive structure. The insulating layer may isolate the conductive structure from one or more conductive layers through which the contact structure extends.

[0257] The base die 644e may include an interconnect layer in contact with the bonding layer 642e. Figure 6E (Not shown in the image). Each of the contact structures 626e-632e and 670e can be coupled to the interconnect layer of the base die 644e. More on this later... Figure 6FA further detailed description of an example of the interconnect layer of the base die 644e is provided. The interconnect layer of the base die 644e can be coupled to the computing die 646e via conductive bonding contacts 656e in the bonding layer 642e. The conductive bonding contacts 656e can be configured to couple the base die 644e and memory dies 602e-608e to the computing die 646e. The computing die 646e can be... Figure 1 An example of computing die 108. Computing die 646e includes a via 652e extending along the Z-direction through computing die 646e and connected to conductive bonding contact 656e. Each of the contact structures 670e and 626e-632e can be coupled to a corresponding one of the vias 652e through the interconnect layer of the base die 644e and the corresponding conductive bonding contact 656e. In some embodiments, via 652e may be a TSV.

[0258] In some embodiments, the base die 644e includes control circuitry configured to control memory dies 602e-608e. The control circuitry may be coupled to memory dies 602e-608e, for example, via contact structures 670e and 626e-632e, the interconnect layer of the base die 644e, and conductive bonding contacts 656e.

[0259] Intermediate layer 648e has surface 658e and surface 660e. Surface 658e can be bonded to computing die 646e. Conductive terminal 662e can be connected to surface 660e. Intermediate layer 648e may include interconnects connecting vias 652e of computing die 646e to conductive terminal 662e. Conductive terminal 662e can be coupled to external devices (e.g., Figure 1 (External host die 112). In some embodiments, the conductive terminal 662e may be a microbump.

[0260] In some implementations, such as Figure 6E As shown, memory dies 602e-606e can have reduced thickness (along the Z direction) by thinning their substrate. The topmost memory die 608e (e.g., the one furthest from the base die 644e among memory dies 602e-608e) may not be thinned. Therefore, the thickness of each of memory dies 602e-606e can be less than the thickness of memory die 608e. The thickness of each of memory dies 602e-608e can be within any suitable range (e.g., between 3 μm and 20 μm).

[0261] Figure 6F This disclosure illustrates some aspects of the content. Figure 6EFigure 600f shows an enlarged view of the interconnect layer 645f in the base die 644e. The interconnect layer 645f is located along the Z-direction between the contact structures 626e-632e and 670e and the bonding layer 642e. The interconnect layer 645f may include interconnects (also referred to herein as “contacts”), including lateral interconnects 647f and VIA contacts (not shown). The contact structures 626e-632e and 670e and the conductive bonding contacts 656e of the bonding layer 642e may be coupled to the interconnects in the interconnect layer 645f. The interconnect layer 645f may also include one or more ILD layers (also referred to as IMD layers) in which the interconnects 647f and VIA contacts may be formed. That is, the interconnect layer 645f may include interconnects 647e and VIA contacts in multiple ILD layers. The interconnects 647f and VIA contacts in the interconnect layer 645f may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The ILD layer in interconnect layer 645f may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant (low k) dielectrics, or any combination thereof.

[0262] Figure 6G A side view of a semiconductor device 600g according to some aspects of this disclosure is shown. The semiconductor device 600g includes memory dies 602g-608g, a base die 644g, a computing die 646g, and an interposer 648g. The memory dies 602g-608g and the base die 644g are stacked sequentially along the Z-direction. The base die 644g and the computing die 646g are integrated at different locations on the interposer 648g along the X-direction. The memory dies 602g-608g are similar to... Figure 3A The memory dies are 602a-608a. The memory dies are 602g-608g. Figure 1 The memory die 102 and Figure 2A Examples of memory dies 204a-204d (e.g., DRAM). The stack of memory devices 602g-608g includes a device region 601g and a connection region 603g adjacent to the device region 601g in a horizontal direction (e.g., the X direction). Memory dies 602g-608g include conductive layers 610g-616g extending in a horizontal direction (e.g., the X direction), respectively. Each of conductive layers 610g-616g is coupled to a memory array or peripheral circuitry in the corresponding memory die within the device region 601g. Each of conductive layers 610g-616g may be coupled to an input / output port of the corresponding memory die, or may be configured to provide one or more of power, clock, or data path signals to the corresponding memory die.

[0263] like Figure 6GAs shown, the semiconductor device 600g includes contact structures 626g-632g in the connection region 603g. The contact structures 626g-632g can be... Figure 2A-2B An example of contact structure 210. The semiconductor device 600g also includes bonding layers (e.g., bonding layers 634g, 636g, and 638g) between adjacent memory dies 602g-608g and a bonding layer 640g between memory die 602g and base die 644g. Each of these bonding layers may include silicon oxide. Base die 644g includes a surface 665g and another surface 667g. Surface 665g is bonded to memory die 602g via bonding layer 640g. Base die 644g also includes a conductive layer 668g and a contact structure 670g connected to the conductive layer 668g. Contact structure 670g extends into base die 644g in the Z direction. Conductive layer 668g may couple circuitry of base die 644g between contact structure 670g. In some embodiments, bonding layers 634g, 636g, 638g, and 640g may be referred to as direct bonding layers, and may have the same characteristics as... Figure 6B The structure of bonding layer 634a described herein is similar to that of the structure described herein. Each of bonding layers 634g, 636g, 638g, and 640g may include at least one dielectric material and does not include conductive bonding contacts.

[0264] Contact structures 626g-632g and 670g extend in a vertical direction (e.g., the Z direction) and are coupled to conductive layers 610g-616g and 668g, respectively. Contact structure 670g extends into the base die 644g and contacts the conductive layer 668g of the base die 644g, but does not extend through the bonding layer 640g. Contact structure 626g extends through the bonding layer 640g into the memory die 602g and contacts the conductive layer 610g of the memory die 602g, but does not extend through the bonding layer 634g. Contact structure 628g extends through the bonding layer 640g, the conductive layer 610g of the memory die 602g, and the bonding layer 634g. Contact structure 628g further extends into the memory die 604g and contacts the conductive layer 612g of the memory die 604g, but does not extend through the bonding layer 636g. Contact structure 630g extends through bonding layer 640g, conductive layer 610g of memory die 602g, bonding layer 634g, memory die 604g, conductive layer 612g, and bonding layer 636g. Contact structure 630g further extends into memory die 606g and contacts conductive layer 614g of memory die 606g, but does not extend through bonding layer 638g. Contact structure 632g extends through bonding layer 640g, conductive layer 610g of memory die 602g, bonding layer 634g, memory die 604g, conductive layer 612g, bonding layer 636g, memory die 606g, conductive layer 614g, and bonding layer 638g. Contact structure 632g further extends into memory die 608g and contacts conductive layer 616g of memory die 608g, but does not extend through memory die 608g. Although Figure 6G An example is shown where contact structures 626g-632g do not extend through conductive layer 668g; however, it should be understood that in some other embodiments, one or more of contact structures 626g-632g may extend through conductive layer 668g.

[0265] In some embodiments, conductive layers 610g-616g may have the same dimensions and may be located at the same position along the X direction. That is, conductive layers 610g-616g may be aligned along the Z direction. Each contact structure in contact structures 626g-632g may include a conductive structure (inner layer) extending along the Z direction and an insulating layer (outer layer) surrounding the conductive structure. The insulating layer may isolate the conductive structure from one or more conductive layers through which the contact structure extends.

[0266] The base die 644g may include an interconnect layer ( Figure 6G (Not shown in the image). The interconnect layer of the base die 644g has... Figure 6FThe structure of interconnect layer 645f described herein is similar to that of the structure described above. Each of contact structures 626g-632g and 670g can be coupled to the interconnect layer of the base die 644g. The base die 644g can be coupled to the computing die 646g via the interconnect layer and the interposer layer 648g. The interposer layer 648g has a surface 658g and a surface 660g. Interconnects in the interconnect layer of the base die 644g can be connected to conductive terminals 664g on surface 658g of the interposer layer 648g. The computing die 646g can be connected to conductive terminals 666g on surface 658g of the interposer layer 648g. The semiconductor device 600g may include conductive terminals 662g connected to surface 660g of the interposer layer 648g. Conductive terminals 664g, 666g, and 662g can be connected via conductive lines in the interposer layer 648g (e.g., as shown in the image). Figure 6G The conductive wire 669g shown is coupled. The conductive terminal 662g can be coupled to an external device (e.g., Figure 1 The external host die 112). In some embodiments, conductive terminals 664g, 666g, and 662g may be microbumps. It should be understood that in practice, the base die 644g, computing die 646g, and interposer 648g may be integrated together using any suitable packaging technology, including, for example, chip-on-wafer (CoWoS) on a substrate.

[0267] In some embodiments, the base die 644g includes control circuitry configured to control memory dies 602g-608g. The control circuitry may be coupled to the memory dies 602g-608g, for example, via contact structures 670g and 626g-632g and the interconnect layer of the base die 644g.

[0268] In some implementations, such as Figure 6G As shown, memory dies 602g-606g can have a reduced thickness (along the Z direction) by thinning their substrate. The topmost memory die 608g (e.g., the one furthest from the base die 644g among memory dies 602g-608g) may not be thinned. Therefore, the thickness of each of memory dies 602g-606g can be less than the thickness of memory die 608g. The thickness of each of memory dies 602g-608g can be within any suitable range (e.g., between 3 μm and 20 μm).

[0269] Figure 7A-7N Example processes for manufacturing a semiconductor device according to some aspects of this disclosure are illustrated. In some embodiments, the processes described herein can be used to manufacture any suitable semiconductor device, such as semiconductor devices 200d, 600a, and 600d.

[0270] Figure 7AThe process is illustrated by providing semiconductor structures 700 and 702, both extending in a horizontal direction (e.g., the X direction). Semiconductor structure 700 may be a carrier wafer. Semiconductor structure 702 may include a conductive layer 710 (e.g., Figure 6A Semiconductor devices or semiconductor dies (e.g., conductive layer 610a) of the semiconductor layer 610a Figure 2D Memory die 204a or Figure 6A The memory die 602a). Semiconductor structure 702 may be stacked on semiconductor structure 700 in a vertical direction (e.g., the Z-direction) and bonded to semiconductor structure 700 via bonding layer 701. Any suitable bonding technique (e.g., direct bonding) can be used to bond semiconductor structures 700 and 702. For example, a first dielectric layer (e.g., silicon oxide) may be deposited on surface 703 of semiconductor structure 700, and a second dielectric layer (e.g., silicon oxide) may be deposited on surface 705 of semiconductor structure 702. By applying pressure and heat, the first and second dielectric layers can be bonded together to form bonding layer 701 between semiconductor structures 700 and 702. Semiconductor structure 700 can serve as a support for semiconductor structure 702. Semiconductor structures 700 and 702 may have any suitable thickness along the Z-direction. In some embodiments, the thickness of semiconductor structure 702 may be in the range of 40 μm and 50 μm.

[0271] like Figure 7B As shown, semiconductor structure 702 is thinned. Thinning semiconductor structure 702 includes removing the top portion of semiconductor structure 702 (e.g., the portion furthest from semiconductor structure 700 along the Z direction). For example, the thickness of semiconductor structure 702 can be reduced from about 40-50 μm to 3-20 μm by thinning. In some embodiments, semiconductor structure 702 includes a substrate on its bottom and is inverted before being bonded to semiconductor structure 700. That is, after inversion, the substrate of semiconductor structure 702 becomes the top of semiconductor structure 702. Therefore, a portion of the substrate of semiconductor structure 702 is removed by thinning the top portion of semiconductor structure 702. In some embodiments, semiconductor structure 702 can still maintain its shape after thinning without significant distortion or deformation due to the support provided by semiconductor structure 700 (e.g., carrier wafer).

[0272] like Figure 7C As shown, a semiconductor structure 704 is provided. Semiconductor structure 704 (e.g., Figure 6A The memory die 604a) includes a conductive layer 712 (e.g., Figure 6A (Conductive layer 612a). In some embodiments, the semiconductor structure 704 includes a substrate in its top portion, which is similar to that described above. Figure 7BThe semiconductor structure 702 is described. A semiconductor structure 704 can be aligned with the semiconductor structure 702 to place conductive layers 712 and 710 in the same location along the X direction. By doing so, conductive layers 712 and 710 can be aligned along the Z direction. In some embodiments, conductive layers 712 and 710 may have the same dimensions. A dielectric layer can be deposited on the bottom surface of the semiconductor structure 704, and a dielectric layer can be deposited on the top surface of the semiconductor structure 702. The semiconductor structure 704 can be stacked on and bonded to the semiconductor structure 702 along the Z direction, similar to... Figure 7A Examples of the described bonding semiconductor structure 702 and semiconductor structure 700.

[0273] like Figure 7D As shown, the dielectric layer of semiconductor structure 704 and the dielectric layer of semiconductor structure 702 can form a bonding layer 707. Semiconductor structure 704 is thinned by removing a top portion (e.g., a portion of the substrate of semiconductor structure 704).

[0274] Figure 7E The illustration shows a provision including a conductive layer 714 (e.g., Figure 6A The semiconductor structure 706 (e.g., conductive layer 614a) is a semiconductor structure. Figure 6A The memory die 606a) and including a conductive layer 716 (e.g., Figure 6A The semiconductor structure 708 (e.g., conductive layer 616a) Figure 6A (Memory die 608a). Semiconductor structure 706 is similar to that of... Figures 7A-7D The described example aligns with, stacks on, and bonds to semiconductor structure 704. Semiconductor structure 706 may also be thinned. Similarly, semiconductor structure 708 aligns with, stacks on, and bonds to semiconductor structure 706. In some embodiments, semiconductor structure 708 is not thinned, so that when the stack of semiconductor structures 704-708 is inverted in a later step, semiconductor structure 708 provides support for other semiconductor structures due to its thickness. Conductive layers 710-716 may have the same length and may be aligned along the Z-direction. In some embodiments, semiconductor structures 704-708 (e.g., before thinning) may have the same structure. Therefore, the order in which semiconductor structures 704-708 are stacked may not affect the manufacturing process. That is, marking semiconductor structures 704-708 may not be necessary.

[0275] While in this example the semiconductor device may include four semiconductor structures 702-708 stacked together, the techniques disclosed herein can be applied to stacking any suitable number of semiconductor structures (e.g., 2, 5, or 8). The number of semiconductor structures can be determined based on factors including technical constraints, thermal considerations, signal integrity and interference, physical size and application, cost and yield, reliability issues, etc. In those cases, the last semiconductor structure furthest from semiconductor structure 700 (rather than, as shown) Figure 7E The fourth one shown can be thicker than the other semiconductor structures along the Z-direction. For example, the last semiconductor structure is not thinned, but the other semiconductor structures are thinned. In this way, when the stacked structure is inverted in a later step, the last semiconductor structure can provide support due to its thickness.

[0276] like Figure 7F As shown, semiconductor structure 700 can be removed using a stripping process. The stack of semiconductor structures 702-708 is then inverted. As the thickest of semiconductor structures 702-708, semiconductor structure 708 now sits at the bottom and supports the other semiconductor structures.

[0277] Figure 7G A mask layer 711 is shown formed on top of a semiconductor structure 702. Openings 713, 715, 717, and 719 are formed in the mask layer 711. In some embodiments, the mask layer 711 comprises a photoresist material, and the openings 713, 715, 717, and 719 can be formed by etching the mask layer 711. The locations of the openings 713, 715, 717, and 719 can be determined such that each contact hole extending along the Z direction (e.g., ...) Figure 7H The contact holes 725, 727, 729 and 731 can extend from one of the openings 713, 715, 717 and 719 to reach the conductive layer 710.

[0278] Figure 7H Contact holes 725, 727, 729, and 731 are shown forming extending along the Z-direction into a semiconductor structure 702. Contact holes 725, 727, 729, and 731 extend from openings 713, 715, 717, and 719, respectively, and reach a conductive layer 710. In some embodiments, contact holes 725, 727, 729, and 731 are formed by etching an insulating material (e.g., silicon oxide) into the semiconductor structure 702 (e.g., using a first etching gas).

[0279] Figure 7I The diagram shows the contact hole 725 being filled with a filler material 718. In some embodiments, the filler material 718 may include any suitable material, such as a dielectric material or a photoresist material in the mask layer 711.

[0280] Figure 7J The diagram shows that contact holes 727, 729, and 731 can be deepened, and the deepened contact holes 727, 729, and 731 extend through conductive layer 710 and reach conductive layer 712. Contact holes 727, 729, and 731 can be deepened by etching through conductive layer 710 (e.g., using a second etching gas) and etching the material (e.g., silicon oxide) between conductive layer 710 and conductive layer 712 (e.g., using a first etching gas). Compared to the first etching gas, the second etching gas can have a faster etching rate for conductive materials (e.g., metals) in the conductive layers (e.g., conductive layers 710-716).

[0281] Figure 7K Contact holes 729 and 731 can be further deepened. Contact hole 727, extending from opening 715 to conductive layer 712, is filled with a filler material (e.g., filler material 718). Contact holes 729 and 731 can be deepened by etching through conductive layer 712 (e.g., using a second etching gas) and etching the material (e.g., silicon oxide) between conductive layer 712 and conductive layer 714 (e.g., using a first etching gas). The deepened contact holes 729 and 731 extend through conductive layers 710 and 712 and reach conductive layer 714. The deepened contact hole 729 can then be filled with a filler material (e.g., filler material 718). Contact hole 731 can be further deepened by etching through conductive layer 714 (e.g., using a second etching gas) and etching the material (e.g., silicon oxide) between conductive layer 714 and conductive layer 716 (e.g., using a first etching gas). The deepened contact hole 731 can extend from opening 719 to conductive layer 716.

[0282] Figure 7L The removal of filler material from contact holes 725, 727, and 729 is illustrated. Mask layer 411 can also be removed using, for example, chemical mechanical planarization (CMP).

[0283] Figure 7MContact structures 726, 728, 730, and 732 are shown formed in contact holes 725, 727, 729, and 731, respectively. Each of the contact structures 726, 728, 730, and 732 may include an outer layer (e.g., outer layer 733) and an inner layer (e.g., inner layer 735) on the inner surface of the outer layer 733. The inner layer may include a conductive material (e.g., copper or tungsten) and may be referred to as a conductive structure. The outer layer may include an insulating material (such as a dielectric material like silicon oxide) and may be referred to as an insulating layer. The contact structures 726, 728, 730, and 732 can be formed by first depositing a dielectric material into the contact holes 725, 727, 729, and 731 to form an insulating layer on the inner surface of the contact holes 725, 727, 729, and 731. Subsequently, the bottom of the insulating layer can be etched away to expose the conductive layers 710, 712, 714, and 716 in the contact holes 725, 727, 729, and 731, respectively. Then, the inner layers of contact structures 726, 728, 730, and 732 can be formed by depositing conductive material into the contact holes 725, 727, 729, and 731. As a result, contact structures 726, 728, 730, and 732 are coupled to conductive layers 710, 712, 714, and 716, respectively, and the corresponding outer layer 733 can isolate each conductive structure from one or more conductive layers through which the contact structure extends. In some embodiments, after deposition, CMP can be used to polish away excess material such as metal and dielectric, leaving a flat surface with a metallic finish in the contact holes.

[0284] Figure 7N The diagram shows a semiconductor structure 744 stacked on and bonded to a semiconductor structure 702. The semiconductor structure 744 can be a base die (e.g., Figure 2A Basic die 212, Figure 6A The base die 644a or Figure 6DThe base die 644d. Semiconductor structure 744 includes vias 750 extending along the Z direction. Semiconductor structure 744 can be bonded to semiconductor structure 702 using any suitable bonding technique. In some embodiments, semiconductor structure 744 and semiconductor structure 702 can be bonded via conductive bonding contacts and a dielectric material. Specifically, a bonding layer 743 can be formed on the top surface of semiconductor structure 702. Bonding layer 743 may include conductive bonding contacts 742 and a dielectric material isolating the conductive bonding contacts 742. Contact structures 726, 728, 730, and 732 are connected to corresponding bonding contacts of conductive bonding contacts 742. In some embodiments, an interconnect layer is formed in semiconductor structure 702 prior to the formation of bonding layer 743. The interconnect layer can be coupled to contact structures 726, 728, 730, and 732. Bonding layer 745 can be formed on the bottom surface of semiconductor structure 744. Bonding layer 745 may include conductive bonding contacts 746 and a dielectric material isolating the conductive bonding contacts 746. The conductive bonding contacts 746 are connected to vias 750 of the semiconductor structure 744. Conductive bonding contacts 742 and 746 may include the same conductive material, such as a metal (e.g., copper). Bonding layers 743 and 745 may include the same dielectric material (e.g., silicon oxide). The semiconductor structure 744 is stacked on the semiconductor structure 702 such that bonding layer 745 contacts bonding layer 743, and each conductive bonding contact 746 contacts a corresponding conductive bonding contact 742. Bonding layers 745 and 743 are performed by applying pressure and heat.

[0285] In some implementations, modifications can be made regarding Figure 7A-7N The described process is to form a semiconductor device having a contact structure extending through the semiconductor structure 744 (e.g., as described in relation to...). Figure 6E and Figure 6G The memory die and the stack of base dies described. For example, before forming a mask layer 711 on top of the semiconductor structure 702 (as... Figure 7G As shown, semiconductor structure 744 can be stacked on semiconductor structure 702 and bonded to semiconductor structure 702 via a dielectric bonding layer. A mask layer 711 can then be formed on top of semiconductor structure 744. Therefore, a contact structure extending through semiconductor structure 744 can be formed by etching mask layer 711 to form openings, forming contact holes extending from the openings to conductive layers 710-716, and forming contact structures in the contact holes, similar to the contact structure shown above. Figure 7G-7M The described process.

[0286] In some embodiments, semiconductor structures 702, 704, 706, 708, and 744 can be fabricated individually, such that limitations in fabricating one of them (e.g., thermal budget) do not limit the process for fabricating the others. In some embodiments, semiconductor structures 702, 704, 706, 708, and 744 can be fabricated in parallel.

[0287] In some implementations, each of the semiconductor structures 702, 704, 706, 708, and 744 includes a semiconductor die (e.g., a memory die or a base die). Each semiconductor die may include fully functional electronic circuitry (e.g., a microprocessor, memory, sensor, or any other suitable type of integrated circuit) and may be encapsulated in a protective package.

[0288] In some embodiments, each of the semiconductor structures 702, 704, 706, 708, and 744 includes a semiconductor wafer. The semiconductor wafer may include multiple semiconductor devices or dies manufactured by depositing multiple layers of various materials and etching them onto the semiconductor wafer in a complex pattern defined by a chip design. (See also: Regarding...) Figure 7A-7N The process is performed at the wafer level and applied to multiple semiconductor wafers to form a stack of semiconductor wafers bonded together. After the process is complete, the stack of semiconductor wafers is diced and cut into individual dies. Each individual die (which may also be referred to as a die) includes fully functional electronic circuitry, which may be a microprocessor, HBM, sensor, or any other suitable type of integrated circuit. In some embodiments, each individual die is encapsulated in a protective package, thereby providing physical support, protection from environmental factors, and connectivity to external devices or systems (e.g., via pins or solder balls).

[0289] Figure 8 A flowchart illustrating an example process 800 for forming a semiconductor device according to some aspects of this disclosure is shown. The semiconductor device may be structurally similar to or identical to semiconductor devices 200d, 600a, 600d, 600e, and 600g, or a portion thereof, or intermediate manufacturing processes of such semiconductor devices. Reference may be made to... Figure 7A-7N To describe process 800. Process 800 may include forming Figure 7A-7N The process of manufacturing semiconductor structures. Process 800 includes steps that can be performed in any suitable order and / or any combination.

[0290] At step 802, a first die and a second die are provided. The first die includes a first conductive layer and at least a first bonding layer. The second die includes a second conductive layer and at least a second bonding layer. The first die may be, for example... Figure 7D The semiconductor structure 702, and the second die can be, for example... Figure 7DThe semiconductor structure 704. In some embodiments, the first bonding layer of the first die and the second bonding layer of the second die each comprise a dielectric material and do not include conductive bonding contacts. In some embodiments, providing the first die includes thinning the first die by thinning the substrate included in the first die (e.g., as per [reference to...]). Figure 7B The thinned semiconductor structure described is 702).

[0291] At step 804, the second die is stacked on top of the first die along a first direction (e.g., the Z direction). In some embodiments, stacking the second die on top of the first die along the first direction includes aligning the second die with the first die to place the second conductive layer and the first conductive layer in the same location along a second direction perpendicular to the first direction (e.g., the X direction).

[0292] At step 806, the second bonding layer of the second die is bonded to the first bonding layer of the first die. For example, the second bonding layer may be a dielectric layer deposited on the bottom surface of the semiconductor structure 704, and the first bonding layer may be a dielectric layer deposited on the top surface of the semiconductor structure 702, as per [reference to...]. Figure 7C Described.

[0293] At step 808, a first contact structure and a second contact structure extending along a first direction are formed. The first contact structure (e.g., Figure 7M The contact structure 726 extends into the first die (e.g., semiconductor structure 702) and contacts the first conductive layer of the first die (e.g., conductive layer 710), without extending through the first bonding layer. The second contact structure (e.g., Figure 7M The contact structure 728 extends through the first conductive layer, the first bonding layer of the first die, and the second bonding layer of the second die and enters the second die (e.g., semiconductor structure 704). The second contact structure contacts the second conductive layer of the second die (e.g., conductive layer 712) without extending through the second die.

[0294] In some embodiments, process 800 further includes on a carrier wafer (e.g., Figure 7A-7N A first die is stacked on a semiconductor structure 700. The first die can be stacked on a carrier wafer before a second die is stacked on top of the first die. The first die is located between the carrier wafer and the second die.

[0295] In some implementations, the first contact structure and the second contact structure are manufactured using the following processes (e.g., as per [reference]). Figure 7H-7M The process involves forming a mask layer (e.g., on top of the first die) to form a mask layer. Figure 7G The mask layer 711) is etched to form the first opening (e.g., Figure 7GThe opening 713) and the second opening (e.g., Figure 7G The opening 715). Then, a first contact hole extending in the first direction is formed (e.g., Figure 7H The contact hole 725) and the second contact hole (e.g., Figure 7H Contact hole 727). The first contact hole extends from the first opening to the first conductive layer, and the second contact hole extends from the second opening to the first conductive layer. The process also includes filling with a filler material (e.g., Figure 7I The first contact hole is filled with filler material 718. The second contact hole is deepened until it extends through the first conductive layer and into the second conductive layer. The filler material in the first contact hole is removed. The process also includes forming a corresponding insulating layer (e.g., ) in each of the first and second contact holes. Figure 7M The outer layer 733). The process also includes forming a conductive structure in the insulating layer of each of the first and second contact holes (e.g., by depositing a conductive material such as copper or tungsten into the first and second contact holes). The first contact structure includes an insulating layer and a conductive structure in the first contact hole, and the second contact structure includes an insulating layer and a conductive structure in the second contact hole.

[0296] In some embodiments, forming the first contact structure and the second contact structure further includes etching the bottom of the insulating layer to expose the first conductive layer of the first die and the second conductive layer of the second die in the first contact hole and the second contact hole, respectively.

[0297] In some embodiments, forming the first contact hole and the second contact hole includes etching the insulating material in the first die using a first etching gas, and deepening the second contact hole includes etching the conductive material of the first conductive layer using a second etching gas different from the first etching gas.

[0298] In some embodiments, process 800 further includes forming a third bonding layer on the top surface of the first die opposite to the first bonding layer (e.g., Figure 7N The third bonding layer includes conductive bonding contacts (e.g., bonding layer 743). Figure 7N The conductive bonding contact 742 and the dielectric material that isolates the conductive bonding contact. The first contact structure and the second contact structure can be coupled to the conductive bonding contact.

[0299] In some implementations, process 800 also includes providing a base die (e.g., Figure 7N The semiconductor structure 744). The base die includes a bottom bonding layer (e.g., Figure 7N The bonding layer 745 includes conductive bonding contacts (e.g., Figure 7N The conductive bonding contacts 746 and the dielectric material that isolates the conductive bonding contacts. The base die may also include vias extending along the first direction. (See also: Regarding...) Figure 7N As described, process 800 may further include stacking a base die on a first die and bonding a bottom bonding layer of the base die to a third bonding layer of the first die. The bottom bonding layer and the third bonding layer may be bonded by bonding a dielectric material of the bottom bonding layer to a dielectric material of the third bonding layer and bonding conductive bonding contacts of the bottom bonding layer to conductive bonding contacts of the third bonding layer.

[0300] The subjects and embodiments of action and operation described in this disclosure can be implemented in digital electronic circuits, in tangibly embodied computer software or firmware, in computer hardware, including the structures disclosed in this disclosure and their structural equivalents, or combinations thereof. Embodiments of the subjects described in this disclosure can be implemented as one or more computer programs, for example, one or more modules of computer program instructions encoded on a computer program carrier for execution by or control of the operation of a data processing device. The carrier can be a tangible, non-transitory computer storage medium. Alternatively or additionally, the carrier can be an artificially generated propagation signal, such as a machine-generated electrical, optical, or electromagnetic signal, generated to encode information for transmission to a suitable receiver device for execution by the data processing device. The computer storage medium can be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination thereof, or a portion thereof. The computer storage medium is not a propagation signal.

[0301] Note that references to "an embodiment," "embodiment," "example embodiment," "some embodiments," "some implementations," etc., in this disclosure indicate that the described embodiments may include specific features, structures, or characteristics, but not every embodiment necessarily includes that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, incorporating other implementations to affect such feature, structure, or characteristic will be within the knowledge of those skilled in the art.

[0302] Generally, terms can be understood at least partly from their use in context. For example, depending at least partly on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least partly on the context, terms such as "a," "an," or "the" can again be understood to convey either a singular or a plural usage. Furthermore, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described; again, this depends at least partly on the context.

[0303] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest possible sense, such that “on” means not only “directly on” but also “on” with an intermediate feature or layer between them. Furthermore, “above” or “on top of” means not only “above” or “on top of” but also “above” or “on top of” without an intermediate feature or layer between them (i.e., directly on).

[0304] Furthermore, for ease of description, this document uses spatially relative terms such as “below,” “under,” “lower,” “above,” “upper,” etc., to describe the relationship between one element or feature as shown in the figure and one or more other elements or features. In addition to the orientations shown in the figures, spatially relative terms are intended to cover different orientations of the apparatus in use or process steps. The apparatus may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein will be interpreted accordingly.

[0305] As used herein, the term "substrate" refers to the material on which subsequent layers of material are added. A substrate includes a "top" surface and a "bottom" surface. The top surface of the substrate is typically where semiconductor devices are formed, and therefore, unless otherwise stated, semiconductor devices are formed on the top side of the substrate. The bottom surface is opposite to the top surface, and therefore the bottom side of the substrate is opposite to the top side. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafers.

[0306] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively far from the substrate. A layer may extend over the entire lower or upper layer structure, or may have a range smaller than that of the lower or upper layer structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, and may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive and contact layers (where contacts, interconnects, and / or vertical interconnect pathways (VIAs) are formed) and one or more dielectric layers.

[0307] As used herein, the term "nominal / nominal value" refers to the expected or target value of a characteristic or parameter of a component or process step set during the design phase of a product or process, and the range of values ​​higher and / or lower than the expected value. As used herein, the range of values ​​may be due to slight variations in manufacturing processes or tolerances. As used herein, the term "about" indicates a value of a given quantity that may vary based on a specific technology node associated with the subject semiconductor device. Based on a specific technology node, the term "about" may indicate a value of a given quantity that varies within, for example, 10-30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0308] In this disclosure, the terms “horizontal / horizontally / laterally” mean a lateral surface nominally parallel to the substrate, and the terms “vertical” or “perpendicularly” mean a lateral surface nominally perpendicular to the substrate.

[0309] As used herein, the term “3D memory” refers to a three-dimensional (3D) semiconductor device having vertically oriented strings of memory cell transistors (referred to herein as “memory strings”, such as NAND strings) on a laterally oriented substrate, such that the memory strings extend in the vertical direction relative to the substrate.

[0310] This disclosure provides numerous different implementations or examples for achieving various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not limiting. For instance, forming a first feature on or over a second feature in the following description may include implementations in which the first and second features can directly contact each other, and may also include implementations in which an additional feature can be formed between the first and second features such that the first and second features do not directly contact each other. Additionally, reference numerals and / or letters may be repeated in various examples throughout this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various implementations and / or configurations discussed.

[0311] The foregoing description of a particular implementation can be easily modified and / or adjusted for various applications. Therefore, based on the teachings and guidance presented herein, such adjustments and modifications are intended to be within the meaning and scope of equivalents of the disclosed implementations.

[0312] While this disclosure includes numerous details of specific embodiments, these should not be construed as limiting the scope of the claims as defined by the claims themselves, but rather as descriptions of features that may be specific to particular embodiments of a particular invention. Certain features described in this disclosure within the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in certain combinations and even initially claimed in this way, one or more features from a claimed combination may be removed from the combination in some cases, and the claims may be directed to sub-combinations or variations thereof.

[0313] Similarly, although operations are depicted in the accompanying drawings in a specific order and are recited in the claims, this should not be construed as requiring these operations to be performed in the specific order shown or in a sequential order, or to perform all of the shown operations to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system modules and components in the above embodiments should not be construed as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0314] Specific embodiments of the subject matter have been described. Other embodiments are also within the scope of the following claims. For example, the actions recited in the claims can be performed in different orders and still achieve the desired result. As an example, the processes depicted in the drawings do not necessarily require the specific order or sequential order shown to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous.

[0315] The scope and extent of this disclosure should not be limited by any of the exemplary embodiments described above, but should be defined solely by the appended claims and their equivalents.

Claims

1. A semiconductor device comprising: a first layer, a second layer, a first die between the first layer and the second layer, and a second die stacked together along a first direction, wherein each of the first die and the second die has a conductive layer, and wherein the first die and the second die are bonded through the second layer; a first contact structure coupled to the conductive layer of the first die, wherein the first contact structure extends along the first direction and contacts the conductive layer of the first die without extending through the second layer, and a second contact structure coupled to the conductive layer of the second die, wherein the second contact structure extends along the first direction through the conductive layer of the first die and the second layer, and contacts the conductive layer of the second die without extending through the second die.

2. The semiconductor device according to claim 1, wherein The conductive layer of the first die and the conductive layer of the second die have a same size and are at a same location along a second direction perpendicular to the first direction.

3. The semiconductor device according to claim 1 or claim 2, wherein Each of the first contact structure and the second contact structure includes a conductive layer extending along the first direction and an insulating layer surrounding the conductive layer.

4. The semiconductor device of any one of claims 1 to 3, wherein: the first layer includes conductive bonding contacts and at least one dielectric material isolating the conductive bonding contacts, and the second layer includes at least one dielectric material and does not include conductive bonding contacts.

5. The semiconductor device of claim 4, wherein: the first layer includes a top bonding layer and a bottom bonding layer, each of the top bonding layer and the bottom bonding layer including conductive bonding contacts and a dielectric material isolating the conductive bonding contacts; the dielectric material of the top bonding layer of the first layer is bonded to the dielectric material of the bottom bonding layer of the first layer; the conductive bonding contacts of the top bonding layer of the first layer are bonded to the conductive bonding contacts of the bottom bonding layer of the first layer; the second layer includes a top bonding layer and a bottom bonding layer, each of the top bonding layer and the bottom bonding layer including a dielectric material and not including conductive bonding contacts; and the dielectric material of the top bonding layer of the second layer is bonded to the dielectric material of the bottom bonding layer of the second layer.

6. The semiconductor device of claim 4, further comprising a base die bonded to the first die by the first layer, wherein, The base die, the first layer, the first die, the second layer, and the second die are stacked along the first direction.

7. The semiconductor device of claim 6, wherein: the base die includes first vias extending along the first direction and coupled to the conductive bonding contacts of the first layer; and each of the first contact structure and the second contact structure is coupled to one of the first vias through one of the conductive bonding contacts of the first layer.

8. The semiconductor device of claim 7, further comprising a compute die and an interposer, wherein, The base die and the compute die are integrated on different locations of the interposer along a second direction perpendicular to the first direction.

9. The semiconductor device of claim 8, wherein: the first via is coupled to a first conductive terminal on a surface of the interposer; the compute die is coupled to a second conductive terminal on the surface of the interposer; and the first conductive terminal and the second conductive terminal are coupled through a conductive line in the interposer.

10. The semiconductor device of claim 7, further comprising a compute die bonded to the base die by a third layer, wherein, the compute die, the third layer, the base die, the first layer, the first die, the second layer, and the second die are stacked along the first direction.

11. The semiconductor device of claim 10, wherein: the third layer includes conductive bonding contacts and at least one dielectric material isolating the conductive bonding contacts.

12. The semiconductor device of claim 11, wherein: the third layer includes a top bonding layer and a bottom bonding layer, each of the top bonding layer and the bottom bonding layer including conductive bonding contacts and a dielectric material isolating the conductive bonding contacts; the dielectric material of the top bonding layer of the third layer is bonded to the dielectric material of the bottom bonding layer of the third layer; and the conductive bonding contacts of the top bonding layer of the third layer are bonded to the conductive bonding contacts of the bottom bonding layer of the third layer.

13. The semiconductor device of claim 11, wherein: the compute die includes a second via extending along the first direction and coupled to the conductive bonding contacts of the third layer; and the first via is coupled to the second via through the conductive bonding contacts of the third layer.

14. The semiconductor device according to claim 10, further comprising an interposer, wherein, the interposer, the compute die, the third layer, the base die, the first layer, the first die, the second layer, and the second die are stacked along the first direction.

15. The semiconductor device of claim 6, further comprising: a third die, the third die being furthest from the base die along the first direction among the first die, the second die, and the third die, wherein a thickness of the first die and a thickness of the second die are each less than a thickness of the third die along the first direction.

16. The semiconductor device according to claim 15, wherein each of the thickness of the first die and the thickness of the second die is in a range between 3 micrometers (pm) and 20 pm.

17. The semiconductor device of any one of claims 1-16, wherein: a dimension of a cross-section of the second contact structure in the first die is greater than a dimension of a cross-section of the second contact structure in the second die, the cross-section of the second contact structure in the first die and the cross-section of the second contact structure in the second die being perpendicular to the first direction.

18. The semiconductor device according to any one of Claims 1 to 17, wherein each of the first contact structure and the second contact structure is a continuous structure.

19. The semiconductor device according to any one of Claims 1 to 18, wherein the first contact structure and the second contact structure are formed through a same process.

20. The semiconductor device according to any one of Claims 1 to 19, wherein each of the first contact structure and the second contact structure has a critical dimension (CD) in a range between 0.5 pm and 10 pm.

21. The semiconductor device according to any one of Claims 1 to 20, wherein at least one of the first die or the second die includes: a memory array including an array of memory cells; and peripheral circuitry coupled to the memory array.

22. The semiconductor device according to claim 21, wherein The at least one of the first die or the second die includes a dynamic random access memory (DRAM) device.

23. The semiconductor device according to claim 6, wherein The base die includes control circuitry configured to control the first die and the second die.

24. The semiconductor device of any one of claims 1 to 23, wherein: a stack structure of the first die and the second die includes a first device region, a second device region, and a connection region between the first device region and the second device region along a second direction perpendicular to the first direction; each of the first die and the second die includes one or more memory arrays in the first device region and the second device region; and the first contact structure and the second contact structure are in the connection region.

25. The semiconductor device of claim 24, wherein: a ratio of a size of a cross section of the connection region to a sum of a first size of a cross section of the first device region and a second size of a cross section of the second device region is in a range between 1 / 6 and 1 / 5; and the cross section of the connection region, the cross section of the first device region, and the cross section of the second device region are perpendicular to the first direction.

26. A semiconductor device, comprising: a base die, a first layer, a second layer, a first die between the first layer and the second layer, and a second die stacked together along a first direction, wherein: each of the base die, the first die, and the second die has a conductive layer; the base die and the first die are bonded through the first layer; and the first die and the second die are bonded through the second layer; a first contact structure coupled to the conductive layer of the base die, wherein the first contact structure extends along the first direction and contacts the conductive layer of the base die without extending through the first layer; a second contact structure coupled to the conductive layer of the first die, wherein the second contact structure extends along the first direction and contacts the conductive layer of the first die without extending through the second layer; and a third contact structure coupled to the conductive layer of the second die, wherein the third contact structure extends along the first direction through the first layer, the conductive layer of the first die, and the second layer, and contacts the conductive layer of the second die without extending through the second die.

27. The semiconductor device of Claim 26, wherein, the conductive layer of the first die and the conductive layer of the second die have a same size and are at a same location along a second direction perpendicular to the first direction.

28. The semiconductor device of claim 26 or claim 27, wherein, each of the first contact structure, the second contact structure, and the third contact structure includes a conductive layer extending along the first direction and an insulating layer surrounding the conductive layer.

29. The semiconductor device of any one of claims 26-28, wherein: the first layer comprises at least one dielectric material and does not comprise a conductive bonding contact; and the second layer comprises at least one dielectric material and does not comprise a conductive bonding contact.

30. The semiconductor device of claim 29, wherein: the first layer comprises a top bonding layer and a bottom bonding layer, each comprising a dielectric material and not comprising a conductive bonding contact; the dielectric material of the top bonding layer of the first layer is bonded to the dielectric material of the bottom bonding layer of the first layer; the second layer comprises a top bonding layer and a bottom bonding layer, each comprising a dielectric material and not comprising a conductive bonding contact; and the dielectric material of the top bonding layer of the second layer is bonded to the dielectric material of the bottom bonding layer of the second layer.

31. The semiconductor device of claim 26, wherein: the base die comprises an interconnect layer extending along a second direction perpendicular to the first direction; and each of the first, second, and third contact structures is coupled to the interconnect layer.

32. The semiconductor device of claim 31, further comprising: a compute die and an interposer, wherein: the base die and the compute die are integrated at different locations on the interposer along the second direction; and the base die and the compute die are coupled through the interconnect layer and the interposer.

33. The semiconductor device of claim 32, wherein: the interconnect layer is coupled to first conductive terminals on a surface of the interposer; the compute die is coupled to second conductive terminals on the surface of the interposer; and the first conductive terminals and the second conductive terminals are coupled through conductive lines in the interposer.

34. The semiconductor device of claim 31, further comprising a compute die bonded to the base die by a third layer, wherein, the compute die, the third layer, the base die, the first layer, the first die, the second layer, and the second die are stacked along the first direction.

35. The semiconductor device of claim 34, wherein: the third layer comprises a conductive bonding contact and at least one dielectric material isolating the conductive bonding contact.

36. The semiconductor device of claim 35, wherein: the third layer comprises a top bonding layer and a bottom bonding layer, each comprising a conductive bonding contact and a dielectric material isolating the conductive bonding contact; the dielectric material of the top bonding layer of the third layer is bonded to the dielectric material of the bottom bonding layer of the third layer; and the conductive bonding contact of the top bonding layer of the third layer is bonded to the conductive bonding contact of the bottom bonding layer of the third layer.

37. The semiconductor device of claim 35, wherein: the compute die comprises a via extending along the first direction and coupled to the conductive bonding contact of the third layer.

38. The semiconductor device of claim 37, further comprising an interposer, wherein, The interposer, the compute die, the third layer, the base die, the first layer, the first die, the second layer, and the second die are stacked along the first direction.

39. The semiconductor device of any one of claims 26 to 38, further comprising a third die that is farthest from the base die in the first direction among the first die, the second die, and the third die, wherein, Along the first direction, each of a thickness of the first die and a thickness of the second die is less than a thickness of the third die.

40. The semiconductor device of any one of claims 26 to 39, wherein: a size of a cross-section of the second contact structure in the first die is greater than a size of a cross-section of the second contact structure in the second die, the cross-section of the second contact structure in the first die and the cross-section of the second contact structure in the second die being perpendicular to the first direction.

41. The semiconductor device according to any one of Claims 26 to 40, wherein, Each of the first contact structure and the second contact structure is a continuous structure.

42. The semiconductor device according to any one of Claims 26 to 41, wherein, The first contact structure and the second contact structure are formed by a same process.

43. The semiconductor device according to any one of Claims 26 to 42, wherein, Each of the first contact structure, the second contact structure, and the third contact structure has a critical dimension (CD) in a range between 0.5 pm and 10 pm.

44. The semiconductor device of any one of claims 26 to 43, wherein, At least one of the first die or the second die includes: a memory array including an array of memory cells; and peripheral circuitry coupled to the memory array.

45. The semiconductor device of Claim 44, wherein, The at least one of the first die or the second die includes a dynamic random access memory (DRAM) device.

46. The semiconductor device according to any one of Claims 26 to 45, wherein, The base die includes control circuitry configured to control the first die and the second die.

47. The semiconductor device of any one of claims 26 to 46, wherein: a stack structure of the first die and the second die includes a first device region, a second device region, and a connection region between the first device region and the second device region along a second direction perpendicular to the first direction; each of the first die and the second die includes one or more memory arrays in the first device region and the second device region; and the first contact structure and the second contact structure are in the connection region.

48. The semiconductor device of claim 47, wherein: a ratio of a size of a cross-section of the connection region to a sum of a first size of a cross-section of the first device region and a second size of a cross-section of the second device region is in a range between 1 / 6 and 1 / 5; and the cross-section of the connection region, the cross-section of the first device region, and the cross-section of the second device region are perpendicular to the first direction.

49. A method comprising: providing a first die and a second die, wherein the first die includes a first conductive layer and at least a first bonding layer, and the second die includes a second conductive layer and at least a second bonding layer; stacking the second die on the first die along a first direction; bonding the second bonding layer to the first bonding layer; and forming a first contact structure and a second contact structure extending along the first direction, wherein: the first contact structure contacts the first conductive layer without extending through the first bonding layer; and the second contact structure extends through the first conductive layer, the first bonding layer, and the second bonding layer, and contacts the second conductive layer without extending through the second die.

50. The method of claim 49, wherein, the first bonding layer and the second bonding layer each include a dielectric material and do not include a conductive bonding contact, and wherein bonding the second bonding layer to the first bonding layer includes bonding the dielectric material of the first bonding layer to the dielectric material of the second bonding layer.

51. The method of claim 49 or claim 50, wherein, stacking the second die on the first die along the first direction includes: aligning the second die with the first die to place the first conductive layer and the second conductive layer at the same location along a second direction that is perpendicular to the first direction, wherein the first conductive layer and the second conductive layer have the same size.

52. The method of any of claims 49-51, further comprising: thinning the first die by thinning a substrate included in the first die.

53. The method of any of claims 49-52, further comprising: bonding a carrier wafer to a surface of the first die, wherein the first die is between the carrier wafer and the second die.

54. The method of any one of claims 49 to 53, wherein, forming the first contact structure and the second contact structure includes: forming a mask layer on top of the first die; etching the mask layer to form a first opening and a second opening; forming a first contact hole and a second contact hole that extend along the first direction, wherein the first contact hole extends from the first opening to the first conductive layer, and the second contact hole extends from the second opening to the first conductive layer; filling the first contact hole with a fill material; deepening the second contact hole until the second contact hole extends through the first conductive layer and to the second conductive layer; removing the fill material in the first contact hole; forming an insulating layer in each of the first contact hole and the second contact hole; and forming the first contact structure in the first contact hole and the second contact structure in the second contact hole by depositing a conductive material into the first contact hole and the second contact hole.

55. The method of claim 54, wherein: forming the first contact hole and the second contact hole includes etching an isolation material in the first die using a first etch gas; and deepening the second contact hole includes etching a conductive material of the first conductive layer using a second etch gas that is different than the first etch gas.

56. The method of any of claims 49-55, further comprising: forming a third bonding layer on a surface of the first die that is opposite the first bonding layer, wherein the third bonding layer includes a conductive bonding contact and a dielectric material that isolates the conductive bonding contact.

57. The method of claim 56, further comprising: providing a base die, wherein the base die includes a via extending along the first direction and a fourth bonding layer including a conductive bonding contact coupled to the via and a dielectric material isolating the conductive bonding contact; and bonding the fourth bonding layer of the base die to the third bonding layer on the surface of the first die.

58. The method of claim 57, wherein, bonding the fourth bonding layer to the third bonding layer includes: bonding the dielectric material of the fourth bonding layer to the dielectric material of the third bonding layer and bonding the conductive bonding contact of the fourth bonding layer to the conductive bonding contact of the third bonding layer.

59. The method of any of claims 49 to 58, further comprising: stacking a base die on the first die, wherein the base die includes a third conductive layer; and forming a third contact structure coupled to the base die, and wherein forming the first contact structure, the second contact structure, and the third contact structure includes: forming a mask layer on top of the base die; etching the mask layer to form a first opening, a second opening, and a third opening; forming a first contact hole, a second contact hole, and a third contact hole extending along the first direction, wherein the first contact hole extends from the first opening to the first conductive layer, the second contact hole extends from the second opening to the first conductive layer, and the third contact hole extends from the third opening to the third conductive layer; filling the first contact hole and the third contact hole with a fill material; deepening the second contact hole until the second contact hole extends through the first conductive layer and to the second conductive layer; removing the fill material in the first contact hole and the third contact hole; forming an insulating layer in each of the first contact hole, the second contact hole, and the third contact hole; and forming the first contact structure in the first contact hole, the second contact structure in the second contact hole, and the third contact structure in the third contact hole by depositing a conductive material into the first contact hole, the second contact hole, and the third contact hole.

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