All-flash array for realizing inter-disk resource sharing based on hardware consistency interconnection

Abstract

The invention belongs to the technical field of electronics, and relates to an all-flash array for realizing inter-disk resource sharing based on hardware consistency interconnection. The all-flash array comprises a plurality of solid state disks; each solid state disk exposes a part of onboard memory through a CXL protocol, and the exposed onboard memory forms a global consistency memory domain, so that communication based on a shared memory can be carried out between the solid state disks; a solid state disk in an idle state is called as a creditor, the creditor calculates computing resources which can be borrowed, and availability of the computing resources is declared by writing idle resource descriptors; and calling the solid state disk lacking computing resources as a debtor, scanning idle resource descriptors of all other solid state disks by the debtor, and selecting at least one creditor to perform resource recovery so as to realize inter-disk resource sharing. According to the method, idle resources are utilized in a peak clipping and valley filling manner in a mode of sharing resources among disks in the all-flash array, so that the resource utilization rate can be improved.

Description

Technical Field

[0001] This invention belongs to the field of electronic technology, specifically relating to an all-flash array that achieves resource sharing between disks based on hardware-consistent interconnection. Background Technology

[0002] Solid-state drives (SSDs) are hard drives made of solid-state electronic storage chips (such as NAND flash memory). Figure 1 The basic architecture of a high-performance solid-state drive (SSD) is demonstrated. The SSD controller connects to the host via a PCIe (Peripheral Component Interconnect Express) channel and a host interface controller. PCIe is a high-speed serial computer expansion bus standard that lacks cache coherency. Furthermore, the SSD integrates multiple embedded processors (such as ARM processors), a DDR DRAM controller, and other dedicated processing devices (such as a DMA engine). The ARM processor is primarily responsible for running the SSD firmware, including command parsing, address translation, and garbage collection. These components are connected to the flash backend via a flash controller. The flash backend typically consists of 8 to 16 flash channels, each containing multiple flash chips. Further, a single flash chip can be divided into 2 to 4 flash planes, each containing thousands of flash blocks. A flash block typically contains hundreds of flash pages.

[0003] An all-flash array (AFA) is a storage array composed of multiple SSDs. An all-flash array is typically a server containing limited CPU resources, memory resources, and dozens or hundreds of solid-state drives. These resources are usually interconnected via a PCIe bus, allowing local or remote users to access the solid-state drives through storage access protocols such as NVMe.

[0004] The disadvantages of existing technologies are as follows:

[0005] 1) In order to achieve higher single-disk performance, more and more computing resources are stacked inside SSDs, including: more powerful processors and sufficient DRAM memory (usually 1GB of memory per TB of capacity), which leads to an increase in the material cost of SSDs.

[0006] 2) In actual production environments, SSD resource utilization is low, with peak load occurring only a small portion of the time, resulting in a large amount of idle and wasted resources. Summary of the Invention

[0007] This invention provides an all-flash array that achieves inter-disk resource sharing based on hardware-coherent interconnects. The aim is to improve resource utilization by utilizing idle resources in a peak-shaving and valley-filling manner through inter-disk resource sharing within the all-flash array. Thus, even with fewer hardware resources allocated to SSDs, the required quality of service for applications can be met, thereby reducing the cost of both SSDs and the all-flash array.

[0008] The technical solution adopted in this invention is as follows:

[0009] An all-flash array for inter-disk resource sharing based on hardware-consistent interconnect includes multiple solid-state drives (SSDs). Each SSD exposes a portion of its onboard memory via the CXL protocol. The exposed onboard memory constitutes a globally consistent memory domain, enabling communication between SSDs based on shared memory. Idle SSDs are designated as lenders. Lenders calculate the available computing resources and announce their availability by writing to a free resource descriptor. SSDs with insufficient computing resources are designated as debiters. Debits scan the free resource descriptors of all other SSDs and select at least one lender for resource reclamation, thus achieving inter-disk resource sharing.

[0010] Furthermore, the solid-state drive (SSD) adopts a resource-decoupled SSD architecture, including a computing end and a data end; the computing end includes an ARM processor, a DDR controller, and onboard DRAM, which is responsible for running the SSD firmware; the data end includes a flash controller, a flash backend, a DMA engine, and a data cache, which is responsible for data transmission and flash I / O; the SSD also includes a CXL controller to support operations related to the CXL protocol.

[0011] Furthermore, the computing terminal implements and runs a daemon process on the ARM processor, and the daemon process includes three functions:

[0012] Resource monitors are used to monitor the resource utilization of the computing and data ends.

[0013] The resource manager is used to borrow or lend computing resources based on the current resource utilization reported by the resource monitor.

[0014] The data proxy acts as a bridge between the computing end of other solid-state drives and the local data end. The computing end of the lender accesses the data end of the borrower by sending encapsulated DMA and flash commands to the data proxy of the borrower. Then, the encapsulated flash commands are decapsulated and sent to the DMA engine and flash controller of the borrower respectively for data transfer and flash I / O.

[0015] Furthermore, the computing resources include processor resources and DRAM resources;

[0016] For processor resources, the following steps are used to achieve processor resource sharing: The host-side NVMe driver redirects some I / O requests that should originally be handled by the debit to the credit; The credit uses its idle processor to manipulate the debit's metadata to assist it in parsing I / O requests; The credit sends DMA and flash instructions to the debit's DMA engine and flash controller for data transfer and flash I / O, respectively; The credit notifies the NVMe driver of the request completion status on behalf of the debit.

[0017] For DRAM resources, DRAM resource sharing is achieved by temporarily caching part of the contents of the debit mapping table in the credit DRAM.

[0018] Furthermore, each SSD monitors the usage of its internal resources and decides whether to lend or borrow resources based on configurable trigger conditions. For processor resources, the lending / borrowing trigger conditions consider the busy status of both the processor and the data terminal. If the utilization of both the processor and the data terminal exceeds a given threshold, it is considered a busy state; otherwise, it is considered an underutilization. If both the processor and the data terminal are busy, the SSD does nothing. If the processor utilization is underutilized, the SSD lends out processor resources. If only the processor is busy, the SSD borrows processor resources. When the resource status of the SSD no longer meets the trigger conditions, the SSD cancels the lending / borrowing.

[0019] Furthermore, the host-side NVMe driver selectively redirects I / O commands to the credit side using a load balancing algorithm.

[0020] Furthermore, the load balancing algorithm includes:

[0021] By leveraging NVMe's weighted round-robin feature, a weight is assigned to each NVMe I / O SQ to indicate the priority of the fetch command. Lower weights are assigned to the SQs of the lender's shadow queue pairs to minimize the impact on the lender's own I / O.

[0022] The host periodically reads the idle resource descriptor to understand the current processor utilization of debit and credit operations, and then controls the number of I / O commands sent to debit and credit operations using the following formula:

[0023]

[0024] Where, N borrow and N lend These represent the number of I / O commands sent to the debit and credit sides, respectively; U borrow and U lend It is the processor utilization rate of the debit and credit sides; W borrowSQ and W shdowSQΣ represents the weights of the SQ of the debit queue pair and the SQ of the shadow queue pair; borrow W and Σ lend W represents the total weight of all NVMe I / O SQs on the debit and credit sides, respectively.

[0025] Furthermore, for DRAM resources, MRC manages DRAM resources and sets borrowing and lending trigger conditions based on the miss rate curve of the current I / O mode.

[0026] Furthermore, for DRAM resources, a log-based crash consistency mechanism is adopted to protect off-site metadata. The log-based crash consistency mechanism includes: when borrowing DRAM begins, the borrower frees up a log page in its local DRAM for each borrowed off-site DRAM segment; subsequently, whenever an off-site DRAM segment is modified, either the borrower or the lender needs to commit the log to the log page associated with that DRAM segment; the lender ensures that the log has been written back to the borrower via a cache flush command; when the log page of an off-site DRAM segment is full, the DRAM segment is flushed back to the borrower's flash memory, and then the corresponding log page is cleared.

[0027] A method for achieving inter-disk resource sharing based on hardware-consistent interconnect, using the aforementioned all-flash array, includes the following steps:

[0028] Each solid-state drive (SSD) exposes a portion of its onboard memory via the CXL protocol. The exposed onboard memory constitutes a globally consistent memory domain, enabling SSDs to communicate with each other based on shared memory.

[0029] The solid-state drives that are in an idle state are called lenders. The lenders calculate the computing resources that can be borrowed and announce the availability of computing resources by writing to the idle resource descriptor.

[0030] Solid-state drives with scarce computing resources are called debit drives. Debit drives scan the free resource descriptors of all other solid-state drives and select at least one credit drive for resource reclamation, thereby achieving resource sharing between drives.

[0031] The key technical points and beneficial effects of this invention are as follows:

[0032] Key technology point 1: It breaks through the black box limitation of traditional solid-state drives and designs a solid-state drive architecture that decouples computing flash memory resources, realizing fine-grained management of internal resources of solid-state drives;

[0033] Key technology point two: It enables the sharing of processor and DRAM resources among different solid-state drives within the all-flash array, improving resource utilization; thus, even if the SSD is equipped with fewer hardware resources, it can still meet the service quality required by the application, thereby reducing the cost of SSDs and all-flash arrays;

[0034] Key technology point three: Transparent I / O redirection and efficient load balancing are achieved when processor resources are shared;

[0035] Key technology point four: When sharing DRAM resources, it is compatible with the power-loss protection mechanism, ensuring crash consistency. Attached Figure Description

[0036] Figure 1 It is the basic architecture of high-performance solid-state drives.

[0037] Figure 2 It is a discrete solid-state drive architecture.

[0038] Figure 3 It uses a transparent I / O redirection mechanism.

[0039] Figure 4 This is Experiment Result 1, where the x-axis represents different working sets and the y-axis represents the throughput of the all-flash array.

[0040] Figure 5 The results are experimental results 2, where (a) is the number of processor cores in the SSD and the vertical axis is the I / O bandwidth of the all-flash array, and (b) is the DRAM capacity in the SSD and the vertical axis is the I / O latency of the all-flash array. Detailed Implementation

[0041] The present invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0042] 1. Overview

[0043] Compared to existing all-flash array designs, this invention differs in four main aspects: First, it replaces traditional PCIe with the Compute Express Link (CXL) hardware coherence interconnect protocol, thereby leveraging its cache coherence capabilities. CXL is an emerging high-speed interconnect technology standard designed to overcome the limitations of the traditional PCIe protocol, providing higher throughput, lower latency, and cache coherence semantics to meet the needs of modern computing and storage systems. Second, it breaks the black-box limitation of traditional solid-state drives (SSDs), enabling fine-grained management of SSD internal resources. Third, it retains only a moderate amount of onboard computing resources (i.e., a relatively weak ARM processor and a small amount of DRAM), reducing material costs while meeting bursty performance demands through resource sharing. Finally, it slightly modifies the host-side NVMe driver to achieve I / O redirection and load balancing. All SSDs in this invention are homogeneous (i.e., equipped with the same hardware resources and running the same firmware).

[0044] The workflow of this invention is as follows:

[0045] 1) During device initialization, each SSD exposes a portion of its onboard memory via the CXL protocol. This exposed memory forms a globally consistent memory domain, enabling SSDs to communicate based on shared memory.

[0046] 2) After that, if a solid-state drive is in an idle state (called a lender), it calculates how many computing resources (i.e., processors and DRAM) can be lent out and announces the availability of these resources by writing to an idle resource descriptor.

[0047] 3) When a solid-state drive (SSD) is short of computing resources (called a borrower, for example, when encountering a burst of I / O or a low DRAM hit rate), it scans the free resource descriptors of all other SSDs and selects a borrower for resource reclamation. This step can be repeated multiple times to borrow more resources from multiple SSDs.

[0048] 4) Regarding processor resource sharing:

[0049] a) The host-side NVMe driver redirects some I / O requests that would normally be handled by the debit side to the credit side.

[0050] b) Then, the lender uses its idle processors to manipulate the debiter's metadata to assist in resolving I / O requests.

[0051] c) Subsequently, the lender sends DMA and flash commands to the debiter's DMA engine and flash controller for data transfer and flash I / O, respectively.

[0052] d) In the backward operation, the lender notifies the NVMe driver of the request completion status on behalf of the debiter.

[0053] 5) Regarding DRAM resource sharing: The debit side can directly cache part of its mapping table in the credit side's DRAM. The borrowed DRAM improves the hit rate and avoids frequent lookups of the mapping table via flash I / O due to DRAM misses, thereby improving performance.

[0054] 2. Decoupled solid-state drive architecture

[0055] Traditional solid-state drives (SSDs) are black boxes, with their internal computing and flash memory resources tightly coupled and invisible to external systems. To address this issue and achieve fine-grained resource management and sharing, this invention employs a resource-decoupled SSD architecture, decomposing the SSD into two parts: a computing end and a data end, such as... Figure 2As shown. The computing side consists of computing resources such as an ARM processor, DDR controller, and onboard DRAM. It is responsible for running the solid-state drive firmware (such as I / O parsing and address translation). The data side includes flash memory resources (such as flash controller and flash backend) and some data-related components (such as DMA engine and data cache). This part is responsible for data transfer and flash I / O. In addition, this invention also incorporates a Type-2 CXL controller to support CXL-related operations, such as exposing the onboard DRAM to the host and other solid-state drives in this invention, and supporting operations on the memory exposed by other solid-state drives.

[0056] On the computing side, this invention implements and runs a daemon process on an ARM processor. It includes three functions: (1) a resource monitor, used to monitor the resource utilization of the computing and data ends; (2) a resource manager, which borrows or lends computing resources based on the current resource utilization reported by the resource monitor; and (3) a data end agent, which bridges the gap between the computing ends of other SSDs and the local data end. Specifically, the data end agent of the borrowing side maintains part of the onboard DRAM for communication between SSDs. Therefore, the computing end of the lending side can access the data end of the borrowing side by sending encapsulated DMA and flash memory instructions to the data end agent of the borrowing side. Then, these encapsulated instructions are decapsulated and sent to the DMA engine and flash memory controller of the borrowing side respectively for data transfer and flash memory I / O.

[0057] 3. Processor resource management

[0058] 1) Triggering conditions for borrowing and lending: In this invention, each solid-state drive (SSD) monitors the usage of its internal resources and decides whether to borrow or lend resources based on configurable triggering conditions, as shown in Table 1. This invention considers both the busy state of the processor and the data end. If their utilization exceeds a given threshold (e.g., 75%), it is considered a busy state, referred to as "busy"; otherwise, it is considered underutilized, referred to as "idle". If both the processor and the data end are busy (1), the SSD will not perform any operation because it has no available processor to share. Furthermore, the benefit of borrowing additional processor resources is minimal because the data end is already under high load. In contrast, the SSD can borrow this resource as long as the processor is not fully utilized (2 and 3). This situation may occur when there is a bottleneck effect (2, such as burst writes) at the back end of the SSD flash memory or when the entire SSD is idle (3, i.e., no I / O requests). Finally, if only the processor is busy (4), the SSD can borrow (i.e., lend) processor resources to maximize the I / O parallelism of the data end, thereby achieving higher throughput. Accordingly, when the resource status of the solid-state drive no longer meets the triggering conditions, the solid-state drive can be canceled (i.e., borrowed) or lent out.

[0059] Table 1: Triggering Conditions for Borrowing and Lending

[0060] label processor Data terminal action Possible situations 1 busy busy none Mixed high load 2 idle busy lend Burst Write 3 idle idle lend No I / O request 4 busy idle borrow Burst Read

[0061] 2) I / O redirection: This invention achieves application-transparent I / O redirection by modifying the host-side NVMe driver. For example... Figure 3 As shown, during SSD initialization, this invention reserves several NVMe I / O queue pairs (called shadow queue pairs) for each SSD. Each queue pair contains one SQ and one CQ, where SQ stands for Submission Queue and CQ stands for Completion Queue. When borrowing processor resources, the lender can specify a shadow queue pair in the free resource descriptor. Subsequently, the borrower selects a normal I / O queue pair (called the borrower queue pair, which also contains one SQ and one CQ) for I / O redirection and records the identifier of the borrower queue pair in the free resource descriptor. Afterward, the host-side NVMe driver binds the borrower queue pair to the shadow queue pair and redirects some I / O commands from the borrower queue pair's SQ to the shadow queue pair's SQ. The lender can then obtain NVMe I / O commands from the shadow queue pair's SQ and assist in processing these commands. During the backward process, the host NVMe driver collects I / O results from the CQ of the borrow queue pair and the CQ of the shadow queue pair, and then submits the I / O completion status to the upper-layer software. When the borrowing ends, the shadow queue pair is unbound.

[0062] 3) Load Balancing: The host-side NVMe driver selectively redirects I / O commands to lenders using a load balancing algorithm. This algorithm consists of two parts. First, NVMe's Weighted Round Robin (WRR) feature assigns a weight to each NVMe I / O SQ, representing the priority of command retrieval. For example, if two SQs have weights of 2 and 1 respectively, the SSD firmware will fetch two I / O commands from the former's SQ and execute one command from the latter's SQ. Using this feature, Espresso can assign lower weights to the lender's shadow queue pairs of SQs to minimize the impact on lender I / O. Second, the host periodically reads the idle resource descriptor to understand the current processor utilization of the debit and credit sides. Then, the host controls the number of I / O commands sent to the debit and credit sides using the following formula:

[0063]

[0064] N borrow and N lend These represent the number of I / O commands sent to the debit and credit sides, respectively. borrow and U lendThis refers to the processor utilization rates for both debit and credit sides. W borrowSQ and W shdowSQ This represents the weights of the SQ of the debit queue pair and the SQ of the shadow queue pair. Finally, Σ borrow W and Σ leng W represents the total weight of all NVMe I / O SQs on the debit and credit sides, respectively. Using this formula, the present invention can selectively redirect I / O commands to balance processor utilization on the debit and credit sides. For example, if N... borrow / N lend If the value is 1, the present invention will redirect I / O commands to the credit side with a 50% probability.

[0065] 4. DRAM Resource Management

[0066] 1) Triggering Conditions for Borrowing / Lending: This invention manages DRAM resources based on the current I / O mode miss rate curve (MRC). Specifically, this invention uses the SHARDS algorithm to predict the MRC. Based on the predicted MRC, the solid-state drive (SSD) can borrow all available DRAM that will not result in a lower DRAM hit rate (i.e., its cache mapping table will not be accessed in the near future). Accordingly, when the SSD's current DRAM miss rate falls below a given threshold, it triggers DRAM borrowing.

[0067] 2) Crash Consistency Guarantee: This invention utilizes the credit DRAM by temporarily caching a portion of the debit mapping table in the credit DRAM, thereby reducing the miss rate and improving I / O performance. However, this approach still presents an unresolved issue in practice: how to guarantee the crash consistency of off-site metadata (i.e., the mapping table stored in the credit DRAM). Specifically, to achieve high availability, modern solid-state drives (SSDs) typically require power loss protection (PLP). When an SSD suddenly loses power, the power holding circuitry and supercapacitors in the SSD can immediately flush the data and metadata from the processor cache and onboard DRAM to the flash backend. This design ensures the crash consistency of the SSD. However, if the dirty mapping table of the debit side is only cached in the credit DRAM, the debit side cannot provide PLP to the off-site metadata. For example, if the credit SSD is permanently removed from the all-flash array, the debit side cannot recover its mapping table, resulting in data loss. To address this issue, this invention designs a log-based crash consistency mechanism to protect off-site metadata. Specifically, when borrowing DRAM begins, the borrower frees up a 4KB log page in its local DRAM for each borrowed 2MB off-site DRAM segment. Subsequently, whenever an off-site DRAM segment is modified, the SSD (borrower or lender) needs to commit the log (such as a redo log) to the log page associated with that DRAM segment. Furthermore, the lender needs to ensure that the log has been written back to the borrower via cache flush commands (such as clwb and DCCSW commands). When the log page of an off-site DRAM segment is full, the DRAM segment is flushed back to the borrower's flash memory, after which the corresponding log page can be cleared.

[0068] 5. Advantages and beneficial effects of the present invention

[0069] The inventors evaluated the solid-state drive design in this invention using the SimpleSSD simulator and simulated the CXL interconnect architecture using the ESF simulator. The inventors configured a baseline solid-state drive as a high-performance storage device (labeled as baseline) with peak read and write bandwidths of 14.3 GB / s and 9.3 GB / s, respectively. Its processor contained six ARM cores using the ARMv8 ISA and a frequency of 1 GHz. Furthermore, its onboard DRAM could accommodate the entire mapping table (i.e., 1 GB of DRAM per TB of flash memory). The inventors provided two CXL 3.0 (PCIe 6.0) lanes for each solid-state drive as its external interconnect, providing a throughput of approximately 16 GB / s. The inventors used a traditional tree topology to connect the solid-state drives and the host. In contrast, prior art design 1, prior art design 2, and the solid-state drive in this invention retain only half of the computing resources (i.e., three ARM cores and 0.5 GB of DRAM per TB of flash memory) to save on solid-state drive material costs. Prior art design 1 is a traditional all-flash array design, and prior art design 2 employs disk virtualization and request redirection.

[0070] like Figure 4 As shown, even with only half the computing resources retained (resulting in a 20% reduction in solid-state drive material costs), this invention maintains comparable throughput to the benchmark across a variety of workloads. On average, compared to existing designs 1 and 2, the throughput of this invention is increased by 26.0% and 12.5%, respectively.

[0071] More experiments such as Figure 5 As shown, the number of ARM cores in the processor of the solid-state drive in the existing design 1 and the present invention is reduced ( Figure 5 (a) and DRAM capacity ( Figure 5 As can be seen in (b) of the paper, when only 1 / 6 of the core count and 1 / 4 of the DRAM capacity of the baseline were retained, the existing design 1 experienced a 52.8% decrease in throughput and a 37.1% increase in latency. In contrast, the present invention achieves throughput and latency comparable to the baseline, while significantly reducing material costs without sacrificing performance.

[0072] The specific embodiments of the present invention disclosed above are intended to help understand the content of the present invention and to implement it accordingly. Those skilled in the art will understand that various substitutions, changes, and modifications are possible without departing from the spirit and scope of the present invention. The present invention should not be limited to the content disclosed in the embodiments of this specification; the scope of protection of the present invention is defined by the claims.

Claims

1. A full-flash array for inter-disk resource sharing based on hardware-consistent interconnection, characterized in that, It includes multiple solid-state drives (SSDs); each SSD exposes a portion of its onboard memory via the CXL protocol. The exposed onboard memory constitutes a globally consistent memory domain, enabling communication between SSDs based on shared memory. Idle SSDs are called lenders. Lenders calculate the available computing resources and announce their availability by writing to a free resource descriptor. SSDs with scarce computing resources are called debiters. Debits scan the free resource descriptors of all other SSDs and select at least one lender to reclaim resources, thus achieving resource sharing between disks.

2. The all-flash array for inter-disk resource sharing based on hardware consistency interconnection as described in claim 1, characterized in that, The solid-state drive (SSD) adopts a resource-decoupled SSD architecture, including a computing end and a data end. The computing end includes an ARM processor, a DDR controller, and onboard DRAM, which is responsible for running the SSD firmware. The data end includes a flash controller, a flash backend, a DMA engine, and a data cache, which are responsible for data transmission and flash I / O. The SSD also includes a CXL controller to support operations related to the CXL protocol.

3. The all-flash array for inter-disk resource sharing based on hardware consistency interconnection as described in claim 2, characterized in that, The computing terminal implements and runs a daemon process on an ARM processor, and the daemon process includes three functions: Resource monitors are used to monitor the resource utilization of the computing and data ends. The resource manager is used to borrow or lend computing resources based on the current resource utilization reported by the resource monitor. The data proxy acts as a bridge between the computing end of other solid-state drives and the local data end. The computing end of the lender accesses the data end of the borrower by sending encapsulated DMA and flash commands to the data proxy of the borrower. Then, the encapsulated flash commands are decapsulated and sent to the DMA engine and flash controller of the borrower respectively for data transfer and flash I / O.

4. The all-flash array for inter-disk resource sharing based on hardware consistency interconnection as described in claim 1, characterized in that, The computing resources include processor resources and DRAM resources; For processor resources, the following steps are used to achieve processor resource sharing: The host-side NVMe driver redirects some I / O requests that should originally be handled by the debit side to the credit side; the credit side uses its idle processor to manipulate the debit side's metadata to assist it in parsing I / O requests; the credit side sends DMA and flash instructions to the debit side's DMA engine and flash controller for data transfer and flash I / O, respectively. The lender, on behalf of the debiter, notifies the NVMe driver of the request completion status; For DRAM resources, DRAM resource sharing is achieved by temporarily caching part of the contents of the debit mapping table in the credit DRAM.

5. The all-flash array for inter-disk resource sharing based on hardware consistency interconnection as described in claim 4, characterized in that, Each SSD monitors the usage of its internal resources and decides whether to lend or borrow resources based on configurable trigger conditions. For processor resources, the lending / borrowing trigger conditions consider the busy status of both the processor and the data terminal. If the utilization of both the processor and the data terminal exceeds a given threshold, it is considered a busy state; otherwise, it is considered an underutilization state. If both the processor and the data terminal are busy, the SSD does nothing. If the processor utilization is underutilized, the SSD lends out processor resources. If only the processor is busy, the SSD borrows processor resources. When the resource status of the solid-state drive no longer meets the triggering conditions, the solid-state drive is canceled from borrowing or lending.

6. The all-flash array for inter-disk resource sharing based on hardware consistency interconnection as described in claim 4, characterized in that, The host-side NVMe driver selectively redirects I / O commands to the credit side using a load balancing algorithm.

7. The all-flash array for inter-disk resource sharing based on hardware consistency interconnection as described in claim 6, characterized in that, The load balancing algorithm includes: By leveraging NVMe's weighted round-robin feature, a weight is assigned to each NVMe I / O SQ to indicate the priority of the fetch command. Lower weights are assigned to the SQs of the lender's shadow queue pairs to minimize the impact on the lender's own I / O. The host periodically reads the idle resource descriptor to understand the current processor utilization of debit and credit operations, and then controls the number of I / O commands sent to debit and credit operations using the following formula: Where, N borrow and N lend These represent the number of I / O commands sent to the debit and credit sides, respectively; U borrow and U lend It is the processor utilization rate of the debit and credit sides; W borrowSQ and W shdowSQ Σ represents the weights of the SQ of the debit queue pair and the SQ of the shadow queue pair; borrow W and Σ lend W represents the total weight of all NVMe I / O SQs on the debit and credit sides, respectively.

8. The all-flash array for inter-disk resource sharing based on hardware consistency interconnection as described in claim 4, characterized in that, For DRAM resources, MRC manages DRAM resources and sets borrowing and lending trigger conditions based on the miss rate curve of the current I / O mode.

9. The all-flash array for inter-disk resource sharing based on hardware consistency interconnection as described in claim 4, characterized in that, For DRAM resources, a log-based crash consistency mechanism is used to protect off-site metadata. The log-based crash consistency mechanism includes: when borrowing DRAM begins, the borrower frees up a log page in its local DRAM for each borrowed off-site DRAM segment; subsequently, whenever an off-site DRAM segment is modified, either the borrower or the lender needs to commit the log to the log page associated with that DRAM segment; the lender ensures that the log has been written back to the borrower via a cache flush command; when the log page of an off-site DRAM segment is full, the DRAM segment is flushed back to the borrower's flash memory, and then the corresponding log page is cleared.

10. A method for achieving inter-disk resource sharing based on hardware-consistent interconnection, characterized in that, Based on any one of claims 1 to 9, the method for achieving inter-disk resource sharing using an all-flash array includes the following steps: Each solid-state drive (SSD) exposes a portion of its onboard memory via the CXL protocol. The exposed onboard memory constitutes a globally consistent memory domain, enabling SSDs to communicate with each other based on shared memory. The solid-state drives that are in an idle state are called lenders. The lenders calculate the computing resources that can be borrowed and announce the availability of computing resources by writing to the idle resource descriptor. Solid-state drives with scarce computing resources are called debit drives. Debit drives scan the free resource descriptors of all other solid-state drives and select at least one credit drive for resource reclamation, thereby achieving resource sharing between drives.

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