Accelerating unit, processor, electronic device and instruction execution method

Abstract

Embodiments of the present application provide an acceleration unit, a processor, an electronic device and an instruction execution method, and relate to the technical field of processors. The acceleration unit comprises a reading subunit and a sending subunit. The reading subunit can read a second instruction from a sending queue connected to a second sending selector when none of the first instructions in the sending queue connected to a first sending selector meets an instruction sending condition, wherein the first sending selector is electrically connected to a first instruction execution unit, the second sending selector is electrically connected to a second instruction execution unit, and the first instruction execution unit and the second instruction execution unit are different instruction execution units in a plurality of instruction execution units. The sending subunit can send the second instruction to the first sending selector, so that the second instruction read by the reading subunit is sent to the first instruction execution unit by the first sending selector, so that the first instruction execution unit executes the second instruction. The acceleration unit can improve the efficiency of the processor in executing instructions.

Description

Technical Field

[0001] This application relates to the field of processor technology, and in particular to an acceleration unit, processor, electronic device, and instruction execution method. Background Technology

[0002] Driven by the demands of modern high-performance computing, processors supporting out-of-order execution have become the mainstream design. In such processors, the instruction issue queue (ICO) is a crucial module for transitioning instructions from sequential to out-of-order execution. The ICO allows instructions created sequentially and placed in the queue to be issued out of order to the execution units for execution.

[0003] Currently, one instruction execution unit corresponds to one issue selector. The issue selector is electrically connected to the issue queue. The issue selector can send the instructions in the connected issue queue that meet the issue conditions to the corresponding instruction execution unit for execution.

[0004] However, if no instructions are assigned in the issue queue connected to the issue selector, or if none of the instructions stored in the issue queue connected to the issue selector meet the issue conditions, the instruction execution unit corresponding to the issue selector is idle, resulting in low efficiency of the processor in processing instructions. Summary of the Invention

[0005] In view of this, embodiments of this application provide an acceleration unit, processor, electronic device, and instruction execution method to at least solve or alleviate the above-mentioned problems.

[0006] According to a first aspect of the embodiments of this application, an acceleration unit is provided, disposed in a processor. The processor includes a plurality of instruction execution units, each instruction execution unit being electrically connected to a send selector, and each send selector being electrically connected to a send queue. Each send selector is configured to send instructions stored in the connected send queue to the connected instruction execution unit, causing the instruction execution unit to execute the instructions. The acceleration unit includes a read subunit and a send subunit. The read subunit is configured to read a second instruction from a send queue connected to a second send selector when none of the first instructions in the send queue connected to the first send selector meet the instruction send conditions. The second instruction is an instruction in the transmission queue connected to the second transmit selector that meets the instruction transmission conditions. The first transmit selector is electrically connected to the first instruction execution unit, and the second transmit selector is electrically connected to the second instruction execution unit. The first instruction execution unit and the second instruction execution unit are different instruction execution units among the plurality of instruction execution units. The transmitting subunit is used to send the second instruction read by the reading subunit to the first transmit selector, so that the second instruction read by the reading subunit is sent by the first transmit selector to the first instruction execution unit, so that the first instruction execution unit executes the second instruction read by the reading subunit.

[0007] In one possible implementation, the transmit queue connected to the second transmit selector includes multiple instruction storage entries, which are used to store instructions. The second transmit selector reads the second instruction from the transmit queue connected to the second transmit selector in descending order of storage time. The read subunit is used to read the second instruction from the transmit queue connected to the second transmit selector in ascending order of storage time.

[0008] In one possible implementation, if the reading subunit and the second transmit selector simultaneously read the second instruction stored in the same instruction storage table entry, the reading subunit stops reading the second instruction, and the second instruction is read by the second transmit selector and sent to the second instruction execution unit.

[0009] In one possible implementation, the reading subunit is configured to read the second instruction from the plurality of instruction storage entries according to a set reading range, wherein the reading range is used to indicate the instruction storage entries of the plurality of instruction storage entries that can be read by the reading subunit.

[0010] In one possible implementation, the acceleration unit further includes a writing subunit; the writing subunit is configured to write a transmitted flag corresponding to the first transmit selector into the identifier bit of the instruction storage table entry storing the second instruction after the sending subunit sends the second instruction to the first transmit selector.

[0011] In one possible implementation, the writing subunit is configured to clear the instruction storage table entry storing the second instruction after the first instruction execution unit successfully executes the second instruction; or, when the first instruction execution unit fails to execute the second instruction, write the identifier bit of the instruction storage table entry storing the second instruction to a transmit flag, so that the reading subunit or the second transmit selector rereads the second instruction.

[0012] In one possible implementation, the instruction issuance conditions include at least that all operands required to execute the instruction are ready.

[0013] According to a second aspect of the present application, a processor is provided, comprising: a plurality of instruction execution units and an acceleration unit as described in the first aspect, each instruction execution unit being electrically connected to a send selector, each send selector being electrically connected to a send queue, the send selector being configured to send instructions stored in the connected send queue to the connected instruction execution units, causing the instruction execution units to execute the instructions.

[0014] According to a third aspect of the embodiments of this application, an electronic device is provided, including: a processor as described in the second aspect above.

[0015] According to a fourth aspect of the embodiments of this application, an instruction execution method is provided, applied to an acceleration unit, the acceleration unit being disposed in a processor, the processor including a plurality of instruction execution units, each instruction execution unit being electrically connected to a send selector, each send selector being electrically connected to a send queue, the send selector being configured to send instructions stored in the connected send queue to the connected instruction execution unit, causing the instruction execution unit to execute the instructions, the method comprising: when none of the first instructions in the send queue connected to the first send selector satisfy the instruction sending condition, reading a second instruction from the send queue connected to a second send selector, wherein the second instruction is an instruction in the send queue connected to the second send selector that satisfies the instruction sending condition, the first send selector being electrically connected to a first instruction execution unit, the second send selector being electrically connected to a second instruction execution unit, the first instruction execution unit and the second instruction execution unit being different instruction execution units among the plurality of instruction execution units; sending the read second instruction to the first send selector, causing the second instruction to be sent by the first send selector to the first instruction execution unit, so that the first instruction execution unit executes the second instruction.

[0016] According to the solution provided in the embodiments of this application, the acceleration unit includes a reading subunit and a sending subunit. When none of the first instructions stored in the sending queue corresponding to the first sending selector connected to the first instruction execution unit meet the instruction sending conditions, the reading subunit can read the second instruction from the sending queue corresponding to the second sending selector connected to the second instruction execution unit. The sending subunit can send the second instruction read by the reading subunit to the first sending selector. The first sending selector can send the second instruction to the first instruction execution unit for execution. This realizes that when the first instruction execution unit is idle, it can help other instruction execution units execute the instructions in the sending queue. Compared with the instruction execution scheme in the prior art, the acceleration unit can enable the instruction execution unit to execute the instructions of other instruction execution units when it is idle, which can improve the efficiency of the processor in executing instructions. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0018] Figure 1 This is a schematic diagram of an acceleration unit provided in an embodiment of this application;

[0019] Figure 2This is a schematic diagram of a launch queue provided in an embodiment of this application;

[0020] Figure 3 This is a schematic diagram of another acceleration unit provided in an embodiment of this application;

[0021] Figure 4 This is a flowchart of an instruction execution method provided in an embodiment of this application. Detailed Implementation

[0022] The present application is described below based on embodiments, but it is not limited to these embodiments. In the detailed description of the present application below, certain specific details are described in detail. Those skilled in the art can fully understand the present application without these details. To avoid obscuring the essence of the present application, well-known methods, processes, and flows are not described in detail. Furthermore, the accompanying drawings are not necessarily drawn to scale.

[0023] First, some nouns or terms that appear in the description of the embodiments of this application shall be interpreted as follows.

[0024] A processor may include multiple instruction execution units. Taking a CPU as an example, an instruction execution unit can be a computational unit within the CPU. Each instruction execution unit is electrically connected to an issue selector, which is electrically connected to an issue queue (IQ). Different issue selectors are electrically connected to different issue queues. An issue selector can issue instructions stored in its connected issue queue to the connected instruction execution unit, enabling the instruction execution unit to execute the instructions. Specifically, after steps such as instruction fetching, decoding, and register renaming, instructions are distributed sequentially by the instruction dispatch module to the issue queues connected to each issue selector. An issue selector can also issue instructions that meet the instruction issuance conditions to the connected instruction execution unit out of order, allowing the instruction execution unit to execute the instructions and perform computational operations. The processor also includes an out-of-order execution unit, which can record the order of instructions to achieve order-preserving operations during out-of-order execution.

[0025] Based on the processor mentioned above Figure 1 This is a schematic diagram of an acceleration unit provided in an embodiment of this application. Figure 1 As shown, the acceleration unit 100 includes a reading subunit 101 and a sending subunit 102.

[0026] The reading subunit 101 is electrically connected to multiple transmit selectors, and the transmitting subunit 102 is electrically connected to the reading subunit 101. When none of the first instructions in the transmit queue connected to the first transmit selector 2011 meet the instruction transmission conditions, the reading subunit 101 can read a second instruction from the transmit queue connected to the second transmit selector 2012. The first instruction is the instruction stored in the transmit queue connected to the first transmit selector 2011, and the second instruction is the instruction stored in the transmit queue connected to the second transmit selector 2012 that meets the instruction transmission conditions. The first transmit selector 2011 is electrically connected to the first instruction execution unit 2021, and the second transmit selector 2012 is electrically connected to the second instruction execution unit 2022. The first instruction execution unit 2021 and the second instruction execution unit 2022 are different instruction execution units among multiple instruction execution units.

[0027] After the reading subunit 101 reads the second instruction, the sending subunit 102 can send the second instruction to the first transmit selector 2011. The first transmit selector 2011 can send the second instruction sent by the sending subunit 102 to the first instruction execution unit 2021. The first instruction execution unit 2021 can execute the second instruction sent by the first transmit selector 2011.

[0028] It should be understood that since none of the first instructions in the transmission queue corresponding to the first transmit selector 2011 connected to the first instruction execution unit 2021 meet the instruction transmission conditions, if the acceleration unit 100 in this embodiment is not set, the first transmit selector 2011 will not transmit instructions to the first instruction execution unit 2021, resulting in the first instruction execution unit 2021 being in an idle state. However, after setting the acceleration unit 100 in this embodiment, it can help other instruction execution units execute instructions when the first instruction execution unit 2021 is in an idle state, thereby improving the efficiency of instruction execution.

[0029] Optionally, the instruction issuance conditions include at least that all operands required to execute the instruction are ready. That is, the instruction issuance conditions include at least that the instruction can be executed and that all data conditions required for the instruction are met.

[0030] In this embodiment, the acceleration unit 100 includes a reading subunit 101 and a sending subunit 102. When none of the first instructions stored in the sending queue corresponding to the first send selector 2011 connected to the first instruction execution unit 2021 meet the instruction sending conditions, the reading subunit 101 can read a second instruction from the sending queue corresponding to the second send selector 2012 connected to the second instruction execution unit 2022. The sending subunit 102 can send the second instruction read by the reading subunit 101 to the first send selector 2011. The first send selector 2011 can send the second instruction to the first instruction execution unit 2021 for execution. This enables other instruction execution units to execute instructions in the sending queue when the first instruction execution unit 2021 is idle. Compared with the instruction execution scheme in the prior art, the acceleration unit 100 can enable the instruction execution unit to execute instructions of other instruction execution units when it is idle, thereby improving the efficiency of the processor in executing instructions.

[0031] Figure 2 This is a schematic diagram of a launch queue provided in an embodiment of this application. For example... Figure 2 As shown, taking the transmit queue of the second transmit selector 2012 as an example, the transmit queue of the second transmit selector 2012 includes multiple instruction storage table entries, such as: Figure 2 The instruction storage table contains entries 1 to N. Each instruction storage table entry can store one instruction. When the instruction dispatch module writes an instruction to the issue queue, it can write the instruction to an empty entry in the instruction storage table.

[0032] Since some operands of subsequent instructions may be the execution results of preceding instructions during instruction execution, the second issue selector 2012, when issuing second instructions from the connected issue queue to the second instruction execution unit 2022, prioritizes sending instructions that meet the instruction issuance conditions and have longer storage times. That is, it prioritizes issuing the second instruction that was written first, so that the second instruction execution unit 2022 can execute the second instruction. Optionally, the second issue selector 2012 can, among the instructions that already meet the instruction issuance conditions, prioritize sending the second instruction with the longest storage time to the second instruction execution unit 2022 according to the instruction storage time indicated by the age matrix.

[0033] To ensure that the second transmit selector 2012 and the acceleration unit 100 do not conflict in reading instructions, the reading subunit 101 of the acceleration unit 100 reads the second instruction from the transmit queue connected to the second transmit selector 2012 in order of shortest to longest storage time, giving priority to the second instruction with shorter storage time and meeting the instruction transmission conditions. That is, the second transmit selector 2012 reads the second instruction in the connected transmit queue in order of longest to shortest storage time, and the reading subunit 101 reads the second instruction in the transmit queue connected to the second transmit selector 2012 in order of shortest to longest storage time.

[0034] It should be understood that since the second instruction is an instruction that satisfies the instruction issuance conditions, the second instruction read by the reading subunit 101 is not related to the preceding instruction, or the execution result of the preceding instruction associated with the second instruction has been determined.

[0035] In this embodiment, the second launch selector 2012 is connected to a launch queue that includes multiple instruction storage entries. The second launch selector 2012 reads the second instruction in the connected launch queue in descending order of storage time, and the reading subunit 101 reads the second instruction in the launch queue connected to the second launch selector 2012 in ascending order of storage time. This reduces the probability that the second launch selector 2012 and the reading subunit 101 will simultaneously read the second instruction stored in the same instruction storage entry, thereby preventing conflicts when the second launch selector 2012 and the reading subunit 101 read instructions and preventing the first instruction execution unit 2021 and the second instruction execution unit 2022 from simultaneously executing the same second instruction, which would otherwise waste the computing power of the instruction execution unit.

[0036] In one possible implementation, although the second transmit selector 2012 reads the second instruction in the connected transmit queue in descending order of storage time, and the reading subunit 101 reads the second instruction in the transmit queue connected to the second transmit selector 2012 in ascending order of storage time, there is still a possibility that the reading subunit 101 and the second transmit selector 2012 may simultaneously read the second instruction stored in the same instruction storage table entry.

[0037] Based on the above, if the reading subunit 101 and the second transmit selector 2012 simultaneously read the second instruction stored in the same instruction storage table entry, then the reading subunit 101 stops reading the second instruction, so that the second instruction is read by the second transmit selector 2012 and sent to the second instruction execution unit 2022, that is, the second instruction in the transmit queue connected to the second transmit selector 2012 is executed preferentially by the second instruction execution unit 2022.

[0038] In one specific implementation, the aforementioned process can be achieved by setting enable conditions. Specifically, when the same instruction storage table entry is simultaneously read by the second transmit selector 2012 and the read subunit 101, the transmit enable condition of the second transmit selector 2012 is enabled, while the transmit enable conditions of the first transmit selector 2011 and the acceleration unit 100 are deactivated. This causes the read subunit 101 to stop reading the second instruction, allowing the second instruction to be read by the second transmit selector 2012 and sent to the second instruction execution unit 2022 for execution.

[0039] In this embodiment, if the reading subunit 101 and the second transmit selector 2012 simultaneously read the second instruction stored in the same instruction storage table entry, the reading subunit 101 stops reading the second instruction, and the second instruction is read by the second transmit selector 2012 and sent to the second instruction execution unit 2022. That is, the same second instruction is preferentially sent to the connected instruction execution unit by the transmit selector connected to the same transmit queue for execution. This can prevent conflicts when the second transmit selector 2012 and the reading subunit 101 read instructions, and prevent the first instruction execution unit 2021 and the second instruction execution unit 2022 from executing the same second instruction at the same time, which would lead to a waste of computing power of the instruction execution unit.

[0040] In one possible implementation, the read subunit 101 can read a second instruction from multiple instruction storage table entries according to a set read range. The read range is used to indicate the instruction storage table entries that can be read by the read subunit 101.

[0041] The readable range of the read subunit 101 in multiple instruction memory entries can be manually configured. For example, it can be configured to read only the first m instruction memory entries, or only the last m instruction memory entries, or only non-contiguous instruction memory entries, etc. When reading the second instruction, the read subunit 101 reads the second instruction in the transmit queue connected to the second transmit selector 2012 in ascending order of storage time within the set read range.

[0042] In this embodiment of the application, the reading subunit 101 can read the second instruction from multiple instruction storage entries according to the set reading range. The readable range of the reading subunit 101 can be manually configured, and instructions that can be executed by other instruction execution units can be set as needed, giving the user a high degree of freedom.

[0043] Figure 3 This is a schematic diagram of another acceleration unit provided in an embodiment of this application, as shown below. Figure 3 As shown, the acceleration unit 100 also includes a writing subunit 103.

[0044] In addition to storing instructions, instruction store entries also use flag bits to indicate the status of the instructions. Specifically, each instruction store entry corresponds to a flag bit. By modifying the value of the flag bit, the status of the instruction can be indicated. For example, when an instruction store entry stores an instruction that meets the instruction issue conditions and is ready to be issued, the flag bit of the instruction store entry is marked as the first flag; when the instruction has been issued to the instruction execution unit by the issue selector, the flag bit of the instruction store entry is marked as the second flag; and when the instruction does not meet the instruction issue conditions, the flag bit of the instruction store entry is marked as the third flag.

[0045] Different send selectors have different flags for their corresponding flag bits, meaning that the flags for each state of the instructions in different send queues are different. After the send subunit 102 sends the second instruction to the first send selector 2011, the write subunit 103 can write the sent flag corresponding to the first send selector 2011 into the flag bit of the instruction storage table entry storing the second instruction, so as to identify that the instruction stored in the instruction storage table entry is sent by the first send selector 2011 to the first instruction execution unit 2021 for execution by the sent flag.

[0046] The following example illustrates this in detail. The transmitted flag corresponding to the first transmit selector 2011 is 10, and the transmitted flag corresponding to the second transmit selector 2012 is 11. When the second instruction in the instruction storage table is transmitted to the second instruction execution unit 2022 by the second transmit selector 2012, the second transmit selector 2012 writes 11 to the flag bit corresponding to the instruction storage table entry. When the second instruction in the instruction storage table entry is read by the read subunit 101 and sent to the first transmit selector 2011 by the send subunit 102, the write subunit 103 writes 10 to the flag bit corresponding to the instruction storage table entry to mark that the second instruction is executed by the first instruction execution unit 2021.

[0047] In this embodiment of the application, the acceleration unit 100 further includes a writing subunit 103. After the sending subunit 102 sends the second instruction to the first send selector 2011, the writing subunit 103 can write the corresponding sent flag of the first send selector 2011 into the flag bit of the instruction storage table entry storing the second instruction. By writing the subunit 103, the instruction stored in the instruction storage table entry can be identified in which instruction execution unit the instruction is sent to for execution. Thus, the execution result can be read from the corresponding instruction execution unit according to the flag bit of the instruction storage table entry, preventing subsequent instructions from failing to execute.

[0048] In one possible implementation, the write subunit 103 may clear the instruction storage table entry storing the second instruction after the first instruction execution unit 2021 successfully executes the second instruction; or, when the first instruction execution unit 2021 fails to execute the second instruction, write the flag bit of the instruction storage table entry storing the second instruction to the transmit flag, so that the read subunit 101 or the second transmit selector 2012 can reread the second instruction.

[0049] Correspondingly, when the execution result of the second instruction is needed, the execution result can be read from the instruction execution unit connected to the issue selector corresponding to the flag bit according to the flag bit of the instruction storage table entry.

[0050] It should be understood that since the second instruction is issued to the first instruction execution unit 2021 but is not executed by the first instruction execution unit 2021, the second instruction is an instruction that meets the instruction issuance conditions. The flag bit of the instruction storage table entry storing the second instruction is written to the pending issuance flag so that the second instruction can be reissued.

[0051] In this embodiment, the write subunit 103 can clear the instruction storage table entry storing the second instruction after the first instruction execution unit 2021 successfully executes the second instruction. Alternatively, when the first instruction execution unit 2021 fails to execute the second instruction, the identifier bit of the instruction storage table entry storing the second instruction is written to a transmit flag, so that the read subunit 101 or the second transmit selector 2012 can reread the second instruction. This achieves clearing the instruction storage table entry after the second instruction is executed, and allowing the second instruction to be re-issued when it fails to execute, preventing subsequent instructions from being unable to be executed due to the first instruction execution unit 2021 failing to execute the second instruction, thus improving the fault tolerance of the instruction execution process.

[0052] This application also provides a processor, which includes a plurality of instruction execution units and the acceleration unit 100 in any of the foregoing embodiments.

[0053] A processor may include multiple instruction execution units. Taking the CPU as an example, each instruction execution unit can be a computational unit within the CPU. Each instruction execution unit is electrically connected to an issue selector, and each issue selector is electrically connected to an issue queue. Different issue selectors are electrically connected to different issue queues. An issue selector can issue instructions stored in its connected issue queue to the connected instruction execution unit, enabling the instruction execution unit to execute the instructions. Specifically, after steps such as instruction fetching, decoding, and register renaming, instructions are distributed sequentially by the instruction dispatch module to the issue queues connected to each issue selector. An issue selector can also issue instructions that meet the instruction issuance conditions to the connected instruction execution unit out of order, allowing the instruction execution unit to execute the instructions and perform computational operations. The processor also includes an out-of-order execution unit, which can record the order of instructions to achieve order-preserving operations during out-of-order execution.

[0054] It should be noted that the application of the acceleration unit 100 in this application embodiment is not limited to the processor, and can also be applied in various other suitable ways. For example, the acceleration unit 100 can also be applied to GPU processors, NPU processors, etc.

[0055] This application also provides an electronic device that includes the processor in the foregoing embodiments, or the acceleration unit 100 in any of the foregoing embodiments.

[0056] In this application embodiment, the processor can be the processor in any of the foregoing embodiments, and the acceleration unit can be the acceleration unit 100 in any of the foregoing embodiments. The specific structure and interaction process can be found in the description of any of the foregoing embodiments, and will not be repeated here.

[0057] The acceleration unit in the foregoing embodiments can be applied to a processor to achieve load balancing among the instruction execution units in the processor. The following description uses an instruction execution method embodiment to illustrate the operation of the acceleration unit in the processor. It should be understood that this instruction execution method embodiment is applied to the acceleration unit located in the processor. The processor can be any of the processors in the foregoing embodiments, and the acceleration unit can be any of the acceleration units 100 in the foregoing embodiments.

[0058] Figure 4 This is a flowchart of an instruction execution method provided in an embodiment of this application. For example... Figure 4 As shown, the instruction execution method includes the following steps:

[0059] Step 401: When none of the first instructions in the transmission queue connected to the first transmission selector meet the instruction transmission conditions, read the second instruction from the transmission queue connected to the second transmission selector.

[0060] The second instruction is an instruction in the transmission queue connected to the second transmission selector that meets the instruction transmission conditions. The first transmission selector is electrically connected to the first instruction execution unit, and the second transmission selector is electrically connected to the second instruction execution unit. The first instruction execution unit and the second instruction execution unit are different instruction execution units among multiple instruction execution units.

[0061] Step 402: Send the read second instruction to the first transmit selector, so that the second instruction is sent by the first transmit selector to the first instruction execution unit, so that the first instruction execution unit executes the second instruction.

[0062] In this embodiment, when none of the first instructions stored in the issue queue corresponding to the first issue selector connected to the first instruction execution unit meet the instruction issue conditions, a second instruction is read from the issue queue corresponding to the second issue selector connected to the second instruction execution unit. The second instruction read by the reading subunit can be sent to the first issue selector, and the first issue selector can issue the second instruction to the first instruction execution unit for execution. This enables other instruction execution units to execute instructions in the issue queue when the first instruction execution unit is idle. Compared with the instruction execution scheme in the prior art, this allows the instruction execution unit to execute instructions of other instruction execution units when it is idle, thereby improving the efficiency of processor instruction execution.

[0063] It should be noted that the instruction execution method in this application embodiment is a specific application of the acceleration unit in the processor in the foregoing embodiments. For the specific instruction execution method, please refer to the description in the foregoing acceleration unit embodiments, which will not be repeated here.

[0064] It should be noted that the user-related information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to sample data used for training the model, data used for analysis, stored data, displayed data, etc.) involved in the embodiments of this application are all information and data authorized by the user or fully authorized by all parties. Furthermore, the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and corresponding operation entry points are provided for users to choose to authorize or refuse.

[0065] It should be understood that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. The focus of each embodiment is to describe the differences from other embodiments. In particular, for the method embodiments, since they are basically similar to the methods described in the apparatus and system embodiments, the description is relatively simple, and the relevant parts can be referred to the descriptions of other embodiments.

[0066] It should be understood that the foregoing describes specific embodiments of this specification. Other embodiments are within the scope of the claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0067] It should be understood that the use of a singular form to describe an element or to show only one element in the accompanying drawings does not imply that the number of such element is limited to one. Furthermore, modules or elements described or shown as separate herein may be combined into a single module or element, and modules or elements described or shown as single herein may be broken down into multiple modules or elements.

[0068] It should also be understood that the terminology and expressions used herein are for descriptive purposes only, and one or more embodiments described herein should not be limited to these terms and expressions. The use of these terms and expressions does not exclude any illustrative and descriptive equivalent features (or parts thereof), and it should be recognized that various modifications that may exist should also be included within the scope of the claims. Other modifications, variations, and substitutions may also exist. Accordingly, the claims should be considered to cover all such equivalents.

Claims

1. An acceleration unit disposed in a processor, the processor comprising a plurality of instruction execution units, each instruction execution unit electrically connected to a send selector, each send selector electrically connected to a send queue, the send selector being configured to send instructions stored in the connected send queue to the connected instruction execution unit, causing the instruction execution unit to execute the instructions, characterized in that, The acceleration unit includes: a reading subunit and a sending subunit; The reading subunit is configured to read a second instruction from the transmission queue connected to the second transmission selector when none of the first instructions in the transmission queue connected to the first transmission selector meet the instruction transmission condition. The second instruction is an instruction that meets the instruction transmission condition in the transmission queue connected to the second transmission selector. The first transmission selector is electrically connected to the first instruction execution unit, and the second transmission selector is electrically connected to the second instruction execution unit. The first instruction execution unit and the second instruction execution unit are different instruction execution units among the multiple instruction execution units; The sending subunit is configured to send the second instruction read by the reading subunit to the first transmission selector, so that the second instruction read by the reading subunit is sent by the first transmission selector to the first instruction execution unit, so that the first instruction execution unit executes the second instruction read by the reading subunit; The transmission queue connected to the second transmission selector includes multiple instruction storage entries, and the instruction storage entries are used to store instructions. The second transmission selector reads the second instruction from the transmission queue connected to the second transmission selector in the order from the longest storage time to the shortest, where; The reading subunit is configured to read the second instruction from the transmission queue connected to the second transmission selector in the order from the shortest storage time to the longest.

2. The acceleration unit according to claim 1, characterized in that, If the reading subunit and the second transmission selector simultaneously read the second instruction stored in the same instruction storage entry, the reading subunit stops reading the second instruction, and the second instruction is read by the second transmission selector and sent to the second instruction execution unit.

3. The acceleration unit according to claim 2, wherein The reading subunit is configured to read the second instruction from the multiple instruction storage entries according to a set reading range, where the reading range is used to indicate the instruction storage entries that can be read by the reading subunit among the multiple instruction storage entries.

4. The acceleration unit according to claim 1, characterized in that, The acceleration unit further includes: a writing subunit; The writing subunit is configured to write the transmitted flag corresponding to the first transmission selector to the identification bit of the instruction storage entry storing the second instruction after the sending subunit sends the second instruction to the first transmission selector.

5. The acceleration unit according to claim 4, wherein The writing subunit is configured to clear the instruction storage entry storing the second instruction after the first instruction execution unit successfully executes the second instruction; Alternatively, when the first instruction execution unit fails to execute the second instruction, write the identification bit of the instruction storage entry storing the second instruction with a pending transmission flag, so that the reading subunit or the second transmission selector reads the second instruction again.

6. The acceleration unit according to any one of claims 1-5, characterized in that, The instruction transmission condition at least includes that all the operands required to execute the instruction are ready.

7. A processor, characterized in that, Includes: The system comprises multiple instruction execution units and an acceleration unit as described in any one of claims 1-6, wherein each instruction execution unit is electrically connected to a transmit selector, and each transmit selector is electrically connected to a transmit queue, wherein the transmit selector is configured to transmit instructions stored in the connected transmit queue to the connected instruction execution unit, thereby causing the instruction execution unit to execute the instructions.

8. An electronic device, characterized in that, include: The processor as described in claim 7.

9. An instruction execution method applied to an acceleration unit, the acceleration unit being disposed in a processor, the processor including a plurality of instruction execution units, each instruction execution unit being electrically connected to a send selector, each send selector being electrically connected to a send queue, the send selector being used to send instructions stored in the connected send queue to the connected instruction execution unit, causing the instruction execution unit to execute the instructions, characterized in that, The method includes: When none of the first instructions in the transmission queue connected to the first transmission selector meet the instruction transmission conditions, a second instruction is read from the transmission queue connected to the second transmission selector. The second instruction is an instruction in the transmission queue connected to the second transmission selector that meets the instruction transmission conditions. The first transmission selector is electrically connected to the first instruction execution unit, and the second transmission selector is electrically connected to the second instruction execution unit. The first instruction execution unit and the second instruction execution unit are different instruction execution units among the plurality of instruction execution units. The read second instruction is sent to the first transmit selector, so that the second instruction is sent by the first transmit selector to the first instruction execution unit, so that the first instruction execution unit executes the second instruction; The second transmit selector is connected to a transmit queue that includes multiple instruction storage entries. These instruction storage entries are used to store instructions. The second transmit selector reads the second instruction from the transmit queue connected to it in descending order of storage time. The step of reading the second instruction from the transmission queue connected to the second transmission selector includes: reading the second instruction from the transmission queue connected to the second transmission selector in ascending order of storage time.

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