Semiconductor structure and method of forming the same

Abstract

This invention relates to the field of semiconductor technology, and particularly to a semiconductor structure and its formation method. The method involves first providing a substrate structure including a substrate layer and an epitaxial layer; etching the epitaxial layer to form a predetermined body region on the surface of the epitaxial layer; depositing a target semiconductor material in the predetermined body region; the target semiconductor material being different from the substrate material; performing ion implantation on the target semiconductor material to form spaced-apart body regions and ion-implanted regions within the body regions; the conductivity type of the body regions being different from that of the substrate structure; forming a first metal layer on the surface of the body regions and a second metal layer on the other side of the substrate layer. This forms a heterojunction body diode between the body region and the epitaxial layer. The heterojunction body diode has advantages such as a low heterojunction electron barrier and a low reverse turn-on voltage, improving reverse recovery characteristics, shortening reverse recovery time, and increasing switching efficiency.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is a widely used semiconductor device in electronic circuits. Due to its high voltage withstand capability, high current handling capability, and excellent switching characteristics, it is widely used in high-efficiency power supply designs. However, the long recovery time of the body diode in the reverse recovery process of a MOSFET leads to significant switching losses and current spikes, increasing electromagnetic interference (EMI), especially in silicon carbide and silicon-based VDMOS (Vertical Double-Diffused Metal-Oxide-Semiconductor Field-Effect Transistor) devices. While the wide bandgap material imparts excellent high-voltage and high-temperature performance, the relatively wide bandgap makes it difficult for the body diode to conduct during reverse recovery.

[0003] Common solutions for optimizing reverse recovery performance include: externally connected fast recovery diodes, integrated heterojunction diodes (HJDs), and integrated Schottky diodes (SBDs). However, external parallel connection increases chip size and introduces complex parasitic parameters; integrated SBDs face the risk of performance degradation at high temperatures; integrated MCDs require complex well region design; and integrated HJDs face the challenge of overcoming inherent material interface defects in heterojunction materials.

[0004] Therefore, there is an urgent need for a semiconductor structure and its formation method that is simple in structure, has good reverse recovery performance optimization, and does not affect the performance of other devices to solve the above technical problems. Summary of the Invention

[0005] To address the problems of the prior art, this application provides a semiconductor structure and a method for forming the same. The technical solution is as follows:

[0006] On one hand, embodiments of this application provide a method for forming a semiconductor structure, the method comprising:

[0007] A substrate structure is provided; the substrate structure includes a substrate layer and an epitaxial layer located on one side surface of the substrate layer;

[0008] The epitaxial layer is etched to form a predetermined body region located on the surface of the epitaxial layer;

[0009] A target semiconductor material is deposited in the predetermined body region; the target semiconductor material is different from the material of the substrate structure.

[0010] The target semiconductor material is subjected to ion implantation to form spaced-apart bulk regions and ion-implanted regions located within the bulk regions; the conductivity type of the bulk regions is different from that of the substrate structure.

[0011] A first metal layer is formed on the surface of the body region and a second metal layer is formed on the other side surface of the substrate layer.

[0012] In one exemplary embodiment, the dielectric constant of the target semiconductor material is less than the dielectric constant of the substrate structure, and / or the carrier mobility of the target semiconductor material is greater than the carrier mobility of the substrate structure.

[0013] In one exemplary embodiment, the semiconductor structure further includes a gate, and when the semiconductor structure is a trench-type VDMOS device, the method for forming the gate includes:

[0014] Trenches are formed in the epitaxial layer;

[0015] A gate oxide layer is formed on the surface of the trench structure to obtain the trench structure;

[0016] The trench structure is filled with polysilicon to form the gate.

[0017] In an exemplary embodiment, when the semiconductor structure is a trench-type VDMOS device, the etching process of the epitaxial layer to form a predetermined body region located on the surface of the epitaxial layer includes:

[0018] The epitaxial layer is etched on both sides of the trench structure to form the preset body region on both sides of the trench structure; the preset body region is equal to the designed thickness of the body region.

[0019] In one exemplary embodiment, the semiconductor structure further includes a gate, and when the semiconductor structure is a planar gate device, the method for forming the gate includes:

[0020] After the body regions are formed, a gate oxide layer is formed on one side surface of the epitaxial layer; the gate oxide layer at least covers the region between the body regions and a portion of the body regions;

[0021] Polysilicon is deposited on the surface of the gate oxide layer to form the gate.

[0022] In one exemplary embodiment, the first metal layer and the gate do not overlap.

[0023] In one exemplary embodiment, when the materials of the substrate layer and the epitaxial layer are silicon, the target semiconductor material includes any one of germanium, silicon germanium, and gallium arsenide; when the materials of the substrate layer and the epitaxial layer are aluminum nitride, the target semiconductor material includes diamond; when the materials of the substrate layer and the epitaxial layer are silicon carbide, the target semiconductor material includes gallium nitride.

[0024] In one exemplary embodiment, depositing the target semiconductor material in the preset body region includes:

[0025] The target semiconductor material is deposited in the preset body region by chemical vapor deposition.

[0026] In one exemplary embodiment, the ion implantation region includes an N+ region and a P+ region; the ion implantation of the target semiconductor material to form a spaced-apart body region and an ion implantation region located within the body region includes:

[0027] The target semiconductor material is subjected to target type ion implantation to form spaced-apart body regions; the conductivity type of the body regions is different from that of the substrate structure.

[0028] P-type ion implantation is performed on the body region to form the P+ region located in the body region; and N-type ion implantation is performed on the body region to form the N+ region located in the body region.

[0029] In another aspect, this application also discloses a semiconductor structure, said semiconductor structure comprising:

[0030] Second metal layer;

[0031] A substrate structure located on the surface of the second metal layer; the substrate structure includes a substrate layer and an epitaxial layer located on one side surface of the substrate layer;

[0032] A spaced-out body region is located in the epitaxial layer; the body region is prepared by etching the epitaxial layer, filling the body region with a target semiconductor material, and then performing ion implantation on the target semiconductor material; the target semiconductor material is different from the material of the substrate structure; the conductivity type of the body region is different from the conductivity type of the substrate structure.

[0033] The ion implantation region is located within the body region;

[0034] The first metal layer located on the surface of the body region.

[0035] In one exemplary embodiment, the dielectric constant of the target semiconductor material is less than the dielectric constant of the substrate structure, and / or the carrier mobility of the target semiconductor material is greater than the carrier mobility of the substrate structure.

[0036] In one exemplary embodiment, the semiconductor structure further includes a gate and a gate oxide layer, the gate being disposed on the surface of the epitaxial layer or in the epitaxial layer, and the body region being disposed on both sides of the gate, wherein the first metal layer and the gate do not overlap; the gate oxide layer is disposed between the epitaxial layer and the gate.

[0037] In an exemplary embodiment, when the semiconductor structure is a trench-type VDMOS device, the semiconductor structure further includes a trench located in the epitaxial layer, the gate is located in the trench, the gate oxide layer is disposed between the trench and the gate, and the body region is disposed on both sides of the trench structure.

[0038] In an exemplary embodiment, when the semiconductor structure is a planar gate device, the gate is located on the surface of the body region, the gate oxide layer is disposed between the gate and the epitaxial layer, and the gate oxide layer and the gate at least cover the region between the body regions and a portion of the body region.

[0039] In one exemplary embodiment, the ion implantation region includes an N+ region and a P+ region, and the N+ region and the P+ region are arranged adjacent to each other.

[0040] In another aspect, this application also discloses an electronic device comprising the aforementioned semiconductor structure.

[0041] The semiconductor structure formation method provided in this application involves first providing a substrate structure including a substrate layer and an epitaxial layer; etching the epitaxial layer to form a predetermined body region on the surface of the epitaxial layer; depositing a target semiconductor material in the predetermined body region; the target semiconductor material being different from the substrate material; performing ion implantation on the target semiconductor material to form spaced-apart body regions and ion implantation regions within the body regions; the conductivity type of the body regions being different from the conductivity type of the substrate structure; forming a first metal layer on the surface of the body regions and a second metal layer on the other side of the substrate layer. Thus, by etching and filling the epitaxial layer with a target semiconductor material different from the substrate material, a heterojunction body diode is formed between the body region and the epitaxial layer. The heterojunction body diode can utilize the low heterojunction electron barrier of the material to obtain a lower reverse turn-on voltage, improving reverse recovery characteristics, shortening reverse recovery time, and increasing switching efficiency. Furthermore, the above semiconductor structure eliminates the need for external parallel diodes or additional integrated diodes, simplifying the process flow and achieving optimized reverse recovery performance while reducing device size. Furthermore, this optimization not only reduces energy loss but also helps meet the stringent performance requirements of modern electric vehicles, renewable energy, and high-frequency switching power supplies, thereby improving the overall reliability and competitiveness of the system. Attached Figure Description

[0042] To more clearly illustrate the technical solutions and advantages in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0043] Figure 1 This is a schematic flowchart of a method for forming a semiconductor structure provided in this application.

[0044] Figures 2-13 This is a schematic cross-sectional view of a semiconductor structure during the formation process of a semiconductor structure provided in an embodiment of this application.

[0045] Figure 14 This is a cross-sectional schematic diagram of a semiconductor structure provided in an embodiment of this application.

[0046] Figure 15 This is a cross-sectional schematic diagram of a gate fabrication process provided in an embodiment of this application.

[0047] Figure 16 This is a cross-sectional schematic diagram of another semiconductor structure provided in an embodiment of this application.

[0048] The following is an explanation of the reference numerals in the accompanying drawings:

[0049] 100 - Substrate structure; 110 - Substrate layer; 120 - Epitaxial layer; 121 - Preset body region; 122 - Target semiconductor material; 123 - Body region; 124 - Ion implantation region; 124a - N+ region; 124b - P+ region;

[0050] 200 - First metal layer;

[0051] 300 - Second metal layer;

[0052] 400 - Trench; 401 - Photoresist layer; 401a - Patterned photoresist; 410 - Gate oxide layer; 420 - Gate. Detailed Implementation

[0053] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0054] The term "an embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of this application. In the description of this application, it should be understood that the terms "upper," "lower," "top," "bottom," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. Moreover, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein.

[0055] When a numerical range is disclosed herein, the range is considered continuous and includes the minimum and maximum values ​​of the range, as well as every value between the minimum and maximum values. Furthermore, when the range refers to an integer, it includes every integer between the minimum and maximum values ​​of the range. Additionally, when multiple ranges are provided to describe a feature or characteristic, the ranges may be combined. In other words, unless otherwise specified, all ranges disclosed herein should be understood to include any and all subranges to which they are included. For example, a specified range from “1 to 10” should be considered to include any and all subranges between the minimum value 1 and the maximum value 10. Exemplary subranges of the range 1 to 10 include, but are not limited to, 1 to 6.1, 3.5 to 7.8, 5.5 to 10, etc.

[0056] As used in this application, the term "layer" refers to a portion of material comprising a region of a certain thickness. A layer may extend over the entire lower or upper layer structure, or it may extend over a localized area of ​​the lower or upper layer structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or between any pair of horizontal planes therebetween. A layer may extend horizontally, vertically, and / or along an irregularly shaped surface. A single layer may comprise multiple layers. For example, a substrate may comprise multiple sublayers, etc., and may have the same or different materials.

[0057] In MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), the body diode is inherently present due to its structural characteristics. Taking a common N-channel MOSFET as an example, the source and drain are isolated by a P-type body region, which is usually shorted to the source. When a PN junction is formed between the source and body region, a parasitic diode, namely the body diode, is naturally constituted. For N-channel MOSFETs, the cathode of the body diode is connected to the drain, and the anode is connected to the source; for P-channel MOSFETs, the direction of the body diode is reversed. When the body diode is reverse biased, its reverse recovery time (trr) and reverse recovery current (Irr) affect efficiency and electromagnetic interference (EMI). Especially in silicon carbide and silicon-based VDMOS devices, the wide bandgap material endows the device with excellent high-voltage and high-temperature performance, but at the same time, the wide bandgap makes it difficult for the body diode to conduct during reverse recovery. Common solutions for optimizing reverse recovery performance include: externally connected fast recovery diodes, integrated heterojunction diodes (HJDs), integrated Schottky diodes (SBDs), and integrated channel diodes (MCDs). However, external parallel connection increases chip size and introduces complex parasitic parameters; integrated SBDs face the risk of performance degradation at high temperatures; integrated MCDs require complex well region designs; and integrated HJDs face the challenge of overcoming inherent material interface defects in heterojunction materials.

[0058] Based on this, embodiments of this application provide a semiconductor structure including a heterojunction body diode integrated from two semiconductor materials. This structure utilizes a low heterojunction electron barrier to achieve a lower reverse turn-on voltage, improves reverse recovery characteristics, shortens reverse recovery time, and increases switching efficiency. This optimization not only reduces energy loss but also helps meet the stringent performance requirements of modern electric vehicles, renewable energy, and high-frequency switching power supplies, thereby enhancing the overall reliability and competitiveness of the system.

[0059] Please see Figure 1 , Figure 1 The diagram shown is a schematic flowchart of a method for forming a semiconductor structure according to an embodiment of this application. Figures 2 to 16 This is a schematic diagram of the semiconductor structure formation process provided in the embodiments of this application.

[0060] Please see Figure 1 In step S101: a substrate structure 100 is provided; the substrate structure 100 includes a substrate layer 110 and an epitaxial layer 120 located on one side surface of the substrate layer 110.

[0061] like Figure 2As shown, the substrate structure 100 includes a substrate layer 110 and an epitaxial layer 120 located on one side surface of the substrate layer 110. The epitaxial layer 120 is epitaxially grown on the surface of the substrate layer 110, and the material of the epitaxial layer 120 is the same as that of the substrate layer 110.

[0062] Here, the epitaxial growth method can be any one of vapor phase epitaxy, chemical vapor deposition (CVD), molecular beam epitaxy (MBE), or ultra-high vacuum chemical vapor deposition (UHV / CVD). To improve interface quality, epitaxial growth is preferably performed in a low-temperature, high-vacuum environment to avoid high-temperature-induced defects. Therefore, molecular beam epitaxy (MBE) and ultra-high vacuum chemical vapor deposition (UHV / CVD) are preferred for epitaxial growth to improve interface quality.

[0063] In specific implementations, the semiconductor material of the semiconductor substrate may include one or more of silicon, germanium, compound semiconductors, and alloy semiconductors. The compound semiconductor may be one or more of silicon carbide, silicon germanium, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide. The alloy semiconductor may be one or more of silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and gallium indium arsenide phosphide.

[0064] It is rhomboid in shape, and the aforementioned substrate layer 110 can be an N-type substrate or a P-type substrate.

[0065] Optionally, embodiments of this application also provide a method for fabricating the substrate structure 100, such as... Figure 3 As shown, the method for fabricating the substrate structure 100 may include the following steps:

[0066] S1011: A substrate is provided, and the substrate is pretreated to obtain the substrate layer 110. Here, the pretreatment includes polishing and cleaning to make the roughness of the substrate layer 110 meet the preset requirements. Polishing and cleaning can be performed using methods in the prior art.

[0067] S1013: Epitaxial growth is performed on the surface of the substrate layer 110 to obtain an epitaxial layer 120 located on the surface of the substrate layer 110. Optionally, after obtaining the epitaxial layer 120, the substrate structure 100 may be annealed to relieve stress.

[0068] In step S103: the epitaxial layer 120 is etched to form a preset body region 121 located on the surface of the epitaxial layer 120.

[0069] Please see Figure 4The pre-defined body region 121 refers to the region formed by etching the epitaxial layer 120. The pre-defined body region 121 can also be called the body region preparation region, used to accommodate the body region 123 prepared in subsequent steps. In a specific embodiment, the etching process can employ either dry etching or wet etching. It should be noted that... Figure 4 The dotted line representing the preset body area 121 means that the current state of this area is that there is no structure.

[0070] Optionally, the preset body region 121 can be the region after a certain thickness of the epitaxial layer 120 has been etched away, or it can be the region obtained by etching a portion of the epitaxial layer 120, depending on the device type at the time.

[0071] In step S105: a target semiconductor material 122 is deposited in the preset body region 121; the target semiconductor material 122 is different from the material of the substrate structure 100.

[0072] Please see Figure 5 The target semiconductor material 122 refers to a semiconductor material different from the substrate structure 100. By depositing the target semiconductor material 122 in the preset body region 121, a heterostructure can be formed between the target semiconductor material 122 and the epitaxial layer 120. Specifically, the thickness of the deposited target semiconductor material 122 is consistent with the depth of the preset body region 121.

[0073] In an exemplary embodiment, step S105 above, depositing the target semiconductor material 122 in the preset body region 121, includes: depositing the target semiconductor material 122 in the preset body region 121 by chemical vapor deposition.

[0074] Specifically, chemical vapor deposition can be used to deposit the target semiconductor material 122 through methods such as atomic layer deposition (ALD), low-temperature vapor deposition (LPCVD), and ultra-high vacuum chemical vapor deposition (UHV / CVD). Among these, ultra-high vacuum chemical vapor deposition is preferred. Using UHV / CVD avoids the introduction of impurities and defects from the high-temperature environment, improving the heterojunction interface quality. This reduces stress and interface defects at the heterojunction interface due to lattice differences, enabling low-temperature epitaxial growth. Therefore, it can improve the stress and interface defects at the heterojunction cross-section between the bulk region 123 and the epitaxial layer 120. The specific process conditions are determined based on the deposition thickness and the deposition material.

[0075] In an exemplary embodiment, in step S105 above, the depth of the preset body region 121 is equal to the designed thickness of the body region 123. The designed thickness of the body region is a key parameter in semiconductor device manufacturing, and device performance, operating conditions, and process limitations must be comprehensively considered. Thus, the traditional process of ion implanting the epitaxial layer 120 to form a single-material body diode can be replaced by depositing a target semiconductor material 122 with a thickness equal to that of the body region 123, and then ion implanting the target semiconductor material 122 to form a heterojunction body diode. This utilizes the potential barrier formed at the heterojunction interface to obtain a lower reverse turn-on voltage, improves reverse recovery characteristics, shortens reverse recovery time, and increases switching efficiency.

[0076] In step S107: Ion implantation is performed on the target semiconductor material 122 to form spaced-apart body regions 123 and ion implantation regions 124 located in the body regions 123; the conductivity type of the body regions 123 is different from the conductivity type of the substrate structure 100.

[0077] Please see Figure 6 Ion implantation is performed on multiple regions of the target semiconductor material 122 deposited in the preset body region 121 to form spaced-apart body regions 123. Here, the conductivity type of the formed body regions 123 differs from that of the substrate structure 100. There are two conductivity types: P-type and N-type. Specifically, when the substrate structure 100 has an N-type conductivity, the body region 123 has a P-type conductivity, and vice versa. The body region 123 can also be called a well region, used to isolate the source and drain, and forms a PN junction with the epitaxial layer 120.

[0078] Please continue reading. Figure 6 After forming the body region 123, ion implantation is performed on the surface of the body region 123 away from the substrate structure 100 as the ion implantation surface to form an ion implantation region 124 located in the body region 123. It should be noted that the type and number of ion implantation regions 124 are not specifically limited here.

[0079] In a specific embodiment, N-type elements are generally pentavalent elements, such as phosphorus (P), arsenic (As), and antimony (Sb); P-type elements are generally trivalent elements, such as boron (B), aluminum (Al), gallium (Ga), and indium (In).

[0080] In one exemplary embodiment, the ion implantation region 124 includes an N+ region 124a and a P+ region 124b, such as Figure 7As shown, the step of ion implantation into the target semiconductor material 122 to form spaced-apart body regions 123 and ion implantation regions 124 located within the body regions 123 includes:

[0081] S1071: Target type ion implantation is performed on the target semiconductor material 122 to form spaced-apart body regions 123; the conductivity type of the body regions 123 is different from the conductivity type of the substrate structure 100.

[0082] Please see Figure 7 The target type ion is determined based on the conductivity type of the body region 123, as long as the conductivity type of the body region 123 is opposite to that of the substrate structure 100.

[0083] In an optional embodiment, prior to step S1071, the formation method further includes: forming a sacrificial layer on the surface of the target semiconductor material 122. Specifically, the sacrificial layer is a silicon oxide layer, which can subsequently serve as a mask for ion implantation, blocking areas that do not require ion implantation. Therefore, before ion implantation, the formation method further includes: forming a sacrificial layer on the surface of the target semiconductor material 122; and performing patterning processing on the sacrificial layer based on photolithography and etching processes to form a patterned sacrificial layer, wherein the etched portion of the patterned sacrificial layer corresponds to the area of ​​the target semiconductor material 122.

[0084] Further, step S1071 includes performing target-type ion implantation on the target semiconductor material 122 using a patterned sacrificial layer as a mask to form the bulk region 123. After ion implantation, the patterned sacrificial layer is removed. Optionally, the thickness of the sacrificial layer is 100 angstroms to 300 angstroms.

[0085] S1073: Perform P-type ion implantation on the body region 123 to form the P+ region 124b located in the body region 123; and perform N-type ion implantation on the body region 123 to form the N+ region 124a located in the body region 123.

[0086] Please continue reading. Figure 7 N-type ions and P-type ions are implanted into the body region 123 to form N+ region 124a and P+ region 124b located in the body region 123. Each body region 123 has an N+ region 124a and a P+ region 124b, and the N+ region 124a and P+ region 124b in each body region 123 are arranged adjacent to each other and located on the side of the body region 123 away from the substrate structure 100.

[0087] Optionally, the ion implantation process can also prepare a sacrificial layer as a mask. The specific process can be referred to in step S1071 for the preparation and removal of the sacrificial layer.

[0088] It should be noted that the fabrication sequence of N+ region 124a and P+ region 124b needs to be arranged reasonably according to the device type and process design. For example, when the semiconductor structure is a CMOS (Complementary Metal-Oxide-Semiconductor) device, N-type impurities (such as phosphorus or arsenic) are implanted first to form the N+ region 124a of the NMOS, and then P-type impurities (such as boron) are implanted to form the P+ region 124b of the PMOS.

[0089] In step S109: a first metal layer 200 is formed on the surface of the body region 123 and a second metal layer 300 is formed on the other side surface of the substrate layer 110.

[0090] Please participate Figure 8 The first metal layer 200 is deposited on the surface of the body region 123 as a source, and the source forms an ohmic contact with the N+ region 124a and the P+ region 124b; and a second metal layer 300 is formed on the surface of the substrate layer 110 as a drain.

[0091] Optionally, the source can be fabricated using a metallization process, while the drain is located on the back side of the substrate, typically by evaporating metal (such as aluminum) to form a good ohmic contact.

[0092] It should be noted that the semiconductor structure proposed in the embodiments of this application is generally a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). Optionally, the MOSFET device can be a horizontal structure device or a vertical structure device. The above-mentioned formation method is applicable not only to horizontal structure devices but also to vertical structure devices. The difference from the prior art is that, according to the device design requirements, the epitaxial layer 120 in the region of the preset body region 121 is etched, and a target semiconductor material 122 different from the epitaxial layer 120 is filled in, and then ion implantation is performed to form a heterojunction. Therefore, it is not affected by the device type.

[0093] This embodiment of the application involves etching the epitaxial layer 120 in the substrate structure 100, depositing a target semiconductor material 122 different from the substrate structure 100 in the etched area, and then ion implanting the target semiconductor material 122 to form a body region 123 with a different conductivity type than the substrate structure 100. This forms a heterojunction body diode between the body region 123 and the epitaxial layer 120. Compared with the pure silicon body diodes in the prior art, the heterojunction body diode can utilize the low heterojunction electron barrier of the material to obtain a lower reverse turn-on voltage, improve reverse recovery characteristics, shorten reverse recovery time, and improve switching efficiency. Furthermore, the above semiconductor structure eliminates the need for an external parallel diode or additional integrated diode, simplifying the process flow and reducing device size while optimizing reverse recovery performance. In addition, this optimization not only reduces energy loss but also helps meet the stringent performance requirements of modern electric vehicles, renewable energy, and high-frequency switching power supplies, thereby improving the overall reliability and competitiveness of the system.

[0094] In one exemplary embodiment, the dielectric constant of the target semiconductor material 122 is less than the dielectric constant of the substrate structure 100, and / or the carrier mobility of the target semiconductor material 122 is greater than the carrier mobility of the substrate structure 100.

[0095] For example, the dielectric constant of a semiconductor material reflects its ability to polarize in an electric field and can be adjusted through its chemical composition and ion concentration. Specifically, making the carrier mobility of the target semiconductor material 122 higher than that of the substrate structure 100 can improve the conductivity of the body diode, increase its current driving capability, and improve its power density per unit area. At the same time, a material with high carrier concentration means lower resistance and less heat generation when the channel is on, which can enhance the efficiency and reliability of the device. Conversely, making the dielectric constant of the target semiconductor material 122 lower than that of the substrate structure 100 can reduce the parasitic capacitance in the MOSFET device, thereby reducing signal transmission delay, improving the high-frequency performance of the device, increasing signal transmission speed, reducing power consumption during switching, and improving device integration and reliability. The semiconductor structure provided in this application utilizes a low dielectric constant and high carrier mobility as the body region 123 of the device. The low dielectric constant and high carrier mobility material enables the new device to have stronger current output performance and lower parasitic capacitance performance, improving the power and efficiency per unit size of the device.

[0096] In one specific embodiment, when the substrate layer 110 and the epitaxial layer 120 are made of silicon, the target semiconductor material 122 includes any one of germanium, silicon germanium, and gallium arsenide; when the substrate layer 110 and the epitaxial layer 120 are made of aluminum nitride, the target semiconductor material 122 includes diamond; when the substrate layer 110 and the epitaxial layer 120 are made of gallium oxide, the target semiconductor material 122 includes silicon carbide; and when the substrate layer 110 and the epitaxial layer 120 are made of silicon carbide, the target semiconductor material is gallium nitride. It should be noted that the above are only examples of several material combinations. Other material combinations are possible as long as the dielectric constant of the target semiconductor material 122 is less than the dielectric constant of the substrate structure 100, and / or the carrier mobility of the target semiconductor material 122 is greater than the carrier mobility of the substrate structure 100.

[0097] Generally, the dielectric constant of germanium may be higher than that of silicon. In this case, the concentration of germanium can be adjusted. Specifically, when the substrate 110 and the epitaxial layer 120 are made of silicon, germanium is deposited in the preset body region 121 of the epitaxial layer 120 as the target semiconductor material. At this time, the dielectric constant is adjusted by controlling the concentration of Ge, so that the dielectric constant of the formed heterojunction diode is biased towards that of silicon. Specifically, the dielectric constant can be adjusted by adjusting the molar ratio of the gas phase precursor (e.g., GeH4 / SiH4) and controlling the atomic fraction of germanium.

[0098] In MOSFET devices, the gate 420 is an essential component; its presence is crucial for the MOSFET to function properly. However, the configuration of the gate 420 varies depending on the MOSFET device structure.

[0099] In an exemplary embodiment, the semiconductor structure further includes a gate 420. When the semiconductor structure is a trench-type VDMOS device, the method for forming the gate 420 includes:

[0100] S201: A trench 400 is formed in the epitaxial layer 120.

[0101] Specifically, a VDMOS (Vertical Double-Diffused MOSFET) device is a power MOSFET specifically designed for high-voltage and high-current applications. Its unique vertical conductivity structure allows current to flow vertically from the source through the channel to the drain. This structure not only improves the device's current handling capability but also enhances switching speed and thermal performance.

[0102] Therefore, as Figure 9 As shown, before forming the body region 123, a trench 400 is first formed. Specifically, a photoresist layer 401 is first formed on the surface of the epitaxial layer 120, and then photolithography is performed on the photoresist layer 401 to form a patterned photoresist layer 401a, thereby revealing the area to be etched. The epitaxial layer 120 is then etched along the patterned photoresist to form the trench 400 within the epitaxial layer 120. Optionally, the etching of the trench 400 can be performed using dry etching or wet etching, preferably dry etching. The depth of the trench 400 is determined based on the device breakdown voltage (BVDSS) and on-resistance (Ron) of the semiconductor structure, and is not specifically limited here. After the etching of the trench 400 is completed, the photoresist layer 401 on the surface of the epitaxial layer 120 is removed.

[0103] Optionally, the bottom edge of the trench 400 is rounded, that is, the trench structure is U-shaped or bowl-shaped. This can reduce the concentration of cells at the bottom, improve the breakdown voltage, and ensure the uniformity of the thickness of the gate oxide layer 410 prepared subsequently.

[0104] S203: A gate oxide layer 410 is formed on the surface of the trench 400 to obtain a trench structure.

[0105] Please see Figure 10 A gate oxide layer 410 is formed on the surface of the trench 400, and the trench 400 covered with the gate oxide layer 410 is called a trench structure. The gate oxide layer 410 exists as an insulating layer. In the trench-type VDMOS device, it is used to isolate the gate 420 from the epitaxial layer 120, or to isolate the gate 420 from the body region 123 and the epitaxial layer 120, preventing short circuits between the gate 420 and the source, or between the gate 420 and the drain, ensuring that only an electric field is applied to the gate 420 without leakage current. Furthermore, the gate oxide layer 410, the gate 420, and the trench 400 constitute a MOS capacitor. When the gate voltage exceeds the threshold voltage, an inversion channel is formed at the interface between the gate oxide layer 410 and the epitaxial layer 120, and the device is turned on; when the gate voltage is removed, the channel disappears, and the device is turned off. Furthermore, in the trench VDMOS, the gate oxide layer 410 also serves as a field plate. In the trench structure, the gate oxide layer 410 forms a vertical long side on the sidewall and bottom edge of the trench 400, redistributing the epitaxial layer 120 cell longitudinally and improving the breakdown voltage.

[0106] Optionally, the gate oxide layer 410 can be one or more of silicon dioxide, hafnium oxide, and aluminum oxide, preferably silicon dioxide.

[0107] Optionally, the gate oxide layer 410 is formed based on a combination of thermal oxidation, deposition, and thermal oxidation processes. Taking silicon dioxide as an example, when the substrate structure 100 is made of silicon and the gate oxide layer 410 is silicon dioxide, it is formed using a thermal oxidation process. When the substrate structure is not made of silicon, a pure silicon thin film is first deposited on the surface of the trench 400, and then the pure silicon thin film is thermally oxidized to form the gate oxide layer 410. The thickness of the pure silicon thin film is determined according to the designed thickness of the gate oxide layer 410; for example, forming 10nm SiO2 using a thermal process requires 4nm of silicon.

[0108] S205: Polysilicon is filled into the trench structure to form the gate 420.

[0109] like Figure 11 In this process, polysilicon is deposited in the trench structure to form the gate 420 in the semiconductor structure, and the filling height of the gate 420 is consistent with the depth of the trench structure.

[0110] In an exemplary embodiment, when the semiconductor structure is a trench-type VDMOS device, the etching process of the epitaxial layer 120 to form a preset body region 121 located on the surface of the epitaxial layer 120 includes: etching the epitaxial layer 120 on both sides of the trench structure to form the preset body region 121 on both sides of the trench structure.

[0111] In this embodiment, as described above, the preset body region 121 is used to accommodate the fabricated body region 123. When the semiconductor structure is a trench-type VDMOS device, the body region 123 is typically disposed on both sides of the trench structure. For trench 400 etching, please refer to... Figure 12 The epitaxial layer 120 is etched on both sides of the trench structure to form at least one preset body region 121 on each side of the trench structure.

[0112] Optionally, the epitaxial layers 120 located on both sides of the trench structure can be etched along the sidewalls of the trench structure, so that the formed preset body region 121 is isolated from the gate 420 formed in step S205 through the gate oxide layer 410, i.e. Figure 13 The structure shown.

[0113] Therefore, when the semiconductor structure is a trench-type VDMOS device, the trench structure and the gate 420 located in the trench structure are first fabricated to form a vertical conductive path. Then, the epitaxial layer 120 is etched to fabricate the preset body region 121. Then, the above steps S105-S109 are performed to form a complete trench-type VDMOS device. The formed trench-type VDMOS device is as follows: Figure 14 As shown.

[0114] In one exemplary embodiment, the first metal layer 200 and the gate 420 do not overlap. This avoids short circuits caused by contact between the gate 420 and the source, and further reduces parasitic capacitance.

[0115] This application embodiment forms a VDMOS device with a heterojunction body diode by etching a trench structure and forming a gate 420 in the trench structure, and ensuring that the gate 420 and the first metal layer 200 have no overlapping area. By utilizing the low heterojunction electron barrier of the heterojunction body diode, a lower reverse turn-on voltage is obtained, which improves the reverse recovery characteristics, shortens the reverse recovery time, and improves the switching efficiency, thereby obtaining a trench-type VDMOS device with excellent reverse recovery performance.

[0116] In an exemplary embodiment, the semiconductor structure further includes a gate 420. When the semiconductor structure is a planar gate device, the method for forming the gate 420 includes: after forming the body region 123, forming a gate oxide layer 410 located on one side surface of the epitaxial layer 120; the gate oxide layer 410 at least covers the epitaxial layer 120 between the body regions 123 and covers a portion of the body regions 123; and depositing polysilicon on the surface of the gate oxide layer 410 to form the gate 420.

[0117] When the semiconductor structure is a planar gate device, the planar gate device is a horizontally structured MOSFET, and its conduction path is lateral. Therefore, the gate 420 of the planar gate device is placed horizontally. For the specific formation process, please refer to [link to documentation]. Figure 15 After forming the body region 123, a gate oxide layer 410 is formed on the surface of the body region 123. In a planar gate device, the gate oxide layer 410 is used to isolate the gate 420 from the body region 123 and the epitaxial layer 120, preventing the gate 420 from contacting the body region 123 and the target semiconductor material 122 between the body regions. Specifically, the gate oxide layer 410 completely covers the target semiconductor material 122 on the side of the epitaxial layer 120 away from the substrate layer 110, and also covers a portion of the body region 123. It should be noted that in a planar gate device, there are at least two spaced-apart body regions 123, and a portion of the surface of each body region 123 is covered with the gate oxide layer 410.

[0118] Optionally, the gate oxide layer 410 is formed based on a combination of thermal oxidation, deposition, and thermal oxidation processes. Taking silicon dioxide as an example, when the substrate structure 100 is made of silicon and the gate oxide layer 410 is silicon dioxide, it is formed using a thermal oxidation process. When the substrate structure 100 is not made of silicon, a pure silicon thin film is first deposited on the surface of the epitaxial layer 120, and then the pure silicon thin film is thermally oxidized to form the gate oxide layer 410. When the substrate layer 110 in the substrate structure 100 is made of silicon and the epitaxial layer 120 is made of silicon-germanium, a pure silicon thin film also needs to be deposited on the surface of the epitaxial layer first, and then the pure silicon thin film is thermally oxidized to form the gate oxide layer 410. This is because germanium oxide has poor physicochemical properties; its thermal stability, dielectric constant, and interface states are all inferior to those of silicon dioxide. The thickness of the pure silicon thin film is determined according to the designed thickness of the gate oxide layer 410. For example, forming 10nm SiO2 using a thermal process requires 4nm of silicon.

[0119] Please continue reading Figure 15 After forming the gate oxide layer 410, polysilicon is deposited on its surface to form the gate 420. Then, P-type and N-type ion implantation are performed in step S107 to form N+ region 124a and P+ region 124b. Next, step S109 is performed to form the first metal layer 200 and the second metal layer 300, resulting in the desired structure. Figure 16 The planar gate device shown.

[0120] In one exemplary embodiment, the first metal layer 200 and the gate 420 do not overlap. This avoids short circuits caused by contact between the gate 420 and the source, and further reduces parasitic capacitance.

[0121] In this embodiment, a planar gate device with a heterojunction body diode is formed by forming a gate 420 on the surface of the body region 123 and the target semiconductor material 122, and ensuring that the gate 420 and the first metal layer 200 have no overlapping area. By utilizing the low heterojunction electronic barrier of the heterojunction body diode, a lower reverse turn-on voltage is obtained, which improves the reverse recovery characteristics, shortens the reverse recovery time, and improves the switching efficiency, thereby obtaining a planar gate device with excellent reverse recovery performance.

[0122] Furthermore, when the semiconductor structure is another type of MOSFET device, the fabrication method of the gate 420 is the same as the prior art. As long as the body region 123 in the original device is fabricated using the methods in steps S101-S109 above, the body diode in the device can be replaced with a heterojunction body diode, thereby optimizing the reverse optimization performance of the device. The formation methods of other types of MOSFET devices will not be described in detail here.

[0123] In summary, the above technical solution forms a heterojunction body diode between the body region 123 and the epitaxial layer 120 by etching the epitaxial layer 120 and then depositing a target semiconductor material 122 different from the substrate structure 100. Ion implantation of the target semiconductor material 122 further transforms this into a single-material body diode, replacing the single-material body diodes of existing technologies. This not only utilizes the low heterojunction electron barrier of the heterostructure to achieve a lower reverse turn-on voltage, improves reverse recovery characteristics, shortens reverse recovery time, and increases switching efficiency, but also eliminates the need for external parallel diodes or additional integrated diodes, simplifying the process flow and reducing device size while optimizing reverse recovery performance. Furthermore, this optimization not only reduces energy loss but also helps meet the stringent performance requirements of modern electric vehicles, renewable energy, and high-frequency switching power supplies, thereby enhancing the overall reliability and competitiveness of the system. Furthermore, the new structure utilizes low dielectric constant and high carrier mobility as the body region 123 and channel region (referring to the trench structure in trench VDMOS devices). The low dielectric constant and high carrier mobility materials enable the new device to have stronger current output performance and lower parasitic capacitance performance, thereby improving the power and efficiency per unit size of the device.

[0124] This application also provides a semiconductor structure prepared based on the above-described formation method. Specifically, the semiconductor structure includes: a second metal layer 300; a substrate structure 100 located on the surface of the second metal layer 300; the substrate structure 100 includes a substrate layer 110 and an epitaxial layer 120 located on one side surface of the substrate layer 110; a spaced-apart body region 123 located in the epitaxial layer 120; the body region 123 is obtained by etching a predetermined body region 121 into the epitaxial layer 120, filling the predetermined body region 121 with a target semiconductor material 122, and then ion implanting the target semiconductor material 122; the target semiconductor material 122 is different from the material of the substrate structure 100; the conductivity type of the body region 123 is different from the conductivity type of the substrate structure 100; an ion implantation region 124 located in the body region 123; and a first metal layer 200 located on the surface of the body region 123.

[0125] Please see Figure 8The semiconductor structure, from bottom to top, comprises a second metal layer 300, a substrate structure 100, and a first metal layer 200. The substrate structure 100 includes a substrate layer 110 and an epitaxial layer 120 located on the surface of the substrate layer 110. The epitaxial layer 120 has spaced-apart body regions 123. The body regions 123 are formed by etching the epitaxial layer 120 to create a predetermined body region 121, filling the predetermined body region 121 with a target semiconductor material 122, and then performing ion implantation on the target semiconductor material 122. The target semiconductor material 122 is different from the material of the substrate structure 100, and the conductivity type of the body region 123 is different from that of the epitaxial layer 120, thereby forming a heterojunction diode between the body region 123 and the epitaxial layer 120. Furthermore, the body region 123 has an ion implantation region 124, which is obtained by ion implantation into the body region 123.

[0126] In an exemplary embodiment, the dielectric constant of the target semiconductor material 122 is less than that of the substrate structure 100, and the carrier mobility of the target semiconductor material 122 is greater than that of the substrate structure 100.

[0127] For example, when the materials of the substrate layer 110 and the epitaxial layer 120 are silicon, the target semiconductor material 122 includes any one of germanium, silicon germanium, and gallium arsenide; when the materials of the substrate layer 110 and the epitaxial layer 120 are aluminum nitride, the target semiconductor material 122 includes diamond; when the materials of the substrate layer 110 and the epitaxial layer 120 are gallium oxide, the target semiconductor material 122 includes silicon carbide; when the materials of the substrate layer 110 and the epitaxial layer 120 are silicon carbide, the target semiconductor material 122 includes gallium nitride.

[0128] In an exemplary embodiment, the semiconductor structure further includes a gate 420 and a gate oxide layer 410. The gate 420 is disposed on the surface of the epitaxial layer 120 or in the epitaxial layer 120, and the body region 123 is disposed on both sides of the gate 420. The first metal layer 200 and the gate 420 do not overlap. The gate oxide layer 410 is disposed between the epitaxial layer 120 and the gate 420. Specifically, when the semiconductor structure is a MOSFET device, the gate 420 is an essential component. The gate 420 is used to control the channel's on and off states; that is, the voltage at the gate 420 determines whether a channel is formed, thereby controlling whether the current between the drain and source is conducted. Depending on the device type, the position of the gate 420 structure may vary. Generally, it is disposed in the epitaxial layer 120 or on the surface of the epitaxial layer 120, and the body region 123 is disposed on both sides of the gate 420. There is no overlap between the gate 420 and the first metal layer 200 (i.e., the source). Furthermore, the gate 420 and the epitaxial layer 120, as well as the gate 420 and the body region 123, are isolated by the gate oxide layer 410. It should be noted here that the gate 420 being located in the epitaxial layer 120 means that the gate 420 is disposed in the trench 400 in the epitaxial layer 120, that is, the gate 420 and the epitaxial layer 120 are in the same layer.

[0129] In an exemplary embodiment, when the semiconductor structure is a trench-type VDMOS device, the semiconductor structure further includes a trench 400 located in the epitaxial layer 120, a gate 420 located in the trench 400, a gate oxide layer 410 disposed between the trench 400 and the gate 420, and a body region 123 disposed on both sides of the trench structure. Figure 14 As shown, when the semiconductor structure is a trench-type VDMOS device, its conduction path is vertical. Therefore, a trench 400 is provided in the epitaxial layer 120, and a gate oxide layer 410 is provided on the surface of the trench 400. The gate 420 is filled in the trench 400, and the body region 123 is provided on both sides of the gate 420. The body region 123 and the gate 420, the body region 123 and the second metal layer 300 are isolated by the gate oxide layer 410.

[0130] Optionally, the distance between the bottom of the trench 400 and the upper surface of the substrate 110 (i.e., the surface where the substrate 110 and the epitaxial layer 120 are connected) is less than the distance between the bottom surface of the body region 123 and the upper surface of the substrate 110. That is, from the cross-sectional view, the trench 400 completely passes through the body region 123. This ensures the formation of the longitudinal trench 400 and guarantees the conduction of the device.

[0131] Optionally, the distance between the bottom of trench 400 and the upper surface of substrate 110 depends on the breakdown electrode design of the device.

[0132] In an exemplary embodiment, when the semiconductor structure is a planar gate device, the gate 420 is located on the surface of the body region 123, and the gate oxide layer 410 is disposed between the gate 420 and the body region 123. The gate oxide layer 410 and the gate 420 at least cover the region between the body regions 123 and a portion of the body region 123. Figure 16 As shown, when the semiconductor structure is a planar gate device, its conductive path is horizontal. Therefore, the gate 420 is disposed on the surface of the epitaxial layer 120, and the body region 123 and the gate 420, the body region 123 and the second metal layer 300 are isolated by the gate oxide layer 410.

[0133] Furthermore, whether it is a trench VDMOS device or a planar gate device, there is no overlapping area between the first metal layer 200 and the gate 420.

[0134] In an exemplary embodiment, the ion implantation region 124 includes an N+ region 124a and a P+ region 124b, and the N+ region 124a and the P+ region 124b are arranged adjacent to each other.

[0135] In some embodiments, the gate oxide layer 410 is formed based on a combination of precipitation and thermal oxidation processes or a thermal oxidation process.

[0136] This semiconductor structure forms a heterojunction body diode between the target semiconductor material and the epitaxial layer, replacing the single-material body diode in existing technologies. This not only utilizes the low heterojunction electron barrier of the heterostructure to achieve a lower reverse turn-on voltage, improves reverse recovery characteristics, shortens reverse recovery time, and increases switching efficiency, but also eliminates the need for external parallel diodes or additional integrated diodes, thus reducing device size. Furthermore, this optimization not only reduces energy loss but also helps meet the stringent performance requirements of modern electric vehicles, renewable energy, and high-frequency switching power supplies, thereby improving the overall reliability and competitiveness of the system. The new structure utilizes low dielectric constant and high carrier mobility in the body and channel regions (referring to the trench structure in trench-type VDMOS devices). The low dielectric constant and high carrier mobility materials give the new device stronger current output performance and lower parasitic capacitance, improving power and efficiency per unit size.

[0137] It should be noted that the semiconductor structure embodiments of this application are based on the semiconductor structure fabrication method embodiments, and both are based on the same inventive concept.

[0138] This application also provides an electronic device, which includes any of the semiconductor structures described in this application, or includes any of the semiconductor structures described in this application. The electronic device can be any electronic product or device such as a mobile phone, tablet computer, laptop computer, netbook, game console, television, VCD, DVD, vehicle terminal, navigator, camera, camcorder, voice recorder, MP3, MP4, PSP, etc., or it can be an intermediate product with the semiconductor device, such as a device motherboard with the semiconductor device. The use of the semiconductor structure in this electronic device improves its working performance accordingly.

[0139] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit the scope of protection of the present invention. Although the present invention has been described in detail with reference to preferred embodiments, it is not limited to those listed in the embodiments. Those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the essence and scope of the technical solutions of the present invention.

Claims

1. A method of forming a semiconductor structure, characterized by, The semiconductor structure is a grooved VDMOS device, and the method includes: A substrate structure is provided; the substrate structure includes a substrate layer and an epitaxial layer located on one side surface of the substrate layer; Trenches are formed in the epitaxial layer; The epitaxial layer is partially etched on both sides of the trench to form a predetermined body region on the surface of the epitaxial layer; the depth of the predetermined body region is equal to the design depth of the body region. A target semiconductor material is deposited in the predetermined body region by chemical vapor deposition; the target semiconductor material is different from the material of the substrate structure; the dielectric constant of the target semiconductor material is lower than that of the substrate structure, and the carrier mobility of the target semiconductor material is greater than that of the substrate structure; the chemical vapor deposition method includes ultra-high vacuum chemical vapor deposition. The target semiconductor material is subjected to ion implantation to form spaced-apart bulk regions and ion-implanted regions located within the bulk regions; the conductivity type of the bulk regions is different from that of the substrate structure. A first metal layer is formed on the surface of the body region and a second metal layer is formed on the other side surface of the substrate layer.

2. The method of forming of claim 1, wherein, The semiconductor structure further includes a gate, and the method for forming the gate includes: A gate oxide layer is formed on the surface of the trench to obtain the trench structure; The trench structure is filled with polysilicon to form the gate.

3. The method of forming of claim 2, wherein, The first metal layer and the gate do not overlap.

4. The method of forming of claim 1, wherein, The ion implantation region includes an N+ region and a P+ region; the ion implantation of the target semiconductor material to form spaced-apart bulk regions and ion implantation regions located within the bulk regions includes: The target semiconductor material is subjected to target type ion implantation to form spaced-apart body regions; the conductivity type of the body regions is different from that of the substrate structure. P-type ion implantation is performed on the body region to form the P+ region located in the body region; and N-type ion implantation is performed on the body region to form the N+ region located in the body region.

5. A method of forming a semiconductor structure, characterized by, The semiconductor structure is a planar gate device, and the method includes: A substrate structure is provided; the substrate structure includes a substrate layer and an epitaxial layer located on one side surface of the substrate layer; The epitaxial layer is partially etched to form a predetermined body region on the surface of the epitaxial layer; the depth of the predetermined body region is equal to the designed depth of the body region; the predetermined body region is a virtual region formed after a certain thickness of the epitaxial layer is etched away. A target semiconductor material is deposited in the predetermined body region by chemical vapor deposition; the target semiconductor material is different from the material of the substrate structure; the dielectric constant of the target semiconductor material is lower than that of the substrate structure, and the carrier mobility of the target semiconductor material is greater than that of the substrate structure; the chemical vapor deposition method includes ultra-high vacuum chemical vapor deposition. The target semiconductor material is subjected to ion implantation to form spaced-apart bulk regions and ion-implanted regions located within the bulk regions; the conductivity type of the bulk regions is different from that of the substrate structure. A first metal layer is formed on the surface of the body region and a second metal layer is formed on the other side of the substrate layer; the area between the spaced-apart body regions is only the target semiconductor material.

6. The method of forming of claim 5, wherein, The semiconductor structure further includes a gate, and the method for forming the gate includes: After the body region is formed, a gate oxide layer is formed on one side surface of the target semiconductor material; the gate oxide layer at least covers the target semiconductor material between the body regions and covers a portion of the body region; Polysilicon is deposited on the surface of the gate oxide layer to form the gate.

7. The method of forming of claim 6, wherein, The first metal layer and the gate do not overlap.

8. The method of forming of claim 5, wherein, The ion implantation region includes an N+ region and a P+ region; the ion implantation of the target semiconductor material to form spaced-apart bulk regions and ion implantation regions located within the bulk regions includes: The target semiconductor material is subjected to target type ion implantation to form spaced-apart body regions; the conductivity type of the body regions is different from that of the substrate structure. P-type ion implantation is performed on the body region to form the P+ region located in the body region; and N-type ion implantation is performed on the body region to form the N+ region located in the body region.

9. A semiconductor structure, characterized by The semiconductor structure is prepared by the semiconductor structure forming method according to any one of claims 1-4, or the semiconductor structure is prepared by the semiconductor structure forming method according to any one of claims 5-8, wherein the semiconductor structure comprises: Second metal layer; A substrate structure located on the surface of the second metal layer; the substrate structure includes a substrate layer and an epitaxial layer located on one side surface of the substrate layer; A body region is spaced out within the epitaxial layer; the body region is prepared by etching the epitaxial layer, filling the body region with a target semiconductor material, and then ion implanting the target semiconductor material; the target semiconductor material is different from the substrate material; the conductivity type of the body region is different from that of the substrate structure; the dielectric constant of the target semiconductor material is lower than that of the substrate structure, and the carrier mobility of the target semiconductor material is higher than that of the substrate structure; the target semiconductor material is prepared by chemical vapor deposition; the chemical vapor deposition method includes ultra-high vacuum chemical vapor deposition. The ion implantation region is located within the body region; The first metal layer located on the surface of the body region.

10. The semiconductor structure of claim 9, wherein, The semiconductor structure further includes a gate and a gate oxide layer. The gate is disposed on the surface of the epitaxial layer or in the epitaxial layer, and the body region is disposed on both sides of the gate. The first metal layer and the gate do not overlap. The gate oxide layer is disposed between the epitaxial layer and the gate.

11. The semiconductor structure of claim 10, wherein, When the semiconductor structure is a trench-type VDMOS device, the semiconductor structure further includes a trench located in the epitaxial layer, the gate is located in the trench, the gate oxide layer is disposed between the trench and the gate, and the body region is disposed on both sides of the trench.

12. The semiconductor structure of claim 10, wherein, When the semiconductor structure is a planar gate device, the gate is located on the surface of the body region, and the gate oxide layer is disposed between the gate and the body region. The gate oxide layer and the gate at least cover the area between the body regions and a portion of the body region.

13. The semiconductor structure of claim 9, wherein, The ion implantation region includes an N+ region and a P+ region, and the N+ region and the P+ region are arranged adjacent to each other.

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