Circuit board, image sensor, and method for manufacturing image sensor

Abstract

Each of circuit substrates functioning as substrates (10a-10 h) is provided with: a switch (107) including four or more selection pins; a logic circuit (108) that outputs an ON signal from one output terminal selected from among four or more mutually independent output terminals when the ON signal is input only from one preset selection pin among the selection pins and the OFF signals are input from all of the other selection pins; and an electrical component that switches between active and inactive on the basis of the output of the logic circuit (108).

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a circuit board, an image sensor, and a manufacturing method of an image sensor. BACKGROUND

[0002] An image sensor that uses sensor ICs (Integrated Circuit) arranged in a length direction for reading of an image, as the sensor section is elongated and high speeded, the signal processing section includes a plurality of signal processing ICs such as FPGAs (Field Programmable Gate Array), AFEs (Analog Front End), and the like. The signal processing ICs that can be mounted on one circuit board are limited in number, and thus are mounted on a plurality of circuit boards. The plurality of circuit boards are synchronized with each other, and perform processing of image signals read out from each sensor IC.

[0003] The plurality of circuit boards that constitute the signal processing section differ from each other in the type of mounting components and the length of the board depending on the function, arrangement order, and the like, and in this case, component management and mounting become complicated, and become a cause of cost increase or mounting error. In contrast, in order to reduce the types of boards, a method of switching of components between effective and ineffective or switching of wiring by a switch is used (for example, Patent Literature 1).

[0004] The semiconductor integrated circuit described in Patent Literature 1 has a keying circuit that holds the output logic of three logic operation circuits and three inverters connected to each output terminal of the logic operation circuit, and thus, when the output of any one of the first logic operation circuits is low, the output of the other first logic operation circuit is forcibly set to high. Thus, it is described that it is possible to set only any one of the output terminals to high.

[0005] Patent Literature 1: Japanese Patent Application Laid-Open No. 2001-244808

[0006] An image sensor needs to read out an image of one line using a single synchronization signal, and a plurality of boards synchronously acquire sensor signals, and output image signals. Thus, at least two kinds of boards that output a source clock and a synchronization signal, and boards that receive them are needed. In addition, in order to make the length of the length direction of one read image a length suitable for the specifications of an image reading device, a plurality of boards that differ in the number of pixels in the length direction in which signal processing can be performed are needed.

[0007] The semiconductor integrated circuit described in Patent Document 1 includes a logic circuit that selects one of three terminals for output based on signals from eight inputs (Q1 to Q8). In contrast, in image sensors, a common substrate is used for component or wiring selection. When manufacturing various substrates with different functions, the logic circuit illustrated in Patent Document 1 has a relatively small number of outputs compared to the number of inputs, which is insufficient. Summary of the Invention

[0008] This disclosure is made in view of the above-mentioned circumstances, with the aim of providing a circuit board, an image sensor, and a method for manufacturing an image sensor that can function as a variety of substrates with different components or wiring.

[0009] To achieve the above objectives, the circuit board of this disclosure includes: a switch having four or more selection pins; a logic circuit that outputs an on signal from one output terminal selected from four or more independent output terminals when an on signal is input from only one pre-set selection pin among the selection pins and an off signal is input from all other selection pins; and an electrical component that switches between active and inactive based on the output of the logic circuit.

[0010] According to this disclosure, the effective and ineffective states of electrical components are switched by the output of a logic circuit based on the input from the selection pin of the switch, thus enabling the circuit board to function as a variety of boards with different components or wiring. Attached Figure Description

[0011] Figure 1 This is a cross-sectional view showing the inter-substrate wiring of the image sensor according to Embodiment 1 of this disclosure.

[0012] Figure 2 This is a top view of a series of substrates used for image processing in an image sensor.

[0013] Figure 3 This is a top view of the substrate used for image processing in an image sensor.

[0014] Figure 4 It is the overall circuit diagram of the logic circuit.

[0015] Figure 5 This is the circuit diagram of the first logic circuit.

[0016] Figure 6 This is a diagram representing the truth table of the first logic circuit.

[0017] Figure 7A This is a diagram showing the truth table of the first and fifth pins of the second logic circuit.

[0018] Figure 7BThis is a diagram showing the truth table of the second and sixth pins of the second logic circuit.

[0019] Figure 7C This is a diagram showing the truth table of the third and seventh pins of the second logic circuit.

[0020] Figure 7D This is a diagram showing the truth table of the fourth and eighth pins of the second logic circuit.

[0021] Figure 8 This is a diagram representing the truth table of the third logic circuit.

[0022] Figure 9 This is a diagram representing the truth table of the fourth logic circuit.

[0023] Figure 10 It is a diagram representing the input and output of a logic circuit.

[0024] Figure 11 This is a circuit diagram of the logic circuit in Implementation Method 2.

[0025] Figure 12 This is a cross-sectional view showing the inter-substrate wiring of an image sensor, representing another example. Detailed Implementation

[0026] (Implementation Method 1)

[0027] Hereinafter, the image sensor 1 according to an embodiment of the present disclosure will be described with reference to the accompanying drawings. The image sensor 1 is an arbitrary line sensor in which sensor ICs are arranged in a straight line, for example, a contact image sensor (CIS) that integrates sensor ICs, light source and lens array.

[0028] Figure 1 This is a cross-sectional view illustrating the inter-substrate wiring of the image sensor 1 according to this embodiment. The length direction of the image sensor 1 is defined as the X-axis, the width direction as the Y-axis, and the height direction, which is perpendicular to both the length and width directions, as the Z-axis. In this embodiment, the length and width directions of the image sensor 1 are respectively relative to the main scanning direction and the sub-scanning direction of the image sensor 1.

[0029] like Figure 1As illustrated, the image sensor 1 includes: a frame 70 that holds optical components and substrates 21 and 22 for signal processing, and a cover 80 that covers the entire frame 70. The cover 80 is fixed to, for example, various connectors including connectors 51 that supply power to each substrate and connectors 52 that output signals for controlling illumination, an air-cooling fan 53, and substrates 40 and 41 for controlling the image sensor 1. The frame 70 and the cover 80 are, for example, made of aluminum.

[0030] The substrates 21 and 22, fixed to the frame 70, have A / D (Analog to Digital) conversion circuits that convert analog signals output by the sensor IC into digital signals. One or more substrates 21 and one or more substrates 22 are arranged along the main scanning direction. The lengths of the main scanning directions of the substrates 21 and 22 are different, with the length of substrate 22 being longer than the length of substrate 21, so that the length of the main scanning direction of the image sensor 1 is a predetermined length.

[0031] Substrates 10a to 10h (hereinafter, sometimes collectively referred to as substrate 10) are fixed to substrates 21 and 22 via isolation members. Substrates 10a to 10h are substrates for applying the required image processing to the digital signals output from substrates 21 and 22, and substrates 10a to 10h respectively input and output source clock, synchronization signal or control signal.

[0032] Substrates 10a to 10h have the same size, components, and wiring, and their functions are switched via a physical switch. While the number of substrates 10 is arbitrary, at least two substrates are used, including one for transmitting a synchronization signal based on a source clock and another for receiving signals. Furthermore, to ensure that the length of the main scan direction for reading an image at one time is a predetermined length, two or more substrates with different pixel counts in the main scan direction capable of signal processing are arranged. In this embodiment, the case where the physical switch is an eight-channel dual in-line package (DIP) switch and the substrates 10 consist of eight substrates 10a to 10h will be described. Details of substrates 10a to 10h will be described later.

[0033] Substrate 30 is fixed to substrates 10a-10h via insulating member 31. Substrate 30 supplies power to substrates 10a-10h and transmits and receives communication signals.

[0034] The image sensor 1 frame 70 may also include a light source for illuminating the object being read and a control board for the light source. The light source may be, for example, an LED (Light Emitting Diode).

[0035] The substrate 40, fixed to the cover 80, is connected to substrates 10a-10h via wiring. The image signal processed by the substrates 10a-10h is converted into a preset specification and output to the outside. The specification of the signal output to the outside is arbitrary, such as CameraLink (registered trademark), CoaXPress (registered trademark), GigEVision (registered trademark), and USB3Vision (registered trademark).

[0036] In addition, the substrate 41 fixed to the cover 80 is a substrate of a microcomputer that manages the image sensor 1 as a whole. It is connected to the substrate 30 through wiring and transmits and receives control signals with the substrates 10 and 30 as well as the outside.

[0037] The image sensor 1 operates as follows: First, the sensor IC receives transmitted or reflected light from the target area illuminated by the light source and outputs an analog signal. The A / D conversion circuits of substrates 21 and 22 convert the analog signal input from the sensor IC into a digital signal. The converted digital signal undergoes signal processing, including image data rearrangement, in substrates 10a to 10h, and is transmitted to substrate 40 via wiring. Substrate 40 converts the received image signal into a preset specification and outputs it externally.

[0038] Additionally, substrate 40 receives control signals input from an external source and outputs them to the microcomputer on substrate 41. Based on the received control signals, the microcomputer on substrate 41 sends control signals to substrates 10a-10h via wiring and substrate 30, and controls substrates 10a-10h. The characteristic feature is that the substrates 10a-10h of the image sensor 1 in this embodiment are circuit boards.

[0039] Figure 2 It is a top view of a series of substrates 10a to 10h for image processing arranged along the main scanning direction, with adjacent substrates connected to each other. Figure 3 This is a top view of a substrate 10. In a circuit board in which identical components are mounted and have the same wiring, substrates 10a to 10h switch the functionality of components by switching on switch 107.

[0040] like Figure 2 , 3 As shown, for example, the substrate 10 includes a master clock 101, a buffer 102 for adjusting the source clock signal output from the master clock 101, a connector 103 for a cable electrically connecting the substrates, a buffer 104 for adjusting the signal input from the preceding substrate, a buffer 105 for adjusting the signal sent to the preceding substrate, and a signal processing IC. The signal processing IC is, for example, an FPGA (Field Programmable Gate Array).

[0041] The substrate 10 is also equipped with a switch 107 that selects the active / inactive state of electrical components of the substrate 10, and a logic circuit 108 that performs logical operations on the output of the switch 107 and outputs the result. Figure 3 As shown, four or more output terminals of logic circuit 108 are connected via wiring 109 to the master clock 101 and the enable terminals of each buffer 102, 104, 105. The connector 103 of substrate 10 is connected to the connector 103 of adjacent substrate 10 via cable 110.

[0042] use Figures 4-10 The switch 107 and logic circuit 108 are described in detail. Switch 107 is a physical switch with four or more channels, such as an eight-channel dual in-line package (DIP-SW) in the figure. One terminal of switch 107 is connected to GND, and the selection pin of the other terminal is pulled up. The first pin P1 to the eighth pin P8, which are the selection pins, are low when switch 107 is turned on (short-circuited) and high when switch 107 is turned off (open).

[0043] Logic circuit 108 is a circuit that, when an on signal is input from only one of the four or more selection pins of switch 107 and an off signal is input from all other pins, outputs an on signal from any one of the four or more independent output terminals through logical operations. In this embodiment, the case where switch 107 has eight channels will be described. That is, when a low-level on signal is input from only one of the first pins P1 to the eighth pin P8 of switch 107 and a high-level off signal is input from all other pins, logic circuit 108, through logical operations, outputs a low-level on signal from any one of the independent output terminals S1 to S8. By setting the low or high output of logic circuit 108 as an enable signal and inputting it to the enable terminals of buffers 102, 104, and 105, the activation or deactivation of the buffers is controlled.

[0044] For example, when the first pin P1 of the switch 107 is set low, the logic circuit 108 performs a logic operation where only the output terminal S1 of the logic circuit 108 is low. In this case, by turning on only the first channel of the switch 107, the turn-on signal output from the output terminal S1 of the logic circuit 108 is input to the buffer 102, thereby making the buffer 102 active, and the clock signal of the master clock 101 is output into the circuit.

[0045] On the other hand, when at least one of the second to eighth channels of the switch 107 on the first substrate 10a is turned on, the output terminal S1 of the logic circuit 108 goes high, thus deactivating the buffer 102 and preventing the clock signal from being output to the circuit. Therefore, using the switch 107, the substrate from which the clock signal is output can be reliably selected. Furthermore, if multiple channels of the switch 107 are mistakenly turned on, the output of the logic circuit 108 goes high, thus avoiding signal collisions due to misoperation.

[0046] Similarly, the output of logic circuit 108 can be input to the enable terminal of master clock 101 to control clock oscillation or stop. In addition, the output of logic circuit 108 can be input to the enable terminals of buffers 104 and 105 to control signal transmission between substrates.

[0047] use Figures 4-10 The structure of logic circuit 108 is explained. Figure 4 This is a diagram showing the overall structure of logic circuit 108. Figure 5 This is a diagram showing the structure of the first logic circuit 1081, which is part of the logic circuit 108. (See diagram below.) Figure 4 As shown, the logic circuit 108 includes a first logic circuit 1081, a second logic circuit 1082, a third logic circuit 1083, and a fourth logic circuit 1084. Figure 6 This is the truth table of the first logic circuit 1081. Figures 7A-7D This is the truth table of the second logic circuit 1082. Figure 8 This is the truth table of the third logic circuit 1083. Figure 9 It is the truth table of the fourth logic circuit 1084. Figure 10 This is a diagram showing the inputs and outputs of logic circuit 108.

[0048] The first pin P1 to the eighth pin P8 of the switch 107, which are the selection pins for each channel, are connected to the input of the first logic circuit 1081. For example... Figure 5 As shown, in the first stage of the first logic circuit 1081, four logic AND circuits 1101 are connected to mutually isolated first pin P1 and fifth pin P5, second pin P2 and sixth pin P6, third pin P3 and seventh pin P7, and fourth pin P4 and eighth pin P8.

[0049] The output of AND circuit 1101 is inverted by NOT circuit 1102 and input to AND circuit 1103 and NOR circuit 1104. The output of AND circuit 1103 is input to NOR circuit 1105, and the output of NOR circuit 1105 is inverted by NOT circuit 1106 and input to NOR circuit 1108.

[0050] The output of logic NOR circuit 1104 is input to logic AND circuit 1107, and its output is input to logic NOR circuit 1108. The output of logic NOR circuit 1108 is inverted by NOT circuit 1109 and then input to logic NOR circuit 1110. Its output is inverted by NOT circuit 1111 and output from the output terminal S of the first logic circuit 1081. L1 Output.

[0051] The truth value of the first logic circuit 1081 with such a structure is represented as follows: Figure 6 .exist Figure 6 In the truth table, the four bits on the vertical axis correspond to the values ​​of pins P3 (third pin), P7 (seventh pin), P4 (fourth pin), and P8 (eighth pin) of switch 107. Similarly, the four bits on the horizontal axis correspond to the values ​​of pins P1 (first pin), P5 (fifth pin), P2 (second pin), and P6 (sixth pin) of switch 107. Here, a value of 0 is considered low, and a value of 1 is considered high.

[0052] like Figure 6 As shown, in 12 cases where at least one of the first pin P1 and the fifth pin P5 is low, when at least one of the second pin P2 and the sixth pin P6 is low, when at least one of the third pin P3 and the seventh pin P7 is low, and when at least one of the fourth pin P4 and the eighth pin P8 is low, the output terminal S of the first logic circuit... L1 The value is low. Otherwise, the output terminal S of the first logic circuit... L1 The value is high.

[0053] like Figure 4 As shown, the second logic circuit 1082 includes four logic XOR circuits 1201. The inputs of each logic XOR circuit 1201 are respectively connected to pins P1 and P5, P2 and P6, P3 and P7, and P4 and P8. The output of each logic XOR circuit 1201 is inverted by a NOT circuit 1202 and output to the third logic circuit 1083.

[0054] Depend on Figures 7A-7D According to the truth table, the output of the second logic circuit 1082 is a high value when the values ​​of the first pin P1 and the fifth pin P5, the second pin P2 and the sixth pin P6, the third pin P3 and the seventh pin P7, the fourth pin P4 and the eighth pin P8 are the same, and a low value when they are different.

[0055] like Figure 4As shown, the third logic circuit 1083 has four NOR circuits 1301. The outputs of the first logic circuit 1081 and the second logic circuit 1082 are input to the inputs of each NOR circuit 1301. The outputs of the NOR circuits 1301 are inverted by the NOT circuit 1302 and input to the fourth logic circuit 1084.

[0056] Depend on Figure 8 According to the truth table, when the outputs of the first logic circuit 1081 and the second logic circuit 1082 are both low, the output of the third logic circuit 1083 becomes a low value; when at least one of the outputs of the first logic circuit 1081 and the second logic circuit 1082 is high, the output of the third logic circuit 1083 becomes a high value.

[0057] like Figure 4 As shown, the fourth logic circuit 1084 has eight NOR circuits 1401. The inputs of each NOR circuit 1401 are connected to the output of the third logic circuit 1083 and pins P1 to P8. The outputs of the NOR circuits 1401 are inverted by the NOT circuits 1402 and then output.

[0058] Depend on Figure 9 According to the truth table, when the output of the third logic circuit 1083 and the values ​​of each selection pin of the switch 107 are both low, the output of the fourth logic circuit 1084, that is, the output of the logic circuit 108, becomes a low value. When at least one of the output of the third logic circuit 1083 and the values ​​of each selection pin of the switch 107 is high, the output of the fourth logic circuit 1084 becomes a high value.

[0059] The inputs and outputs of the logic circuit 108 with the structure described above are shown below. Figure 10 In logic circuit 108, when a low-level on signal is input only from the first pin P1 due to only the first channel of switch 107 being on, a low-level on signal is output from output terminal S1. Similarly, when a low-level on signal is input only from the fifth pin P5, the second pin P2, the sixth pin P6, the third pin P3, the seventh pin P7, the fourth pin P4, and the eighth pin P8, low-level on signals are output from output terminals S5, S2, S6, S3, S7, S4, and S8, respectively. On the other hand, when two or more channels of switch 107 are on, or when all channels are off, a high-level off signal is output from any output terminal. In other words, logic circuit 108 outputs an on signal from any output terminal selected from the mutually independent output terminals S1 to S8 because only one of the first to eighth channels of switch 107 is on.

[0060] The output of the logic circuit 108, which operates in this way, can control the activation / deactivation of electrical components, including the master clock 101 of substrates 10a to 10h. Furthermore, in a structure without the logic circuit 108 and where the switch 107 is directly connected to the enable terminals of each electrical component, malfunctions can occur due to multiple channels of the eight channels of the switch 107 being incorrectly activated. However, by using the logic circuit 108, such malfunctions can be avoided.

[0061] also, Figures 4-9 The structure of the logic circuit 108 shown is an example and can be replaced. For example, the combination of a NOR circuit and a NOT circuit can be replaced with an OR circuit. Alternatively, the combination of an AND circuit and a NOT circuit can be replaced with a NAND circuit. Furthermore, the combination of an XOR circuit and a NOT circuit can be replaced with an NXOR circuit.

[0062] Reference Figure 1 , 2 The manufacturing method of the image sensor 1 configured as described above will be explained.

[0063] First, the substrates 21 and 22 with A / D conversion circuits are fixed along the arrangement direction of the sensor ICs, i.e., the main scanning direction. Figure 1 The sensor IC frame 70 is shown. Next, substrates 10a to 10h are fixed to substrates 21 and 22 respectively via the isolator 25 (substrate fixing step).

[0064] Subsequently, the operation Figure 2 The switches 107 of each of the substrates 10a to 10h shown are configured such that only one preset selection pin of the switch 107 of each substrate 10a to 10h is turned on, while the other selection pins are turned off. As a result, an output input signal is selected from the eight independent outputs of the logic circuit 108, thereby effectively switching the corresponding electrical component (switch setting step).

[0065] Next, substrate 30 is fixed to substrates 10a-10h via spacer 31. Then, substrates 40 and 41 fixed to the cover, connectors 51 and 52, and FAN53 are connected to substrates 10 and 30 fixed to frame 70 via wiring. Then, cover 80 is fixed relative to frame 70.

[0066] As explained above, the image sensor 1 of this embodiment, serving as a substrate for processing image signals acquired from a sensor IC, uses a substrate 10 having identical components and wiring. A switch 107 and a logic circuit 108 that performs logic operations on the input signals from the switch 107 and outputs the results are mounted on the substrate 10. The logic circuit 108 performs a logic operation by outputting a low value from any one of the first pins P1 to the eighth pin P8 of the switch 107 when only one pin is low. The output of the logic circuit 108 is input to the enable terminals of buffers 102, 104, and 105, thereby controlling the activation or deactivation of the buffers. Therefore, to realize a strip-shaped image sensor, it is not necessary to use multiple circuit boards for image processing; a single circuit board can be used. Furthermore, since a single circuit board is used, the manufacturing process can be simplified.

[0067] Furthermore, when using a microcomputer or FPGA to select the board function, a startup time of several milliseconds to several seconds is required after power-on. However, in this embodiment, the board function is selected through a combination of logic elements, thus significantly shortening the startup time. In addition, since the board function selection is implemented with a simple structure such as switch 107 and logic circuit 108, the cost can also be reduced.

[0068] (Implementation Method 2)

[0069] The image sensor 1 of Embodiment 2 of this disclosure is a line sensor having the same structure as the image sensor 1 of Embodiment 1, in which sensor ICs are arranged in a straight line. The structure of the logic circuit 128 mounted on the substrate 10 is different from that of Embodiment 1. The image sensor 1 of Embodiment 2 will be described in detail with reference to the accompanying drawings.

[0070] Figure 11 This diagram illustrates the structure of a portion of the logic circuit 128 in Embodiment 2. In addition to the logic circuit 108 of Embodiment 1, the logic circuit 128 also includes a full-level AND circuit 1281, which serves as a multi-level AND circuit, between the logic circuit 108 and specific electrical components. That is, as shown... Figure 11 As shown, logic circuit 128 includes a full logic AND circuit 1281, which is used to output the logic AND of output signals from all output terminals except one selected from the output terminals S1 to S8 of the fourth logic circuit 1084. Figure 11 In this process, the logical OR operation of the output signals from output terminals S2 to S8 (excluding output terminal S1) is sequentially calculated. As a result, when any one of the values ​​at output terminals S2 to S8 is low, the logic circuit 128 outputs signals from output terminal S... AThe output is low when all values ​​of output terminals S2 to S8 are high, from output terminal S... A High output.

[0071] The output S of logic circuit 128 A An enable signal is input to the enable terminal of a specific electrical component, thereby enabling or disabling that component. The specific electrical component, for example, is the master clock 101, based on the output S... A Controls the oscillation or stopping of the clock.

[0072] Furthermore, one of the output terminals selected from the output terminals S1 to S8 of the fourth logic circuit 1084 is directly connected to the buffers 102, 104, and 105, which are other electrical components, and is controlled to be active or inactive.

[0073] Thus, by incorporating switch 107 and logic circuit 128, the elongated image sensor 1 can be realized without using multiple circuit boards for image processing; it can be achieved with a single circuit board. Furthermore, using a single circuit board also simplifies the manufacturing process.

[0074] As explained above, in the image sensor 1 of this embodiment, the logic circuit 128 that outputs the enable signal includes a full logic AND circuit 1281. This full logic AND circuit 1281 outputs a logic AND of the output signals from all output terminals except one selected from the output terminals S1 to S8 of the fourth logic circuit 1084. Thus, the output signals from one output terminal S1 of the full logic circuit 128 are ANDed. A The signal can also be used as an enable signal, thus reliably switching the electrical components between active and inactive states.

[0075] Furthermore, although the above embodiments 1 and 2 describe the case where the switch 107 has eight channels and the logic circuit 108 has eight outputs, the same implementation is also possible when the switch 107 has four to seven channels and the logic circuit 108 has four to seven outputs.

[0076] For example, when switch 107 has four channels, this can be implemented by fixing all of the fifth pin P5, sixth pin P6, seventh pin P7, and eighth pin P8 of the first logic circuit 1081 to high (pull-up). Similarly, this can be implemented by fixing the sixth pin P6, seventh pin P7, and eighth pin P8 of the first logic circuit 1081 to high when switch 107 has five channels, fixing the seventh pin P7 and eighth pin P8 of the first logic circuit 1081 to high when switch 107 has six channels, and fixing the eighth pin P8 of the first logic circuit 1081 to high when switch 107 has seven channels.

[0077] Since when switch 107 has four to seven channels, the output terminals S5, S6, S7, and S8 of the fourth logic circuit 1084, which correspond to the pins that are fixed as high among the fifth pin P5, sixth pin P6, seventh pin P7, and eighth pin P8 of the first logic circuit 1081, become high, these output terminals are fixed as high (pull-up).

[0078] Furthermore, although the structure of logic circuit 108 was described as an example of a logic circuit for outputting an enable signal in embodiments 1 and 2 above, any other logic circuit may be used as long as it is a logic circuit that performs logic operations on four or more on or off input signals and outputs an on or off signal from any one of four or more output terminals selected by each other independently.

[0079] Furthermore, although in embodiments 1 and 2 described above, substrates 10a to 10h are constructed from a single circuit board, and the function of substrate 10 is switched via switch 107 and logic circuits 108 and 128, the invention is not limited to this. For example, substrate 10 may also include the function of substrate 30. That is, as... Figure 12 As shown, a circuit board can also be used to form a board 11 (11a-h) that includes the functions of board 10 and board 30, and the functions of board 11 can be switched by a switch 107 and logic circuits 108 and 128. Figure 12 This is a diagram illustrating image sensor 2 as another example. This allows for a further reduction in the number of substrate types.

[0080] The various forms disclosed herein will be recorded hereafter as appendices.

[0081] (Note 1) A circuit board, comprising:

[0082] A switch that includes four or more selection pins;

[0083] A logic circuit that, when receiving an ON signal from only one of the preset selection pins and an OFF signal from all the other selection pins, outputs an ON signal from one of four or more independent output terminals; and

[0084] Electrical components that switch between active and inactive states based on the output of the logic circuit.

[0085] (Note 2) According to the circuit board described in Note 1, wherein,

[0086] The switch is a physical switch that includes eight selection pins.

[0087] The logic circuit includes a first logic circuit that outputs an enable signal when an enable signal is input from at least one of the select pins pre-defined among the select pins and other select pins isolated from the select pin.

[0088] (Note 3) According to the circuit board described in Note 2, wherein,

[0089] The logic circuit further includes: a second logic circuit that calculates the logical XOR of the input from one selection pin and the input from the other selection pins; a third logic circuit that calculates the logical OR of the output of the first logic circuit and the output of the second logic circuit; and a fourth logic circuit that calculates the logical OR of the inputs from the eight selection pins and the output of the third logic circuit.

[0090] (Note 4) The circuit board according to any one of Notes 1 to 3, wherein,

[0091] The logic circuit includes a full logic AND circuit that performs a logic AND operation on the outputs from all output terminals other than the selected output terminal.

[0092] At least one of the electrical components switches between active and inactive based on the output of the full logic AND circuit.

[0093] (Note 5) The circuit board according to any one of Notes 1 to 4, wherein,

[0094] The electrical component is a clock or a buffer.

[0095] (Note 6) An image sensor comprising a plurality of circuit boards as described in any one of Notes 1 to 5, wherein...

[0096] The electrical components, which are activated by selection via the selection pins of the switches on each circuit board, perform image processing on the output signal of the sensor IC.

[0097] (Appendix 7) A method for manufacturing an image sensor, comprising the following steps:

[0098] In the substrate fixing step, multiple substrates for image processing are fixed relative to a frame on which sensor ICs are fixed, along the arrangement direction of the sensor ICs. The multiple substrates for image processing are equipped with: a switch including four or more selection pins, a logic circuit performing logic operations on inputs from the selection pins, and electrical components that switch between active and inactive states based on the output of the logic circuit; and

[0099] The switch setting step involves setting only one of the preset selection pins to be on and setting all other selection pins to be off, thereby selecting one output terminal from four or more independent output terminals of the logic circuit to output a signal that enables the electrical component.

[0100] This disclosure can be implemented in various ways and with variations without departing from the broad spirit and scope of this disclosure. Furthermore, the above-described embodiments are illustrative of this disclosure and not intended to limit its scope. That is, the scope of this disclosure is defined by the claims, not the embodiments. Moreover, various variations implemented within the scope of the claims and their equivalents are considered to be within the scope of this disclosure.

[0101] This application is based on Japanese Patent Application No. 2023-091875, filed on June 2, 2023. The description, claims, and drawings of Japanese Patent Application No. 2023-091875 are incorporated herein by reference in their entirety.

[0102] Explanation of reference numerals in the attached figures

[0103] 1, 2... Image sensor; 10, 10a~10h, 11, 11a~11h, 21, 22, 30... Substrate; 25, 31... Isolator; 40, 41... Substrate; 51, 52... Connector; 53... FAN; 70... Frame; 80... Cover; 101... Master clock; 102, 104, 105... Buffer; 103... Connector; 106... FPGA; 107... Switch; 108, 128... Logic circuit; 109... Wiring; 110... Cable; 1 081...First logic circuit; 1082...Second logic circuit; 1083...Third logic circuit; 1084...Fourth logic circuit; 1101, 1103, 1107...AND circuit; 1102, 1106, 1109, 1111...NOT circuit; 1104, 1105, 1108, 1110...NOR circuit; 1201...XOR circuit; 1202, 1302, 1402...NOT circuit; 1301, 1401...NOR circuit; 1501...AND circuit.

Claims

1. A circuit board, characterized in that, have: A switch that includes four or more selection pins; A logic circuit that, when receiving an ON signal from only one of the pre-defined selection pins and an OFF signal from all the other selection pins, outputs an ON signal from one of four or more independent output terminals. as well as Electrical components that switch between active and inactive states based on the output of the logic circuit.

2. The circuit board according to claim 1, characterized in that, The switch is a physical switch that includes eight selection pins. The logic circuit includes a first logic circuit that outputs an enable signal when an enable signal is input from at least one of the select pins pre-defined among the select pins and other select pins isolated from the select pin.

3. The circuit board according to claim 2, characterized in that, The logic circuit also includes: The second logic circuit calculates the logical XOR of the input from one of the selection pins and the input from the other selection pins; A third logic circuit calculates the logical OR of the outputs of the first logic circuit and the second logic circuit; and The fourth logic circuit calculates the logical OR of the inputs from the eight selection pins and the output of the third logic circuit.

4. The circuit board according to any one of claims 1 to 3, characterized in that, The logic circuit includes a full logic AND circuit that performs a logic AND operation on the outputs from all output terminals other than the selected output terminal. At least one of the electrical components switches between active and inactive based on the output of the full logic AND circuit.

5. The circuit board according to any one of claims 1 to 4, characterized in that, The electrical component is a clock or a buffer.

6. An image sensor comprising a circuit board according to any one of claims 1 to 5, characterized in that, The electrical components, which are activated by selection via the selection pins of the switches on each circuit board, perform image processing on the output signal of the sensor IC.

7. A method for manufacturing an image sensor, characterized in that, It includes the following steps: In the substrate fixing step, multiple substrates for image processing are fixed relative to a frame on which sensor ICs are fixed along the arrangement direction of the sensor ICs. The multiple substrates for image processing are equipped with: a switch including four or more selection pins, a logic circuit that performs logic operations on the input from the selection pins, and an electrical component that switches between active and inactive based on the output of the logic circuit. and The switch setting step involves setting only one of the preset selection pins to be on and setting all other selection pins to be off, thereby selecting one output terminal from four or more independent output terminals of the logic circuit to output a signal that enables the electrical component.

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