Reproduction code phase generation device, baseband signal processing system and method

Abstract

The invention relates to the technical field of satellite navigation and positioning, and provides a reproduction code phase generation device and a baseband signal processing system and method, and the device comprises a code sequence generation unit which is used for generating a pseudo-random code sequence synchronized with a target satellite signal under the driving of a secondary code phase signal, and outputting at least two continuous chips; the phase control signal generation unit is used for generating a phase control signal with a preset time interval, and the preset time interval is smaller than the time of a complete chip; the phase interval generation unit is used for generating an intermediate phase signal with a preset phase interval according to the phase control signal and the at least two continuous chips; and the phase storage unit is used for sampling and storing the intermediate phase signal at each preset time interval and outputting N paths of reproduction code phases. The device is used for generating multiple paths of high-resolution local reproduction code phases so as to support high-precision code phase tracking of satellite signals.

Description

Technical Field

[0001] This invention relates to the field of satellite navigation and positioning technology, and in particular to a reproducible code phase generation device, a baseband signal processing system and method. Background Technology

[0002] In related technologies, the tracking channel in a satellite positioning receiver typically includes a numerically controlled oscillator (NCO), a code generator, and a code shift register to generate local copy codes for code stripping. Traditional structures provide three phase paths for the reproducible code—early, prompt, and late—through the code shift register, with a phase interval typically half a chip.

[0003] However, to improve multipath resistance, support unambiguous tracking of Binary Offset Carrier (BOC) signals, and enhance robustness under interference conditions, receivers need to provide multiple reproducible code phases with narrow phase spacing. Existing technologies mainly achieve this in two ways: one is to increase the system operating clock frequency to obtain finer phase resolution; the other is to increase the number of code NCOs to achieve multi-path independent phase control.

[0004] The aforementioned solutions suffer from increased power consumption and high hardware resource overhead, especially when smaller phase intervals or multiple parallel outputs are required. Therefore, there is an urgent need for a reproducible code phase generation device, a baseband signal processing system, and a method to address these issues. Summary of the Invention

[0005] This invention provides a code phase generation device, a baseband signal processing system, and a method for generating multiple high-resolution local code phases in a baseband signal processing system to support high-precision code phase tracking of satellite signals.

[0006] According to a first aspect of the present invention, a reproducible code phase generation apparatus is provided, comprising: a code sequence generation unit, configured to generate a pseudo-random code sequence synchronized with a target satellite signal under the drive of a secondary code phase signal, and output at least two consecutive code chips; the at least two consecutive code chips include a current code chip and a next code chip; a phase control signal generation unit, configured to generate a phase control signal having a predetermined time interval, the predetermined time interval being less than the time of a complete code chip; a phase interval generation unit, wherein a first input terminal is connected to the output terminal of the code sequence generation unit, configured to receive at least two consecutive code chips; and a second input terminal is connected to the output terminal of the phase control signal generation unit, configured to receive a phase control signal; the phase interval generation unit is configured to generate a plurality of intermediate phase signals between the current code chip and the next code chip according to the predetermined phase interval in the phase control signal, the intermediate phase signals being used to control the timing of the pseudo-random code sequence switching from the current code chip to the next code chip; and a phase storage unit, wherein an input terminal is connected to the output terminal of the phase interval generation unit, configured to sample and store the intermediate phase signals at each predetermined time interval, and output N reproducible code phases, where N is an integer greater than 1.

[0007] In one embodiment, the phase control signal generation unit includes: a phase accumulator, which is used to accumulate phase according to a frequency control word under the drive of a working clock to obtain an accumulated phase value; when the accumulated value reaches its maximum representation range and wraps back to zero, a secondary code phase overflow signal is generated; the secondary code phase overflow signal is used to generate the basic timing reference for the sub-chip level phase control signal.

[0008] In one embodiment, the phase control signal generating unit further includes an interval counter, which counts based on the secondary code phase overflow signal to generate a code generation signal for controlling the generation of a pseudo-random code sequence.

[0009] In one embodiment, the phase control signal generating unit further includes a frequency division module, which divides the frequency control word by a preset frequency division coefficient to obtain the minimum phase increment of the device. This phase increment is smaller than the phase increment represented by the frequency control word, and is used to generate a phase control signal smaller than the chip level.

[0010] In one embodiment, the phase interval generation unit includes: a code value buffer unit for storing the current code chip; a phase calculation unit for determining whether the accumulated value of the phase accumulator reaches a preset threshold at each valid edge of the phase control signal, and updating the next code chip to the current code chip when the preset threshold is reached, and storing it in the code value buffer unit; and a phase interval selector for controlling the code value buffer unit to batch shift out a preset number of recurring code phases in each code phase cycle; wherein, the intermediate phase signal is the input value of the code value buffer unit.

[0011] In one embodiment, the phase storage unit includes an N-stage shift register, which is used to shift the intermediate phase signal sequentially under the drive of each secondary code phase signal, and output N channels of reproducible code phase in parallel in each clock cycle.

[0012] In one implementation, N is a positive integer power of 2.

[0013] In one implementation, the time for a complete chip is N times a predetermined time interval.

[0014] According to a second aspect of the present invention, a baseband signal processing system is provided, comprising: an apparatus according to any one of the first aspects; for code phase tracking of a target satellite signal.

[0015] In one embodiment, the system further includes: a complex demodulation unit, a correlation integration unit, and a loop tracking unit; the complex demodulation unit is used to perform quadrature demodulation on the received intermediate frequency digital signal to generate a complex digital baseband signal containing complete phase and amplitude information; the first input terminal of the correlation integration unit is connected to the output terminal of the phase storage unit and is used to receive the N-channel reproducible code phase; the second input terminal of the correlation integration unit is used to acquire the complex digital baseband signal; the correlation integration unit is used to perform correlation operations between each channel reproducible code phase and the complex digital baseband signal, and integrate the correlation results to generate N-channel integral values; the loop tracking unit is used to determine the code phase error based on the N-channel integral values ​​and adjust the local code phase to improve the code phase tracking accuracy of the target satellite signal.

[0016] According to a third aspect of the present invention, a method for generating and controlling a reproducible code phase is provided, which controls the apparatus of any one of the first aspects, comprising: controlling a code sequence generation unit to generate a pseudo-random code sequence synchronized with a target satellite signal under the drive of a secondary code phase signal, and outputting at least two consecutive code chips; the at least two consecutive code chips including a current code chip and a next code chip; controlling a phase control signal generation unit to generate a phase control signal having a predetermined time interval, the predetermined time interval being less than the time of a complete code chip; controlling a phase interval generation unit to receive at least two consecutive code chips and receive the phase control signal; and generating a plurality of intermediate phase signals between the current code chip and the next code chip according to the predetermined phase interval in the phase control signal, the intermediate phase signals being used to control the timing of the pseudo-random code sequence switching from the current code chip to the next code chip; and controlling a phase storage unit to sample and store the intermediate phase signals at each predetermined time interval, and output N reproducible code phases, where N is an integer greater than 1.

[0017] Compared with existing technologies, the advantages of this invention are as follows: By generating multiple intermediate phase signals between the current chip and the next chip, this invention can achieve sub-chip level or higher phase resolution without relying on a high-frequency clock. Specifically, the phase interval generation unit generates multiple intermediate phase signals at predetermined phase intervals during the transition from the current chip to the next chip, based on a predetermined time interval "less than a complete chip time" set in the phase control signal. These signals precisely control the specific time when the pseudo-random code sequence switches from the current chip to the next chip, thereby refining the code phase control precision to multiple discrete time nodes within the chip. This invention avoids the practice in traditional solutions of increasing the system master clock frequency to several times the chip rate to obtain high phase resolution, achieving fine code phase control while maintaining a relatively low system operating clock frequency. Therefore, it reduces the dynamic power consumption of digital circuits, which is beneficial for miniaturization and low-power design of the receiver. Attached Figure Description

[0018] Figure 1 This is a structural block diagram of a reproducible code phase generation device according to an exemplary embodiment.

[0019] Figure 2 This is a schematic diagram of a reproducible code phase generation device with a phase interval selector, according to another exemplary embodiment.

[0020] Figure 3 This is a schematic diagram of a code phase generation device equipped with a code digitally controlled oscillator and a frequency division module, according to yet another exemplary embodiment.

[0021] Figure 4 This is a structural block diagram of a baseband signal processing system according to an exemplary embodiment.

[0022] Figure 5 This is a flowchart illustrating a reproducible code phase generation control method according to an exemplary embodiment.

[0023] Explanation of the reference numerals in the figure: 10. Code sequence generation unit; 20. Phase control signal generation unit; 30. Phase interval generation unit; 4. Phase storage unit; 5. Reproducible code phase generation device; 6. Correlation integration unit; 7. Loop tracking unit; 8. Complex demodulation unit; 9. Baseband signal processing system; 11. Code numerically controlled oscillator; 21. Code generator; 22. Logic frequency divider module; 31. Phase calculation unit; 41. Shift register. Detailed Implementation

[0024] Unless otherwise defined, the technical or scientific terms used in this specification should have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. Specific embodiments of the invention will be described below with reference to the accompanying drawings. It should be noted that, in order to provide a concise description, this specification cannot provide a detailed description of all features of the actual embodiments. Without departing from the spirit and scope of the invention, those skilled in the art can make modifications and substitutions to the embodiments of the invention, and the resulting embodiments are also within the protection scope of the invention.

[0025] like Figure 1 As shown, the first embodiment of the present invention provides a code phase generation device 5, comprising: a code sequence generation unit 10, used to generate a pseudo-random code sequence synchronized with a target satellite signal under the drive of a secondary code phase signal, and output at least two consecutive code chips; the at least two consecutive code chips include a current code chip and a next code chip; a phase control signal generation unit 20, used to generate a phase control signal with a predetermined time interval, the predetermined time interval being less than the time of a complete code chip; and a phase interval generation unit 30, the first input terminal of which is connected to the output terminal of the code sequence generation unit 10, used to receive the at least two consecutive code chips; Its second input terminal is connected to the output terminal of the phase control signal generation unit 20, and is used to receive the phase control signal; the phase interval generation unit 30 is used to generate multiple intermediate phase signals between the current chip and the next chip according to the predetermined phase interval in the phase control signal, and the intermediate phase signals are used to control the timing of the pseudo-random code sequence switching from the current chip to the next chip; the phase storage unit 4, whose input terminal is connected to the output terminal of the phase interval generation unit 30, is used to sample and store the intermediate phase signals at each predetermined time interval, and output N channels of reproducible code phase, where N is an integer greater than 1.

[0026] In some examples, the number of code sequence generation units and the number of code sequence generation units are both 1. The phase storage unit samples and stores the multiple intermediate phase signals generated above within each code phase cycle, and can output N channels of reproducible code phases in parallel. Since these phase signals all originate from the same code sequence and the same phase control timing, their "phase difference" is essentially a manifestation of "time difference," rather than the result of "independent phase accumulators." Therefore, there is no need to configure an independent NCO for each channel to maintain its own code phase counter or frequency control word, avoiding the structure of adding multiple code NCOs required in traditional solutions to achieve multi-channel independent phase control. Compared to increasing the number of NCOs, this solution also significantly reduces the occupation of hardware logic resources, lowers circuit area and design complexity, and is particularly suitable for applications requiring the output of a large number of reproducible code phases.

[0027] like Figure 2 As shown, in some specific embodiments, the code sequence generation unit 10 is a code digitally controlled oscillator 11; the phase control signal generation unit 20 includes a code generator 21 and a logic frequency divider module 22; the phase interval generation unit 30 is a phase interval selector; and the phase storage unit 4 is a shift register 41.

[0028] It is worth noting that this embodiment, by introducing a phase control signal generation unit 20 to generate control signals with time intervals less than one chip period, and combining this with a phase interval generation unit 30 to interpolate the original code sequence, can generate intermediate phase signals with higher accuracy than sub-chip level, such as fine intervals of 1 / 4 or 1 / 8 chip, without relying on ultra-high system clock frequencies. The resulting N-channel reproducible code phase supports high-density sampling near the code correlation peak, facilitating accurate estimation of signal arrival time offsets higher than sub-chip offsets through correlation value trends. This achieves pseudorange measurement with a time resolution superior to a full chip, significantly improving positioning accuracy.

[0029] This embodiment generates multi-phase signals by interpolating based on the code sequence, avoiding the need for multiple code numerically controlled oscillators (NCOs) required in traditional solutions to achieve independent phase control of multiple channels. Compared to solutions that increase the number of NCOs, this embodiment significantly reduces the occupation of hardware logic resources (such as registers, adders, etc.), lowers circuit area and design complexity, and is particularly suitable for application scenarios that require the output of a large number of reproducible code phases.

[0030] Because it eliminates the need to increase the operating clock frequency of the entire baseband processing system several times to achieve fine-grained phase resolution, this invention achieves high-precision phase generation while maintaining a low system clock frequency. This significantly reduces the dynamic power consumption of digital circuits, facilitating receiver miniaturization and low-power design. The multi-path narrow-interval reproducible code phase generated by this device can be used to construct a dense array of correlation sampling points, helping to accurately capture the correlation function envelope of BOC-type modulated signals, effectively solving the main peak and side lobe ambiguity problem, improving ambiguity-free tracking capability, and enhancing the receiver's robustness in multipath and interference environments.

[0031] In one embodiment, the phase control signal generating unit 20 includes a phase accumulator, which is used to accumulate phase according to a frequency control word under the drive of a working clock to obtain an accumulated phase value.

[0032] like Figure 2 and Figure 3As shown, in some specific embodiments, the phase accumulator includes a code space NCO oscillator 11, which receives a configurable frequency control word code_space_nco_delta and accumulates the frequency control word under the drive of the operating clock Fs to generate a code space NCO phase value. When the accumulated value overflows, a code space overflow signal is generated to indicate the completion of a phase step cycle.

[0033] In other specific embodiments, the frequency control word code_space_nco_delta is set to an integer multiple of the target code rate. For example, in the BeiDou system B1 band civilian signal B1I, if the code rate is 2.046MHz and the operating clock Fs is 4.096MHz, then code_space_nco_delta is configured to be twice the code rate, causing the code digitally controlled oscillator 11 to generate an overflow once every two accumulations, corresponding to a time interval of 1 / 2 chip.

[0034] In one possible implementation, the phase control signal generating unit further includes an interval counter (not shown in the figure), which counts based on the secondary code phase overflow signal to generate a code generation signal for controlling the generation of pseudo-random code sequences.

[0035] like Figure 3 As shown, in some specific embodiments, the phase control signal generation unit 20 further includes a frequency division module, used to divide the frequency control word code_space_nco_delta by a preset frequency division coefficient, such as 8, to obtain a minimum phase increment of the device, used to generate a phase control signal smaller than the chip level. For example, after dividing code_space_nco_delta by 8, a secondary counter or judgment logic is driven to further divide each 1 / 2 chip period into 8 equally spaced timing positions, thereby supporting a 1 / 16 chip level phase resolution.

[0036] In some examples, the frequency divider module is a logic frequency divider module 22. The logic frequency divider module 22 includes a numerical scaling submodule, used to divide the frequency control word code_space_nco_delta by a preset division coefficient to generate a smaller secondary phase increment. In this embodiment, the division coefficient is 8, and the division operation is implemented by right-shifting by 3 bits. This design eliminates the need for multipliers and dividers, requiring only shift logic, resulting in low hardware resource consumption.

[0037] In other examples, the logic divider module 22 further includes a finite state machine (not shown), whose input signals include: an operating clock Fs, such as 4.096MHz; an overflow signal overflow_pulse from the code numerically controlled oscillator 11; and a phase resolution configuration signal to indicate 1 / 2, 1 / 4, 1 / 8, and 1 / 16 chip modes. The finite state machine waits for the overflow pulse in an idle state; once an overflow is detected, it enters a "phase subdivision" state.

[0038] In some other examples, the logic frequency divider module 22 also includes a sub-phase generation sub-module (not shown in the figure). After the finite state machine enters the "phase subdivision" state, this logic generates eight intermediate phase control signals spacephase1 to spacephase8 in the next system clock cycle to drive subsequent code value selection and storage operations.

[0039] In some specific embodiments, the phase control signal generation unit 20 further includes an interval counter (SpaceCounter), which counts based on the secondary code phase overflow signal and controls the shift number operation of the code shift register 41 according to the shift number signal (Shift Num). For example, when the system is configured with a 1 / 16 chip interval, after each overflow of the code digital oscillator 11 (corresponding to 1 / 2 chip), the interval counter controls the code shift register 41 to shift in 8 new phase values ​​at once to achieve batch update of phase data.

[0040] In some examples, the code shift register 41code_corr_buff is composed of multiple cascaded D flip-flops, and its operation is as follows: Data Input (D): The D terminal of each D flip-flop receives the corresponding code value output from code_buff. For example, under the drive of control signals x1 to x8, code_buff[7] to code_buff[0] are used as input data for the eight D flip-flops, ready to be written to the corresponding positions of code_corr_buff. Clock Input (C): The C terminal of each D flip-flop receives the shift enable pulse (such as x1 to x8) generated by the phase interval selector. This pulse is activated in parallel after the secondary code phase overflow event and serves as the write clock, controlling the data to be latched into the D flip-flop at a specific timing point.

[0041] It is worth noting that when the configurable phase interval is 1 / 2, code_corr_buff only moves into the value of code_buff[7]; when the configurable phase interval is 1 / 4, code_corr_buff moves into the values ​​of code_buff[7] and code_buff[3] at the same time; when the configurable phase interval is 1 / 8, code_corr_buff moves into the values ​​of code_buff[7], code_buff[5], code_buff[3] and code_buff[1] at the same time; and when the configurable phase interval is 1 / 16, code_corr_buff moves into the values ​​of code_buff at the same time.

[0042] In some specific embodiments, the output phase value of the code numerically controlled oscillator 11 is also used to generate a secondary code phase signal Fc, the frequency of which is equal to the code rate of the target satellite signal, and is used to drive the code sequence generation unit 10 to generate new pseudo-random codes. By integrating or cascading the code numerically controlled oscillator 11 with the code NCO function, the phase control and code generation are synchronized and coordinated.

[0043] like Figure 3 As shown, in some specific embodiments, the phase control signal generated by the phase control signal generation unit 20 includes multi-level phase shift control signals, such as x1, x2, ..., x8. These signals are generated by the phase value of the code digitally controlled oscillator 11 after logical judgment or decoding, and are used to control the multiplexer or combinational logic in the phase interval generation unit 30 to determine whether to select the current code or the next code as the intermediate phase signal output at different phase times.

[0044] In one implementation, the frequency control word code_space_nco_delta is used to determine the generation rhythm and timing reference of the secondary code phase step value; the code phase step value is used to further control the generation period of the secondary code phase signal to adjust the chip update rate of the code sequence generation unit 10.

[0045] In some specific embodiments, the frequency control word code_space_nco_delta is configured to be an integer multiple of the target satellite signal code rate, for example, twice, so that the time increment corresponding to each accumulation of the code digitally controlled oscillator 11 under the drive of the working clock Fs is... . This is one complete chip cycle. When the accumulated value overflows, a basic phase control pulse (i.e., Code Space Overflow) is generated. The period of this pulse is 1 / 2 chip time, which serves as the main timing reference for the entire multi-phase generation system.

[0046] In other specific embodiments, the code phase step value is not directly generated by code_space_nco_delta, but is achieved by further dividing the period corresponding to the basic phase control pulse, such as 1 / 2 chip, into M equally spaced sub-periods. Specifically, code_space_nco_delta is divided by a preset frequency division factor, such as 8, to obtain a finer secondary phase increment, which is used to determine whether the phase should be updated at the 8 sub-positions within each 1 / 2 chip period. The finest time interval generated thus is:

[0047] This achieves a code phase step value of 1 / 16 of a chip, used to support high-density output of 16 channels of reproducible code phase.

[0048] In some specific embodiments, the timing reference corresponding to the code phase step value, i.e., the basic phase overflow period, is used to generate the secondary code phase signal Fc. Specifically, by counting or dividing every K basic phase overflow pulses, for example, K=2, a periodic pulse signal with a frequency equal to the target signal code rate is generated as Fc. For example, in the BeiDou B1I signal, the code rate is 2.046MHz. When the basic overflow period is 1 / 2 chip, every two overflow pulses generate one Fc pulse, making the Fc frequency precisely 2.046MHz.

[0049] In some specific embodiments, the secondary code phase signal Fc is output to the code sequence generation unit 10, such as the Linear Feedback Shift Register (LFSR), to drive it to generate a new chip in each Fc cycle. Since the Fc frequency is strictly equal to the code rate, the chip update rate of the code sequence generation unit 10 is synchronized with the satellite signal, ensuring that the locally generated pseudo-code sequence is aligned with the received signal at the chip level.

[0050] In one embodiment, the phase control signal generating unit 20 further includes: a comparator for comparing the accumulated phase value with a preset overflow threshold to generate a comparison result; and a pulse generating circuit for generating a pulse each time the phase accumulation overflows, based on the comparison result, as the phase control signal.

[0051] In some specific embodiments, the preset overflow threshold corresponds to a standard value of the code frequency control value.

[0052] like Figure 1 and Figure 2As shown, in one embodiment, the phase interval generation unit 30 includes: a code value buffer unit for storing the current code chip; a phase calculation unit 31 for determining whether the accumulated value of the phase accumulator reaches a preset threshold at each effective edge of the phase control signal, and updating the next code chip to the current code chip when the preset threshold is reached, and storing it in the code value buffer unit; and a phase interval selector for controlling the code value buffer unit to batch shift out a preset number of recurring code phases in each code phase cycle; wherein, the intermediate phase signal is the input value of the code value buffer unit.

[0053] In some specific embodiments, the code value buffer unit is an 8-bit or 16-bit register (code_buff), the width of which is related to the maximum phase resolution supported by the system. For example, in a system that supports a 1 / 16 chip interval, the code_buff is 8 bits wide and is used to store the code values ​​of 8 candidate phases in each 1 / 2 chip period. code_buffer[0] to code_buffer[7] represent the 8 storage units in the code_buff from the least significant bit to the most significant bit, respectively, used to store the code values ​​at different phase points.

[0054] In other specific embodiments, the "preset threshold" corresponds to the modulus of the code space NCO 11. When the accumulator output overflows, a code space overflow signal is generated, which serves as a "valid edge" to trigger subsequent operations.

[0055] In some specific embodiments, the phase gap selector does not directly "update the next chip to the current chip," but instead utilizes the characteristics of the code sequence generation unit 10 to predict or directly output the next chip while generating the current chip. Therefore, the phase gap selector receives a total of two bits: the current PN code and the next PN code from the LFSR.

[0056] In some specific embodiments, during each operating clock cycle, the phase interval selector determines, based on the fine phase increment generated by code_space_nco_delta / 8, whether the code phase should remain at the "current code" or switch to the "next code" within the current clock cycle. Specifically, if the code numerically controlled oscillator 11 does not overflow, the current code is stored at the corresponding position in code_buff; if the code numerically controlled oscillator 11 overflows, the next code is stored at the corresponding position in code_buff.

[0057] In one embodiment, the phase storage unit 4 includes an N-stage shift register 41, which is used to shift the intermediate phase signal sequentially under the drive of each secondary code phase signal, and output N channels of reproducible code phase in parallel in each clock cycle.

[0058] like Figure 3 As shown, in some specific embodiments, the N-stage shift register 41 is a 16-bit wide code-correlation buffer register (code_corr_buff), where N=16, used to store 16 channels of reproducible code phases with fixed phase intervals. These 16 phase channels cover multiple sampling points within a complete chip period, supporting fine-grained phase configurations such as leading phase, immediate phase, and subsequent phase.

[0059] In other specific embodiments, the shift operation of the shift register 41 is performed in batches under the drive of the basic phase control signal, namely the overflow signal of the code digitally controlled oscillator 11. Specifically, when the period is 1 / 2 chip, when the code digitally controlled oscillator 11 overflows, the system writes the 8 intermediate phase signals stored in the code value buffer unit into the high 8 bits of code_corr_buff in parallel at one time, while the original data is shifted left by 8 bits and the low 8 bits are discarded.

[0060] In one implementation, N is 2 raised to the power of 0.

[0061] In some specific embodiments, when the system supports a minimum phase interval of 1 / 16 chip, N is configured to 16, indicating that 16 equally spaced recurring code phase sampling points can be provided within a complete chip period, covering the entire correlation peak region from leading to lagging.

[0062] In one implementation, the time for a complete chip is N times the predetermined time interval.

[0063] In some specific embodiments, the timing of a complete chip is determined by the target satellite signal regime.

[0064] In some examples, the time of the complete code chip of the B1I signal of the BeiDou Navigation Satellite System The time of the complete chip of the L1 band coarse acquisition code (C / A) signal of the Global Positioning System (GPS). .

[0065] like Figure 4 As shown, a second embodiment of the present invention provides a baseband signal processing system 9, including the apparatus described in any of the above embodiments.

[0066] In some embodiments, the baseband signal processing system 9 further includes: a complex demodulation unit 8, a correlation integration unit 6, and a loop tracking unit 7. The complex demodulation unit 8 is used to perform quadrature demodulation on the received intermediate frequency digital signal to generate a complex digital baseband signal containing complete phase and amplitude information. The first input terminal of the correlation integration unit 6 is connected to the output terminal of the phase storage unit 4 and is used to receive the N-channel reproducible code phase. The second input terminal of the correlation integration unit 6 is used to acquire the complex digital baseband signal. The correlation integration unit 6 is used to perform correlation operations between each channel reproducible code phase and the complex digital baseband signal, and integrate the correlation results to generate N-channel integral values. The loop tracking unit 7 is used to determine the code phase error based on the N-channel integral values ​​and adjust the local code phase to achieve code phase tracking of the target satellite signal.

[0067] In some specific embodiments, the system further includes: a radio frequency front end, used to receive radio frequency signals from the target satellite, and perform low-noise amplification, down-conversion, and analog-to-digital conversion to generate the digital baseband signal.

[0068] In other specific embodiments, the loop tracking unit 7 includes: a phase detector: calculating the code phase error based on N-channel integral values. For example, an early-late discriminator is used. A loop filter, typically a second- or third-order digital loop filter, is used to smooth the phase error signal and suppress noise. A digitally controlled oscillator interface is used to convert the filtered error signal into frequency control word increments, used to adjust the cumulative acceleration rate of the code digitally controlled oscillator 11.

[0069] like Figure 5 As shown, a third embodiment of the present invention provides a reproducible code phase generation control method for controlling the apparatus described in any of the above embodiments, comprising: S1, controlling a code sequence generation unit to generate a pseudo-random code sequence synchronized with a target satellite signal under the drive of a secondary code phase signal, and outputting at least two consecutive code chips; the at least two consecutive code chips include a current code chip and a next code chip; S2, controlling a phase control signal generation unit to generate a phase control signal with a predetermined time interval, the predetermined time interval being less than the time of a complete code chip; S3, controlling a phase interval generation unit to receive the at least two consecutive code chips and the phase control signal; and generating multiple intermediate phase signals between the current code chip and the next code chip according to the predetermined phase interval in the phase control signal, the intermediate phase signals being used to control the timing of the pseudo-random code sequence switching from the current code chip to the next code chip; S4, controlling a phase storage unit to sample and store the intermediate phase signals at each predetermined time interval, and outputting N reproducible code phases, where N is an integer greater than 1.

[0070] In this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The term "multiple" refers to two or more unless otherwise expressly defined.

[0071] The above description of the embodiments is intended to enable those skilled in the art to understand and apply the present invention. It will be apparent to those skilled in the art that various modifications can be made to these embodiments, and the general principles described herein can be applied to other embodiments without creative effort. Therefore, the present invention is not limited to the embodiments described herein, and any improvements and modifications made by those skilled in the art based on the disclosure of the present invention without departing from the scope and spirit of the invention are within the scope of the present invention.

Claims

1. A replica code phase generation apparatus, characterized by comprising: The application relates to a code sequence generating device for generating a pseudo-random code sequence synchronized with a target satellite signal, comprising: a code sequence generating unit for generating a pseudo-random code sequence synchronized with a target satellite signal under the driving of a sub-code phase signal and outputting at least two continuous code chips; the at least two continuous code chips include a current code chip and a next code chip; a phase control signal generating unit for generating a phase control signal with a predetermined time interval, wherein the predetermined time interval is smaller than the time of a complete code chip; a phase interval generating unit, a first input end of which is connected to the output end of the code sequence generating unit and is used for receiving the at least two continuous code chips; a second input end of the phase interval generating unit is connected to the output end of the phase control signal generating unit and is used for receiving the phase control signal; the phase interval generating unit is used for generating a plurality of intermediate phase signals between the current code chip and the next code chip according to the predetermined phase interval in the phase control signal, and the intermediate phase signals are used for controlling the time when the pseudo-random code sequence is switched from the current code chip to the next code chip; a phase storage unit, an input end of which is connected to the output end of the phase interval generating unit and is used for sampling and storing the intermediate phase signals at each predetermined time interval and outputting N-way reproduced code phases, wherein N is an integer greater than 1.

2. The apparatus of claim 1, wherein, The phase control signal generating unit comprises: a phase accumulator, which is used for performing phase accumulation according to a frequency control word under the driving of a working clock to obtain an accumulated phase value; when the accumulated value reaches its maximum representation range and is wrapped to zero, a sub-code phase overflow signal is generated; the sub-code phase overflow signal is used for generating a basic time sequence reference of the phase control signal at a sub-code chip level.

3. The apparatus of claim 2, wherein, The phase control signal generating unit further comprises an interval counter, which is used for counting based on the sub-code phase overflow signal to generate a code generation signal for controlling the generation of the pseudo-random code sequence.

4. The apparatus of claim 2, wherein, The phase control signal generating unit further comprises a frequency division module, which is used for dividing the frequency control word by a preset frequency division coefficient to obtain the minimum phase increment of the device, wherein the phase increment is smaller than the phase increment represented by the frequency control word and is used for generating the phase control signal at a smaller level than the sub-code chip level.

5. The apparatus of claim 2, wherein, The frequency control word is used for determining the generation rhythm and time sequence reference of a code phase step value; and the code phase step value is used for controlling the generation period of the sub-code phase signal to adjust the code chip update rate of the code sequence generating unit.

6. The apparatus of claim 1, wherein, The phase interval generating unit comprises: a code value buffer unit used for storing the current code chip; a phase calculation unit used for judging whether the accumulated value of the phase accumulator reaches a preset threshold at each active edge of the phase control signal, and updating the next code chip as the current code chip and storing the next code chip in the code value buffer unit when the accumulated value reaches the preset threshold; a phase interval selector used for controlling the code value buffer unit to batch remove a preset number of reproduced code phases in each sub-code phase period; wherein the intermediate phase signal is the input value of the code value buffer unit.

7. The apparatus of claim 1, wherein, The phase storage unit comprises an N-stage shift register, which is used for sequentially shifting the intermediate phase signals under the driving of each sub-code phase signal and outputting N-way reproduced code phases in parallel at each clock period.

8. The apparatus of claim 1, wherein, N is a positive integer power of 2.

9. The apparatus of claim 1 or 7, wherein, The time of a complete chip is N times of the predetermined time interval.

10. A baseband signal processing system, characterized by The application comprises the following steps: The device according to any one of claims 1-9 is used for code phase tracking of a target satellite signal.

11. The system of claim 10, wherein, The system further comprises a complex demodulation unit, a correlation integration unit and a loop tracking unit. The complex demodulation unit is used for quadrature demodulation of a received intermediate frequency digital signal to generate a complex digital baseband signal containing complete phase and amplitude information. The first input end of the correlation integration unit is connected to the output end of the phase storage unit and is used for receiving the N-path reproduced code phases; the second input end of the correlation integration unit is used for acquiring the complex digital baseband signal. The correlation integration unit is used for correlation operation of each reproduced code phase with the complex digital baseband signal and integration of the correlation result to generate N-path integration values. The loop tracking unit is used for determining code phase errors according to the N-path integration values and adjusting a local code phase to improve code phase tracking precision of the target satellite signal.

12. A replica code phase generation control method for controlling the apparatus of any one of claims 1 to 9, characterized by, The application comprises the following steps: The code sequence generation unit is controlled to generate a pseudo-random code sequence synchronized with the target satellite signal under the drive of the sub-code phase signal and to output at least two continuous chips; the at least two continuous chips include a current chip and a next chip; The phase control signal generation unit is controlled to generate a phase control signal with a predetermined time interval, which is less than the time of a complete chip; The phase interval generation unit receives the at least two continuous chips and receives the phase control signal and generates a plurality of intermediate phase signals between the current chip and the next chip according to a predetermined phase interval in the phase control signal, which is used for controlling the time when the pseudo-random code sequence switches from the current chip to the next chip; The phase storage unit samples and stores the intermediate phase signals at each predetermined time interval and outputs N-path reproduced code phases, N being an integer greater than 1.

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