DRAM (Dynamic Random Access Memory) dynamic repair method based on unit damage trend identification

Abstract

The invention relates to the technical field of DRAM (Dynamic Random Access Memory) dynamic repair, in particular to a DRAM dynamic repair method based on unit damage trend identification. The method comprises the following steps: receiving a logic address request sent by a CPU (Central Processing Unit), sending a reading command to a DRAM (Dynamic Random Access Memory), and obtaining return data and ECC (Error Correction Code When a single-bit error is detected, the error is corrected according to ECC verification data, correct data is returned, meanwhile, the damage trend of a surrounding area is pre-judged based on physical correlation of DRAM unit damage, a DRAM address and the surrounding area are marked as isolation addresses, and the data are moved to an SRAM; establishing a repair mapping table in the SRAM, and writing the repair mapping table into the nonvolatile memory through the bus interface; reading the mapping table during cold start of the system, judging whether the address is an isolation address or not according to the mapping table in subsequent access, and if yes, accessing the SRAM to obtain data. According to the invention, a single-bit error is prevented from being evolved into a multi-bit error, and the system reliability is improved.

Description

Technical Field

[0001] This invention relates to the field of DRAM dynamic repair, specifically a DRAM dynamic repair method based on cell damage trend identification. Background Technology

[0002] With the rapid development of cloud computing, edge computing and Internet of Things technologies, DRAM, as a core storage component, faces the challenge of increasing cell failure rate when operating in harsh environments for extended periods. Ensuring high system reliability and continuous stable operation has become an urgent technical challenge to be solved.

[0003] In existing technologies, mainstream DRAM reliability assurance schemes employ the ECC SECDED error correction mechanism, which can correct single-bit errors and detect double-bit errors. However, this scheme has significant drawbacks: First, it can only passively correct errors that have already occurred and cannot predict the spread of DRAM cell damage; second, when an error occurs in a memory cell, due to the physical correlation of DRAM cell damage, neighboring cells will successively fail, eventually leading to double-bit or even multi-bit errors in the same area. The SECDED mechanism can only detect double-bit errors but cannot correct them, causing system crashes; furthermore, existing schemes lack persistent isolation mechanisms for problematic areas, meaning that the system will still access the damaged DRAM area after a restart, causing errors to recur. These shortcomings severely limit the lifespan of DRAM in high-reliability applications. Summary of the Invention

[0004] This invention provides a dynamic DRAM repair method based on cell damage trend identification. By predicting the spread trend of DRAM cell damage and isolating the problem area in advance, it effectively prevents single-bit errors from evolving into uncorrectable multi-bit errors. This solves the technical defects of existing ECC schemes, which can only passively correct errors and cannot persistently isolate damaged areas, thus significantly improving system reliability.

[0005] To achieve the above objectives, the present invention provides the following technical solution: A dynamic DRAM repair method based on cell damage trend identification includes: S100: Receives the logical address request sent by the CPU, sends a read command to the DRAM and obtains the returned data and the corresponding ECC check data, regenerates the ECC check data based on the returned data and compares it with the obtained ECC check data; S200: When a single-bit error exists in the comparison result, the single-bit error is corrected according to the ECC check data and the corrected data is returned. At the same time, the damage trend of the DRAM cell is identified, the DRAM address where the single-bit error occurred is marked as an isolation address, and the data corresponding to the isolation address is moved from DRAM to SRAM. S300: Establish a repair mapping table in SRAM, record the mapping relationship between the isolated address and the SRAM storage address, and write the repair mapping table into non-volatile memory through the bus interface; S400: During system cold boot, the repair mapping table is read from non-volatile memory. In subsequent accesses, the repair mapping table is used to determine whether the address to be accessed is an isolated address. If it is, the data is obtained by accessing the memory address mapped in SRAM, and the isolated address in DRAM is no longer accessed.

[0006] As a preferred embodiment of the present invention, the step of regenerating ECC verification data and comparing it with the acquired ECC verification data includes: The returned data is regenerated using the SECDED encoding mechanism; The regenerated ECC check data is compared with the acquired ECC check data to identify single-bit errors and their locations.

[0007] As a preferred technical solution of the present invention, the identification of DRAM cell damage trend includes: based on the physical correlation of DRAM cell damage, when a DRAM cell with a single-bit error is detected, it is predicted that the memory cells in the area surrounding the isolation address have a tendency to successively have errors, and the DRAM address and the address area within a preset range around it are marked as isolation addresses.

[0008] As a preferred embodiment of the present invention, the step of moving the data corresponding to the isolation address from DRAM to SRAM includes: Determine the range of data blocks corresponding to the isolated address, wherein the range of data blocks includes the address where the error occurred and addresses within a preset range around it; Allocate storage space from SRAM that is the same size as the range of the data block; The data after ECC correction is written into the allocated SRAM storage space.

[0009] As a preferred embodiment of the present invention, the repair mapping table includes: The isolated address field records addresses in DRAM that are marked as isolated. The SRAM address field records the storage address of the corresponding data in SRAM. The valid flag field indicates whether the mapping relationship is valid.

[0010] As a preferred embodiment of the present invention, the step of writing the repair mapping table into the non-volatile memory via the bus interface includes: transferring the repair mapping table from SRAM to the bus via the APB bus interface, and writing the repair mapping table into a preset storage area in the Flash memory.

[0011] As a preferred embodiment of the present invention, the step of determining whether the address to be accessed is an isolated address includes: Receive the address to be accessed from the CPU; Search the repair mapping table for the isolated address field that matches the address to be accessed; If a matching isolated address is found and the corresponding valid flag is valid, then the address to be accessed is determined to be an isolated address.

[0012] The beneficial effects of this invention are: 1. By using a proactive identification mechanism for cell damage trends, the damage trend of surrounding memory cells can be predicted and isolated in advance when a single-bit error is detected. This overcomes the limitation of traditional ECC schemes, which can only correct errors after the fact. It effectively prevents single-bit errors from evolving into uncorrectable multi-bit errors, fundamentally eliminates the risk of system crash due to continuous damage to DRAM cells, and significantly improves the reliability of the system under harsh environments and long-term operating conditions.

[0013] 2. By repairing the persistent storage and cold start recovery mechanism of the mapping table, the isolation state of the DRAM problem area can continue to take effect after power failure and restart, avoiding the process of error detection and data migration after restart, realizing the accumulation and continuity of the repair effect, and effectively extending the usable life of DRAM chips in the gradual aging process.

[0014] 3. Through the collaborative mechanism of SRAM data migration and access redirection, transparent isolation of faulty areas is achieved, so that the CPU is completely unaware of the damaged state of the underlying DRAM cells during normal access. This ensures data correctness and access continuity, and avoids the spread of errors caused by continuous access to damaged cells. It provides a cost-effective reliability guarantee solution for application scenarios with extremely high availability requirements. Attached Figure Description

[0015] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings: Figure 1 This is a flowchart illustrating a dynamic DRAM repair method based on cell damage trend identification according to the present invention. Detailed Implementation

[0016] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0017] Example 1: As Figure 1 As shown, this invention discloses a dynamic DRAM repair method based on cell damage trend identification. This method is implemented through a FIX IP module, which is integrated into the memory controller and acts as an intermediate layer between the CPU and DRAM. This module is responsible for address translation, ECC verification, error detection and correction, data migration, and mapping table management. The FIX IP module integrates SRAM for storing migrated data and the repair mapping table, and communicates with the non-volatile memory via the APB bus interface. Specifically, it includes the following steps: S100: Receives the logical address request sent by the CPU, sends a read command to the DRAM and obtains the returned data and the corresponding ECC check data, regenerates the ECC check data based on the returned data and compares it with the obtained ECC check data; Further, the step of regenerating the ECC verification data and comparing it with the acquired ECC verification data includes: The returned data is regenerated using the SECDED encoding mechanism; The regenerated ECC check data is compared with the acquired ECC check data to identify single-bit errors and their locations.

[0018] Specifically, after receiving a logical address request from the CPU, the FIX IP module first converts the logical address into a physical address for the DRAM, and then sends a read command to the DRAM through the standard DRAM interface (CA / DQ signal line).

[0019] After receiving a read command, the DRAM accesses the corresponding memory cell (CELL) based on the address information, reads the stored data, and returns it. Because this invention employs an inline ECC scheme, ECC verification data and actual data are stored in the same DRAM channel. Therefore, while reading the actual data, the FIX IP module generates a separate ECC read command to retrieve the ECC verification data corresponding to that address from the DRAM. For DRAMs with a fixed 16-bit channel width, such as LPDDR4 / LPDDR5, the memory channel is partitioned, with a dedicated portion used to store ECC data.

[0020] After receiving the data returned from DRAM, the FIX IP module immediately uses the SECDED encoding mechanism to regenerate ECC check data. Specifically, SECDED encoding generates corresponding check bits for the 8-bit data, and calculates the new ECC check code using Hamming code encoding rules.

[0021] Next, the FIX IP module compares the regenerated ECC check data bit by bit with the original ECC check data obtained from DRAM. By comparing the differences between the two sets of ECC data, it can identify whether an error occurred during data transmission or storage. If the two sets of ECC data match perfectly, it indicates that the returned data is correct; if there is a difference, the SECDED mechanism can locate the position of the error bit through the XOR operation of the check bits and determine whether the error is a single-bit error or a double-bit error. This comparison result will serve as the basis for the error handling judgment in the subsequent step S200.

[0022] S200: When a single-bit error exists in the comparison result, the single-bit error is corrected according to the ECC check data and the corrected data is returned. At the same time, the damage trend of the DRAM cell is identified, the DRAM address where the single-bit error occurred is marked as an isolation address, and the data corresponding to the isolation address is moved from DRAM to SRAM. Furthermore, the identification of DRAM cell damage trends includes: based on the physical correlation of DRAM cell damage, when a DRAM cell with a single-bit error is detected, it is predicted that the memory cells in the area surrounding the isolation address have a tendency to successively experience errors, and the DRAM address and the address area within a preset range around it are marked as isolation addresses.

[0023] Furthermore, the step of moving the data corresponding to the isolation address from DRAM to SRAM includes: Determine the range of data blocks corresponding to the isolated address, wherein the range of data blocks includes the address where the error occurred and addresses within a preset range around it; Allocate storage space from SRAM that is the same size as the range of the data block; The data after ECC correction is written into the allocated SRAM storage space.

[0024] Specifically, when the ECC check comparison result obtained by S100 shows a single-bit error, the FIX IP module first locates the specific position of the error bit according to the SECDED mechanism. Using the check bit information in the ECC check data, the module can accurately identify which bit in the 8-bit data has an error and flip the error bit (i.e., change 0 to 1 or 1 to 0), thus completing the single-bit error correction. The corrected data is immediately returned to the CPU through the DRAM interface to ensure the normal operation of the system.

[0025] Simultaneously, the FIX IP module initiates a DRAM cell failure trend identification mechanism. This mechanism is based on a crucial principle of DRAM physical characteristics: DRAM cell failures are physically correlated. When an error occurs in a memory cell, due to the diffusion effect of factors such as manufacturing defects, increased charge leakage, or physical damage, adjacent memory cells around that cell will also successively fail. If only the current single-bit error is corrected without preventative measures, over time, the continuous failure of surrounding cells will lead to double-bit or even multi-bit errors within the same data block. The SECDED mechanism can only detect double-bit errors but cannot correct them, ultimately causing system crashes.

[0026] Therefore, upon detecting a single-bit error, the FIX IP module immediately marks the DRAM address where the error occurred as an isolated address, indicating that the address and its surrounding area are at risk of continued damage, and the address area will no longer be used in subsequent accesses.

[0027] Next, the data migration operation is performed. The FIX IP module first determines the data block range corresponding to the isolated address. This data block range includes not only the address where the error occurred, but also the address region within a preset range around it, to fully cover the memory cells that may be affected by the damage trend. The size of the data block range is determined according to the physical architecture characteristics of the DRAM, and is usually divided into units of rows or pages.

[0028] After determining the data block range, the FIX IP module allocates storage space of the same size as the data block from its internally integrated SRAM. SRAM, as a reliable replacement storage medium, offers higher stability and faster access speeds. The module writes the ECC-corrected correct data into the allocated SRAM storage space, completing the safe transfer of data. This transfer operation protects useful data from loss due to continued DRAM cell damage and achieves early isolation of problematic areas, effectively preventing single-bit errors from evolving into uncorrectable multi-bit errors, thereby enhancing system stability and the robustness of the DRAM chips.

[0029] S300: Establish a repair mapping table in SRAM, record the mapping relationship between the isolated address and the SRAM storage address, and write the repair mapping table into non-volatile memory through the bus interface; Furthermore, the repair mapping table includes: The isolated address field records addresses in DRAM that are marked as isolated. The SRAM address field records the storage address of the corresponding data in SRAM. The valid flag field indicates whether the mapping relationship is valid.

[0030] Furthermore, the step of writing the repair mapping table into the non-volatile memory via the bus interface includes: transferring the repair mapping table from SRAM to the bus via the APB bus interface, and writing the repair mapping table into a preset storage area in the Flash memory.

[0031] Specifically, after the data migration is complete, the FIX IP module establishes a repair mapping table in SRAM to record and manage the mapping relationship between all isolated addresses and their corresponding storage locations in SRAM. This repair mapping table is organized using a structured data format, and each mapping record contains three key fields: The isolated address field records the original addresses in DRAM that are marked as isolated. This field stores complete physical address information, including address components such as Bank, Row, and Column, so that accurate matching can be achieved during subsequent accesses.

[0032] The SRAM address field records the actual storage address of the corresponding data in the SRAM. Since the data has been moved from DRAM to SRAM, this field specifies the internal SRAM address that should be used to access the data.

[0033] The valid flag field indicates whether the mapping relationship is valid. When the flag is valid, it means that the mapping relationship of the isolated address is currently effective, and the system should use the SRAM address for access; when the flag is invalid, it means that the mapping relationship has expired or been deleted.

[0034] After the repair mapping table is established, the FIX IP module needs to persistently store the table so that the repair information can be retained after a system power failure and restart. The module communicates with peripheral devices in the SOC through the APB bus interface. Specifically, the FIX IP module, as the master device of the APB bus, reads the data of the repair mapping table from SRAM and transmits it to the NorFlash non-volatile memory connected to the bus via the APB bus.

[0035] Upon receiving a write command, NorFlash stores the repair mapping table in a pre-allocated dedicated storage area. This area has a fixed starting address and size in the Flash address space and is specifically used to store DRAM repair-related configuration information. By writing the mapping table to NorFlash, the repair mapping relationship will not be lost even if the system loses power or undergoes a cold boot, ensuring the continued effectiveness of the dynamic repair mechanism.

[0036] S400: During system cold boot, the repair mapping table is read from non-volatile memory. In subsequent accesses, the repair mapping table is used to determine whether the address to be accessed is an isolated address. If it is, the data is obtained by accessing the memory address mapped in SRAM, and the isolated address in DRAM is no longer accessed.

[0037] Furthermore, the step of determining whether the address to be accessed is an isolated address includes: Receive the address to be accessed from the CPU; Search the repair mapping table for the isolated address field that matches the address to be accessed; If a matching isolated address is found and the corresponding valid flag is valid, then the address to be accessed is determined to be an isolated address.

[0038] Specifically, when a cold boot occurs, the FIX IP module actively accesses the NorFlash non-volatile memory via the APB bus interface during the initialization phase, reading the previously saved repair mapping table from a preset storage area. The read mapping table data is loaded into the SRAM inside the FIX IP module, restoring all marked isolated addresses and their corresponding SRAM storage address mappings. Through this recovery process, the system can immediately identify and avoid problematic areas in DRAM after boot, without having to go through the error detection and data relocation process again.

[0039] During normal system operation, whenever the CPU issues a new memory access request, the FIX IP module executes an address determination process. Specifically, the module first receives the address to be accessed from the CPU. This address is in logical address form, and after address translation, the corresponding DRAM physical address is obtained.

[0040] Next, the FIX IP module performs a lookup operation in the loaded repair mapping table. The module iterates through all records in the mapping table, comparing the address to be accessed with the isolation address field of each record. If an isolation address field that exactly matches the address to be accessed is found in the mapping table, the module further checks the corresponding valid flag bit. Only when the valid flag bit is valid is the address to be accessed confirmed as an isolated address.

[0041] Once the address to be accessed is determined to be an isolated address, the FIX IP module immediately extracts the corresponding SRAM address field from the mapping record and redirects the access request to the SRAM. The module directly accesses the mapped storage address in the SRAM, reads the previously moved and saved data, and returns the data to the CPU. Throughout the access process, the isolated address region in DRAM is not accessed, thus avoiding reading data from the damaged DRAM cell and completely isolating the problematic area.

[0042] If no record matching the address to be accessed is found in the mapping table, or if the valid flag of the found record is invalid, it means that the DRAM area corresponding to the address to be accessed is normally available. At this time, the FIX IP module sends a read command directly to the DRAM according to the normal procedure, retrieves the data from the address to be accessed in the DRAM, and returns it to the CPU.

[0043] Through the address judgment and access redirection mechanism described above, this invention achieves transparent isolation of problematic DRAM regions. The system automatically bypasses the damaged region during normal access, ensuring data integrity and preventing error propagation due to continuous access to damaged cells, thereby significantly improving system reliability and DRAM lifespan.

[0044] In summary, this embodiment achieves intelligent identification and dynamic repair of DRAM cell damage trends through the FIX IP module. When a single-bit error is detected, not only is immediate correction performed, but more importantly, the damage propagation trend in the surrounding area is predicted based on physical correlation, allowing for early isolation of the problematic area and data migration to SRAM. Through persistent storage of the repair mapping table and access redirection mechanisms, transparent isolation of the faulty area is achieved, effectively preventing single-bit errors from evolving into uncorrectable multi-bit errors, significantly improving system reliability and DRAM lifespan under long-term operating conditions.

[0045] Example 2: A cloud computing equipment manufacturer faced severe reliability challenges when developing its next-generation edge computing server product. This server needed to operate stably for extended periods in harsh environments such as unattended communication base stations and industrial control sites, with wide temperature fluctuations (-40℃ to 85℃) and infrequent on-site maintenance. While traditional LPDDR4 memory solutions were equipped with ECC SECDED error correction mechanisms, the failure rate of DRAM cells increased significantly under extreme temperature and long-term operating conditions. Actual testing showed that after six months of continuous operation, approximately 12% of the devices experienced system restarts due to double-bit memory errors, severely impacting the continuity of IoT data acquisition and edge computing tasks. Therefore, the manufacturer adopted a dynamic DRAM repair method based on cell damage trend identification, as described in this invention, in its new edge computing server.

[0046] In the third month of operation of an edge server deployed at an outdoor communication base station, the ambient temperature reached 68°C. The FIX IP module detected a single-bit error at a certain physical address. This address stored the temperature sensor data buffer reported by an IoT device. The solution of this invention immediately corrected the error and returned the correct data, ensuring the normal operation of the data processing flow. Simultaneously, based on the physical correlation of the DRAM cell damage, the FIX IP module marked the entire 8KB data block (containing 2048 consecutive addresses) containing the damaged address as an isolated region and moved all valid data within it to the on-chip SRAM. The repair mapping table was written to the onboard NorFlash via the APB bus for persistent storage.

[0047] Over the next three weeks of operation, eight addresses within the isolated region experienced memory errors, confirming the physical pattern of DRAM cell damage propagation. Because these addresses had been isolated beforehand, all access to that region was redirected to SRAM, and the system remained completely unaware of the ongoing deterioration at the underlying DRAM layer.

[0048] Comparative tests showed that servers in the same batch that did not adopt this invention's solution developed a double-bit error in the same area 16 days after the first single-bit error was detected. The ECC mechanism could only detect but not correct it, causing the industrial control data acquisition task to be interrupted and requiring on-site technical personnel to perform hardware repairs, with a single maintenance cost exceeding 8,000 yuan. Servers using this invention's solution, through proactive isolation three weeks in advance, successfully avoided the occurrence of double-bit errors, ensuring the continuous and stable operation of the system.

[0049] After deploying the solution of this invention on 50 edge servers, the manufacturer saw the device availability increase from 89.5% to 99.2% within a 6-month operating cycle, and the number of on-site maintenance due to memory errors decreased from an average of 2.3 times per unit to 0.1 times, significantly reducing operation and maintenance costs and improving the service quality of IoT infrastructure.

[0050] Finally, it should be noted that the above descriptions are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A DRAM dynamic repair method based on cell damage trend identification, characterized in that, The method comprises the following steps: S100: receiving a logical address request sent by a CPU, sending a read command to a DRAM, obtaining returned data and corresponding ECC check data, regenerating ECC check data according to the returned data, and comparing the regenerated ECC check data with the obtained ECC check data; S200: when the comparison result has a single-bit error, correcting the single-bit error according to the ECC check data, returning the corrected data, identifying a damage trend of a DRAM unit, marking a DRAM address where the single-bit error occurs as an isolated address, and moving data corresponding to the isolated address from the DRAM to an SRAM; S300: establishing a repair mapping table in the SRAM, recording a mapping relationship between the isolated address and an SRAM storage address, and writing the repair mapping table into a non-volatile memory through a bus interface; S400: reading the repair mapping table from the non-volatile memory when the system is cold started, and judging whether a to-be-accessed address is an isolated address according to the repair mapping table in subsequent access, if yes, accessing a mapped storage address in the SRAM to obtain data, and not accessing the isolated address in the DRAM.

2. The DRAM dynamic repair method based on cell damage trend identification according to claim 1, characterized in that, The step of regenerating the ECC check data and comparing the regenerated ECC check data with the obtained ECC check data comprises: regenerating the ECC check data according to a SECDED encoding mechanism; comparing the regenerated ECC check data with the obtained ECC check data to identify a single-bit error and an error position.

3. The DRAM dynamic repair method based on cell damage trend identification of claim 1, wherein, The step of identifying the damage trend of the DRAM unit comprises:

4. The DRAM dynamic repair method based on cell damage trend identification of claim 1, wherein, based on physical correlation of DRAM unit damage, when a DRAM unit where the single-bit error occurs is detected, it is predicted that storage units in a region around the isolated address have a trend of successively occurring errors, and addresses in a region within a preset range around the DRAM address are marked as isolated addresses. The step of moving data corresponding to the isolated address from the DRAM to the SRAM comprises: determining a data block range corresponding to the isolated address, the data block range comprising the address where the error occurs and addresses within a preset range around the address; allocating a storage space with a same size as the data block range from the SRAM; 5. The DRAM dynamic repair method based on cell damage trend identification of claim 1, wherein, writing the ECC-corrected data into the allocated SRAM storage space. The repair mapping table comprises: an isolated address field, recording addresses marked as isolated in the DRAM; an SRAM address field, recording storage addresses of corresponding data in the SRAM; 6. The DRAM dynamic repair method based on cell damage trend identification of claim 1, wherein, an effective flag field, indicating whether the mapping relationship is effective.

7. The DRAM dynamic repair method based on cell damage trend identification of claim 1, wherein, The step of writing the repair mapping table into the non-volatile memory through the bus interface comprises: transferring the repair mapping table from the SRAM to a bus through an APB bus interface, and writing the repair mapping table into a preset storage region in a Flash memory. The step of judging whether the to-be-accessed address is an isolated address comprises: receiving a to-be-accessed address sent by a CPU; finding a matching isolated address field in the repair mapping table; if the matching isolated address is found and a corresponding effective flag is effective, it is determined that the to-be-accessed address is an isolated address.

Images