Test structure, mismatch qualification method for static random access memory cells

Abstract

The application provides a test structure and a mismatch identification method of a static random access memory cell. The test structure comprises: a static random access memory cell comprising a first transfer transistor and a second transfer transistor; a measurement unit comprising a first measurement transistor connected to a first bit line and a second measurement transistor connected to a second bit line; wherein the first measurement transistor is used as a resistor when the first storage node is at a high level and the second storage node is at a low level to measure a first target current; the second measurement transistor is used as a resistor when the first storage node is at a low level and the second storage node is at a high level to measure a second target current; and the static random access memory cell is identified as having a mismatch when the first target current and the second target current are inconsistent. In this way, the mismatch identification of the static random access memory cell can be realized with less area occupation.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of semiconductor memory, and in particular, to a test structure and a mismatch identification method for a static random access memory cell. BACKGROUND

[0002] At present, in very large scale integrated circuit (VLSI) design, static random access memory (SRAM) is widely used due to its high-speed read-write performance and easy integration characteristics. Due to the influence of process deviation and other factors in the manufacturing process, the transistors used in the SRAM memory cell may have a parameter mismatch phenomenon, such as threshold voltage mismatch, which causes the data of the memory cell to be unable to be normally read and written, thereby affecting the reliability and function of the overall circuit.

[0003] In order to solve this problem, a specific test structure (testkey) is usually designed in the related art, and a wafer level reliability test (WAT test) is performed to detect whether the transistors in the SRAM memory cell have a mismatch.

[0004] However, the existing test structure occupies a large area in chip design, which limits the layout and placement of other important structures. SUMMARY

[0005] Therefore, embodiments of the present application are dedicated to providing a test structure and a mismatch identification method for a static random access memory cell, which can identify the mismatch of the static random access memory cell while occupying a small area.

[0006] An embodiment of the present application provides a test structure, comprising: a static random access memory cell comprising a first transmission transistor and a second transmission transistor; wherein the first transmission transistor is connected to a first storage node and a first bit line respectively; the second transmission transistor is connected to a second storage node which is logically complementary to the first storage node and a second bit line which is inverted to the first bit line respectively; a measurement unit comprising a first measurement transistor connected to the first bit line and a second measurement transistor connected to the second bit line; wherein the first measurement transistor is used as a resistor to measure a first target current when the first storage node is at a high level and the second storage node is at a low level; the second measurement transistor is used as a resistor to measure a second target current when the first storage node is at a low level and the second storage node is at a high level; wherein the static random access memory cell is identified as having a mismatch when the first target current and the second target current are inconsistent.

[0007] Optionally, the first and second measurement transistors are N-type MOS transistors; in the case that the first storage node is at a low level, the channel of the first measurement transistor is controlled to be turned on, and the channel of the second measurement transistor is in a closed state; wherein the gate of the second measurement transistor is connected as a resistor between the second bit line and the ground line; or, in the case that the second storage node is at a low level, the channel of the first measurement transistor is in a closed state, and the channel of the second measurement transistor is controlled to be turned on; wherein the gate of the first measurement transistor is connected as a resistor between the first bit line and the ground line.

[0008] Optionally, the gates of the first and second measurement transistors are made of polysilicon, so as to be used as a polysilicon resistor when the channel of the first or second measurement transistor is in a closed state.

[0009] Optionally, the first and second measurement transistors are symmetrically arranged; the polysilicon resistor comprises a main body portion and an extension portion extending outward from both ends of the main body portion; wherein the main body portion and the extension portion have different extension directions, respectively.

[0010] Optionally, a first metal contact for applying a gate control voltage is arranged on the main body portion; a second metal contact and a third metal contact are arranged on the extension portions at both ends of the main body portion, respectively; wherein the second metal contact is used for connecting the first bit line or the second bit line, and the third metal contact is used for connecting the ground line.

[0011] Another embodiment of the present application provides a mismatch identification method for a static random access memory unit, which uses the test structure as described above to identify the mismatch, and the method comprises: in the case that the first storage node is at a high level and the second storage node is at a low level, controlling the first transfer transistor, the second transfer transistor and the second measurement transistor to be turned on, and using the first measurement transistor in a closed state as a resistor to form a conduction path between the first bit line and the ground line; after the first and second transfer transistors are closed, a first target current flowing through the first measurement transistor is measured; or, in the case that the first storage node is at a low level and the second storage node is at a high level, controlling the first transfer transistor, the second transfer transistor and the first measurement transistor to be turned on, and using the second measurement transistor in a closed state as a resistor to form a conduction path between the second bit line and the ground line; after the first and second transfer transistors are closed, a second target current flowing through the second measurement transistor is measured; wherein, in the case that the first target current and the second target current are inconsistent, it is identified that the static random access memory unit has a mismatch.

[0012] Optionally, the static random access memory unit comprises a first inverter corresponding to the first storage node and a second inverter corresponding to the second storage node; in the case that the first target current is inconsistent with the second target current, it is determined that there is a mismatch between the pull-down transistor in the first inverter and the pull-down transistor in the second inverter.

[0013] Optionally, control ends of the first transmission transistor and the second transmission transistor are connected to a word line, so as to control the turn-on and turn-off of the first transmission transistor and the second transmission transistor through the word line.

[0014] Optionally, the first measurement transistor and the second measurement transistor are N-type MOS transistors; in the case that the first storage node is at a high level and the second storage node is at a low level, the first transmission transistor, the second transmission transistor and the second measurement transistor are controlled to be turned on, and the first measurement transistor in the off state is used as a resistance; in the step of forming a turn-on path between the first bit line and the ground line, the gate of the first measurement transistor in the off state is connected to the first bit line and the ground line respectively, so that the gate of the first measurement transistor in the off state is used as a resistance between the first bit line and the ground line; in the case that the first storage node is at a low level and the second storage node is at a high level, the first transmission transistor, the second transmission transistor and the first measurement transistor are controlled to be turned on, and the second measurement transistor in the off state is used as a resistance; in the step of forming a turn-on path between the second bit line and the ground line, the gate of the second measurement transistor in the off state is connected to the second bit line and the ground line respectively, so that the gate of the second measurement transistor in the off state is used as a resistance between the second bit line and the ground line.

[0015] Optionally, the static random access memory unit has a specified timing specification and a standard target current determined according to the specified timing specification; the method further comprises: in the case that the first target current is inconsistent with the standard target current, it is determined that the pull-down transistor in the second inverter does not match the specified timing specification; or, in the case that the second target current is inconsistent with the standard target current, it is determined that the pull-down transistor in the first inverter does not match the specified timing specification.

[0016] The unexpected effect of the plurality of embodiments provided in the application is that the first measurement transistor connected with the first bit line and the second measurement transistor connected with the second bit line are used as the measurement unit, so that in the case that the first storage node is high and the second storage node is low, i.e. reading logic "1", the first measurement transistor can be used as a resistor to measure the first target current, and in the case that the first storage node is low and the second storage node is high, i.e. reading logic "0", the second measurement transistor can be used as a resistor to measure the second target current, so that in the case that the first target current and the second target current are inconsistent, it can be determined that the static random access memory unit has a mismatch. In this way, the first measurement transistor and the second measurement transistor are multiplexed as resistors when reading different logic bits, and whether the static random access memory unit has a mismatch is determined by comparing the current flowing through, which improves the utilization rate of the first measurement transistor and the second measurement transistor, and thus less area occupation can be achieved. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 The layout schematic diagram of the test structure provided for an embodiment of the application.

[0018] Figure 2 The equivalent circuit diagram of the test structure provided for an embodiment of the application.

[0019] Figure 3 The timing specification comparison schematic diagram of the SRAM read operation provided for an embodiment of the application.

[0020] REFERENCE SIGNS:

[0021] 10, test structure; 11, static random access memory unit; 111, first inverter; 112, second inverter; 12, measurement unit; 121, main body part; 1211, first metal contact; 1212, second metal contact; 1213, third metal contact; 122, epitaxial part; Q1, first storage node; Q2, second storage node; BL, first bit line; BL / , second bit line; WL, word line; PG1, first transfer transistor; PG2, second transfer transistor; M1, first measurement transistor; M2, second measurement transistor; I R1 , first target current; I R2 , second target current. DETAILED DESCRIPTION

[0022] The technical solutions in the embodiments of the application will be clearly and completely described below with reference to the drawings in the embodiments of the application. Obviously, the described embodiments are only a part of the embodiments of the application, not all the embodiments of the application.

[0023] In this application, the accompanying drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly show the details of the local features.

[0024] Unless otherwise stated, all technical and scientific terms used in this application have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The term "and / or" as used in this application includes any and all combinations of one or more of the associated listed items. The singular forms "a," "the," and "the" as used in embodiments of this application are also intended to include the plural forms unless the context clearly indicates otherwise.

[0025] In the description of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, features defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0026] In the description of this application, the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "height", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the purpose of simplifying the description of this application and do not indicate that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. In other words, they should not be construed as limitations on this application.

[0027] In the description of this application, unless otherwise expressly defined, the terms "installation," "connection," "linking," "fixing," "setting," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can also refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0028] A testkey is a critical structure in integrated circuit manufacturing used for process monitoring and device performance evaluation. It typically includes basic components such as resistors, capacitors, and transistors, and their combinations, used for process development, production monitoring, device characteristic analysis, and reliability verification. To meet diverse testing requirements and measurement accuracies, testkeys usually occupy a significant area on wafer dicing slots or dedicated test chips, sometimes exceeding 30% of the chip's functional area. For example, a complete testkey set may contain over 500 different types, covering verification needs for multiple modules, including logic, memory, and analog.

[0029] In related technologies, in order to monitor and identify the mismatch phenomenon of transistors in SRAM, it is usually necessary to design separate test structures for pull-down transistors (PD), pull-up transistors (PU), transfer transistors (PG) in SRAM, as well as for the overall characteristics of SRAM. The reusability of components in these test structures is low, resulting in a large area required and affecting the placement of other important test structures.

[0030] Therefore, it is necessary to provide a test structure that can determine whether there is a mismatch in the transistors in SRAM while occupying a small area.

[0031] Please see Figure 1 and Figure 2 One embodiment of this application provides a test structure. Specifically, refer to... Figure 1 The test structure 10 may include a static random access memory (SRAM) unit 11 and a measurement unit 12. The test structure 10 can be used to monitor whether there is a mismatch in the SRAM unit 11. Figure 1 In this context, Bulk represents the body potential; Figure 1 In this context, NW represents an N-type well; Figure 1 In this context, PW represents a P-type well; Figure 1 In this context, N+ represents the N-type heavily doped region; Figure 1 In this context, "Poly" represents a polycrystalline silicon layer. Figure 1 In this context, AA represents the active region; Figure 1 In this context, CT represents a contact hole; Figure 1 In this context, "Metal" represents a metal layer. Figure 1 In this context, Pin1 represents pin 1; Figure 1 In this context, Pin2 represents pin 2; Figure 1 In this context, Pin3 represents pin 3; Figure 1 In this context, Pin4 represents pin 4.

[0032] Static Random Access Memory (SRAM) cells are high-speed storage cells implemented based on bistable circuits. When powered on, they can provide temporary data cache for the processor with near-zero latency read and write speeds and are widely used in CPU caches, register files, and embedded systems.

[0033] In this embodiment, the static random access memory (SRAM) cell 11 can be composed of six metal-oxide-semiconductor field-effect transistors (MOSFETs), i.e., a 6T-SRAM cell. Specifically, the SRAM cell 11 may include two transfer transistors and two cross-coupled inverters. The two cross-coupled inverters can be composed of pull-down transistors and pull-up transistors, respectively, forming a stable memory node. In the SRAM cell 11, the two transfer transistors are used to control the connection between different memory nodes and their corresponding bit lines (BL or BL / ), and trigger data read / write operations through word line (WL) signals.

[0034] Specifically, refer to Figure 2 The static random access memory (SRAM) cell 11 is composed of a first transfer transistor PG1, a second transfer transistor PG2, a first pull-down transistor PD1, a second pull-down transistor PD2, a first pull-up transistor PU1, and a second pull-up transistor PU2. PD1 and PU1 form a first inverter 111, forming a first memory node Q1. PD2 and PU2 form a second inverter 112, forming a second memory node Q2 that is logically complementary to the first memory node Q1. The control terminal of PG1 is connected to the word line WL, and its source and drain terminals are connected to the first bit line BL and the first memory node Q1, respectively. The control terminal of PG2 is connected to the word line WL, and its source and drain terminals are connected to the second bit line BL and the second memory node Q2, respectively. Figure 2 VDD in the text represents the power supply voltage; Figure 2 In this context, GND represents the ground terminal.

[0035] In some embodiments, the read operation of the static random access memory cell 11 can be implemented by activating the word line WL. Specifically, during the read operation, a high-level signal is applied to the word line WL, thereby activating the first transfer transistor PG1 and the second transfer transistor PG2, turning them on. At this time, the first transfer transistor PG1 connects the first bit line BL to the first memory node Q1, and the second transfer transistor PG2 connects the second bit line BL / to the second memory node Q2. Since the first memory node Q1 and the second memory node Q2 are logically complementary, when Q1 is high (logic 1), Q2 is low (logic 0), and vice versa. During the read process, the bit lines BL and BL / are typically pre-charged to a high level (e.g., VDD). When the transfer transistors PG1 and PG2 are on, the potential of the first memory node Q1 is transferred to the first bit line BL through PG1, and the potential of the second memory node Q2 is transferred to the second bit line BL / through PG2. Since Q1 and Q2 are complementary, when Q1 is high, the potential of BL remains high, while the potential of BL / is pulled down. Conversely, when Q1 is low, the potential of BL is pulled down, while the potential of BL / remains high. When the potential of BL or BL / drops to a certain voltage difference ΔV, it can be detected, amplified, and output with read data consistent with the complementary states of Q1 and Q2.

[0036] In this embodiment, the measurement unit 12 can be disposed on the periphery of the static random access memory (SRAM) unit 11 and is used to test the transistors in the SRAM unit 11. Specifically, the measurement unit 12 may include a first measurement transistor M1 and a second measurement transistor M2. The first measurement transistor M1 and the second measurement transistor M2 can be electrically connected to the SRAM unit 11 via a metal interconnect.

[0037] Optionally, the first measuring transistor M1 and the second measuring transistor M2 can be N-type MOS transistors.

[0038] In this embodiment, the first measurement transistor M1 can be connected between the first measurement line BL and the ground line, and the second measurement transistor M2 can be connected between the first measurement line BL / and the ground line. Specifically, taking an N-type MOS transistor as an example, the drains of M1 and M2 are connected to BL and BL / respectively, and their sources are grounded respectively.

[0039] In this embodiment, when the static random access memory unit 11 performs a read logic 1 operation, Q1 is at a high level and Q2 is at a low level. By controlling M2 to turn on, M1 is used as a resistor, and the first target current I flowing through M1 can be measured after WL is turned off. R1 I can understand. R1=(VDD-ΔV) / R1, where R1 is the equivalent resistance of M1 when it is used as a resistor. When the static random access memory unit 11 performs a read logic 0 operation, Q1 is low and Q2 is high. By controlling M1 to open and M2 to be used as a resistor, the second target current I flowing through M2 can be measured after WL is closed. R2 It can be understood that IR2 = (VDD - ΔV) / R2, where R2 is the equivalent resistance of M2 when it is used as a resistor.

[0040] In this embodiment, by comparing the first target current I R1 With the second target current I R2 The size of I can be used to determine whether there is a mismatch between pull-down transistors PD1 and PD2 in static random access memory cell 11. Specifically, if I R1 with I R2 The inconsistency indicates a mismatch between PD1 and PD2, resulting in a mismatch in the bit line discharge process of static random access memory cell 11 when reading logic 0 and logic 1. In other words, it can be concluded that static random access memory cell 11 is mismatched.

[0041] In this embodiment, an unexpected effect is that by using the first measurement transistor M1 connected to the first bit line BL and the second measurement transistor M2 connected to the second bit line BL / as measurement unit 12, when the first storage node Q1 is high and the second storage node Q2 is low (i.e., when reading logic 1), the first measurement transistor M1 can be used as a resistor to measure the first target current I. R1 Simultaneously, when the first storage node Q1 is low and the second storage node Q2 is high (i.e., when the read logic is 0), the second measurement transistor PG2 can be used as a resistor to measure the second target current I. R2 Thus, it is possible to achieve the first target current I R1 With the second target current I R2 In cases of inconsistency, a mismatch is identified in the static random access memory (SRAM) cell 11. Thus, when reading different logic bits, the first measurement transistor PG1 and the second measurement transistor PG2 are reused as resistors, and the mismatch in the SRAM cell 11 is determined by comparing the current flowing through them. This improves the utilization rate of the first measurement transistor PG1 and the second measurement transistor PG2, thereby achieving a smaller area footprint.

[0042] Furthermore, this embodiment can also integrate the test structure of the pull-down transistor in SRAM with the SRAM test structure. Specifically, the test structure 10 provided in this embodiment can be used to monitor whether there is a mismatch in the pull-down transistor in SRAM. At the same time, since the operation of reading logic 0 and logic 1 needs to be performed separately during the use of test structure 10, it can also be reused as part of the SRAM test structure, saving the overall test structure area.

[0043] In some embodiments, when the first storage node is low, the channel of the first measurement transistor is controlled to be turned on, and the channel of the second measurement transistor is turned off. The gate of the second measurement transistor is connected as a resistor between the first bit line and ground. Alternatively, when the second storage node is low, the channel of the first measurement transistor is turned off, and the channel of the second measurement transistor is controlled to be turned on. The gate of the second measurement transistor is connected as a resistor between the second bit line and ground.

[0044] In some embodiments, M1 and M2 can be N-type MOS transistors. When the static random access memory cell 11 performs a read logic 1 operation, Q1 is high and Q2 is low. M2 can be turned on by applying a gate control voltage, while M1 can be turned off without applying a gate control voltage. At this time, the gate terminals of M1 can be connected to BL and ground respectively to apply a potential difference to the gate of M1 and form a current conduction path, thus enabling M1 to be used as a resistor. Similarly, when the static random access memory cell 11 performs a read logic 0 operation, Q1 is low and Q2 is high. M2 can be turned on by applying a gate control voltage, while M1 can be turned off without applying a gate control voltage. At this time, the gate terminals of M1 can be connected to BL and ground respectively to apply a potential difference to the gate of M1 and form a current conduction path, thus enabling M1 to be used as a resistor.

[0045] In some embodiments, the gates of the first and second measurement transistors are made of polysilicon to function as polysilicon resistors when the channel of either the first or second measurement transistor is in the off state. Polysilicon resistors provide precise resistance adjustment and current limiting capabilities in semiconductor devices, while operating stably in high-temperature, high-integration environments. The resistance value of a polysilicon resistor can be precisely controlled by adjusting the doping concentration and size of the polysilicon, thereby meeting the needs of different circuit designs. For example, in test structure 10, the polysilicon resistor can be used as part of the testkey. Simultaneously, its compact design saves chip area and avoids impacting the layout of other important test structures 10.

[0046] In some embodiments, the first and second measurement transistors are symmetrically arranged. By employing a symmetrical arrangement of the first and second measurement transistors, the electrical characteristics of each transistor in the test circuit can be more balanced, thereby improving the performance and reliability of the test structure 10. Furthermore, in the test structure 10, the symmetrically arranged transistors can effectively reduce test noise and improve detection sensitivity, thus more accurately identifying mismatch problems in the static random access memory cell 11. In addition, the symmetrical arrangement can also optimize the area utilization of the test structure 10.

[0047] In some embodiments, the polysilicon resistor includes a main body portion and epitaxial portions extending outward from both ends of the main body portion. The main body portion and the epitaxial portions have different extending directions.

[0048] In some embodiments, the polysilicon gate of the first measuring transistor M1 or the second measuring transistor M2 may include a body portion 121 and an epitaxial portion 122. Specifically, as shown... Figure 1 As shown, the main body portion 121 and the epitaxial portion 122 of the polysilicon gate have different extension directions. For example, the main body portion 121 has a first extension direction and the epitaxial portion 122 has a second extension direction, wherein the first extension direction and the second extension direction are at an angle, such as 90 degrees.

[0049] The segmented design of the main body 121 and the epitaxial portion 122 optimizes the resistance distribution of the polysilicon resistors. Furthermore, the corner design formed by the main body 121 and the epitaxial portion 122 allows for higher resistance values ​​to be achieved with less area, thus improving the flexibility of device layout in the test structure 10.

[0050] In some embodiments, a first metal contact 1211 for applying a gate control voltage is provided on the main body 121; a second metal contact 1212 and a third metal contact 1213 are respectively provided on the extension portions 122 at both ends of the main body 121; wherein, the second metal contact 1212 is used to connect to the first bit line or the second bit line, and the third metal contact 1213 is used to connect to the ground line.

[0051] When used as a resistor, a current conduction path can be established through the second metal contact 1212 and the third metal contact 1213. By placing the second metal contact 1212 and the third metal contact 1213 on the extension portion 122, the length of the current flow path can be increased, the current density can be reduced, thereby reducing power loss and heat generation. This helps to improve the overall efficiency and reliability of the test structure 10.

[0052] Another embodiment of this application provides a mismatch identification method for static random access memory (SRAM) cells. The mismatch identification method utilizes the aforementioned test structure to identify mismatches in the transistors within the SRAM cells. The mismatch identification method may include steps S110-S120 or S210-S220.

[0053] S110: When the first storage node is high and the second storage node is low, control the first transmission transistor, the second transmission transistor and the second measurement transistor to turn on, and use the first measurement transistor in the off state as a resistor to form a conduction path between the first bit line and the ground line.

[0054] S120: After turning off the first transmission transistor and the second transmission transistor, the first target current flowing through the first measurement transistor is measured.

[0055] S210: When the first storage node is low and the second storage node is high, control the first transmission transistor, the second transmission transistor and the first measurement transistor to turn on, and use the second measurement transistor in the off state as a resistor to form a conduction path between the second bit line and the ground line.

[0056] S220: After turning off the first transmission transistor and the second transmission transistor, a second target current flowing through the second measurement transistor is measured; wherein, if the first target current and the second target current are inconsistent, it is determined that the static random access memory cell has a mismatch.

[0057] The principles and functions of each step in the method for identifying mismatches in static random access memory (SRAM) cells can be explained with reference to the aforementioned embodiments, and will not be repeated here.

[0058] In this embodiment, an unexpected effect is that by using the first measurement transistor connected to the first bit line and the second measurement transistor connected to the second bit line as measurement units, when the first storage node is high and the second storage node is low (i.e., reading logic 1), the first measurement transistor can be used as a resistor to measure the first target current. Conversely, when the first storage node is low and the second storage node is high (i.e., reading logic 0), the second measurement transistor can be used as a resistor to measure the second target current. This allows for the identification of a mismatch in the static random access memory (SRAM) cell when the first and second target currents are inconsistent. Thus, by multiplexing the first and second measurement transistors as resistors when reading different logic bits, and comparing the currents flowing through them to determine if a mismatch exists in the SRAM cell, the utilization rate of the first and second measurement transistors is improved, resulting in a smaller area footprint.

[0059] In some embodiments, the static random access memory unit includes a first inverter corresponding to a first memory node and a second inverter corresponding to a second memory node; if the first target current and the second target current are inconsistent, it is determined that there is a mismatch between the pull-down transistor in the first inverter and the pull-down transistor in the second inverter.

[0060] In some embodiments, the control terminals of the first and second transmission transistors are connected to word lines to control the on and off states of the first and second transmission transistors via word lines.

[0061] In some embodiments, the first and second measurement transistors are N-type MOS transistors; the step of controlling the first transmission transistor, the second transmission transistor, and the second measurement transistor to conduct when the first storage node is high and the second storage node is low, and using the first measurement transistor in the off state as a resistor to form a conduction path between the first bit line and the ground line includes: connecting the gate terminals of the first measurement transistor to the first bit line and the ground line respectively, so that the gate of the first measurement transistor in the off state acts as a resistor between the first bit line and the ground line; the step of controlling the first transmission transistor, the second transmission transistor, and the first measurement transistor to conduct when the first storage node is low and the second storage node is high, and using the second measurement transistor in the off state as a resistor to form a conduction path between the second bit line and the ground line includes: connecting the gate terminals of the second measurement transistor to the second bit line and the ground line respectively, so that the gate of the second measurement transistor in the off state acts as a resistor between the second bit line and the ground line.

[0062] The principles and functions of each step in the above embodiments can be explained with reference to the corresponding embodiments mentioned above, and will not be repeated here.

[0063] Please see Figures 1 to 3 Tables 1 and 2. In some embodiments, the static random access memory cell has a specified timing specification and a standard target current determined according to the specified timing specification; the method further includes: if the first target current is inconsistent with the standard target current, determining that the pull-down transistor in the second inverter does not match the specified timing specification; or, if the second target current is inconsistent with the standard target current, determining that the pull-down transistor in the first inverter does not match the specified timing specification.

[0064] A timing specification is a set of timing parameters and requirements that an SRAM must meet during operation to ensure that the SRAM functions correctly and meets performance metrics. In some embodiments, specifying the timing specification can be defined as the time interval Δt1 required to reliably detect the potential difference ΔV between the first bit line BL and the second bit line BL / during an SRAM read operation. It can be understood that during an SRAM read operation, under normal circumstances, the potential of BL or BL / after Δt1 is VDD-ΔV. Therefore, the standard target current I measured under normal conditions using the first and second measurement transistors as resistance measurements can be determined. normal The value is (VDD-ΔV) / R1 or (VDD-ΔV) / R2. If the first target current I is measured at this time... R1 Or the second target current I R2 With standard target current I normal If there is an inconsistency, it indicates that PD1 or PD2 does not match the specified timing specification.

[0065] Specifically, by setting the potential connected to the test structure according to Table 1 and executing the mismatch identification method for static random access memory cells, the measured first target current I can be obtained. R1 Second target current I R2 If I at this time R1 Or I R2 Not equal to I normal This indicates that the corresponding pull-down transistor does not match the specified timing specification. Specifically, for example... Figure 3 As shown in Table 2, if I R1 Or I R2 Less than I normal This indicates that the time interval Δt2 required for PD1 or PD2 to generate a potential difference ΔV is less than Δt1, meaning the potential difference ΔV is detected too quickly. If I R1 Or I R2 Greater than Inormal This indicates that the time interval Δt3 required for PD1 or PD2 to generate a potential difference ΔV is greater than Δt1, meaning the detection of the potential difference ΔV is too slow. Figure 3 In this context, Target indicates that the detected potential difference ΔV meets the specified timing specification; Figure 3 In this context, "Fast" indicates that the potential difference ΔV is detected too quickly. Figure 3 The "Slow" in the text indicates that the potential difference ΔV was detected too slowly.

[0066] Table 1

[0067]

[0068] Table 2

[0069]

[0070] It is understood that the specific examples in this document are only intended to help those skilled in the art better understand the embodiments of this application, and are not intended to limit the scope of the invention.

[0071] It is understood that in the various embodiments of this application, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0072] It is understood that the various embodiments described in this application can be implemented individually or in combination, and the embodiments of this application are not limited in this respect.

[0073] It is understood that in the description of this application, when describing the structure of a component, when referring to a layer or region as being "above" or "on top of" another layer or region, it may mean that it is directly above another layer or region, or that it contains other layers or regions between itself and another layer or region. Furthermore, if the component is flipped, the layer or region will be located "below" or "under" another layer or region.

[0074] The above description is merely a specific embodiment of this application, but the protection scope of this invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the protection scope of this application.

Claims

1. A test structure, characterized by, The test structure comprises: a static random access memory unit comprising a first transfer transistor and a second transfer transistor; wherein the first transfer transistor is connected to a first storage node and a first bit line respectively; and the second transfer transistor is connected to a second storage node which is logically complementary to the first storage node and a second bit line which is inversely connected to the first bit line; a measurement unit comprising a first measurement transistor connected to the first bit line and a second measurement transistor connected to the second bit line; wherein the first measurement transistor is used as a resistor when the first storage node is at a high level and the second storage node is at a low level, to measure a first target current; and the second measurement transistor is used as a resistor when the first storage node is at a low level and the second storage node is at a high level, to measure a second target current; wherein the static random access memory unit is identified as having a mismatch when the first target current is inconsistent with the second target current.

2. The test structure of claim 1, wherein, The first measurement transistor and the second measurement transistor are N-type MOS transistors; when the first storage node is at a low level, the channel of the first measurement transistor is controlled to be turned on, and the channel of the second measurement transistor is in a closed state; wherein the gate of the second measurement transistor is connected as a resistor between the second bit line and the ground line; or, when the second storage node is at a low level, the channel of the first measurement transistor is in a closed state, and the channel of the second measurement transistor is controlled to be turned on; wherein the gate of the first measurement transistor is connected as a resistor between the first bit line and the ground line.

3. The test structure of claim 2, wherein, The gates of the first measurement transistor and the second measurement transistor are made of polysilicon, to be used as a polysilicon resistor when the channel of the first measurement transistor or the second measurement transistor is in a closed state.

4. The test structure of claim 3, wherein, The first measurement transistor and the second measurement transistor are symmetrically arranged; and the polysilicon resistor comprises a main body portion and an extension portion extending outward from both ends of the main body portion; wherein the main body portion and the extension portion have different extension directions respectively.

5. The test structure of claim 4, wherein, A first metal contact for applying a gate control voltage is arranged on the main body portion; a second metal contact and a third metal contact are arranged on the extension portions at both ends of the main body portion respectively; wherein the second metal contact is used to connect the first bit line or the second bit line, and the third metal contact is used to connect the ground line.

6. A method of mismatch qualification of a static random access memory cell, the method comprising: A method for mismatch identification using the test structure of claim 1, the method comprising: when the first storage node is at a high level and the second storage node is at a low level, controlling the first transfer transistor, the second transfer transistor and the second measurement transistor to be turned on, and using the first measurement transistor in a closed state as a resistor to form a conduction path between the first bit line and the ground line; after turning off the first transfer transistor and the second transfer transistor, measuring a first target current flowing through the first measurement transistor; or, In the case that the first storage node is at low level and the second storage node is at high level, the first transfer transistor, the second transfer transistor and the first measurement transistor are controlled to be turned on, and the second measurement transistor in the off state is used as a resistor to form a conduction path between the second bit line and the ground line; After the first transfer transistor and the second transfer transistor are turned off, the second target current flowing through the second measurement transistor is measured; and in the case that the first target current is inconsistent with the second target current, it is determined that the static random access memory unit has a mismatch.

7. The method of claim 6, wherein, The static random access memory unit comprises a first inverter corresponding to the first storage node and a second inverter corresponding to the second storage node. In the case that the first target current is inconsistent with the second target current, it is determined that the pull-down transistor in the first inverter and the pull-down transistor in the second inverter have a mismatch.

8. The method of claim 6, wherein, The control ends of the first transfer transistor and the second transfer transistor are connected to the word line, so as to control the turn-on and turn-off of the first transfer transistor and the second transfer transistor through the word line.

9. The method of claim 8, wherein, The first measurement transistor and the second measurement transistor are N-type MOS transistors. In the case that the first storage node is at high level and the second storage node is at low level, the first transfer transistor, the second transfer transistor and the second measurement transistor are controlled to be turned on, and the first measurement transistor in the off state is used as a resistor to form a conduction path between the first bit line and the ground line, comprising: The gate of the first measurement transistor is connected to the first bit line and the ground line respectively, so that the gate of the first measurement transistor in the off state is used as a resistor between the first bit line and the ground line. In the case that the first storage node is at low level and the second storage node is at high level, the first transfer transistor, the second transfer transistor and the first measurement transistor are controlled to be turned on, and the second measurement transistor in the off state is used as a resistor to form a conduction path between the second bit line and the ground line, comprising: The gate of the second measurement transistor is connected to the second bit line and the ground line respectively, so that the gate of the second measurement transistor in the off state is used as a resistor between the second bit line and the ground line.

10. The method of claim 7, wherein, The static random access memory unit has a specified timing specification and a standard target current determined according to the specified timing specification; the method further comprises: In the case that the first target current is inconsistent with the standard target current, it is determined that the pull-down transistor in the second inverter does not match the specified timing specification; Or, in the case that the second target current is inconsistent with the standard target current, it is determined that the pull-down transistor in the first inverter does not match the specified timing specification.

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