A soft start circuit for reducing inrush current

Abstract

The application belongs to the field of electronic circuits and provides a soft start circuit for reducing inrush current. The circuit comprises a first soft start module, a second soft start module and an operational amplifier module, and the operational amplifier module is connected with the first soft start module, the second soft start module and the input end of an analog integrated circuit respectively. In the soft start process, the two target voltages are respectively raised to a first reference voltage and a second reference voltage at different rates within the same time through code value control, and then when the first reference voltage and the second reference voltage change, the operational amplifier module is prevented from misjudging the change direction of the input voltage of the analog integrated circuit, the input voltage of the analog integrated circuit is prevented from generating a large overshoot or undershoot due to misjudgment, and the stability of the analog integrated circuit is improved. Based on the different rising rates of the two target voltages, the operational amplifier module automatically judges whether the input voltage of the analog integrated circuit slowly rises to positive voltage or slowly falls to negative voltage, so as to reduce the inrush current.

Description

Technical Field

[0001] This application belongs to the field of electronic circuit technology, and in particular relates to a soft-start circuit for reducing surge current. Background Technology

[0002] In many high-performance analog integrated circuits, such as high-voltage operational amplifiers, source drivers for LCD (Liquid Crystal Display) panels, and motor drive circuits, the input stage needs to process signals that exceed the range of conventional power supply voltages. To achieve this, a circuit structure called a "rail-to-rail input stage" is commonly used. This structure typically consists of a pair of PMOS (P-channel Metal-Oxide-Semiconductor Field-Effect Transistors) input differential pairs and a pair of NMOS (N-channel Metal-Oxide-Semiconductor Field-Effect Transistors) input differential pairs connected in parallel, responsible for processing input signals close to the positive and negative power supply voltages, respectively.

[0003] However, this classic parallel input stage structure has an inherent flaw: during the transient process of chip power-on or wake-up from shutdown mode, the failure of internal node potentials to establish synchronously can lead to a huge transient inrush current (i.e., surge current), which can cause the circuit to fail to start normally or be permanently damaged. To prevent surge current, a soft-start circuit is usually added before the input stage structure. Existing technologies include digital counter-controlled soft-start: this technology uses a clock-driven counter, and the output value of the counter generates a stepped or successively approximating ramp voltage through a digital-to-analog converter, which serves as the input stage of the next stage circuit. Since this circuit requires modules such as a clock generator, counter, and digital-to-analog converter, it significantly increases the complexity, power consumption, and area of ​​the circuit. Existing technologies also include piecewise linear or step-wise soft-start: this technology first charges the output capacitor to a certain level with a lower current, and then switches to the normal closed-loop control mode. However, at the moment of switching between different stages, the sudden change in loop parameters may cause voltage / current glitches or loop instability. Summary of the Invention

[0004] This application provides a soft-start circuit that reduces inrush current, which can solve the problems of high circuit complexity, high power consumption, large area and poor stability in the prior art.

[0005] In a first aspect, embodiments of this application provide a soft-start circuit for reducing inrush current, including a first soft-start module, a second soft-start module, and an operational amplifier module, wherein the operational amplifier module is connected to the input terminals of the first soft-start module, the second soft-start module, and an analog integrated circuit, respectively.

[0006] The first soft-start module is used to output a first target voltage that rises at a first rate according to a first reference voltage and a first preset code value, and rises to the first reference voltage within a preset time; the second soft-start module is used to output a second target voltage that rises at a second rate according to a second reference voltage and a second preset code value, and rises to the second reference voltage within a preset time; the operational amplifier module is used to determine the direction of change of the input voltage of the analog integrated circuit according to the first target voltage and the second target voltage; wherein, the first preset code value corresponds to the second reference voltage, and the second preset code value corresponds to the first reference voltage.

[0007] In one possible implementation of the first aspect, the operational amplifier module includes a first operational amplifier, a second operational amplifier, a first resistor, and a second resistor. The first input terminal of the first operational amplifier is connected to the first soft-start module, the first input terminal of the second operational amplifier is connected to the second soft-start module, the second input terminal of the first operational amplifier is connected to the first terminal of the first resistor and the first terminal of the second resistor, the second terminal of the second resistor is connected to the output terminal of the first operational amplifier and the input terminal of the analog integrated circuit, and the first terminal of the first resistor is connected to the output terminal of the second operational amplifier and the second input terminal of the second operational amplifier.

[0008] In one possible implementation of the first aspect, the first soft-start module includes a first comparison unit, a first capacitor unit, a first logic unit, a second logic unit, and a first current unit. The first current unit is connected to the first comparison unit and the first capacitor unit, the first comparison unit is connected to the first capacitor unit and the second logic unit, and the first capacitor unit is connected to the first comparison unit, the first logic unit, the second logic unit, and the operational amplifier module.

[0009] The first logic unit is configured to output a third preset code value based on the first preset code value; the first capacitor unit is configured to determine its capacitance value based on the third preset code value, thereby causing the first target voltage to rise to a first reference voltage within a preset time; the first current unit is configured to output a first current and a second current based on a first enable signal; the first comparison unit is configured to output a first level signal based on the first reference voltage, the first target voltage, and the first current; the second logic unit is configured to disconnect based on the first level signal; the first capacitor unit is further configured to start charging based on a second enable signal, the first level signal, and the second current, causing the first target voltage to rise at a first rate; when the first target voltage is greater than the first preset voltage, the first comparison unit outputs a second level signal; the first capacitor unit is further configured to stop charging based on the second level signal; the second logic unit is further configured to switch the first target voltage to the first reference voltage based on the second level signal.

[0010] In one possible implementation of the first aspect, the first logic unit includes a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a seventh inverter, an eighth inverter, a first AND gate, a second AND gate, and a NAND gate; the input terminal of the first inverter is used to receive the first bit value of the first preset code value, and the output terminal of the first inverter is used to output the first bit value of the third preset code value and is connected to the first capacitor unit; the input terminal of the second inverter is used to receive the second bit value of the first preset code value, and the output terminal of the second inverter is used to output the third preset code value. The third inverter receives the second bit value from the first preset code value and connects it to the first capacitor unit. The input of the third inverter receives the third bit value from the first preset code value, and the output of the third inverter outputs the third bit value from the third preset code value and connects it to the first capacitor unit. The input of the fourth inverter receives the fourth bit value from the first preset code value, and the output of the fourth inverter outputs the fourth bit value from the third preset code value and connects it to the first capacitor unit. The input of the fifth inverter receives the fifth bit value from the first preset code value and outputs the third bit value from the first preset code value. The fifth bit of the three preset code values ​​is connected to the first capacitor unit. The input of the sixth inverter is used to receive the sixth bit of the first preset code value. The output of the sixth inverter is used to output the sixth bit of the third preset code value and is connected to the first capacitor unit. The input of the seventh inverter is used to receive the seventh bit of the first preset code value. The input of the eighth inverter is used to receive the eighth bit of the first preset code value. The output of the seventh inverter is used to output the seventh bit of the third preset code value and is connected to the first input of the first AND gate and the first NAND gate, respectively. The input terminal is connected to the first capacitor unit. The output terminal of the eighth inverter is used to output the eighth bit of the third preset code value and is connected to the second input terminal of the first AND gate, the first input terminal of the second AND gate, and the first capacitor unit respectively. The second input terminal of the NAND gate receives the power supply voltage. The output terminal of the first AND gate is used to output the ninth bit of the third preset code value and is connected to the first capacitor unit. The output terminal of the NAND gate is connected to the second input terminal of the second AND gate. The output terminal of the second AND gate is used to output the tenth bit of the third preset code value and is connected to the first capacitor unit.

[0011] In one possible implementation of the first aspect, the first capacitor unit includes a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor; a first terminal of the first capacitor is connected to the source of the first transistor, the gate of the first transistor is connected to the first logic unit, and is used to receive the first bit of the third preset code value; the drain of the first transistor is connected to the drain of the second transistor, and... The drains of the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the twelfth transistor, and the thirteenth transistor, the first comparator unit, the second logic unit, and the operational amplifier module are connected. The gate of the thirteenth transistor is connected to the drain of the eleventh transistor, the first comparator unit, and the second logic unit. The source of the thirteenth transistor is connected to the first current unit. The gates of both the eleventh and twelfth transistors are used to receive the second enable signal. The first terminal of the second capacitor is connected to the source of the second transistor, and the gate of the second transistor is connected to the first logic unit, for receiving the second bit code value in the third preset code value. The first terminal of the third capacitor is connected to the source of the third transistor, and the gate of the third transistor is connected to the first logic unit, for receiving the third bit code value in the third preset code value. The first terminal of the fourth capacitor is connected to the source of the fourth transistor, and the gate of the fourth transistor is connected to the first logic unit, for receiving the fourth bit code value in the third preset code value. The first terminal of the fifth capacitor is connected to the source of the fifth transistor, and the gate of the fifth transistor is connected to the first logic unit, for receiving the third preset code value. The fifth bit value in the third preset code value; the first terminal of the sixth capacitor is connected to the source of the sixth transistor, and the gate of the sixth transistor is connected to the first logic unit, for receiving the sixth bit value in the third preset code value; the first terminal of the seventh capacitor is connected to the source of the seventh transistor, and the gate of the seventh transistor is connected to the first logic unit, for receiving the seventh bit value in the third preset code value; the first terminal of the eighth capacitor is connected to the source of the eighth transistor, and the gate of the eighth transistor is connected to the first logic unit, for receiving the tenth bit value in the third preset code value; the first terminal of the ninth capacitor is connected to the source of the ninth transistor, and the gate of the ninth transistor is connected to the first logic unit.The tenth capacitor is used to receive the ninth bit of the third preset code value. The first terminal of the tenth capacitor is connected to the source of the tenth transistor, and the gate of the tenth transistor is connected to the first logic unit. The tenth capacitor is used to receive the eighth bit of the third preset code value. The second terminals of the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, and tenth capacitors, as well as the sources of the eleventh and twelfth transistors, are all grounded.

[0012] In one possible implementation of the first aspect, the first comparison unit includes a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a third resistor, and a fourth resistor; the gate of the fourteenth transistor is used to receive a first reference voltage; the source of the fourteenth transistor is connected to the source of the fifteenth transistor and the first current unit, respectively; the drain of the fourteenth transistor is connected to the first terminal of the third resistor and the source of the seventeenth transistor, respectively; the gate of the fifteenth transistor receives a first target voltage; the drain of the fifteenth transistor is connected to the first terminal of the fourth resistor, the source of the sixteenth transistor, and the drain of the eighteenth transistor, respectively; the gate of the sixteenth transistor is connected to the gate of the seventeenth transistor, the drain of the sixteenth transistor, and the first current unit, respectively; the drain of the seventeenth transistor is connected to the first current unit, the gate of the eighteenth transistor, the first capacitor unit, and the second logic unit, respectively; the source of the eighteenth transistor is connected to the first current unit; and the second terminals of the third resistor and the fourth resistor are both grounded.

[0013] In one possible implementation of the first aspect, the second logic unit includes a nineteenth transistor, a twentieth transistor, a twenty-first transistor, a twenty-second transistor, and a twenty-third transistor; the source of the nineteenth transistor and the source of the twenty-first transistor both receive a power supply voltage; the gate of the nineteenth transistor is connected to the gate of the twenty-first transistor, the first comparator unit, and the first capacitor unit, respectively; the drain of the nineteenth transistor is connected to the drain of the twenty-first transistor, the gate of the twenty-first transistor, and the gate of the twenty-second transistor, respectively; the drain of the twenty-first transistor is connected to the drain of the twenty-second transistor and the gate of the twenty-third transistor, respectively; the drain of the twenty-third transistor is used to receive a first reference voltage; the source of the twenty-third transistor is connected to the first comparator unit, the first capacitor unit, and the operational amplifier module, respectively; and the sources of the twenty-first transistor and the twenty-second transistor are both grounded.

[0014] In one possible implementation of the first aspect, the first current unit includes a 24th transistor, a 25th transistor, a 26th transistor, a 27th transistor, a 28th transistor, a 29th transistor, a 30th transistor, a 31st transistor, a 32nd transistor, a 33rd transistor, a 34th transistor, a 35th transistor, a 36th transistor, and a first current source; the sources of the 24th transistor, the 25th transistor, the 27th transistor, the 29th transistor, the 31st transistor, the 33rd transistor, and the 35th transistor all receive a power supply voltage; the gate of the 24th transistor is used to receive a first enable signal; the drain of the 24th transistor is connected to the drain of the 25th transistor, the gate of the 25th transistor, the gate of the 27th transistor, the gate of the 29th transistor, the gate of the 31st transistor, the gate of the 33rd transistor, the gate of the 35th transistor, and the source of the 26th transistor, respectively. The gates of transistors 26, 28, 30, 32, 34, and 36 all receive a first bias voltage. The drain of transistor 26 is connected to the first terminal of the first current source, and the second terminal of the first current source is grounded. The drain of transistor 27 is connected to the source of transistor 28, and the drain of transistor 28 is connected to the first comparator unit. The drain of transistor 29 is connected to the source of transistor 30, and the drain of transistor 30 is connected to the first comparator unit. The drain of transistor 31 is connected to the source of transistor 32, and the drain of transistor 32 is connected to the first comparator unit. The drain of transistor 33 is connected to the source of transistor 34, and the drain of transistor 34 is connected to the first comparator unit. The drain of transistor 35 is connected to the source of transistor 36, and the drain of transistor 36 is connected to the first capacitor unit.

[0015] In one possible implementation of the first aspect, the second soft-start module includes a second comparison unit, a second capacitor unit, a third logic unit, and a second current unit. The second current unit is connected to the second comparison unit and the second capacitor unit, respectively. The second comparison unit is connected to the second capacitor unit and the third logic unit, respectively. The second capacitor unit is connected to the second comparison unit, the third logic unit, and the operational amplifier module, respectively.

[0016] The second capacitor unit is used to determine its capacitance value according to the second preset code value, and then raise the second target voltage to the second reference voltage within a preset time. The second current unit is used to output a third current and a fourth current according to a first enable signal. The second comparison unit is used to output a third level signal according to the second reference voltage, the second target voltage and the third current. The third logic unit is used to disconnect according to the third level signal. The second capacitor unit is also used to start charging according to the second enable signal, the third level signal and the third current, so that the second target voltage rises at a second rate. When the second target voltage is greater than the second preset voltage, the second comparison unit outputs a fourth level signal. The second capacitor unit is also used to stop charging according to the fourth level signal. The third logic unit is also used to switch the second target voltage to the second reference voltage according to the fourth level signal.

[0017] In one possible implementation of the first aspect, the second capacitor unit includes an eleventh capacitor, a twelfth capacitor, a thirteenth capacitor, a fourteenth capacitor, a fifteenth capacitor, a sixteenth capacitor, a seventeenth capacitor, an eighteenth capacitor, a nineteenth capacitor, a thirty-seventh transistor, a thirty-eighth transistor, a thirty-ninth transistor, a fortieth transistor, a forty-first transistor, a forty-second transistor, a forty-third transistor, a forty-fourth transistor, a forty-fifth transistor, a forty-sixth transistor, a forty-seventh transistor, and a forty-eighth transistor.The first terminal of the eleventh capacitor is connected to the source of the thirty-seventh transistor. The gate of the thirty-seventh transistor is used to receive the first bit of the second preset code value. The drain of the thirty-seventh transistor is connected to the drains of the thirty-eighth transistor, the thirty-ninth transistor, the fortieth transistor, the forty-first transistor, the forty-second transistor, the forty-third transistor, the forty-fourth transistor, the forty-fifth transistor, the forty-seventh transistor, the forty-eighth transistor, the second comparison unit, the third logic unit, and the operational amplifier module. The source of the forty-eighth transistor is connected to the second current unit. The gate of the forty-eighth transistor is connected to the drain of the forty-sixth transistor, the second comparison unit, and the third logic unit. The gates of the forty-sixth and forty-seventh transistors are both used to receive a second enable signal. The first terminal of the twelfth capacitor is connected to the source of the thirty-eighth transistor. The gate of the thirty-eighth transistor is used to receive the second bit code value in the second preset code value. The first terminal of the thirteenth capacitor is connected to the source of the thirty-ninth transistor. The gate of the thirty-ninth transistor is used to receive the third bit code value in the second preset code value. The fourteenth capacitor... The first terminal of the 18th capacitor is connected to the source of the 40th transistor, and the gate of the 40th transistor is used to receive the fourth bit value in the second preset code value. The first terminal of the 15th capacitor is connected to the source of the 41st transistor, and the gate of the 41st transistor is used to receive the fifth bit value in the second preset code value. The first terminal of the 16th capacitor is connected to the source of the 42nd transistor, and the gate of the 42nd transistor is used to receive the sixth bit value in the second preset code value. The first terminal of the 17th capacitor is connected to the source of the 43rd transistor, and the gate of the 43rd transistor is used to receive the seventh bit value in the second preset code value. The first terminal of the 18th capacitor... The first terminal of the 19th capacitor is connected to the source of the 44th transistor, and the gate of the 44th transistor is used to receive the eighth bit of the second preset code value. The first terminal of the 19th capacitor is connected to the source of the 45th transistor, and the gate of the 45th transistor receives the power supply voltage. The second terminals of the 11th, 12th, 13th, 14th, 15th, 16th, 17th, 18th, and 19th capacitors, as well as the sources of the 46th and 47th transistors, are all grounded.

[0018] In one possible implementation of the first aspect, the second comparison unit includes a forty-ninth transistor, a fiftieth transistor, a fifty-first transistor, a fifty-second transistor, a fifty-third transistor, a fifth resistor, and a sixth resistor; the gate of the forty-ninth transistor is used to receive a second reference voltage; the source of the forty-ninth transistor is connected to the source of the fiftieth transistor and the second current unit; the drain of the forty-ninth transistor is connected to the first terminal of the fifth resistor and the source of the fifty-second transistor; the gate of the fiftieth transistor receives a second target voltage; the drain of the fiftieth transistor is connected to the first terminal of the sixth resistor, the source of the fifty-first transistor, and the drain of the fifty-third transistor; the gate of the fifty-first transistor is connected to the gate of the fifty-second transistor, the drain of the fifty-first transistor, and the second current unit; the drain of the fifty-second transistor is connected to the second current unit, the gate of the fifty-third transistor, the second capacitor unit, and the third logic unit; the source of the fifty-third transistor is connected to the second current unit; and the second terminals of the fifth resistor and the sixth resistor are both grounded.

[0019] In one possible implementation of the first aspect, the third logic unit includes a 54th transistor, a 55th transistor, a 56th transistor, a 57th transistor, and a 58th transistor; the source of the 54th transistor and the source of the 56th transistor both receive a power supply voltage; the gate of the 54th transistor is connected to the gate of the 55th transistor, the second comparator unit, and the second capacitor unit, respectively; the drain of the 54th transistor is connected to the drain of the 55th transistor, the gate of the 56th transistor, and the gate of the 57th transistor, respectively; the drain of the 56th transistor is connected to the drain of the 57th transistor and the gate of the 58th transistor, respectively; the drain of the 58th transistor is used to receive a second reference voltage; the source of the 58th transistor is connected to the second comparator unit, the second capacitor unit, and the operational amplifier module, respectively; and the sources of the 55th transistor and the 57th transistor are both grounded.

[0020] In one possible implementation of the first aspect, the second current unit includes a 59th transistor, a 60th transistor, a 61st transistor, a 62nd transistor, a 63rd transistor, a 64th transistor, a 65th transistor, a 66th transistor, a 67th transistor, a 68th transistor, a 69th transistor, a 70th transistor, a 71st transistor, and a second current source; the gate of the 59th transistor is used to receive a first enable signal, and the sources of the 59th transistor, the 60th transistor, the 62nd transistor, the 64th transistor, the 66th transistor, the 68th transistor, and the 70th transistor all receive a power supply voltage; the drain of the 59th transistor is connected to the drain of the 60th transistor, the gate of the 60th transistor, the gate of the 62nd transistor, the gate of the 64th transistor, the gate of the 66th transistor, the gate of the 68th transistor, the gate of the 70th transistor, and the source of the 61st transistor; the 61st transistor... The gates of the body transistor, the sixty-third transistor, the sixty-fifth transistor, the sixty-seventh transistor, the sixty-ninth transistor, and the seventy-first transistor all receive a second bias voltage. The drain of the sixty-first transistor is connected to the first terminal of the second current source, and the second terminal of the second current source is grounded. The drain of the sixty-second transistor is connected to the source of the sixty-third transistor, and the drain of the sixty-third transistor is connected to the second comparator unit. The drain of the sixty-fourth transistor is connected to the source of the sixty-fifth transistor, and the drain of the sixty-fifth transistor is connected to the second comparator unit. The drain of the sixty-sixth transistor is connected to the source of the sixty-seventh transistor, and the drain of the sixty-seventh transistor is connected to the second comparator unit. The drain of the sixty-eighth transistor is connected to the source of the sixty-ninth transistor, and the drain of the sixty-ninth transistor is connected to the second comparator unit. The drain of the seventyth transistor is connected to the source of the seventy-first transistor, and the drain of the seventy-first transistor is connected to the second capacitor unit.

[0021] Secondly, embodiments of this application provide an analog integrated circuit, including the soft-start circuit for reducing surge current as described in any one of the first aspects.

[0022] Thirdly, embodiments of this application provide an electronic device including the analog integrated circuit described in any one of the second aspects.

[0023] The beneficial effects of the embodiments in this application compared with the prior art are:

[0024] This application provides a soft-start circuit for suppressing surges, including a first soft-start module, a second soft-start module, and an operational amplifier module. The operational amplifier module is connected to the input terminals of the first soft-start module, the second soft-start module, and the analog integrated circuit, respectively.

[0025] The first soft-start module is used to output a first target voltage that rises at a first rate based on a first reference voltage and a first preset code value, and rises to the first reference voltage within a preset time. The second soft-start module is used to output a second target voltage that rises at a second rate based on a second reference voltage and a second preset code value, and rises to the second reference voltage within a preset time. The operational amplifier module is used to determine the direction of change of the analog integrated circuit input voltage based on the first target voltage and the second target voltage, that is, whether the input voltage of the analog integrated circuit slowly rises towards positive voltage (i.e., positive voltage soft start) or slowly decreases towards negative voltage (i.e., negative voltage soft start). The first preset code value corresponds to the second reference voltage, and the second preset code value corresponds to the first reference voltage.

[0026] The soft-start circuit proposed in this application controls the first and second target voltages to rise to the first and second reference voltages at different rates within the same time frame during the soft-start process through code value control. This prevents the operational amplifier module from misjudging the direction of change in the input voltage of the analog integrated circuit when the first and second reference voltages change, avoiding large overshoot or undershoot due to misjudgment, and ultimately improving the stability of the analog integrated circuit. Simultaneously, based on the different rise rates of the first and second target voltages, the operational amplifier module can automatically determine whether the input voltage of the analog integrated circuit is slowly rising towards positive voltage or slowly decreasing towards negative voltage. That is, this application can achieve both positive and negative voltage soft-start, thereby reducing the inrush current of the analog integrated circuit during power-on startup or wake-up from shutdown mode. Compared to existing piecewise linear or step-wise soft-start circuits, this application proposes a novel soft-start architecture: during the soft-start process, the input voltage of the analog integrated circuit changes slowly to reduce inrush current during power-on or wake-up from shutdown mode; simultaneously, code value control improves the stability of the analog integrated circuit; during the soft-start process, no mode switching is required, completely eliminating voltage / current glitches or loop instability caused by sudden changes in loop parameters during mode switching. Compared to existing digital counter-controlled soft-start circuits, this application proposes a novel soft-start architecture: eliminating the need for clock generators, counters, analog-to-digital converters, and other modules, soft-starting of the analog integrated circuit can be achieved with only three functional modules, optimizing circuit complexity, power consumption, and area.

[0027] It is understood that the beneficial effects of the second and third aspects mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a schematic diagram of a soft-start circuit for reducing surge current provided in an embodiment of this application;

[0030] Figure 2 This is a circuit connection diagram of the operational amplifier module in this application;

[0031] Figure 3 This is a schematic diagram of a soft-start circuit for reducing inrush current provided in another embodiment of this application;

[0032] Figure 4 This is a circuit connection diagram of the first soft-start module in this application;

[0033] Figure 5 This is a circuit connection diagram of the second soft-start module in this application.

[0034] In the diagram: 10, soft-start circuit; 11, first soft-start module; 111, first comparator unit; 112, first capacitor unit; 113, first logic unit; 114, second logic unit; 115, first current unit; 12, second soft-start module; 121, second comparator unit; 122, second capacitor unit; 123, third logic unit; 124, second current unit; 13, operational amplifier module; 20, analog integrated circuit. Detailed Implementation

[0035] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0036] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0037] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0038] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [the described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [the described condition or event] is detected," or "in response to detection of [the described condition or event]."

[0039] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0040] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0041] To address the problems of high circuit complexity, high power consumption, and large area in existing digital counter-controlled soft-start circuits, as well as the poor stability of existing piecewise linear or step-type soft-start circuits, this application provides a soft-start circuit for reducing inrush current. The circuit includes a first soft-start module, a second soft-start module, and an operational amplifier module. The operational amplifier module is connected to the first soft-start module, the second soft-start module, and the input terminal of the analog integrated circuit. During the soft-start process, the proposed soft-start circuit uses code value control to cause the first target voltage and the second target voltage to rise to the first reference voltage and the second reference voltage at different rates within the same time period. This prevents the operational amplifier module from misjudging the direction of change in the input voltage of the analog integrated circuit when the first and second reference voltages change, thus avoiding large overshoot or undershoot of the analog integrated circuit's input voltage due to misjudgment, ultimately improving the stability of the analog integrated circuit. Meanwhile, based on the different rise rates of the first and second target voltages, the operational amplifier module can automatically determine whether the input voltage of the analog integrated circuit is slowly rising towards positive voltage or slowly falling towards negative voltage. This means that this application can achieve both positive and negative voltage soft-start, thereby reducing the inrush current of the analog integrated circuit during power-on startup or wake-up from shutdown mode. Compared with existing piecewise linear or step-wise soft-start circuits, this application proposes a new soft-start architecture: during soft-start, the input voltage of the analog integrated circuit changes slowly to reduce its inrush current during power-on startup or wake-up from shutdown mode; simultaneously, code value control improves the stability of the analog integrated circuit; during soft-start, no mode switching is required, completely eliminating the voltage / current glitches or loop instability problems that may be caused by sudden changes in loop parameters during mode switching. Compared with existing digital counter control soft-start circuits, this application proposes a new soft-start architecture: without the need for clock generators, counters, analog-to-digital converters, etc., soft-start of analog integrated circuits can be achieved through only three functional modules, thus optimizing circuit complexity, power consumption, and area.

[0042] To illustrate the technical solution described in this application, specific embodiments are provided below.

[0043] Figure 1 A schematic diagram of a soft-start circuit 10 provided in an embodiment of this application is shown, as follows: Figure 1 As shown, the soft-start circuit 10 includes a first soft-start module 11, a second soft-start module 12, and an operational amplifier module 13. The operational amplifier module 13 is connected to the input terminals of the first soft-start module 11, the second soft-start module 12, and the analog integrated circuit 20, respectively. In this embodiment, the analog integrated circuit 20 is a high-voltage operational amplifier.

[0044] Specifically, the first soft-start module 11 is used to output a first target voltage Vo1 that rises at a first rate based on the first reference voltage VREF1 and the first preset code values ​​SET11-SET18, and rises to the first reference voltage VREF1 within a preset time. The second soft-start module 12 is used to output a second target voltage Vo2 that rises at a second rate based on the second reference voltage VREF2 and the second preset code values ​​SET21-SET28, and rises to the second reference voltage VREF2 within a preset time. The operational amplifier module 13 is used to determine the direction of change of the input voltage VIN of the analog integrated circuit 20 based on the first target voltage Vo1 and the second target voltage Vo2, that is, whether the input voltage VIN of the analog integrated circuit 20 slowly rises towards positive voltage (i.e., positive voltage soft start) or slowly falls towards negative voltage (i.e., negative voltage soft start). The first preset code values ​​SET11-SET18 correspond to the second reference voltage VREF2, and the second preset code values ​​SET21-SET28 correspond to the first reference voltage VREF1. It should be noted that the preset time is determined by the product of the first reference voltage VREF1 and the capacitance value inside the first soft-start module 11, or by the product of the second reference voltage VREF2 and the capacitance value inside the second soft-start module 12. Therefore, the product of the first reference voltage VREF1 and the capacitance value inside the first soft-start module 11 is equal to the product of the second reference voltage VREF2 and the capacitance value inside the second soft-start module 12. The capacitance value inside the first soft-start module 11 is determined by the first preset code value SET11-SET18, and the first preset code value SET11-SET18 and the second reference voltage VREF1 are equal. Correspondingly, the capacitance value inside the second soft-start module 12 is determined by the second preset code values ​​SET21-SET28, and the second preset code values ​​SET21-SET28 correspond to the first reference voltage VREF1. This ensures that when the first reference voltage VREF1 and the second reference voltage VREF2 change, the capacitance value inside the second soft-start module 12 and the capacitance value inside the first soft-start module 11 will change accordingly, ensuring that the first target voltage Vo1 and the second target voltage Vo2 rise to the first reference voltage VREF1 and the second reference voltage VREF2 at different rates within the same time. This process prevents the operational amplifier module 13 from misjudging the direction of change of the input voltage VIN of the analog integrated circuit 20 when the first reference voltage VREF1 and the second reference voltage VREF2 change, thereby avoiding large overshoot or undershoot of the input voltage VIN of the analog integrated circuit 20 and improving the stability of the analog integrated circuit 20.

[0045] In summary, the soft-start circuit 10 proposed in this application controls the first target voltage Vo1 and the second target voltage Vo2 to rise to the first reference voltage VREF1 and the second reference voltage VREF2 at different rates within the same time period during the soft-start process through code value control. This prevents the operational amplifier module 13 from misjudging the direction of change of the input voltage VIN of the analog integrated circuit 20 when the first reference voltage VREF1 and the second reference voltage VREF2 change, thus avoiding large overshoot or undershoot of the input voltage VIN of the analog integrated circuit 20 due to misjudgment, ultimately improving the stability of the analog integrated circuit 20. Simultaneously, based on the different rise rates of the first target voltage Vo1 and the second target voltage Vo2, the operational amplifier module 13 can automatically determine whether the input voltage VIN of the analog integrated circuit 20 is slowly rising towards positive voltage or slowly decreasing towards negative voltage. That is, this application can achieve both positive and negative voltage soft-start, thereby reducing the inrush current of the analog integrated circuit 20 during power-on startup or wake-up from shutdown mode. Compared to existing piecewise linear or step-wise soft-start circuits, this application proposes a novel soft-start architecture: during the soft-start process, the input voltage of the analog integrated circuit 20 is changed slowly to reduce inrush current during power-on or wake-up from shutdown mode; simultaneously, code value control improves the stability of the analog integrated circuit; during the soft-start process, no mode switching is required, completely eliminating voltage / current glitches or loop instability caused by sudden changes in loop parameters during mode switching. Compared to existing digital counter control-type soft-start circuits, this application proposes a novel soft-start architecture: without the need for clock generators, counters, analog-to-digital converters, etc., soft-start of the analog integrated circuit can be achieved through only three functional modules, optimizing circuit complexity, power consumption, and area.

[0046] It should be noted that the working order of the analog integrated circuit 20, the operational amplifier module 13, the first soft-start module 11, and the second soft-start module 12 is as follows: the analog integrated circuit 20 starts working first according to its enable signal, then the operational amplifier module 13 starts working according to its enable signal, and finally the first soft-start module 11 and the second soft-start module 12 both start working according to the first enable signal and the second enable signal.

[0047] In one embodiment of this application, such as Figure 2As shown, the operational amplifier module 13 includes a first operational amplifier OP1, a second operational amplifier OP2, a first resistor R1, and a second resistor R2. The first input terminal of the first operational amplifier OP1 is connected to the first soft-start module 11, and the first input terminal of the second operational amplifier OP2 is connected to the second soft-start module 12. The second input terminal of the first operational amplifier OP1 is connected to the first terminal of the first resistor R1 and the first terminal of the second resistor R2, respectively. The second terminal of the second resistor R2 is connected to the output terminal of the first operational amplifier OP1 and the input terminal of the analog integrated circuit 20, respectively. The first terminal of the first resistor R1 is connected to the output terminal of the second operational amplifier OP2 and the second input terminal of the second operational amplifier OP2, respectively. In this embodiment, the first operational amplifier OP1 is a low-voltage operational amplifier with a positive first input terminal and a negative second input terminal. The connection configuration of the second operational amplifier OP2 forms a buffer to improve the driving capability of the second target voltage Vo2; its first input terminal is positive, and its second input terminal is negative.

[0048] Specifically, the operational amplifier module 13 automatically compares the first target voltage Vo1 and the second target voltage Vo2 using the first resistor R1 and the second resistor R2, thereby determining whether the input voltage VIN of the analog integrated circuit 20 is slowly rising towards a positive voltage or slowly falling towards a negative voltage. To enable the first resistor R1 and the second resistor R2 to automatically compare the first target voltage Vo1 and the second target voltage Vo2, the following relationship exists between the first target voltage Vo1 and the second target voltage Vo2:

[0049] (1);

[0050] (2);

[0051] The resistance of the second resistor R2 is four times that of the first resistor R1.

[0052] When the first target voltage Vo1 is greater than 4 / 5 of the second target voltage Vo2, the input voltage VIN of the analog integrated circuit 20 slowly rises towards a positive voltage. When the first target voltage Vo1 is less than 4 / 5 of the second target voltage Vo2, the input voltage VIN of the analog integrated circuit 20 slowly decreases towards a negative voltage. When the first target voltage Vo1 is equal to 4 / 5 of the second target voltage Vo2, the input voltage VIN of the analog integrated circuit 20 is zero.

[0053] In one embodiment of this application, such as Figure 3As shown, the first soft-start module 11 includes a first comparison unit 111, a first capacitor unit 112, a first logic unit 113, a second logic unit 114, and a first current unit 115. The first current unit 115 is connected to the first comparison unit 111 and the first capacitor unit 112, respectively. The first comparison unit 111 is connected to the first capacitor unit 112 and the second logic unit 114, respectively. The first capacitor unit 112 is connected to the first comparison unit 111, the first logic unit 113, the second logic unit 114, and the operational amplifier module 13, respectively.

[0054] Specifically, the first logic unit 113 is used to output a third preset code value SET31-SET40 according to the first preset code value SET11-AET18. The first capacitor unit 112 is used to determine its capacitance value according to the third preset code value SET31-SET40, and then raise the first target voltage Vo1 to the first reference voltage VREF1 within a preset time. The first current unit 115 is used to output a first current and a second current according to the first enable signal EN1. The first enable signal EN1 is high. When the first soft-start module 11 first starts working, the first target voltage Vo1 is zero, and the first comparison unit 111 is used to output a first level signal according to the first reference voltage VREF1, the first target voltage Vo1, and the first current. In this embodiment, the first level signal is low. The second logic unit 114 is used to disconnect according to the first level signal. The first capacitor unit 112 is also used to start charging according to the second enable signal EN2, the first level signal, and the second current, causing the first target voltage Vo1 to rise at a first rate. The second enable signal EN2 is low. It should be understood that the first soft-start module 11 starts working when the first enable signal EN1 is high and the second enable signal EN2 is low. When the first target voltage Vo1 is greater than the first preset voltage, the first comparison unit 111 outputs a second level signal. In this embodiment, the second level signal is high. The first capacitor unit 112 is also used to stop charging according to the second level signal. The second logic unit 114 is also used to switch the first target voltage Vo1 to the first reference voltage VREF1 according to the second level signal.

[0055] It should be noted that the first soft-start module 11 does not work when the first enable signal EN1 is low and the second enable signal EN2 is high.

[0056] In one embodiment of this application, such as Figure 4As shown, the first logic unit 113 includes a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a fifth inverter INV5, a sixth inverter INV6, a seventh inverter INV7, an eighth inverter INV8, a first AND gate AND1, a second AND gate AND2, and a NAND gate NAND. The input of the first inverter INV1 is used to receive the first bit value SET11 from the first preset code values ​​SET11-SET18, and the output of the first inverter INV1 is used to output the first bit value SET31 from the third preset code values ​​SET31-SET40, and is connected to the first capacitor unit 112. The input of the second inverter INV2 is used to receive the first preset... The second bit value SET12 in the code values ​​SET11-SET18 is used to output the second bit value SET32 in the third preset code values ​​SET31-SET40, and is connected to the first capacitor unit 112. The input of the third inverter INV3 is used to receive the third bit value SET13 in the first preset code values ​​SET11-SET18, and the output of the third inverter INV3 is used to output the third bit value SET33 in the third preset code values ​​SET31-SET40, and is connected to the first capacitor unit 112. The input of the fourth inverter INV4 is used to receive the fourth bit value SET14 in the first preset code values ​​SET11-SET18, and the fourth inverter INV... The output terminal of inverter 4 is used to output the fourth bit code value SET34 from the third preset code values ​​SET31-SET40, and is connected to the first capacitor unit 112. The input terminal of the fifth inverter INV5 is used to receive the fifth bit code value SET15 from the first preset code values ​​SET11-SET18, and the output terminal of the fifth inverter INV5 is used to output the fifth bit code value SET35 from the third preset code values ​​SET31-SET40, and is connected to the first capacitor unit 112. The input terminal of the sixth inverter INV6 is used to receive the sixth bit code value SET16 from the first preset code values ​​SET11-SET18, and the output terminal of the sixth inverter INV6 is used to output the sixth bit code value SET34 from the third preset code values ​​SET31-SET40. 36, and connected to the first capacitor unit 112, the input terminal of the seventh inverter INV7 is used to receive the seventh bit code value SET17 in the first preset code values ​​SET11-SET18, the input terminal of the eighth inverter INV8 is used to receive the eighth bit code value SET18 in the first preset code values ​​SET11-SET18, the output terminal of the seventh inverter INV7 is used to output the seventh bit code value SET37 in the third preset code values ​​SET31-SET40, and is connected to the first input terminal of the first AND gate AND1, the first input terminal of the NAND gate NAND and the first capacitor unit 112 respectively, and the output terminal of the eighth inverter INV8 is used to output the eighth bit code value SET38 in the third preset code values ​​SET31-SET40.The first AND gate (AND1), the second AND gate (AND2), and the first capacitor unit (112) are connected to their respective inputs. The second input of the NAND gate (NAND) receives the power supply voltage VPP. The output of the first AND gate (AND1) is used to output the ninth bit value SET39 from the third preset code values ​​SET31-SET40, and is connected to the first capacitor unit (112). The output of the NAND gate (NAND) is connected to the second input of the second AND gate (AND2). The output of the second AND gate (AND2) is used to output the tenth bit value SET40 from the third preset code values ​​SET31-SET40, and is also connected to the first capacitor unit (112).

[0057] Specifically, the first logic unit 113 is essentially a logic circuit composed of inverters, AND gates, and NAND gates. By performing logic operations on the first preset code values ​​SET11-SET18, the third preset code values ​​SET31-SET40 are obtained. The first preset code values ​​SET11-SET18 correspond to the second reference voltage VREF2. Therefore, when the second reference voltage VREF2 changes, the first preset code values ​​SET11-SET18 will change accordingly, thereby causing a change in the capacitance value of the first capacitor unit 112. Ultimately, this ensures that the first target voltage Vo1 and the second target voltage Vo2 rise to the first reference voltage VREF1 and the second reference voltage VREF2 at different rates within the same time period.

[0058] In one embodiment of this application, such as Figure 4As shown, the first capacitor unit 112 includes a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a ninth capacitor C9, a tenth capacitor C10, a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, and a thirteenth transistor M13. The first terminal of the first capacitor C1 is connected to the source of the first transistor M1, and the gate of the first transistor M1 is connected to the first logic unit 113 for receiving signals. The first code value SET31 in the third preset code values ​​SET31-SET40 is connected to the drains of the second transistor M1, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, the twelfth transistor M12, the thirteenth transistor M13, the first comparison unit 111, the second logic unit 114, and the operational amplifier module 13. The gate of the thirteenth transistor M13 is connected to the drain of the eleventh transistor M11, the first comparison unit 111, and the second logic unit 114. The source of the thirteenth transistor M13 is connected to the first current unit 115. The gates of the eleventh transistor M11 and the twelfth transistor M12 are both used to receive the second enable signal EN2. The first terminal of the second capacitor C2 is connected to the source of the second transistor M2, and the gate of the second transistor M2 is connected to the first logic unit 113 to receive the second bit code value SET32 in the third preset code values ​​SET31-SET40. The first terminal of the third capacitor C3 is connected to the source of the third transistor M3, and the gate of the third transistor M3 is connected to the first logic unit 113 to receive the third bit code value SET33 in the third preset code values ​​SET31-SET40. The first terminal of the fourth capacitor C4 is connected to the fourth transistor M4. The source of the fourth transistor M4 is connected to the source of the fifth transistor M5, and the gate of the fifth transistor M5 is connected to the first logic unit 113 to receive the fourth bit code value SET34 in the third preset code values ​​SET31-SET40. The first terminal of the fifth capacitor C5 is connected to the source of the fifth transistor M5, and the gate of the fifth transistor M5 is connected to the first logic unit 113 to receive the fifth bit code value SET35 in the third preset code values ​​SET31-SET40. The first terminal of the sixth capacitor C6 is connected to the source of the sixth transistor M6, and the gate of the sixth transistor M6 is connected to the first logic unit 113 to receive the sixth bit code value SET36 in the third preset code values ​​SET31-SET40. The first terminal of the seventh capacitor C7 is connected to the source of the seventh transistor M7.The gate of the seventh transistor M7 is connected to the first logic unit 113 to receive the seventh bit value SET37 in the third preset code values ​​SET31-SET40. The first terminal of the eighth capacitor C8 is connected to the source of the eighth transistor M8, and the gate of the eighth transistor M8 is connected to the first logic unit 113 to receive the tenth bit value SET40 in the third preset code values ​​SET31-SET40. The first terminal of the ninth capacitor C9 is connected to the source of the ninth transistor M9, and the gate of the ninth transistor M9 is connected to the first logic unit 113 to receive the ninth bit value SET39 in the third preset code values ​​SET31-SET40. The first terminal of capacitor C10 is connected to the source of transistor M10. The gate of transistor M10 is connected to the first logic unit 113, used for the eighth bit value SET38 in the third preset code values ​​SET31-SET40. The second terminals of capacitors C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, the source of transistor M11, and the source of transistor M12 are all grounded.

[0059] Specifically, when the second enable signal EN2 is low, the eleventh transistor M11 and the twelfth transistor M12 are disconnected under the control of the second enable signal EN2, and the first capacitor unit 112 can perform corresponding actions according to the level signal output by the first comparison unit 111. At this time, the first enable signal EN1 should be high, that is, the first soft-start module 11 starts to work.

[0060] The capacitance value of the first capacitor unit 112 is controlled by the third preset code value SET31-SET40. The capacitance value of the first capacitor unit 112 is determined by controlling the on / off state of the transistor above each capacitor.

[0061] When the first comparison unit 111 outputs a first-level signal, the thirteenth transistor M13 is turned on under the control of the first-level signal, charging the capacitor in the first capacitor unit 112 according to the second current output by the first current unit 115, causing the first target voltage Vo1 to gradually increase at a first rate. When the first target voltage Vo1 is greater than the first preset voltage, the first comparison unit 111 outputs a second-level signal. The thirteenth transistor M13 is turned off under the control of the second-level signal, stopping the charging of the capacitor in the first capacitor unit 112.

[0062] When the second enable signal EN2 is high, the eleventh transistor M11 and the twelfth transistor M12 are turned on under the control of the second enable signal EN2, and the first capacitor unit 112 cannot perform the corresponding action. At this time, the first enable signal EN1 should be low, that is, the first soft-start module 11 does not work.

[0063] In one embodiment of this application, such as Figure 4 As shown, the first comparison unit 111 includes a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, a seventeenth transistor M17, an eighteenth transistor M18, a third resistor R3, and a fourth resistor R4. The gate of the fourteenth transistor M14 is used to receive a first reference voltage VREF1. The source of the fourteenth transistor M14 is connected to the source of the fifteenth transistor M15 and the first current unit 115, respectively. The drain of the fourteenth transistor M14 is connected to the first terminal of the third resistor R3 and the source of the seventeenth transistor M17, respectively. The gate of the fifteenth transistor M15 receives a first target voltage Vo1. The drain of transistor M15 is connected to the first terminal of the fourth resistor R4, the source of the sixteenth transistor M16, and the drain of the eighteenth transistor M18. The gate of the sixteenth transistor M16 is connected to the gate of the seventeenth transistor M17, the drain of the sixteenth transistor M16, and the first current unit 115. The drain of the seventeenth transistor M17 is connected to the first current unit 115, the gate of the eighteenth transistor M18, the first capacitor unit 112, and the second logic unit 114. The source of the eighteenth transistor M18 is connected to the first current unit 115. The second terminals of the third resistor R3 and the fourth resistor R4 are both grounded.

[0064] Specifically, when the first soft-start module 11 starts working, the first target voltage Vo1 is zero. Since the first reference voltage VREF1 is greater than the first target voltage Vo1, after the first comparison structure composed of the fourteenth transistor M14 and the fifteenth transistor M15, it is known that the first voltage VDP1 is less than the second voltage VDP2. After the first voltage VDP1 and the second voltage VDP2 are compared by the second comparison structure composed of the sixteenth transistor M16 and the seventeenth transistor M17, a first level signal is output. The eighteenth transistor M18 is turned on under the control of the first level signal and outputs current to the fourth resistor R4 to prevent the first target voltage Vo1 from overshooting. As the first target voltage Vo1 gradually increases and exceeds the first preset voltage, the first voltage VDP1 is greater than the second voltage VDP2. After the first voltage VDP1 and the second voltage VDP2 are compared by the second comparison structure composed of the sixteenth transistor M16 and the seventeenth transistor M17, a second level signal is output. The eighteenth transistor M18 is turned off under the control of the second level signal, at which point the soft start ends.

[0065] In one embodiment of this application, such as Figure 4 As shown, the second logic unit 114 includes a nineteenth transistor M19, a twentieth transistor M20, a twenty-first transistor M21, a twenty-second transistor M22, and a twenty-third transistor M23. The source of the nineteenth transistor M19 and the source of the twenty-first transistor M21 both receive the power supply voltage VPP. The gate of the nineteenth transistor M19 is connected to the gate of the twentieth transistor M20, the first comparator unit 111, and the first capacitor unit 112, respectively. The drain of the nineteenth transistor M19 is connected to the drain of the twentieth transistor M20, the gate of the twenty-first transistor M21, and the gate of the twenty-second transistor M22, respectively. The drain of the twenty-first transistor M21 is connected to the drain of the twenty-second transistor M22 and the gate of the twenty-third transistor M23, respectively. The drain of the twenty-third transistor M23 is used to receive the first reference voltage VREF1. The source of the twenty-third transistor M23 is connected to the first comparator unit 111, the first capacitor unit 112, and the operational amplifier module 13, respectively. The sources of the twentieth transistor M20 and the twenty-second transistor M22 are both grounded.

[0066] Specifically, the second logic unit 114 essentially consists of two cascaded inverters and one switching transistor. The nineteenth transistor M19 and the twentieth transistor M20 form an inverter, as do the twenty-first transistor M21 and the twenty-second transistor M22. The twenty-third transistor M23 is the switching transistor. When the first comparator unit 111 outputs a first-level signal, the two cascaded inverters sequentially invert the first-level signal. Since the first-level signal is low, it remains low after two inversions, and the twenty-third transistor M23 is turned off under the control of the low level. When the first comparator unit 111 outputs a second-level signal, the two cascaded inverters sequentially invert the second-level signal. Since the second-level signal is high, it remains high after two inversions, and the twenty-third transistor M23 is turned on under the control of the high level, switching the first target voltage Vo1 to the first reference voltage VREF1.

[0067] In one embodiment of this application, such as Figure 4As shown, the first current unit 115 includes the twenty-fourth transistor M24, the twenty-fifth transistor M25, the twenty-sixth transistor M26, the twenty-seventh transistor M27, the twenty-eighth transistor M28, the twenty-ninth transistor M29, the thirtieth transistor M30, the thirty-first transistor M31, the thirty-second transistor M32, the thirty-third transistor M33, the thirty-fourth transistor M34, the thirty-fifth transistor M35, the thirty-sixth transistor M36, and a first current source Ix; the source of the twenty-fourth transistor M24, the source of the twenty-fifth transistor M25, the source of the twenty-seventh transistor M27, and the twenty-ninth transistor M26. The sources of transistors M29, M31, M33, and M35 all receive the power supply voltage VPP. The gate of transistor M24 receives the first enable signal EN1. The drain of transistor M24 is connected to the drain and gate of transistors M25, M27, M29, M31, M33, M35, and M26, respectively. The source of transistor M26 is connected to the source of transistor M28. The gates of transistors M28, M29, M20, M31, M32, M34, and M36 all receive the first bias voltage Vbias1. The drain of transistor M26 is connected to the first terminal of the first current source Ix, and the second terminal of the first current source Ix is grounded. The drain of transistor M27 is connected to the source of transistor M28. The drain of transistor M28 is connected to the first comparator unit 111. The twenty-ninth transistor M29... The drain of transistor M31 is connected to the source of transistor M32, the drain of transistor M32 is connected to the first comparator unit 111, the drain of transistor M33 is connected to the source of transistor M34, the drain of transistor M34 is connected to the first comparator unit 111, the drain of transistor M35 is connected to the source of transistor M36, and the drain of transistor M36 is connected to the first capacitor unit 112.

[0068] Specifically, when the first enable signal EN1 is high, the twenty-fourth transistor M24 is turned off under the control of the first enable signal EN1, and the first current unit 115 can output current normally. At this time, the second enable signal EN2 should be low, that is, the first soft-start module 11 starts to work.

[0069] The current generated by the first current source Ix is mirrored by a current mirror composed of the twenty-fifth transistor M25, the twenty-seventh transistor M27, the twenty-ninth transistor M29, the thirty-first transistor M31, the thirty-third transistor M33, and the thirty-fifth transistor M35. The mirrored first current (which includes four sub-currents) is used to provide bias current for the first comparator unit 111, and the mirrored second current is used to charge the first capacitor unit 112.

[0070] When the first enable signal EN1 is low, the twenty-fourth transistor M24 is turned on under the control of the first enable signal EN1, and the first current unit 115 cannot output current normally. At this time, the second enable signal EN2 should be high, that is, the first soft-start module 11 does not work.

[0071] It should be noted that the first preset voltage is , where I M27 For the current flowing through the twenty-seventh transistor M27, I M18 K1 is the current flowing through the eighteenth transistor M18, and K1 is a coefficient.

[0072] In one embodiment of this application, such as Figure 3 As shown, the second soft-start module 12 includes a second comparison unit 121, a second capacitor unit 122, a third logic unit 123, and a second current unit 124. The second current unit 124 is connected to the second comparison unit 121 and the second capacitor unit 122, respectively. The second comparison unit 121 is connected to the second capacitor unit 122 and the third logic unit 123, respectively. The second capacitor unit 122 is connected to the second comparison unit 121, the third logic unit 123, and the operational amplifier module 13, respectively.

[0073] Specifically, the second capacitor unit 122 is used to determine its capacitance value according to the second preset code values ​​SET21-SET28, thereby raising the second target voltage Vo2 to the second reference voltage VREF2 within a preset time. The second current unit 124 is used to output a third current and a fourth current according to the first enable signal EN1. The first enable signal EN1 is high. When the second soft-start module 12 first starts working, the second target voltage Vo2 is zero, and the second comparison unit 121 is used to output a third level signal according to the second reference voltage VREF2, the second target voltage Vo2, and the third current. In this embodiment, the third level signal is low. The third logic unit 123 is used to disconnect according to the third level signal. The second capacitor unit 122 is also used to start charging according to the second enable signal EN2, the third level signal, and the third current, causing the second target voltage Vo2 to rise at a second rate. The second enable signal EN2 is low. When the second target voltage Vo2 is greater than the second preset voltage, the second comparison unit 121 outputs a fourth level signal. In this embodiment, the fourth level signal is high. The second capacitor unit 122 is also used to stop charging according to the fourth level signal. The third logic unit 123 is also used to switch the second target voltage Vo2 to the second reference voltage VREF2 according to the fourth level signal.

[0074] It should be noted that the second soft-start module 12 does not work when the first enable signal EN1 is low and the second enable signal EN2 is high.

[0075] In one embodiment of this application, such as Figure 5As shown, the second capacitor unit 122 includes an eleventh capacitor C11, a twelfth capacitor C12, a thirteenth capacitor C13, a fourteenth capacitor C14, a fifteenth capacitor C15, a sixteenth capacitor C16, a seventeenth capacitor C17, an eighteenth capacitor C18, a nineteenth capacitor C19, a thirty-seventh transistor M37, a thirty-eighth transistor M38, a thirty-ninth transistor M39, a fortieth transistor M40, a forty-first transistor M41, a forty-second transistor M42, a forty-third transistor M43, a forty-fourth transistor M44, a forty-fifth transistor M45, a forty-sixth transistor M46, a forty-seventh transistor M47, and a forty-eighth transistor M48; the first terminal of the eleventh capacitor C11 is connected to the thirty-seventh transistor... The source of M37 is connected, and the gate of the thirty-seventh transistor M37 is used to receive the first code value SET21 in the second preset code value SET21-SET-28. The drain of the thirty-seventh transistor M37 is connected to the drains of the thirty-eighth transistor M38, the thirty-ninth transistor M39, the fortieth transistor M40, the forty-first transistor M41, the forty-second transistor M42, the forty-third transistor M43, the forty-fourth transistor M44, the forty-fifth transistor M45, the forty-seventh transistor M47, the forty-eighth transistor M48, the second comparison unit 121, the third logic unit 123, and the operational amplifier module 13. The source of transistor M48 is connected to the second current unit 124. The gate of the forty-eighth transistor M48 is connected to the drain of the forty-sixth transistor M46, the second comparison unit 121, and the third logic unit 123, respectively. The gates of the forty-sixth transistor M46 and the forty-seventh transistor M47 are both used to receive the second enable signal EN2. The first terminal of the twelfth capacitor C12 is connected to the source of the thirty-eighth transistor M38. The gate of the thirty-eighth transistor M38 is used to receive the second bit code value SET22 in the second preset code values ​​SET21-SET28. The first terminal of the thirteenth capacitor C13 is connected to the source of the thirty-ninth transistor M39. The gate of the thirty-ninth transistor M39 is used to receive the second preset code value SET22. In the second preset code values ​​SET21-SET28, the third bit value SET23 is connected to the source of the fortieth transistor M40, and the gate of the fortieth transistor M40 is used to receive the fourth bit value SET24 in the second preset code values ​​SET21-SET28. The first terminal of the fifteenth capacitor C15 is connected to the source of the forty-first transistor M41, and the gate of the forty-first transistor M41 is used to receive the fifth bit value SET25 in the second preset code values ​​SET21-SET28. The first terminal of the sixteenth capacitor C16 is connected to the source of the forty-second transistor M42, and the gate of the forty-second transistor M42 is used to receive the sixth bit value SET26 in the second preset code values ​​SET21-SET28.The first terminal of the seventeenth capacitor C17 is connected to the source of the forty-third transistor M43. The gate of the forty-third transistor M43 is used to receive the seventh bit value SET27 in the second preset code values ​​SET21-SET28. The first terminal of the eighteenth capacitor C18 is connected to the source of the forty-fourth transistor M44. The gate of the forty-fourth transistor M44 is used to receive the eighth bit value SET28 in the second preset code values ​​SET21-SET28. The first terminal of the nineteenth capacitor C19 is connected to the source of the forty-fifth transistor M45. The gate of the forty-fifth transistor M45 receives the power supply voltage VPP. The second terminals of the eleventh capacitor C11, the twelfth capacitor C12, the thirteenth capacitor C13, the fourteenth capacitor C14, the fifteenth capacitor C15, the sixteenth capacitor C16, the seventeenth capacitor C17, the eighteenth capacitor C18, the nineteenth capacitor C19, the source of the forty-sixth transistor M46, and the source of the forty-seventh transistor M47 are all grounded.

[0076] Specifically, when the second enable signal EN2 is low, the forty-sixth transistor M46 and the forty-seventh transistor M47 are disconnected under the control of the second enable signal EN2, and the second capacitor unit 122 can perform corresponding actions according to the level signal output by the second comparison unit 121. At this time, the first enable signal EN1 should be high, that is, the second soft-start module 12 starts to work.

[0077] The capacitance value of the second capacitor unit 122 is controlled by the second preset code value SET21-SET28. The capacitance value of the second capacitor unit 122 is determined by controlling the on / off state of the transistor above each capacitor.

[0078] When the second comparator unit 121 outputs a third-level signal, the forty-eighth transistor M48 is turned on under the control of the third-level signal, charging the capacitor in the second capacitor unit 122 according to the fourth current output by the second current unit 124, causing the second target voltage Vo2 to gradually increase at the second rate. When the second target voltage Vo2 is greater than the second preset voltage, the second comparator unit 121 outputs a fourth-level signal, and the forty-eighth transistor M48 is turned off under the control of the fourth-level signal, stopping the charging of the capacitor in the second capacitor unit 122.

[0079] When the second enable signal EN2 is high, the forty-sixth transistor M46 and the forty-seventh transistor M47 are turned on under the control of the second enable signal EN2, and the second capacitor unit 122 cannot perform the corresponding action. At this time, the first enable signal EN1 should be low, that is, the second soft-start module 12 does not work.

[0080] In one embodiment of this application, such as Figure 5As shown, the second comparison unit 121 includes a forty-ninth transistor M49, a fiftieth transistor M50, a fifty-first transistor M51, a fifty-second transistor M52, a fifty-third transistor M53, a fifth resistor R5, and a sixth resistor R6. The gate of the forty-ninth transistor M49 is used to receive the second reference voltage VREF2. The source of the forty-ninth transistor M49 is connected to the source of the fiftieth transistor M50 and the second current unit 124, respectively. The drain of the forty-ninth transistor M49 is connected to the first terminal of the fifth resistor R5 and the source of the fifty-second transistor M52, respectively. The gate of the fiftieth transistor M50 receives the second target voltage Vo2. The drain of transistor M50 is connected to the first terminal of the sixth resistor R6, the source of the fifty-first transistor M51, and the drain of the fifty-third transistor M53, respectively. The gate of the fifty-first transistor M51 is connected to the gate of the fifty-second transistor M52, the drain of the fifty-first transistor M51, and the second current unit 124, respectively. The drain of the fifty-second transistor M52 is connected to the second current unit 124, the gate of the fifty-third transistor M53, the second capacitor unit 122, and the third logic unit 123, respectively. The source of the fifty-third transistor M53 is connected to the second current unit 124. The second terminals of the fifth resistor R5 and the sixth resistor R6 are both grounded.

[0081] Specifically, when the second soft-start module 12 starts working, the second target voltage Vo2 is zero. Since the second reference voltage VREF2 is greater than the second target voltage Vo2, after the first-stage comparison structure composed of the forty-ninth transistor M49 and the fiftieth transistor M50, it is determined that the third voltage VDP3 is less than the fourth voltage VDP4. After the second-stage comparison structure composed of the fifty-first transistor M51 and the fifty-second transistor M52, the third voltage VDP3 and the fourth voltage VDP4 output a third-level signal. The fifty-third transistor M53 is turned on under the control of the third-level signal and outputs current to the sixth resistor R6 to prevent the second target voltage Vo2 from overshooting. As the second target voltage Vo2 gradually increases and exceeds the second preset voltage, the third voltage VDP3 becomes greater than the fourth voltage VDP4. After the second-stage comparison structure composed of the fifty-first transistor M51 and the fifty-second transistor M52 outputs a fourth-level signal, the fifty-third transistor M53 is turned off under the control of the fourth-level signal, at which point the soft start ends.

[0082] In one embodiment of this application, such as Figure 5As shown, the third logic unit 123 includes a fifty-fourth transistor M54, a fifty-fifth transistor M55, a fifty-sixth transistor M56, a fifty-seventh transistor M57, and a fifty-eighth transistor M58. The sources of both the fifty-fourth transistor M54 and the fifty-sixth transistor M56 receive the power supply voltage VPP. The gate of the fifty-fourth transistor M54 is connected to the gate of the fifty-fifth transistor M55, the second comparator unit 121, and the second capacitor unit 122, respectively. The drain of the fifty-fourth transistor M54 is connected to the gate of the fifty-fifth transistor M55. The drain of transistor M56, the gate of transistor M57, and the gate of transistor M58 are connected. The drain of transistor M56 is connected to the drain of transistor M57 and the gate of transistor M58. The drain of transistor M58 is used to receive the second reference voltage VREF2. The source of transistor M58 is connected to the second comparator unit 121, the second capacitor unit 122, and the operational amplifier module 13. The sources of transistor M55 and transistor M57 are both grounded.

[0083] Specifically, the third logic unit 123 essentially consists of two cascaded inverters and one switching transistor. Transistors M54 (54) and M55 (55), and M56 (56) and M57 (57) form an inverter. Transistor M58 is the switching transistor. When the second comparator unit 121 outputs a third-level signal, the two cascaded inverters sequentially invert the third-level signal. Since the third-level signal is low, it remains low after two inversions, and transistor M58 is turned off under the control of the low level. When the second comparator unit 121 outputs a fourth-level signal, the two cascaded inverters sequentially invert the fourth-level signal. Since the fourth-level signal is high, it remains high after two inversions, and transistor M58 is turned on under the control of the high level, switching the second target voltage Vo2 to the second reference voltage VREF2.

[0084] In one embodiment of this application, such as Figure 5As shown, the second current unit 124 includes a fifty-ninth transistor M59, a sixtieth transistor M60, a sixty-first transistor M61, a sixty-second transistor M62, a sixty-third transistor M63, a sixty-fourth transistor M64, a sixty-fifth transistor M65, a sixty-sixth transistor M66, a sixty-seventh transistor M67, a sixty-eighth transistor M68, a sixty-ninth transistor M69, a seventyth transistor M70, a seventy-first transistor M71, and a second current source Iy; the gate of the fifty-ninth transistor M59 is used to receive the first enable signal EN1, and the source of the fifty-ninth transistor M59, the sixtyth transistor M60, and the sixtyth transistor M62... The sources of transistors M60, M62 (sixty-second), M64 (sixty-fourth), M66 (sixty-sixth), M68 (sixty-eighth), and M70 (seventieth) all receive the power supply voltage VPP. The drain of transistor M59 is connected to the drain of transistor M60, the gate of transistor M60, the gate of transistor M62, the gate of transistor M64, the gate of transistor M66, the gate of transistor M68, the gate of transistor M70, and the source of transistor M61. The gates of transistors M61 (sixty-first), M63 (sixty-third), M65 (sixty-fifth), M67 (sixty-seventh), M69 (sixty-ninth), and M71 (seventy-first) all receive the second bias voltage Vbias2. The drain of transistor M61 is connected to the first terminal of the second current source Iy, and the second terminal of the second current source Iy is grounded. The drain of transistor M62 is connected to the source of transistor M63. The drain of transistor M63 is connected to the second comparator unit 121. The drain of transistor M64... The drain of transistor M65 is connected to the source of transistor M65, the drain of transistor M65 is connected to the second comparator unit 121, the drain of transistor M66 is connected to the source of transistor M67, the drain of transistor M67 is connected to the second comparator unit 121, the drain of transistor M68 is connected to the source of transistor M69, the drain of transistor M69 is connected to the second comparator unit 121, the drain of transistor M70 is connected to the source of transistor M71, and the drain of transistor M71 is connected to the second capacitor unit 122.

[0085] Specifically, when the first enable signal EN1 is high, the fifty-ninth transistor M59 is disconnected under the control of the first enable signal EN1, and the second current unit 124 can output current normally. At this time, the second enable signal EN2 should be low, that is, the second soft-start module 12 starts to work.

[0086] The current generated by the second current source Iy is mirrored by a current mirror composed of the sixtieth transistor M60, the sixty-second transistor M62, the sixty-fourth transistor M64, the sixty-sixth transistor M66, the sixty-eighth transistor M68, and the seventieth transistor M70. The mirrored third current (which includes four sub-currents) is used to provide bias current for the second comparator unit 121, and the mirrored fourth current is used to charge the second capacitor unit 122.

[0087] When the first enable signal EN1 is low, the fifty-ninth transistor M59 is turned on under the control of the first enable signal EN1, and the second current unit 124 cannot output current normally. At this time, the second enable signal EN2 should be high, that is, the second soft-start module 12 does not work.

[0088] It should be noted that the second preset voltage is , where I M62 For the current flowing through the sixty-second transistor M62, I M53 K2 is the current flowing through the fifty-third transistor M53, and K2 is a coefficient.

[0089] This application also provides an analog integrated circuit, including the soft-start circuit described above. Since the electronic device provided in this application adopts all the technical solutions of all the above embodiments, it possesses at least all the beneficial effects brought about by the technical solutions of the above embodiments, and will not be elaborated further here.

[0090] For example, analog integrated circuits can be high-voltage operational amplifiers, source drivers for LCD panels, motor drive circuits, etc.

[0091] This application also provides an electronic device including the analog integrated circuit described above. Since the electronic device provided in this application employs all the technical solutions of all the above embodiments, it possesses at least all the beneficial effects brought about by the technical solutions of the above embodiments, and will not be elaborated upon further here. The electronic device provided in this application can be any electronic device containing the analog integrated circuit described above.

[0092] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0093] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A soft start circuit for reducing inrush current, characterized by, The soft start circuit comprises a first soft start module, a second soft start module and an operational amplifier module, the first input end of the operational amplifier module is connected with the first soft start module, the second input end of the operational amplifier module is connected with the second soft start module, and the output end of the operational amplifier module is connected with the input end of the analog integrated circuit; The first soft start module is used for outputting a first target voltage rising at a first rate according to a first reference voltage and a first preset code value, and rising to the first reference voltage within a preset time; The second soft start module is used for outputting a second target voltage rising at a second rate according to a second reference voltage and a second preset code value, and rising to the second reference voltage within a preset time; the operational amplifier module is used for determining the change direction of the input voltage of the analog integrated circuit according to the first target voltage and the second target voltage; wherein the first preset code value corresponds to the second reference voltage, and the second preset code value corresponds to the first reference voltage; The first soft start module comprises a first comparison unit, a first capacitor unit, a first logic unit, a second logic unit and a first current unit, the first current unit is connected with the first comparison unit and the first capacitor unit respectively, the first comparison unit is connected with the first capacitor unit and the second logic unit respectively, and the first capacitor unit is connected with the first comparison unit, the first logic unit, the second logic unit and the operational amplifier module respectively; The first logic unit is used for outputting a third preset code value according to the first preset code value; the first capacitor unit is used for determining the capacitance value according to the third preset code value, so as to make the first target voltage rise to the first reference voltage within a preset time; the first current unit is used for outputting a first current and a second current according to a first enable signal; the first comparison unit is used for outputting a first level signal according to the first reference voltage, the first target voltage and the first current; the second logic unit is used for being turned off according to the first level signal; the first capacitor unit is also used for starting charging according to a second enable signal, the first level signal and the second current, so as to make the first target voltage rise at the first rate; when the first target voltage is greater than a first preset voltage, the first comparison unit outputs a second level signal; the first capacitor unit is also used for stopping charging according to the second level signal; and the second logic unit is also used for being turned on according to the second level signal, so as to switch the first target voltage to the first reference voltage.

2. The soft start circuit to reduce inrush current according to claim 1, characterized in that, The operation amplification module comprises a first operation amplifier, a second operation amplifier, a first resistor and a second resistor, the first input end of the first operation amplifier is connected with the first soft start module, the first input end of the second operation amplifier is connected with the second soft start module, the second input end of the first operation amplifier is connected with the first end of the first resistor and the first end of the second resistor respectively, the second end of the second resistor is connected with the output end of the first operation amplifier and the input end of the analog integrated circuit respectively, and the first end of the first resistor is connected with the output end of the second operation amplifier and the second input end of the second operation amplifier respectively.

3. The soft start circuit to reduce inrush current of claim 1, wherein, The first logic unit comprises a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a seventh inverter, an eighth inverter, a first AND gate, a second AND gate and a NAND gate; an input end of the first inverter is used for receiving a first bit code value in a first preset code value, an output end of the first inverter is used for outputting a first bit code value in a third preset code value and is connected with the first capacitor unit, an input end of the second inverter is used for receiving a second bit code value in the first preset code value, an output end of the second inverter is used for outputting a second bit code value in the third preset code value and is connected with the first capacitor unit, an input end of the third inverter is used for receiving a third bit code value in the first preset code value, an output end of the third inverter is used for outputting a third bit code value in the third preset code value and is connected with the first capacitor unit, an input end of the fourth inverter is used for receiving a fourth bit code value in the first preset code value, an output end of the fourth inverter is used for outputting a fourth bit code value in the third preset code value and is connected with the first capacitor unit, an input end of the fifth inverter is used for receiving a fifth bit code value in the first preset code value, an output end of the fifth inverter is used for outputting a fifth bit code value in the third preset code value and is connected with the first capacitor unit, an input end of the sixth inverter is used for receiving a sixth bit code value in the first preset code value, an output end of the sixth inverter is used for outputting a sixth bit code value in the third preset code value and is connected with the first capacitor unit, an input end of the seventh inverter is used for receiving a seventh bit code value in the first preset code value, an input end of the eighth inverter is used for receiving an eighth bit code value in the first preset code value, an output end of the seventh inverter is used for outputting a seventh bit code value in the third preset code value and is connected with a first input end of the first AND gate, a first input end of the NAND gate and the first capacitor unit respectively, an output end of the eighth inverter is used for outputting an eighth bit code value in the third preset code value and is connected with a second input end of the first AND gate, a first input end of the second AND gate and the first capacitor unit respectively, a second input end of the NAND gate receives a power supply voltage, an output end of the first AND gate is used for outputting a ninth bit code value in the third preset code value and is connected with the first capacitor unit, an output end of the NAND gate is connected with a second input end of the second AND gate, an output end of the second AND gate is used for outputting a tenth bit code value in the third preset code value and is connected with the first capacitor unit.

4. The soft start circuit to reduce inrush current of claim 1, wherein, The first capacitor unit includes a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor and a thirteenth transistor; a first end of the first capacitor is connected with a source electrode of the first transistor, a gate electrode of the first transistor is connected with the first logic unit, for receiving a first bit code value in the third preset code value, drain electrodes of the first transistor are respectively connected with drain electrodes of the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the twelfth transistor, the thirteenth transistor, the first comparison unit, the second logic unit and the operational amplification module, a gate electrode of the thirteenth transistor is respectively connected with a drain electrode of the eleventh transistor, the first comparison unit and the second logic unit, a source electrode of the thirteenth transistor is connected with the first current unit, a gate electrode of the eleventh transistor and a gate electrode of the twelfth transistor are both for receiving a second enable signal, a first end of the second capacitor is connected with a source electrode of the second transistor, a gate electrode of the second transistor is connected with the first logic unit, for receiving a second bit code value in the third preset code value, a first end of the third capacitor is connected with a source electrode of the third transistor, a gate electrode of the third transistor is connected with the first logic unit, for receiving a third bit code value in the third preset code value, a first end of the fourth capacitor is connected with a source electrode of the fourth transistor, a gate electrode of the fourth transistor is connected with the first logic unit, for receiving a fourth bit code value in the third preset code value, a first end of the fifth capacitor is connected with a source electrode of the fifth transistor, a gate electrode of the fifth transistor is connected with the first logic unit, for receiving a fifth bit code value in the third preset code value, a first end of the sixth capacitor is connected with a source electrode of the sixth transistor, a gate electrode of the sixth transistor is connected with the first logic unit, for receiving a sixth bit code value in the third preset code value, a first end of the seventh capacitor is connected with a source electrode of the seventh transistor, a gate electrode of the seventh transistor is connected with the first logic unit, for receiving a seventh bit code value in the third preset code value, a first end of the eighth capacitor is connected with a source electrode of the eighth transistor, a gate electrode of the eighth transistor is connected with the first logic unit, for receiving a tenth bit code value in the third preset code value, a first end of the ninth capacitor is connected with a source electrode of the ninth transistor, a gate electrode of the ninth transistor is connected with the first logic unit, for receiving a ninth bit code value in the third preset code value,A first end of the tenth capacitor is connected with a source of the tenth transistor, a gate of the tenth transistor is connected with the first logic unit, for an eighth bit code value in the third preset code value, a second end of the first capacitor, a second end of the second capacitor, a second end of the third capacitor, a second end of the fourth capacitor, a second end of the fifth capacitor, a second end of the sixth capacitor, a second end of the seventh capacitor, a second end of the eighth capacitor, a second end of the ninth capacitor, a second end of the tenth capacitor, a source of the eleventh transistor and a source of the twelfth transistor are grounded.

5. The soft start circuit to reduce inrush current of claim 1, wherein, The first comparison unit comprises a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a third resistor and a fourth resistor; a gate of the fourteenth transistor is used for receiving a first reference voltage, sources of the fourteenth transistor and the fifteenth transistor are connected with the first current unit respectively, a drain of the fourteenth transistor is connected with a first end of the third resistor and a source of the seventeenth transistor respectively, a gate of the fifteenth transistor receives a first target voltage, a drain of the fifteenth transistor is connected with a first end of the fourth resistor, a source of the sixteenth transistor and a drain of the eighteenth transistor respectively, a gate of the sixteenth transistor is connected with a gate of the seventeenth transistor, a drain of the sixteenth transistor and the first current unit respectively, a drain of the seventeenth transistor is connected with the first current unit, a gate of the eighteenth transistor, the first capacitor unit and the second logic unit respectively, a source of the eighteenth transistor is connected with the first current unit, and second ends of the third resistor and the fourth resistor are grounded.

6. The soft start circuit to reduce inrush current of claim 1, wherein, The second logic unit comprises a nineteenth transistor, a twentieth transistor, a twenty-first transistor, a twenty-second transistor and a twenty-third transistor; sources of the nineteenth transistor and the twenty-first transistor receive a power supply voltage, a gate of the nineteenth transistor is connected with a gate of the twentieth transistor, the first comparison unit and the first capacitor unit respectively, a drain of the nineteenth transistor is connected with a drain of the twentieth transistor, a gate of the twenty-first transistor and a gate of the twenty-second transistor respectively, a drain of the twenty-first transistor is connected with a drain of the twenty-second transistor and a gate of the twenty-third transistor respectively, a drain of the twenty-third transistor is used for receiving the first reference voltage, sources of the twenty-third transistor are connected with the first comparison unit, the first capacitor unit and the operational amplification module respectively, and sources of the twentieth transistor and the twenty-second transistor are grounded.

7. The soft start circuit to reduce inrush current of claim 1, wherein, The first current unit includes a twenty-fourth transistor, a twenty-fifth transistor, a twenty-sixth transistor, a twenty-seventh transistor, a twenty-eighth transistor, a twenty-ninth transistor, a thirtieth transistor, a thirty-first transistor, a thirty-second transistor, a thirty-third transistor, a thirty-fourth transistor, a thirty-fifth transistor, a thirty-sixth transistor and a first current source; the source of the twenty-fourth transistor, the source of the twenty-fifth transistor, the source of the twenty-seventh transistor, the source of the twenty-ninth transistor, the source of the thirty-first transistor, the source of the thirty-third transistor and the source of the thirty-fifth transistor all receive a power supply voltage, the gate of the twenty-fourth transistor is configured to receive a first enable signal, the drain of the twenty-fourth transistor is connected with the drain of the twenty-fifth transistor, the gate of the twenty-fifth transistor, the gate of the twenty-seventh transistor, the gate of the twenty-ninth transistor, the gate of the thirty-first transistor, the gate of the thirty-third transistor, the gate of the thirty-fifth transistor and the source of the twenty-sixth transistor respectively, the gate of the twenty-sixth transistor, the gate of the twenty-eighth transistor, the gate of the thirtieth transistor, the gate of the thirty-second transistor, the gate of the thirty-fourth transistor and the gate of the thirty-sixth transistor all receive a first bias voltage, the drain of the twenty-sixth transistor is connected with a first end of the first current source, a second end of the first current source is grounded, the drain of the twenty-seventh transistor is connected with the source of the twenty-eighth transistor, the drain of the twenty-eighth transistor is connected with the first comparison unit, the drain of the twenty-ninth transistor is connected with the source of the thirtieth transistor, the drain of the thirtieth transistor is connected with the first comparison unit, the drain of the thirty-first transistor is connected with the source of the thirty-second transistor, the drain of the thirty-second transistor is connected with the first comparison unit, the drain of the thirty-third transistor is connected with the source of the thirty-fourth transistor, the drain of the thirty-fourth transistor is connected with the first comparison unit, the drain of the thirty-fifth transistor is connected with the source of the thirty-sixth transistor, and the drain of the thirty-sixth transistor is connected with the first capacitor unit.

8. The soft start circuit to reduce inrush current according to claim 1 or 2, characterized in that, The second soft start module includes a second comparison unit, a second capacitor unit, a third logic unit and a second current unit, the second current unit is connected with the second comparison unit and the second capacitor unit respectively, the second comparison unit is connected with the second capacitor unit and the third logic unit respectively, and the second capacitor unit is connected with the second comparison unit, the third logic unit and the operational amplifier module respectively. The second capacitor unit is configured to determine its capacitance value according to the second preset code value, so as to make the second target voltage rise to a second reference voltage within a preset time. The second current unit is configured to output a third current and a fourth current according to a first enable signal; the second comparison unit is configured to output a third level signal according to the second reference voltage, the second target voltage and the third current; The third logic unit is configured to be turned off according to the third level signal; the second capacitor unit is further configured to start charging according to a second enable signal, the third level signal and the third current, and to make the second target voltage rise at a second rate; When the second target voltage is greater than a second preset voltage, the second comparison unit outputs a fourth level signal; the second capacitor unit is further configured to stop charging according to the fourth level signal; and the third logic unit is further configured to be turned on according to the fourth level signal, and to switch the second target voltage to a second reference voltage.

9. The soft start circuit to reduce inrush current of claim 8, wherein, The second capacitor unit includes an eleventh capacitor, a twelfth capacitor, a thirteenth capacitor, a fourteenth capacitor, a fifteenth capacitor, a sixteenth capacitor, a seventeenth capacitor, an eighteenth capacitor, a nineteenth capacitor, a thirty-seventh transistor, a thirty-eighth transistor, a thirty-ninth transistor, a fortieth transistor, a forty-first transistor, a forty-second transistor, a forty-third transistor, a forty-fourth transistor, a forty-fifth transistor, a forty-sixth transistor, a forty-seventh transistor, and a forty-eighth transistor.A first end of the eleventh capacitor is connected with a source electrode of the thirty-seventh transistor, a gate electrode of the thirty-seventh transistor is used for receiving a first bit code value in the second preset code value, drain electrodes of the thirty-seventh transistor are respectively connected with a drain electrode of the thirty-eighth transistor, a drain electrode of the thirty-ninth transistor, a drain electrode of the fortieth transistor, a drain electrode of the forty-first transistor, a drain electrode of the forty-second transistor, a drain electrode of the forty-third transistor, a drain electrode of the forty-fourth transistor, a drain electrode of the forty-fifth transistor, a drain electrode of the forty-seventh transistor, a drain electrode of the forty-eighth transistor, the second comparison unit, the third logic unit and the operational amplification module, a source electrode of the forty-eighth transistor is connected with the second current unit, gate electrodes of the forty-eighth transistor are respectively connected with a drain electrode of the forty-sixth transistor, the second comparison unit and the third logic unit, the gate electrode of the forty-sixth transistor and the gate electrode of the forty-seventh transistor are both used for receiving a second enable signal, a first end of the twelfth capacitor is connected with a source electrode of the thirty-eighth transistor, a gate electrode of the thirty-eighth transistor is used for receiving a second bit code value in the second preset code value, a first end of the thirteenth capacitor is connected with a source electrode of the thirty-ninth transistor, a gate electrode of the thirty-ninth transistor is used for receiving a third bit code value in the second preset code value, a first end of the fourteenth capacitor is connected with a source electrode of the fortieth transistor, a gate electrode of the fortieth transistor is used for receiving a fourth bit code value in the second preset code value, a first end of the fifteenth capacitor is connected with a source electrode of the forty-first transistor, a gate electrode of the forty-first transistor is used for receiving a fifth bit code value in the second preset code value, a first end of the sixteenth capacitor is connected with a source electrode of the forty-second transistor, a gate electrode of the forty-second transistor is used for receiving a sixth bit code value in the second preset code value, a first end of the seventeenth capacitor is connected with a source electrode of the forty-third transistor, a gate electrode of the forty-third transistor is used for receiving a seventh bit code value in the second preset code value, a first end of the eighteenth capacitor is connected with a source electrode of the forty-fourth transistor, a gate electrode of the forty-fourth transistor is used for receiving an eighth bit code value in the second preset code value, a first end of the nineteenth capacitor is connected with a source electrode of the forty-fifth transistor, a gate electrode of the forty-fifth transistor receives a power supply voltage, second ends of the eleventh capacitor, the twelfth capacitor, the thirteenth capacitor, the fourteenth capacitor, the fifteenth capacitor, the sixteenth capacitor, the seventeenth capacitor, the eighteenth capacitor, the nineteenth capacitor, a source electrode of the forty-sixth transistor and a source electrode of the forty-seventh transistor are all grounded.

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