Inverter circuit and method for adaptively adjusting dynamic crossover point of inverter circuit

Abstract

The invention provides an inverter circuit and a method for adaptively adjusting a dynamic crossover point of the inverter circuit. The inverter circuit comprises a first metal oxide semiconductor transistor, a second metal oxide semiconductor transistor, an adjustable pull-up circuit, an adjustable pull-down circuit and a control circuit. The first metal oxide semiconductor transistor is provided with a control end for receiving a first input signal, a first connecting end and a second connecting end. The second metal oxide semiconductor transistor has a control terminal for receiving the first input signal, a first connection terminal, and a second connection terminal coupled to the second connection terminal of the first metal oxide semiconductor transistor. The adjustable pull-up circuit is coupled between a first connection terminal of the first metal oxide semiconductor transistor and a first reference voltage. The adjustable pull-down circuit is coupled between the first connection end of the second metal oxide semiconductor transistor and a second reference voltage. The control circuit adaptively adjusts the pull-up strength of the adjustable pull-up circuit and the pull-down strength of the adjustable pull-down circuit.

Description

Technical Field

[0001] This invention relates to inverter design, and more particularly to an inverter circuit with a dynamic crossing point and a method for adaptively adjusting the dynamic crossing point of the inverter circuit. Background Technology

[0002] A limiting amplifier (LA) is used to amplify the output of a transimpedance amplifier (TIA) to a reliable voltage level. Ideally, the output level of the limiting amplifier should be a fixed value regardless of the input level. For example, a limiting amplifier may contain a gain stage, an alternating current (AC) coupling stage, and one or more limiting amplifier stages. However, the limiting amplifier stage may contain a slicer that receives the input signal of the limiting amplifier stage, which includes duty cycle errors caused by the gain stage (which transmits transimpedance amplifier noise to the input signal of the limiting amplifier stage) and / or baseline wander caused by the AC coupling stage located after the gain stage. The slicer can be simply implemented using a complementary metal-oxide-semiconductor (CMOS) inverter. Therefore, an innovative inverter design is needed to address the duty cycle error problem and / or baseline wander problem. Summary of the Invention

[0003] One of the objectives of this invention is to provide an inverter circuit with a dynamic crossover point and a method for adaptively adjusting the dynamic crossover point of the inverter circuit.

[0004] In one embodiment of the present invention, an inverter circuit is disclosed. The inverter circuit includes a first metal-oxide-semiconductor (MOS) transistor, a second MOS transistor, an adjustable pull-up circuit, an adjustable pull-down circuit, and a control circuit. The first MOS transistor has a control terminal, a first connection terminal, and a second connection terminal for receiving a first input signal of the inverter circuit. The second MOS transistor has a control terminal, a first connection terminal, and a second connection terminal coupled to the second connection terminal of the first MOS transistor for receiving the first input signal of the inverter circuit. The adjustable pull-up circuit is coupled between the first connection terminal of the first MOS transistor and a first reference voltage. The adjustable pull-down circuit is coupled between the first connection terminal of the second MOS transistor and a second reference voltage. The control circuit is used to adaptively adjust the pull-up strength of the adjustable pull-up circuit and the pull-down strength of the adjustable pull-down circuit.

[0005] In one embodiment of the present invention, a method for adaptively adjusting the dynamic crossover point of an inverter circuit is disclosed. The method includes: receiving a first input signal of the inverter circuit at a control terminal of a first metal-oxide-semiconductor transistor and a control terminal of a second metal-oxide-semiconductor transistor; and adaptively adjusting the pull-up strength of an adjustable pull-up circuit and the pull-down strength of an adjustable pull-down circuit, wherein the adjustable pull-up circuit is coupled between a first connection terminal of the first metal-oxide-semiconductor transistor and a first reference voltage, the adjustable pull-down circuit is coupled between a first connection terminal of the second metal-oxide-semiconductor transistor and a second reference voltage, and a second connection terminal of the first metal-oxide-semiconductor transistor is coupled to a second connection terminal of the second metal-oxide-semiconductor transistor.

[0006] The dynamic crossover inverter proposed in this invention facilitates easier level transitions for unhealthy input signals (represented by relatively small input swings that do not fully transition from low to high logic levels). For example, the dynamic crossover inverter proposed in this invention can solve the duty cycle error problem encountered by standard inverters. Furthermore, the cross-coupled dynamic crossover inverter proposed in this invention can solve the duty cycle error and baseline drift problems encountered by standard inverters. Attached Figure Description

[0007] Figure 1 This is a schematic diagram of an inverter circuit operating in the first output state OUT = high level, according to an embodiment of the present invention.

[0008] Figure 2 This is a schematic diagram of an inverter circuit operating in the second output state OUT = low level, according to an embodiment of the present invention.

[0009] Figure 3 The operation flowchart of the inverter circuit shown in Figures 1 and 2 is an embodiment of the present invention.

[0010] Figure 4 This is a comparison diagram of a standard inverter with a fixed X point and a dynamic crossover inverter with a dynamic X point proposed in this invention.

[0011] Figure 5 This is a schematic diagram of another inverter circuit according to an embodiment of the present invention.

[0012] [Symbol Explanation]

[0013] 100, 500: Inverter circuit

[0014] 102: Adjustable pull-up circuit

[0015] 104: Adjustable pull-down circuit

[0016] 106: Control Circuit

[0017] 502_1, 502_2: Dynamic crossover inverters

[0018] 504_1, 504_2: Standard inverters

[0019] M1, M2, M3, M4, M5, M6, M11, M21, M31, M41, M51, M61, M71, M81, M12, M22, M32, M42, M52, M62, M72, M82: Metal-oxide-semiconductor transistors

[0020] IN: Input signal

[0021] INP: Positive Input Signal

[0022] INN: Negative Input Signal

[0023] OUT: Output signal

[0024] INV1, INV2, INV11, INV21, INV12, INV22: Inverters

[0025] OUT_D: Control signal

[0026] VDD: Supply voltage

[0027] GND: Grounding voltage

[0028] S1: Input signal of the first inverter

[0029] S2: Output signal of the first inverter

[0030] S3: Input signal for the second inverter

[0031] S4: Output signal of the second inverter

[0032] S302, S304, S306, S308, S310, S312, S314: Steps Detailed Implementation

[0033] Certain terms are used in the specification and claims to refer to specific elements. Those skilled in the art will understand that hardware manufacturers may use different names to refer to the same element. This specification and claims do not distinguish elements based on differences in name, but rather on differences in function. The terms "comprising" and "including" used throughout the specification and claims are open-ended and should be interpreted as "comprising but not limited to." Furthermore, the term "coupled" or "coupled" herein includes any direct and indirect electrical connection means. Therefore, if a first device is described as coupled to a second device, it means that the first device can be directly electrically connected to the second device, or indirectly electrically connected to the second device through other devices and connection means.

[0034] Figure 1 This is a schematic diagram of an inverter circuit operating in a first output state OUT = High, according to an embodiment of the present invention. The inverter circuit 100 may be part of a clipping unit in a limiting amplifier; however, this is merely illustrative and not intended to limit the invention. In fact, any signal processing circuit using the inverter circuit 100 falls within the scope of this invention. In this embodiment, the inverter circuit 100 is a dynamically crossover inverter (DX-INV) with a dynamic crossing point (hereinafter referred to as "X point"). Figure 1As shown, the inverter circuit 100 includes a metal-oxide-semiconductor (MOS) transistor (e.g., a P-type metal-oxide-semiconductor (PMOS) transistor) M1, a MOS transistor (e.g., an N-type metal-oxide-semiconductor (NMOS) transistor) M2, an adjustable pull-up circuit 102, an adjustable pull-down circuit 104, and a control circuit 106. The MOS transistor M1 has a control terminal (e.g., gate) for receiving the input signal IN of the inverter circuit 100, a first connection terminal (e.g., source), and a second connection terminal (e.g., drain). The MOS transistor M2 has a control terminal (e.g., gate) for receiving the input signal IN from the inverter circuit 100, a first connection terminal (e.g., source) and a second connection terminal (e.g., drain) connected to the second connection terminal (e.g., drain) of the MOS transistor M1. Therefore, an output signal OUT is generated at the second connection terminal (e.g., drain) of the MOS transistors M1 and M2.

[0035] An adjustable pull-up circuit 102 is coupled between a first terminal (e.g., the source) of MOS transistor M1 and a first reference voltage (e.g., the supply voltage VDD). An adjustable pull-down circuit 104 is coupled between a first terminal (e.g., the source) of MOS transistor M2 and a second reference voltage (e.g., the ground voltage GND). A control circuit 106 is used to adaptively adjust the pull-up strength of the adjustable pull-up circuit 102 and the pull-down strength of the adjustable pull-down circuit 104.

[0036] In this embodiment, the adjustable pull-up circuit 102 includes parallel MOS transistors (e.g., PMOS transistors) M3 and M5. MOS transistor M3 has a control terminal (e.g., gate) connected to a second reference voltage (e.g., ground voltage GND), a first connection terminal (e.g., source) connected to a first reference voltage (e.g., supply voltage VDD), and a second connection terminal (e.g., drain) connected to the first connection terminal (e.g., source) of MOS transistor M1. MOS transistor M5 has a control terminal (e.g., gate) for receiving a control signal OUT_D, a first connection terminal (e.g., source) connected to the first reference voltage (e.g., supply voltage VDD), and a second connection terminal (e.g., drain) connected to the first connection terminal (e.g., source) of MOS transistor M1. Since MOS transistor M3 is biased by ground voltage GND, it is turned on to provide a fixed resistance value. The on / off status of MOS transistor M5 is adaptively controlled based on the logic level of the control signal OUT_D.

[0037] The adjustable pull-down circuit 104 includes MOS transistors (e.g., NMOS transistors) M4 and M6. MOS transistor M4 has a control terminal (e.g., gate) connected to a first reference voltage (e.g., supply voltage VDD), a first connection terminal (e.g., source) connected to a second reference voltage (e.g., ground voltage GND), and a second connection terminal (e.g., drain) connected to the first connection terminal (e.g., source) of MOS transistor M2. MOS transistor M6 has a control terminal (e.g., gate) for receiving a control signal OUT_D, a first connection terminal (e.g., source) connected to the second reference voltage (e.g., ground voltage GND), and a second connection terminal (e.g., drain) connected to the first connection terminal (e.g., source) of MOS transistor M2. Since MOS transistor M4 is biased by the supply voltage VDD, it is turned on to provide a fixed resistance value. The on / off state of MOS transistor M6 is adaptively controlled according to the logic level of the control signal OUT_D.

[0038] In this embodiment, the control circuit 106 can generate the control signal OUT_D required to achieve the dynamic X point. For example, the control circuit 106 can be implemented using inverters INV1 and INV2 connected in series. Inverter INV1 is used to receive a first inverter input signal S1 derived from the output signal OUT (e.g., S1=OUT), and to generate a first inverter output signal S2 based on the first inverter input signal S1 (i.e., ...). Inverter INV2 is used to receive a second inverter input signal S3 derived from the first inverter output signal S2 (e.g., S3 = S2), and to generate a second inverter output signal S4 based on the second inverter input signal S3 (i.e., ...). The output signal S4 of the second inverter can be used as the control signal OUT_D for both the adjustable pull-up circuit 102 and the adjustable pull-down circuit 104.

[0039] Specifically, the control circuit 106 receives the output signal OUT generated at the second connection terminal (e.g., drain) of MOS transistors M1 and M2, and adjusts the pull-up and pull-down strengths according to the output signal OUT, wherein the logic level of the control signal OUT_D is the same as the logic level of the output signal OUT. In this embodiment, when the output signal OUT has a high logic level due to the low logic level of the input signal IN (e.g., OUT=High), MOS transistor M6 is turned on, and MOS transistor M5 is not turned on. Figure 1 As shown, the pull-up strength is lower than the pull-down strength, resulting in a lower X point, which is beneficial for the transition of the output level from 1 to 0. Therefore, when the current input state is 0 and the next input state is 1, the X point will be set to a lower level because the current input state is 0. And because the lower X point can cause earlier crossing, the transition from the current output state 1 to the next output state 0 can start earlier.

[0040] Figure 2 This is a schematic diagram of an inverter circuit operating in the second output state OUT = Low, according to an embodiment of the present invention. In this embodiment, when the output signal OUT has a low logic level because the input signal IN is a high logic level (e.g., OUT = Low), MOS transistor M6 is not turned on, and MOS transistor M5 is turned on. Figure 2 As shown, the pull-up strength is higher than the pull-down strength, resulting in a higher X point, which is beneficial for the transition of the output level from 0 to 1. Therefore, when the current input state is 1 and the next input state is 0, the X point will be set to a higher level because the current input state is 1. Furthermore, since the higher X point can cause crossover to occur earlier, the transition from the current output state 0 to the next output state 1 can start earlier.

[0041] Figure 3This is a flowchart of the operation of the inverter circuit 100 shown in Figures 1 and 2 of an embodiment of the present invention. In step S302, it is checked whether the voltage level of the input signal IN is lower than the current level of point X. If the voltage level of the input signal IN is lower than the current level of point X, the output signal OUT will have a high logic level due to the transition from low logic level to high logic level (step S304). Therefore, the output node of inverter INV1 has a low logic level, the output node of inverter INV2 has a high logic level, MOS transistor M5 is not turned on, MOS transistor M6 is turned on, and point X will drop from the current level to a lower level (step S306). In step S308, it is checked whether the input signal IN has changed from a low logic level to a high logic level. If the input signal IN has not changed from a low logic level to a high logic level, the current level of point X (i.e., the lower level) will remain unchanged, and the process will enter step S308 again. If the input signal IN has changed from a low logic level to a high logic level, the process will enter step S310.

[0042] It should be noted that if the voltage level of the input voltage IN is not lower than the current level of point X (step S302) or the input signal IN has a transition from a low logic level to a high logic level (step S308), the process proceeds to step S310. In step S310, since the output signal OUT will have a low logic level due to the transition from a high logic level to a low logic level, the output node of inverter INV1 becomes a high logic level, the output node of inverter INV2 becomes a low logic level, MOS transistor M5 is turned on, MOS transistor M6 is not turned on, and point X rises from the current level to a higher level (step S312). In step S314, it is checked whether the input signal IN has a transition from a high logic level to a low logic level. If the input signal IN does not have a transition from a high logic level to a low logic level, the current level of point X (i.e., the higher level) will remain unchanged, and the process will again proceed to step S314. If the input signal IN has a transition from a high logic level to a low logic level, the process proceeds to step S304. It should be noted that if the voltage level of the input voltage IN is lower than the current level of point X (step S302) or the input signal IN has a transition from a high logic level to a low logic level (step S314), the process will proceed to step S304.

[0043] Figure 4This is a comparison diagram of a standard inverter (STD-INV) with a fixed X-point and a dynamic crossover inverter (DX-INV) with a dynamic X-point proposed in this invention. The DX-INV proposed in this invention can lower the X-point (which corresponds to the specific time point at which the output signal OUT begins to transition from a high logic level when the input signal IN transitions from a low logic level to a predetermined voltage level, and vice versa) to a lower level, making the 1→0 transition time T1' of the DX-INV output earlier than the 1→0 transition time T1 of the STD-INV output. Furthermore, the DX-INV proposed in this invention can raise the X-point to a higher level, making the 0→1 transition time T2' of the DX-INV output earlier than the 0→1 transition time T2 of the STD-INV output. Figure 4 As shown, DX-INV has a large input difference. / ( & The output swing generated by the DX-INV is greater than that of the STD-INV. Therefore, the DX-INV proposed in this invention can make the level transition of unhealthy input signals (which represent relatively small input swings that do not fully cross from low logic level to high logic level) easier. For example, the DX-INV proposed in this invention can solve the duty cycle error problem encountered by the STD-INV.

[0044] Figure 1 The inverter circuit 100 shown is a dynamic crossover inverter (DX-INV) with a dynamic X-point. In some embodiments of the invention, this dynamic crossover inverter (DX-INV) can be used as an auxiliary circuit to assist the level transition of a standard inverter (STD-INV) at its output node.

[0045] Figure 5 This is a schematic diagram of another inverter circuit according to an embodiment of the present invention. The inverter circuit 500 may be part of a clipping unit in a limiting amplifier; however, this is merely illustrative and not intended to limit the invention. In fact, any signal processing circuit using the inverter circuit 500 falls within the scope of this invention. In this embodiment, the inverter circuit 500 is a cross-coupled dynamic crossover inverter. Figure 5 As shown, the inverter circuit 500 includes multiple dynamic crossover inverters 502_1, 502_2 and multiple standard inverters 504_1, 504_2. Each dynamic crossover inverter 502_1, 502_2 can have the same characteristics as... Figure 1The inverter circuit 100 shown has the same circuit structure; therefore, the dynamic crossover inverter 502_1 includes MOS transistors M11, M21, M31, M41, M51, M61 and inverters INV11 and INV21; another dynamic crossover inverter 502_2 includes MOS transistors M12, M22, M32, M42, M52, M62 and inverters INV12 and INV22. In this embodiment, the inverter circuit 500 is a differential circuit that receives a differential input consisting of a positive input signal INP and a negative input signal INN. Regarding the dynamic crossover inverter 502_1, the control terminals (e.g., gates) of MOS transistors M11 and M21 receive the positive input signal INP. Regarding the dynamic crossover inverter 502_2, the control terminals (e.g., gates) of MOS transistors M12 and M22 receive the negative input signal INN. Since those skilled in the art should be able to easily understand the operating principles of the dynamic crossover inverters 502_1 and 502_2 after reading the above paragraphs concerning inverter circuit 100, similar descriptions are omitted here for the sake of brevity.

[0046] Standard inverters 504_1 and 504_2 have the same circuit structure. Regarding standard inverter 504_1, MOS transistor (e.g., PMOS transistor) M71 has a control terminal (e.g., gate) for receiving the positive input signal INP of the differential input, a first connection terminal (e.g., source) coupled to a first reference voltage (e.g., supply voltage VDD), and a second connection terminal (e.g., drain) coupled to the output terminal of inverter INV12 included in dynamic crossover inverter 502_2; and MOS transistor (e.g., NMOS transistor) M81 has a control terminal (e.g., gate) for receiving the positive input signal INP of the differential input, a first connection terminal (e.g., source) coupled to a second reference voltage (e.g., ground voltage GND), and a second connection terminal (e.g., drain) coupled to MOS transistor M71 and the output terminal of inverter INV12 included in dynamic crossover inverter 502_2.

[0047] Regarding the standard inverter 504_2, the MOS transistor (e.g., PMOS transistor) M72 has a control terminal (e.g., gate) for receiving the negative input signal INN of the differential input, a first connection terminal (e.g., source) coupled to a first reference voltage (e.g., supply voltage VDD), and a first connection terminal (e.g., drain) coupled to the output terminal of the inverter INV11 included in the dynamic crossover inverter 502_1; and the MOS transistor (e.g., NMOS transistor) M82 has a control terminal (e.g., gate) for receiving the negative input signal INN of the differential input, a first connection terminal (e.g., source) coupled to a second reference voltage (e.g., ground voltage GND), and a second connection terminal (e.g., drain) coupled to the second connection terminal of the MOS transistor M72 and the output terminal of the inverter INV11 included in the dynamic crossover inverter 502_1.

[0048] Standard inverters 504_1 and 504_2 serve as the primary paths of inverter circuit 500, while dynamic crossover inverters 502_1 and 502_2 serve as auxiliary paths. Inverter circuit 500 with the cross-coupled dynamic crossover inverter architecture proposed in this invention can be considered a voltage-mode slicer that requires no reset clock input. The cross-coupling connection allows a sufficiently high-gain dynamic crossover inverter 502_1 (with an earlier transition time due to the dynamic X point) to assist the level transition of the output node of the standard inverter 504_2 with a fixed X point, and also allows a sufficiently high-gain dynamic crossover inverter 502_2 (with an earlier transition time due to the dynamic X point) to assist the level transition of the output node of the standard inverter 504_1 with a fixed X point. For example, the cross-coupled dynamic crossover inverter proposed in this invention can solve the duty cycle error and baseline drift problems encountered by standard inverters.

[0049] Consider the cases where the positive input signal INP has a low-to-high level transition and the negative input signal INN has a high-to-low level transition. The input of inverter INV21, included in the dynamic crossover inverter 502_1, will have a low-to-high level transition, and this transition will begin earlier than the low-to-high level transition of the output of the standard inverter 504_2. Similarly, the input of inverter INV22, included in the dynamic crossover inverter 502_2, will have a high-to-low level transition, and this transition will begin earlier than the high-to-low level transition of the output of the standard inverter 504_1. In this way, the low-to-high level transition of the output of the standard inverter 504_2 can be enhanced by the dynamic crossover inverter 502_1, and the high-to-low level transition of the output of the standard inverter 504_1 can be enhanced by the dynamic crossover inverter 502_2.

[0050] Consider another case where the positive input signal INP has a high-to-low transition and the negative input signal INN has a low-to-high transition. The inverter INV21 included in the dynamic crossover inverter 502_1 has a high-to-low input transition, and this transition begins earlier than the high-to-low transition of the output of the standard inverter 504_2. The inverter INV22 included in the dynamic crossover inverter 502_2 has a low-to-high input transition, and this transition begins earlier than the low-to-high transition of the output of the standard inverter 504_1. In this way, the high-to-low transition of the output of the standard inverter 504_2 can be amplified by the dynamic crossover inverter 502_1, and the low-to-high transition of the output of the standard inverter 504_1 can be amplified by the dynamic crossover inverter 502_2.

[0051] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be within the scope of the present invention.

Claims

1. An inverter circuit, comprising: a first metal oxide semiconductor transistor having a control terminal to receive a first input signal of the inverter circuit, a first connection terminal, and a second connection terminal; a second metal oxide semiconductor transistor having a control terminal to receive the first input signal of the inverter circuit, a first connection terminal, and a second connection terminal coupled to the second connection terminal of the first metal oxide semiconductor transistor; an adjustable pull-up circuit coupled between the first connection terminal of the first metal oxide semiconductor transistor and a first reference voltage; an adjustable pull-down circuit coupled between the first connection terminal of the second metal oxide semiconductor transistor and a second reference voltage; and a control circuit to adaptively adjust a pull-up strength of the adjustable pull-up circuit and a pull-down strength of the adjustable pull-down circuit.

2. The inverter circuit of claim 1, wherein the control circuit is further to receive an output signal generated by the second connection terminal of the first metal oxide semiconductor transistor and the second connection terminal of the second metal oxide semiconductor transistor, and to adjust the pull-up strength and the pull-down strength in dependence on the output signal.

3. The inverter circuit of claim 2, wherein the pull-up strength is higher than the pull-down strength when the output signal has a first logic level, and the pull-up strength is lower than the pull-down strength when the output signal has a second logic level.

4. The inverter circuit of claim 2, wherein the control circuit comprises: a first inverter to receive a first inverter input signal derived from the output signal, and to generate a first inverter output signal in dependence on the first inverter input signal; and a second inverter to receive a second inverter input signal derived from the first inverter output signal, and to generate a second inverter output signal in dependence on the second inverter input signal, wherein the adjustable pull-up circuit and the adjustable pull-down circuit are both controlled in dependence on the second inverter output signal.

5. The inverter circuit of claim 4, wherein the adjustable pull-up circuit comprises: a third metal oxide semiconductor transistor having a control terminal to receive the second inverter output signal, a first connection terminal coupled to the first reference voltage, and a second connection terminal coupled to the first connection terminal of the first metal oxide semiconductor transistor; and the adjustable pull-down circuit comprises: a fourth metal oxide semiconductor transistor having a control terminal to receive the second inverter output signal, a first connection terminal coupled to the second reference voltage, and a second connection terminal coupled to the first connection terminal of the second metal oxide semiconductor transistor.

6. The inverter circuit of claim 4, further comprising: a third metal oxide semiconductor transistor having a control terminal to receive a second input signal of the inverter circuit, a first connection terminal coupled to the first reference voltage, and a second connection terminal coupled to an output terminal of the first inverter, wherein the first input signal and the second input signal are differential inputs of the inverter circuit; and ​ a fourth metal oxide semiconductor transistor having a control terminal to receive the second input signal of the inverter circuit, a first connection terminal coupled to the second reference voltage, and a second connection terminal coupled to the second connection terminal of the third metal oxide semiconductor transistor and the output terminal of the first inverter.

7. The inverter circuit of claim 1, wherein the inverter circuit is part of a clipper in a limiting amplifier.

8. A method for adaptively adjusting a dynamic crossover point of an inverter circuit, comprising: receiving a first input signal of the inverter circuit at a control terminal of a first metal oxide semiconductor transistor and a control terminal of a second metal oxide semiconductor transistor; and adaptively adjusting a pull-up strength of an adjustable pull-up circuit coupled between a first connection terminal of the first metal oxide semiconductor transistor and a first reference voltage, and a pull-down strength of an adjustable pull-down circuit coupled between a first connection terminal of the second metal oxide semiconductor transistor and a second reference voltage, wherein a second connection terminal of the first metal oxide semiconductor transistor is coupled to a second connection terminal of the second metal oxide semiconductor transistor.

9. The method of claim 8, wherein adaptively adjusting the pull-up strength of the adjustable pull-up circuit and the pull-down strength of the adjustable pull-down circuit comprises: receiving an output signal generated by the second connection terminal of the first metal oxide semiconductor transistor and the second connection terminal of the second metal oxide semiconductor transistor; and adjusting the pull-up strength and the pull-down strength in accordance with the output signal.

10. The method of claim 9, wherein the pull-up strength is higher than the pull-down strength when the output signal has a first logic level, and the pull-up strength is lower than the pull-down strength when the output signal has a second logic level.

11. The method of claim 9, wherein adjusting the pull-up strength and the pull-down strength in accordance with the output signal comprises: generating a first inverter output signal in accordance with a first inverter input signal derived from the output signal; generating a second inverter output signal in accordance with a second inverter input signal derived from the first inverter output signal; and controlling the adjustable pull-up circuit and the adjustable pull-down circuit in accordance with the second inverter output signal.

12. The method of claim 11, wherein controlling the adjustable pull-up circuit and the adjustable pull-down circuit in accordance with the second inverter output signal comprises: outputting the second inverter output signal to a control terminal of a third metal oxide semiconductor transistor included in the adjustable pull-up circuit, wherein a first connection terminal of the third metal oxide semiconductor transistor is coupled to the first reference voltage, and a second connection terminal of the third metal oxide semiconductor transistor is coupled to the first connection terminal of the first metal oxide semiconductor transistor; and outputting a complement of the second inverter output signal to a control terminal of a fourth metal oxide semiconductor transistor included in the adjustable pull-down circuit, wherein a first connection terminal of the fourth metal oxide semiconductor transistor is coupled to the second reference voltage, and a second connection terminal of the fourth metal oxide semiconductor transistor is coupled to the first connection terminal of the second metal oxide semiconductor transistor. outputting the second inverter output signal to a control terminal of a fourth metal oxide semiconductor transistor included in the adjustable pull-down circuit, wherein a first connection terminal of the fourth metal oxide semiconductor transistor is coupled to the second reference voltage, and a second connection terminal of the fourth metal oxide semiconductor transistor is coupled to the first connection terminal of the second metal oxide semiconductor transistor.

13. The method of claim 11, further comprising: receiving a second input signal of the inverter circuit at a control terminal of a third metal oxide semiconductor transistor and a control terminal of a fourth metal oxide semiconductor transistor, wherein a first connection terminal of the third metal oxide semiconductor transistor is coupled to the first reference voltage, a first connection terminal of the fourth metal oxide semiconductor transistor is coupled to the second reference voltage, a second connection terminal of the third metal oxide semiconductor transistor is coupled to a second connection terminal of the fourth metal oxide semiconductor transistor, and the first input signal and the second input signal are differential inputs of the inverter circuit; and outputting the first inverter output signal to the second connection terminal of the third metal oxide semiconductor transistor and the second connection terminal of the fourth metal oxide semiconductor transistor.

14. The method of claim 8, wherein the inverter circuit is part of a clipper in a limiting amplifier.

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